Humberto Fonseca
Andrew Beckett
Analogue design challenges in nanometer process nodes
2 © 2014 Cadence Design Systems, Inc. All rights reserved. Looking for IPs ? http://ip.cadence.com
• Introduction to Cadence IP portfolio
• Analogue circuit design problems in nanometer technologies
• Low voltage bandgap design
• Low voltage buffer design
• Conclusion
Analogue design challenges in nanometer process nodes
3 © 2014 Cadence Design Systems, Inc. All rights reserved. Looking for IPs ? http://ip.cadence.com
Cadence has a large footprint in the IP market
Pre - 2013
AnalogueTeam joins
IPG
Tensilica joins IPG
Cosmic joins IPG
2014 …
Evatronix to join IPG
Denali joins Cadence Systems
2013
• Denali acquisition - strong memory IP and models
• Fabless analogue team – expands analogue capabilities
• OEM IP acquisition provides key mobile IP technology
• Tensilica adds innovative and system level IP to portfolio
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• Evatronix will complement USB and memory IP offering
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• Poor output impedance characteristic
• High Leakage: gate leakage, drain to source leakage
• Low supply voltages: – As low as 800mV,
– Vth has not scaled relative to the supply level and can be as high as 500mV
• Conventional analogue circuits such as bandgaps, current mirrors, etc, become challenging to design at this voltage level
Analogue Design problems in nanometer technologies:
VDD
VSS
VD
D
PMOS
Vth
NMOS
Vth
Vin
Range of
input
common
modes not
supported
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Voltage doublers to solve local headroom problems
Low
Power
Oscillator
0.7V Supply
High voltage island
Band
Gap
VDD
VDD
clk
clkb Vout = 2xVDD
Charge
Pump
Voltage
Doubler
0.5V
Output
Voltage
SoC Supply Voltage=0.7V
Local High Voltage Island = ~1.6V
Band Gap Output voltage = ~1.2V
Voltage [
V]
Example Very low supply low drop-out (LDO) regulator
Voltage doubler unit element:
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Bandgap conventional approaches
1.2V
Topology 1 Topology 2 • Topology 1: – Not compatible with a low voltage
supply by the need to stack the PTAT and CTAT components in the same branch
• Topology 2: – Is compatible with a low voltage
however:
– Area is dominated by the passive components and in order to achieve low supply current the resistors have to be large, several MΩ, impacting area
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Switched capacitor bandgap reference to achieve low voltage, low power and low noise
R1
R2
ph0
ph2
ph2
ph0
ph1
ph1
C1
C2
VOUT
< 0.8V ph0
ph1
ph2
Bandgap OFF Bandgap OFF
• The PTAT and CTAT components are added using charge sharing between C1 and C2, converging to Vbg/2 ~0.6V
• C1 and C2 alternate between storing CTAT and PTAT to remove the impact of mismatches between C1 and C2 reducing their area. Cout stores the output voltage
• During ph1 phase the band gap circuitry is powered down in therefore dramatically reducing the average power consumption.
• The pulsed band gap pushes the low frequency noise down by the ON/OFF ratio.
R2
R1
Amplifies the
PTAT component
PTAT
CTAT
Cout
ph1 forces bandgap power down
Bandgap
ON Bandgap
ON
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Switched capacitor bandgap reference start-up simulations
Bandgap output voltage, stored in Cout
Control pulses Pulsed band gap voltage
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Spectre switched capacitor bandgap noise simulation results
Always ON bandgap noise profile
Switched band
gap noise profile
The technique presented leads to a 19dB improvement in the band gap noise performance
AC+ Noise
analysis
PAC+ Pnoise
analysis
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Cascode devices replaced by replicas of the differential pair
Supply > 1VGS + 3xVDSAT Supply > 1VGS + 2xVDSAT
Conventional 2
stage amplifier
with cascode
devices
2 stage amplifier with
replicas of the
differential pair
replacing the
cascode devices
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Active cascodes to ensure good matching even within the triode region
• MC1 has its source tied to VOUT therefore creating the floating bias voltage VG referred to it.
• For low VOUT MC3 and MC2 have little impact on the circuit performance and do not significantly add to the overall voltage headroom
• As VOUT approaches the VDD MC2 and MC3 force MPOUT, M1 and M2 to have the same VDS.
• When MPOUT enters its triode region M1 and M2 are forced into triode as well
2 stage
amplifier with
an active
cascode
MC1
VG
VOUT
MPOUT M1 M2
MC2 MC3
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Nested loops to achieve high gain without cascodes
Load
Vout Ref Primary
Differential
Pair
Secondary
Differential
Pair
Main
Loop
DC Gain
Boost
Loop
• Achieves 2nd order gain characteristics and it is stabilized as if two separate first order loops
• DC Gain Boost loop pole should be an order of magnitude small than the output load pole
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Voltage reference buffer using a mix of techniques
• Active cascode on the PMOS side to maintain good gain characteristic for output voltages close to VDD.
• Replicas of the differential pair in order to achieve good matching in the NMOS current sources,
• Nested gain loop to achieve high DC gain
Vin
Vout
Example use case
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Reference buffer using a mix of techniques, simulation results
Step response
Example using a 16nm FinFET process and 0.9V supply, with 100ohm load
Step response Input DC Sweep
The output
voltage
compresses only
at 10mV below
the supply
Supply
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• Traditional analogue circuit design is feasible at nanometer nodes
• Optimized topologies are required to maintain headroom & common mode range
• Additional variation can be managed through calibration – Digital complexity is cheap for area and power
• Cadence IP has been developed on 28nm, 16nm and 14nm technologies using these and similar techniques
Conclusion