Abstract— Power supply noise management continues to be achallenge with the scaling of CMOS technologies. Use of on-chip decoupling capacitors (decaps) is the most common noisesuppression technique and has significant associated area andleakage costs. There are numerous methods of implementingdecaps and it is not always clear which implementation isthe most optimal for the given design constraints. This papercharacterizes various decap implementations including MOS-based decaps, multilayer metal decaps, and metal-insulator-metal decaps using postlayout simulations in a 65-nm CMOStechnology, and provides an outline for determining the mostoptimal selection and design of decaps based on area, leakage,and location. Hybrid structures are further shown to boost thearea efficiency of conventional nMOS decaps by an additional∼25%.
Index Terms— Decoupling capacitor (decap), integrated circuit(IC) design, power supply noise.
I. INTRODUCTION
AS CMOS technology continues to advance into the deepsubmicrometer regime, present-day integrated circuits
(ICs) have become increasingly sensitive to various noisesources including power supply, or switching, noise. This noiseis correlated to the switching activity and current consumptionof circuits in the presence of inductive, capacitive, and resistiveparasitics along the power grid. The faster the circuit switchand/or the more current they draw, the larger the noise seen onthe supply lines. If the power supply voltage droops too low,circuit performance and functionality can be compromised.Large overshoots can have circuit reliability implications, suchas electromigration issues and degradation of the gate oxideof transistors, in addition to compromising functionality. Forexample, in a 0.13-μm technology, a 10% voltage variationhas been shown to result in a 30% variation in the delay oftypical gates [1]. The jitter of timing signals is also linearlyproportional to noise on the supply [2], and supply noise canfurther adversely affect the stability of static random accessmemory (SRAM) cells [3].
The most common technique to suppress power supplynoise is to place a relatively large bypass/decoupling capacitor
Manuscript received August 8, 2011; revised January 12, 2012; acceptedApril 12, 2012. Date of publication July 13, 2012; date of current versionMarch 18, 2013. This work was supported in part by the Natural Sciencesand Engineering Research Council of Canada.
Color versions of one or more of the figures in this paper are availableonline at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TVLSI.2012.2198501
(decap) between the supply rails. Decaps have been used bothon- and off-chip for over 40 years. The decap provides a lowimpedance path and shunts or bypasses high-frequency noiseon the supply to ground and vice versa. When placed as partof an isolation circuit between a noise-generating circuit anda sensitive circuit, the decap serves to “decouple” the noisebetween the sensitive circuit, and thus the terms bypass anddecoupling are used interchangeably for these capacitors.
There are several methods of implementing decaps on-chipand each has its limitations primarily with regard to area andleakage power consumption. The optimal choice of decap thusdepends on circuit constraints and process technology. Furthercomplicating this decision is the availability of increasedoptions within the technology such as multithreshold devicesand an increase in available metal layers which provide moreways in which the decaps can be implemented. Furthermore,parasitic resistances associated with the decaps are technologyand frequency specific and play a role in determining theoverall impedance of the decap. Therefore, the optimal choiceof decap implementation is not always evident for a givenset of constraints and technology. This paper characterizesvarious decap implementations including MOS-based decaps,metal-insulator-metal (MIM) decaps, and metal decaps, usingpostlayout simulations in a standard CMOS 65-nm technologyso as to enable the most favourable decap implementation tobe apparent for the given chip design constraints. The effectof layout on decap characteristics is also considered. Hybriddecap implementations are further investigated and shown toprovide increased capacitance with no additional cost in areaor power.
II. GENERAL DECAP MODEL
Fig. 1 illustrates a general decap model for on-chip decaps.The values of the components shown determine the overalldecap impedance (or admittance), which is directly related tothe level of noise suppression seen on the supply.
The overall decap effective capacitance Ceff , comprises ofthe area capacitance of the decap C , a fringe capacitive com-ponent Cfringe, and a coupling capacitive component Ccoupling,as illustrated in Fig. 2 for a parallel plate capacitor. Thecapacitance Cfringe results between the sidewalls of the decapand an alternate terminal in any adjacent layers, and Ccouplingresults between adjacent terminals in the same layer.
The amount of decoupling capacitance on a typical chip canbe relatively large. For example, the total decap on typicalmicroprocessor chips ranges in hundreds of nanofarads [4]and can occupy more than 20% of the total chip area [5].
CHARANIA et al.: ANALYSIS AND DESIGN OF ON-CHIP DECOUPLING CAPACITORS 649
Gnd
ESR
Fig. 1. General decap model.
Gnd
Gnd Gnd
CCfringe Cfringe
Fig. 2. Capacitive components of a parallel plate decap.
In order to minimize the area utilized by decaps for supplynoise suppression, decaps with relatively high capacitancesare desirable. The capacitance C is given by the well-knownequation
C = εA
t(1)
where ε is the permittivity of the dielectric, A the crosssectional area of the capacitor, and t the dielectric thickness.Therefore, in order to maximize capacitance per unit area of adecap, a thin dielectric (and/or large permittivity) is desirable.
A shortcoming of using a thin dielectric, is the resultingtunneling leakage current. Decap leakage typically contributes10%–20% of the overall power budget of a chip [6]. Not onlydoes leakage affect the chip’s power consumption but it alsoreduces the effectiveness of the decap [4] due to the loss ofcharge. The dielectric leakage effect is represented by meansof resistor Rleakage between the supply and ground terminals.
Another parameter of interest in the decap model is theequivalent series resistance (ESR). All capacitors exhibit afinite amount of ESR that can vary with frequency. The ESRis not a physical resistor but rather an “equivalent” resistancethat results from the conducting electrodes as well as theinsulating dielectric. For the purposes of modeling, the ESRof a capacitor is typically represented as a single parasiticelement in series with the capacitor. The presence of theESR undesirably increases the impedance between the decapterminals.
Conversely, the ESR can also play a role in dampingoscillations that may result from the LC tank formed bythe capacitance and parasitic inductances along the powergrid [7]. Therefore, it should be kept in mind that whereoscillations are present, the ESR can desirably dissipate energythus potentially reducing the overall supply noise.
The ESR can further have electrostatic discharge (ESD)implications [8]. In modern CMOS technologies, the oxide isrelatively thin and thus more prone to breakdown as a resultof an ESD event. A simple protection scheme is to inserta resistance in series with the capacitor to limit the voltageseen across the dielectric layer [8]. Decaps with an inherentlarge ESR can therefore desirably provide some level of ESD
Gnd(a)
Gnd(b)
Gnd(c)
Fig. 3. Configurations for (a) nMOS decap, (b) pMOS decap, and (c) CMOSdecap.
protection without the need for additional area to implementadded resistance.
Like ESR, there can also be an equivalent series inductance(ESL) associated with decaps. The presence of this additionalinductance can further increase the impedance of the decap.Fortunately, the ESL of on-chip decaps is small and its effectsare typically neglected.
III. SURVEY OF DECAP TYPES
On-chip decaps can be realized in a variety of waysdepending on which process layers and/or devices are used toimplement the capacitance. In this paper, decaps achievable ina standard 65-nm CMOS process are considered. These decapsare essentially MOS-based decaps as well as decaps imple-mented using the various metal layers. While MIM capacitorsare an additional process option, they are frequently offered invarious processes, and MIM decaps are thus included in theanalysis. Other capacitive structures achievable in nonstandardCMOS technologies include poly-insulator-poly capacitors anddeep trench capacitors, however, these are not considered inthis paper.
A. MOS Decaps
In a standard CMOS 65-nm technology, the gate oxidelayer provides the thinnest dielectric layer, and MOS-baseddecaps are thus the most area-efficient and most commonlyimplemented structures [4]. One drawback of these decapsis the resulting leakage current which increases exponentiallywith decreasing oxide thickness [9].
1) nMOS, pMOS, and CMOS Decaps: MOS-based decapscan be implemented as nMOS decaps, pMOS decaps, or acombination of these as CMOS decaps, as illustrated in Fig. 3.CMOS decaps are commonly used within standard cells sincea portion of the area within these cells is typically reservedfor pMOS transistors and a portion for nMOS transistors.
2) Thick Oxide MOS Decaps: For designs in which leakagecurrents are an important constraint, thick oxide MOS devicescan be used to minimize the leakage across the gate oxidelayer [10]. The oxide thickness in these devices is typicallythree times larger than that of their standard counterparts. Anexpected drawback of this implementation, however, is thereduction in capacitance per unit area.
3) Variable Threshold Voltage MOS Decaps: The availabil-ity of variable threshold voltage devices in modern technolo-gies provides additional transistors with which MOS decapscan be implemented. Low threshold voltage devices have ahigher semiconductor doping level and subsequently a lowerchannel resistance, and thus ESR, compared to the higherthreshold voltage devices.
650 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 21, NO. 4, APRIL 2013
Gnd
Fig. 4. Back-to-back decap configuration.
4) Accumulation Mode MOS Decaps: The MOS decapsdiscussed previously are essentially inversion mode devices.Accumulation mode transistors can also be used to implementdecaps and design kits, typically model accumulation modenMOS (A-nMOS) devices, for use as varactors.
B. Back-To-Back MOS Decaps
A cross-coupled, or back-to-back, MOS decap design hasalso been discussed in the literature [8] and is illustrated inFig. 4. This design inherently provides an additional resistance(the device channel resistance) in series with the capacitancefor the purpose of providing local ESD protection to thedecap. The oxide breakdown voltage is almost linearly pro-portional to oxide thickness [11] and for a thin oxide nMOSdevice in a typical 65-nm technology, the oxide breakdownvoltage is only around 1.2 to 2 V [12]. Since this voltageis close to the operating voltage of 1 V of these devices,the additional resistance inherent in this decap design canprovide a degree of protection against oxide breakdown dueto supply voltage oscillations, as described earlier. It does,however, tradeoff an increase in the overall impedance of thestructure.
C. Gated Decaps
In gated decaps, a control transistor is placed in series withthe decap, as illustrated in Fig. 5. The transistor here serves toreduce the chip power consumption [13] by enabling the decapto be deactivated when certain circuit blocks are inactive, thuseliminating the associated decap leakage current. The gatefurther enables the isolation of the decap in the event of shortsbetween the plates of the capacitor due to process defects. Theadded channel resistance in series with the capacitor, however,results in an increase in decap impedance. The control tran-sistor thus has conflicting constraints of minimizing its ON
resistance and channel leakage.
D. MIM Decap
Some process options offer MIM decaps where additionalsteps are introduced into the process specifically for fabricatingcapacitors. Fig. 6 illustrates the cross section of a MIMcapacitor fabricated between Metals 7 and 8 of a CMOSprocess.
E. Metal Decaps
The various metal layers available in CMOS fabricationtechnologies can be used to form lateral and/or vertical capac-itors. Lateral capacitors are formed by coupling capacitances
Gnd
Fig. 5. Gated decap configuration.
Fig. 6. Cross section of a MIM capacitor.
Fig. 7. Top view of an interdigitated MOM decap.
between two traces on the same metal layer separated bya dielectric. In the CMOS process, lateral capacitors aregenerally referred to as metal–oxide–metal (MOM) capacitors.MOM capacitors are typically formed as interdigitated struc-tures as illustrated in the decap in Fig. 7, where alternatinglines are used to form the two terminals of the capacitor.Quasifractal capacitors have also been studied in the litera-ture [14] where the perimeter of the capacitive structures ismaximized with respect to area, however, the interdigitatedstructure designed with minimum design rules provides themost lateral coupling capacitance per unit area.
IV. ANALYSIS OF DECAP TYPES
Table I lists the various decap implementations analyzed.Different multilayer metal decaps are further considered inSection V. All the analyses are based on postlayout simula-tions in a 65-nm CMOS technology.
The particular layout implementation of a decap affects itsoverall capacitance and area. For example, a fixed MOS oxidecapacitance can be implemented using a single polysiliconfinger or multiple parallel polysilicon fingers. The multiplefinger structure will have a larger fringe component comparedto the single finger structure, however, it will also have a largerarea due to the minimum spacing requirements between thefeatures. In addition, the frequency response of the MOS-baseddecaps has been shown to degrade with increasing channellength due to larger channel resistances at high frequencies [4],
CHARANIA et al.: ANALYSIS AND DESIGN OF ON-CHIP DECOUPLING CAPACITORS 651
TABLE I
LEGEND FOR VARIOUS DECAP CONFIGURATIONS ANALYZED
Symbol Description
nMOS nMOS decap
nMOS_25 2.5-V thick oxide nMOS capacitor
nMOS_LVT Low threshold voltage nMOS capacitor
A_nMOS A_nMOS capacitor
pMOS pMOS capacitor
CMOS nMOS and pMOS capacitors
MIM MIM capacitor
GATED Gated nMOS capacitor
B2B Back-to-back capacitor
MOM_M1 Interdigitated Metal 1 MOM capacitor
Fig. 8. Layout of an nMOS decap.
which further constrains the finger length. Furthermore, plac-ing multiple fingers in parallel reduces the overall ESR andESL of the decaps. Therefore, for the purpose of comparing thearea efficiency of the various decap structures, a fixed layouttopology is selected for the decap structures considered. EachMOS-based decap is designed as a 6 × 6 array with a gatelength of 1 μm. This length provides a practical layout withoutsignificantly affecting the frequency response, as shown laterin this section. The width of each structure is designed suchthat each decap has a layout-extracted value of Ceff equal to∼500 fF at 100 MHz. The MIM decap and MOM_M1decap are similarly designed to provide a Ceff equal to∼500 fF at 100 MHz with the specific dimensions governedby design rules. The area of each structure thus differs basedon how area efficient the particular implementation is. Theextracted capacitance includes the oxide capacitance as wellas any fringe/coupling capacitances that are present and isthe overall capacitance of the decap structure. Each decapis thus designed independent of the circuit environment inwhich it may be used, and while the exact magnitude ofthe suppression is dependent on the frequency componentsof the specific supply waveform, the degree of suppressionis designed to be approximately the same for each decap at100 MHz independent of the circuit environment. Care wasalso taken to minimize the area occupied by each decap. Thefrequency response is studied from 100 MHz to 30 GHz, therange in which the models used are valid. The specific layoutparameters for each decap are given in Table II with the layoutfor an nMOS decap illustrated in Fig. 8.
A. Effective Capacitance (Ceff )
The effective capacitance of each decap structure wasdetermined in postlayout simulation by placing a sinusoidalAC test voltage on a 1-V DC supply across the decap. Since
TABLE II
DESIGN PARAMETERS FOR VARIOUS DECAP
CONFIGURATIONS ANALYZED
Decap Layoutconfiguration
Unit L(μm)
Unit W(μm)
Area(μm2)
Layout-extractedCeff (fF)
nMOS 6 × 6 array 1 0.83 55 500
nMOS_25 6 × 6 array 1 2.29 135 500
nMOS_LVT 6 × 6 array 1 0.82 55 501
A_nMOS 6 × 6 array 1 0.80 61 498
pMOS 6 × 6 array 1 0.91 61 501
CMOS 6 × 6 p-array 1 0.42 75 493
6 × 6 n-array 1 0.42
MIM 7 × 7 array 2.01 2.01 1343 507
GATED 6 × 6 array 1 0.83 73 500
Gate: 0.06 40
B2B 6 × 6 p-array 1 0.43 75 500
6 × 6 n-array 1 0.43
MOM_M1 Interdigitated 6.7 0.09 1201 507
the inductive parasitics of most on-chip decaps are negligible,the ESL is neglected in the model. The general decap model[Fig. 9(a)] is thus reduced to that shown in Fig. 9(b).
The decap impedance, Z , is given by
Z =Rleakage
(ESR + 1
j ·ω·Ceff
)
Rleakage + ESR + 1j ·ω·Ceff
. (2)
Separating the real and imaginary parts, Z becomes
Z =
⎛⎜⎜⎜⎝
Rleakage·ESR(Rleakage+ESR)(Rleakage+ESR)2+ 1
ω2·C2eff
+ Rleakage
ω2·C2eff
((Rleakage+ESR)2+ 1
ω2·C2eff
)
⎞⎟⎟⎟⎠
+ j
⎛⎜⎜⎜⎝
Rleakage(Rleakage+ESR)
ω·Ceff
((Rleakage+ESR)2+ 1
ω2·C2eff
)
+ Rleakage·ESR
ω·Ceff
((Rleakage+ESR)2+ 1
ω2·C2eff
)
⎞⎟⎟⎟⎠. (3)
At frequencies in the range of interest (greater than 100MHz), Z can be simplified to
Z ≈ Rleakage
Rleakage + ESR
(ESR + 1
j · ω · Ceff
). (4)
Since Rleakage >> ESR, Z can be further simplified to
Z ≈ ESR + 1
j · ω · Ceff(5)
and the model is further simplified to that shown in Fig. 9(c).Ceff can thus be determined from
Ceff = 1
2 · π · f · |Z | · sin θ= |I |
2 · π · f · |V | · sin θ(6)
where f is the frequency of the test signal, θ is the phasedifference between the voltage across and current through thedecap, and |V| and |I| are the magnitudes of the AC voltageand current of the decap, respectively.
652 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 21, NO. 4, APRIL 2013
Fig. 9. (a) Full decap model. (b) Simplified decap model with leakage.(c) Simplified decap model without leakage.
Fig. 10. Effective capacitance versus frequency for various decaps.
Fig. 10 illustrates effective capacitance versus frequencyfor the various decap structures considered. The nMOS andpMOS decaps have very similar frequency responses fordevices with a length of 1 μm in the 65-nm technology.The thick oxide decap and low threshold voltage decap alsohave similar frequency responses to the standard nMOS andpMOS devices. The A_nMOS decap exhibits a slight increasein effective capacitance with frequency, which is attributed tothe channel charge having progressively less time to dischargebetween cycles resulting in greater shielding of the parasiticcapacitances in series with the gate capacitance. The back-to-back design has the poorest response followed by the Metal 1MOM decap. This is due to the higher series resistance inthese devices (as will be shown) that limits the flow of carriersat high frequencies [4]. The GATED design and MIM decapperform better, although not as well as the standard nMOSand pMOS decaps.
Fig. 11 illustrates the effective capacitance per unit areaversus frequency for each structure and thus indicates thearea efficiency of each decap. The standard and low thresholdvoltage nMOS decaps are the most area-efficient structuresin the frequency range considered, with the A_nMOS decapbecoming comparable with increasing frequency. The lowthreshold voltage device thus provides no visible improvementin capacitance per unit area. The pMOS decap also performsrelatively well in terms of area efficiency, and using a CMOSdecap, as is often done within standard cells, results in a poorerarea efficiency compared to using either an individual nMOSor pMOS structure. As expected, the thick oxide nMOS decaphas a significantly poorer area efficiency compared to thestandard nMOS design, followed by the back-to-back design,and both MIM and Metal 1 MOM decaps are the most area-inefficient designs.
Fig. 11. Effective capacitance per unit area versus frequency for variousdecaps.
Fig. 12. ESR for various decaps.
B. ESR
Following the analysis used to determine Ceff , the ESRs ofthe decap structures studied can be obtained from
ESR = |Z | · cos θ = |V | · cos θ
|I | . (7)
Fig. 12 illustrates the ESR of the various decaps versus fre-quency. A general trend of decreasing resistance is seen withincreasing frequency for all designs. The back-to-back designexhibits the largest ESR over most frequencies as expectedfrom the added channel resistances in series with the oxidecapacitances in this design. The various MOS-based designshave relatively low ESRs (<11 � over most frequencies),with the exception of the back-to-back design which has thelargest ESR.
C. Impedance
The overall impedance of each decap directly determinesthe extent of supply noise suppression that it provides and isan approximate function of both the ESR and Ceff according to(5). The impedance magnitude normalized to an area of 1 μm2
is plotted in Fig. 13 for each decap configuration considered.The trend in area efficiency with respect to impedance is thesame as that observed with respect to effective capacitanceas seen in Fig. 11, since Ceff is the dominant component ofthe impedance. Numerical values of the normalized impedancemagnitude are further provided for convenience in Table III at100 MHz, and 1, 10, and 30 GHz.
CHARANIA et al.: ANALYSIS AND DESIGN OF ON-CHIP DECOUPLING CAPACITORS 653
Fig. 14 shows the dielectric leakage currents measured atDC for each of the decap designs compared, with the effectivecapacitance per unit area at 10 GHz is also provided herefor convenience. While the data at only a single frequency isgiven, the relative trends are representative over most of therange of frequencies considered (as seen from Fig. 11).
The nMOS decap has the highest leakage current (and thusgreatest power dissipation) due to the thickness of thin oxideand the relatively small channel resistance; the pMOS andA_nMOS decaps have approximately one-third this leakage.In the latter two devices, the smaller leakage is attributed totheir slightly larger ESR compared to the nMOS device.
The thick oxide nMOS, MIM, and Metal 1 MOM decapshave almost no leakage current, with the thick oxidenMOS decap having the largest corresponding area effi-ciency. The thick oxide nMOS decap is thus the mostdesirable structure where leakage power is the primary con-straint in a design, providing negligible dielectric leakagecurrent at the cost of ∼60% in effective capacitance perunit area.
In most design situations both power and area are ofconcern, and in this case, both the pMOS and A_nMOSdecaps provide a good tradeoff between power and area,with the A_nMOS performing slightly better in terms ofarea efficiency at frequencies >∼10 GHz, and the pMOS
Fig. 14. Effective capacitance per unit area (at 10 GHz) and dielectric leakagecurrent (at DC) for various decap configurations.
decap performing slightly better in terms of leakage. As isevident from Fig. 14, the pMOS and A_nMOS decaps givea significant reduction in leakage (∼70%) with a relativelysmall reduction in effective capacitance per unit area (∼10%)compared to the nMOS decap.
While this analysis is conducted at the 65-nm technologynode, it can be noted that with the advent of high-k materialsfor use as the gate dielectric for subsequent technologies, theleakage power of decaps can be significantly reduced. Thehigher permittivity enables the thickness of the dielectric to beincreased which exponentially decreases the leakage current ofthe device. Thus, as CMOS technology continues to scale, thenMOS decap is likely to be the decap of choice with bothminimum area and power.
It should also be noted that, although a decrease in effectivecapacitance per unit area and an increase in leakage is seenwith the gated nMOS decap compared to the standard nMOSdecap, the purpose of the gated structure is to actually reducethe overall leakage power by modulating the gate to beclosed when the decap is not in use. Thus, depending on thecircuitry with which the gated decap is used, this decap canprovide a desirable alternative to the standard nMOS, pMOSor A_nMOS decap structures.
E. Capacitance—Voltage (CV) Response
MOS-based capacitors behave as varactors due to the vari-ation in channel charge with varying voltage which leads tovarying degrees of shielding of the depletion layer capacitancein these devices. Fig. 15 illustrates the CV characteristicsfor the various decap configurations measured at 100 MHz.The MIM and Metal 1 MOM decaps provide the most stablecapacitance over varying voltages. The supply voltage on mostchips, however, does not typically vary more than 15% [6],and the region of interest in the CV curve is indicated bythe shaded region. In this region, none of the decap structuresexhibit a significant variation in capacitance.
V. ANALYSIS OF MULTILAYER METAL DECAPS
Multilayer MOM capacitors can be formed using inter-digitated structures in multiple metal layers with vias usedto connect the traces of each corresponding terminal. As is
654 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 21, NO. 4, APRIL 2013
Fig. 15. Capacitance-voltage plots for various decaps measured at 100 MHz.
GndVdd Dielectric
Metal 2
Metal 4
Metal 3
Metal 5
Metal 7
Metal 6
Metal 2
Metal 4
Metal 3
Metal 5
Metal 7
Metal 6
Metal 2
Metal 4
Metal 3
Metal 5
Metal 7
Metal 6
Metal 2
Metal 4
Metal 3
Metal 5
Metal 7
Metal 6
(a) Stacked (b) Alternating
steehS )d(evitatoR )c(
Fig. 16. Cross sectional view (not to scale) of (a) stacked multilayerMOM decap, (b) alternating multilayer MOM decap, (c) RTMOM decap, and(d) multilayer decap using metal sheets.
evident, there is freedom in the orientation of the structure ineach layer relative to other layers, for example, the structurescan be parallel to each other and stacked as illustrated inFig. 16(a), parallel to each other with the terminals alternat-ing in the vertical direction as illustrated in Fig. 16(b), orperpendicular to each other as in rotative metal capacitors(RTMOM) capacitors, as illustrated in Fig. 16(c). An alternatemultilayer metal decap can also be formed using sheets ofmetal layers with alternating terminals creating a series ofvertical capacitors as illustrated in Fig. 16(d).
One question that arises when considering various metaldecaps is whether multilayer interdigitated metal (MOM)decaps [Fig. 16(a)–(c)] are more area efficient than a seriesof vertical decaps formed using sheets of metal layers[Fig. 16(d)]. Which decap is more area efficient dependson the dielectric properties and achievable feature dimen-sions and spacings in the particular process technology used.Fig. 17(a) and (b) illustrates an alternating two-layer MOMdecap and a two-layer metal decap using metal sheets, respec-tively, designed in a 65-nm CMOS technology. The MOMdecap uses minimum dimensions for reliability, and bothstructures are designed to have the same area.
TABLE IV
COMPARISON OF AN MOM DECAP AND A VERTICAL METAL DECAP
The capacitances of the MOM decap Ca, and the decapusing metal sheets Cb per unit width W , are given in Table IV,where Ca_vertical is the vertical capacitance and Ca_lateral thelateral capacitance of the MOM decap. As can be seen, thetotal capacitance of the metal decap using metal sheets isapproximately 47% less than that of the MOM decap. Themultilayer interdigitated structure is thus more desirable thana simple noninterdigitated metal decap using metal sheets interms of capacitance per unit area. This advantage in capaci-tance is primarily a result of the minimum spacing dimensionbetween the metal features being significantly smaller than thethickness of the dielectric between the metal layers, which istypical of most processes. In addition, while it can be expectedthat the metal thickness will decrease with technology scaling,the minimum space requirements are correspondingly expectedto decrease thus compensating for the effect of the decrease inmetal thickness. The superiority of the interdigitated structureis thus expected to be evident over various processes.
A. Effective Capacitance (Ceff )
Fig. 18 shows the effective capacitance versus frequencyfor the multilayer metal structures of Fig. 16. Metals 2–7 areused in these structures since Metal 1 is typically reservedfor low-level routing, and Metals 8 and 9 have design rulesthat result in a minimal increase in capacitance of the overallstructures and are typically reserved for top-level routing. Allthe structures are designed to have the same area, and the graphthus provides an indication of the relative area efficienciesof the structures (shown on the secondary axis). The rotativestructure, followed very closely by the alternating structure,provides the largest effective capacitance in the given area.The rotative structure also has the simpler layout of the two
CHARANIA et al.: ANALYSIS AND DESIGN OF ON-CHIP DECOUPLING CAPACITORS 655
Fig. 18. Effective capacitance and effective capacitance per unit area versusfrequency for various multilayer metal decaps.
and it can be noted that the particular layout configuration usedcan cause a variation in the overall effective capacitance. Thestructures simulated in Fig. 18 use minimum dimensions forreliability in a 65-nm technology. It can further be seen thatthe stacked structure is less area efficient than the rotative andalternating structures, and the multilayer decap using metalsheets has the poorest area efficiency compared to the othermultilayer metal decaps as was theoretically demonstratedearlier.
B. ESR
Fig. 19 shows the corresponding ESR for the structuressimulated in Fig. 18. The alternating structure exhibits thelargest ESR due to its routing complexity. The stacked androtative structures are comparatively simpler to realize inlayout and thus exhibit correspondingly smaller ESRs. Thedecap structure realized with metal sheets has the smallest ESRdue to the fact that the metal sheets have a smaller resistancethan the traces used in the interdigitated structures.
C. Impedance
The impedance magnitude with associated normalizedimpedance magnitude (on the secondary axis) is plotted inFig. 20 for the various multilayer metal decaps. Again, follow-ing from the effective capacitance trends, the rotative decap,followed closely by the alternating decap, provides the lowestimpedance structures subsequently followed by the stackedstructure, with the metal sheet structure significantly lagging.
D. Placement of Multilayer Metal Decaps
The multilayer metal structures discussed thus far have theadvantage of satisfying the metal fill requirements of chips
Fig. 20. Impedance magnitude and normalized impedance magnitude forvarious multilayer metal decaps.
while providing decoupling capacitance between the supplyand ground nodes. The interdigitated structures can be placedin each metal layer in any part of the chip, including on topof the existing circuitry, where the corresponding metal layersare not being used for routing, thus allowing additional decapto be obtained at no additional cost in area. In other words,these multilayer structures are desirable as metal fill patternssince they serve to simultaneously provide metal fill as wellas decoupling capacitance.
VI. LAYOUT CONSIDERATIONS
As was described earlier, the specific layout topology canhave a significant impact on the area occupied by a particulardecap. In the case of MOS decaps, as was seen earlier,the capacitance is primarily a result of the vertical oxidecapacitance between the gate and the silicon substrate. Thereis also a fringe component between the sidewalls and thesubstrate, and a coupling component between the sidewallsand the substrate contacts. When implementing MOS decaps,there is freedom in the number and size of the unit fingers usedto implement the gate of the devices. Using multiple fingersto implement a particular decap compared to an equivalentsingle-finger implementation, for example, can have two maineffects. First, the multifinger decap will have a larger fringecomponent than its single-finger equivalent due to the addi-tional sidewall area. Second, the overall area of the multifingerstructure will be larger than its single-finger equivalent due tothe spacing requirements between the fingers in the multi-finger structure. The magnitude of these effects will varydepending on the specific layout configuration chosen. Fourdifferent nMOS layout configurations were simulated and thetwo effects quantified and summarized in Table V. As can beseen, the decap area does not vary significantly for designswith 12 or less fingers, and a relatively small (<2%) increasein capacitance is attributed to additional fringe capacitancewhere the number of fingers is increased in the dimensionrange considered.
Another important consideration, however, in determiningthe most optimal layout configuration of an MOS decap is thefrequency response of the capacitance since the voltage alongthe channel length L of an MOS capacitor has been shown tovary with frequency [4]. The overall effective capacitance per
656 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 21, NO. 4, APRIL 2013
TABLE V
EFFECTIVE CAPACITANCE OF VARIOUS nMOS DECAP CONFIGURATIONS
Fig. 21. Effective capacitance per unit area for various lengths for nMOS,pMOS, and A_nMOS decaps.
unit area can be graphically observed for the three generaltypes of MOS decaps (pMOS, nMOS, and A_nMOS) inFig. 21. Here the length of each finger is varied, and thusthe total number of fingers is varied for each type of decap asindicated. As can be seen, the A_nMOS decap is the most sen-sitive to L, and the nMOS decap the least sensitive. The resultsfurther show that all of the nMOS, pMOS, and A_nMOSdecaps with an L of 3 μm provide the best capacitance per unitarea over most frequencies considered. pMOS devices with anL of 12 μm and greater, and A_nMOS devices with an L of6 μm and greater, should be avoided when high-frequencynoise components are present as a significant degradation ineffective capacitance occurs with increasing frequency.
MIM decaps are similarly expected to exhibit variations inarea based on their layout configuration although they showa more constant frequency response, however these decapsare not specifically considered in this analysis since theirarea efficiency was found to be approximately an order ofmagnitude smaller than that of nMOS decaps and are thus notrecommended for the implementation of decaps. In the case ofmetal decaps, since a significant portion of their capacitancecomes from the lateral capacitance between metal traces,adhering to minimum design rules for width and spacing is rec-ommended to maximize the area efficiency of these structures.
Fig. 22. Effective capacitance and effective capacitance per unit area versusfrequency for hybrid decaps and an nMOS decap.
VII. HYBRID DECAPS
In this section, the combination of more than one decap toform a decap hybrid structure is investigated. While it wasshown earlier that MOS-based decaps provide the most area-efficient designs, these structures utilize only a few processlayers, namely, the gate oxide, poly, and typically a singlemetal layer for routing. This leaves multiple metallizationlayers available for providing additional capacitance withinthe same area. In a hybrid structure, a multilayer metal decapis physically placed on top of, and electrically connected inparallel with, an MOS-based decap to increase capacitance perunit area.
While metal is typically placed on top of various parts of thechip including decaps using an automated algorithm in a metalfill procedure to meet metal density requirements, this metalis typically not designed to provide capacitance between thesupply and ground terminals. It is preferentially left floating,however, all the fill can also be tied to ground where sufficientcomputer resources are not available to deal with the floatingmetal. It is generally not connected to the supply as there canbe floating supplies in a design due to power gating. Therefore,using the hybrid structure, the available metal layers can beused efficiently in increasing the overall decap capacitancewhile simultaneously fulfilling metal fill requirements.
Clearly, a number of MOS and metal decap combinationsare possible. In this section, a combination of nMOS +RTMOM decaps, and nMOS + RTMOM + MIM decapsare investigated. In the nMOS + RTMOM decap, Metals 2–7are used for the RTMOM. In the nMOS_RTMOM + MIM,only Metals 2–6 are used since the MIM decap is fabricatedbetween Metals 7 and 8, and the design rules preclude the useof Metal 7 under a MIM capacitor.
Fig. 22 illustrates the effective capacitance versus frequencyfor the hybrid decaps, where the area of each individual decapcomprised in the hybrid structures is kept the same. The datafor a simple nMOS decap with the same area is also includedfor comparison. As shown Fig. 22, an increase in effectivecapacitance of ∼25% is obtained with both hybrid structurescompared to a simple nMOS decap.
It can also be seen that omitting one metal layer (Metal 7)in the nMOS + RTMOM + MIM decap reduces any gains incapacitance from the MIM decap and no noticeable improve-
CHARANIA et al.: ANALYSIS AND DESIGN OF ON-CHIP DECOUPLING CAPACITORS 657
Fig. 23. ESR for hybrid decaps and an nMOS decap.
Fig. 24. Impedance magnitude and normalized impedance magnitude forhybrid decaps and an nMOS decap.
ment is seen with this hybrid structure compared to the nMOS+ RTMOM hybrid. Thus, including an MIM decap as part ofthe hybrid structure is not recommended.
The corresponding ESR, and absolute and normalizedimpedance magnitudes are given in Figs. 23 and 24, respec-tively. A decrease in ESR is seen with both hybrid structurescompared to the nMOS decap since the additional metal layersthat form the MOM decap serve to reduce the overall seriesresistance. Again, following from the effective capacitanceplot, the impedance magnitude of both hybrid decap structuresis lower (by up to 28% in the frequency range considered) thanthat of the standard nMOS decap.
Lastly, the dielectric current of the nMOS + RTMOMhybrid structure was observed to be negligibly higher thanthe nMOS decap alone. Therefore, the boost in effectivecapacitance is obtained at essentially no cost in leakage power.
VIII. SELECTION OF DECAPS
The following guidelines can be used to determine whichdecap structure is most appropriate based on given designconstraints in a 65-nm CMOS technology.
1) Where area is the primary constraint in a design,an nMOS + RTMOM multilayer metal hybrid decapprovides the most area-efficient structure in terms ofeffective capacitance and impedance magnitude. Theseshould be placed in the “whitespace” of the chip.
TABLE VI
SELECTION OF DECAPS BASED ON VARIOUS DESIGN CONSTRAINTS
+ RTMOM∗Area and Standard cell CMOS + RTMOM∗/∗∗power‡ Device whitespace pMOS∗∗∗/A_nMOS∗∗∗∗
Metal whitespace RTMOM∗Alternating multilayer metal decaps provide similar capacitance.** RTMOM can be omitted where there is dense metal routing present.*** Where power is more important than area.**** Where area is more important than power.‡ Gating can also be used to reduce power consumption.
2) Within standard cells, CMOS decap + RTMOM hybridstructures should be used. In all other areas ofthe chip, including where active circuitry is present,RTMOM structures should be placed to provide decapwhile simultaneously satisfying metal fill requirements.The RTMOM structures can be formed using all avail-able metal layers from Metals 2–7.
3) The alternating interdigitated multilayer metal decapperforms similarly to the RTMOM decap in terms ofarea efficiency with respect to effective capacitance andimpedance, and can replace the RTMOM decap. Thealternating structure does, however, have a greater layoutcomplexity.
4) Where both area and dielectric leakage power are ofconcern, the pMOS and A_nMOS decaps provide a goodtradeoff between area efficiency and leakage (∼70% lessleakage for ∼10% more area compared to the nMOSdecap), with the A_nMOS performing slightly better interms of area efficiency at frequencies >10 GHz andthe pMOS having slightly lower leakage. Thus, whereleakage is an additional constraint to area, an A_nMOS+ RTMOM hybrid or pMOS + RTMOM hybrid decapshould be used in the whitespace.
5) Where leakage power is the primary constraint in adesign and must be minimized at the cost of area, thethick oxide nMOS decap is the most desirable structureproviding negligible leakage current at the cost of ∼60%of area. Thus a thick oxide nMOS + RTMOM decaphybrid should be used in the whitespace and a thickoxide CMOS + RTMOM hybrid should be used withinstandard cells.
6) Gating decaps can further minimize leakage current byisolating the decaps when not required. The magnitudeof the overall savings in power, is based on the specificcircuit to which the decaps are attached. Gating canbe considered as an additional means of saving leakagepower.
658 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 21, NO. 4, APRIL 2013
7) For noise components in the range of 100 MHz to30 GHz, an L of ∼3 μm should be used for MOS-baseddecaps.
The decaps recommended for various design constraints aresummarized in Table VI.
IX. CONCLUSION
This paper characterized various decap structures in a typi-cal 65-nm CMOS process, and provided a set of guidelinesto enable the most optimal decap design selection for thegiven chip constraints. Standard decap structures includingMOS-based structures and metal-based structures were stud-ied. MIM decaps were also studied as they are a commonprocess option. Postlayout simulations showed that nMOSdecaps were the most area-efficient decap type with respectto overall decap capacitance and impedance, while pMOS andA_nMOS decaps provided a good compromise between areaand leakage currents. It was further shown that multilayermetal decap structures provide an attractive alternative thatcan be placed in areas of the chip with existing circuitry whileadditionally satisfying metal-fill requirements.
This paper also investigated the optimal sizing for MOS-based decaps. It showed that a gate length of ∼3 μm was themost optimal choice in the given technology studied.
Hybrid decap structures that combine more than a singledecap type were further found to provide an additional boostin decap capacitance compared to the corresponding individualstructures. For example, an nMOS + RTMOM hybrid decaphad ∼25% greater capacitance than an nMOS decap.
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Tasreen Charania (SM’00) received the B.A.Sc.degree (Hons.) in chemical engineering in 1998,and the M.A.Sc. degree in electrical engineering in2001 from the University of Waterloo, Waterloo,ON, Canada, where she is currently pursuing thePh.D. degree in electrical engineering.
She was with Nortel Networks, Ottawa, ON, whereshe was involved in semiconductor fabrication. Shewas also with Sirific Wireless Corporation, Waterloo,as a Layout Design Engineer, and MBM Law asa Patent Specialist. Her current research interests
include power supply noise measurement and mitigation on CMOS integratedcircuits.
Ms. Charania was a recipient of the Natural Sciences and EngineeringResearch Council of Canada Postgraduate Scholarship, the Ontario GraduateScholarship, the Ontario Graduate Scholarship in Science and Technology,the President’s Graduate Scholarship, the Provost Women’s Doctoral EntranceAward, the Faculty of Engineering Award, and three Nortel Networks Recog-nition Awards.
Ajoy Opal (S’86–M’88) received the B.Tech. degreefrom the Indian Institute of Technology, New Delhi,India, in 1981, and the M.A.Sc. and Ph.D. degreesfrom the University of Waterloo, Waterloo, ON,Canada, in 1984 and 1987, respectively.
He was with Bell-Northern Research, where hewas involved in the research on analog circuit sim-ulation from 1989 to 1992. Since 1992, he has beena Professor with the Department of Electrical andComputer Engineering, University of Waterloo. Heis involved in the research on the simulation of
analog and mixed digital–analog circuits, such as switched-capacitor,switched-current, and oversampled sigma–delta modulators. His currentresearch interests include circuit theory and filter design.
Manoj Sachdev (F’97) received the B.E. degree(Hons.) in electronics and communication engineer-ing from the University of Roorkee, Roorkee, India,and the Ph.D. degree from Brunel University, Mid-dlesex, U.K.
He has been a Professor with the Electrical andComputer Engineering Department, University ofWaterloo, Waterloo, ON, Canada, since 1998. He iscurrently the Department Chair with the Universityof Waterloo and holds the University of WaterlooResearch Chair. He was with Semiconductor Com-
plex Ltd., Chandigarh, India, from 1984 to 1989, where he designed CMOSintegrated circuits. From 1989 to 1992, he was with the ASIC Division, SGS-Thomson, Milan, Italy. In 1992, he joined Philips Research Laboratories,Eindhoven, The Netherlands, where he researched various aspects of VLSItesting and manufacturing. He has written five books, two book chapters, andhas contributed to over 150 technical articles in conferences and journals. Heholds over 25 granted and pending U.S. patents. His current research interestsinclude low-power and high-performance digital circuit design, mixed-signalcircuit design, and testing and manufacturing issues of integrated circuits.
Dr. Sachdev was a recipient of several awards, including the EuropeanDesign and Test Conference Best Paper Award in 1998 and VLSI TestSymposium Best Panel Award in 2004, and the corecipient of the InternationalTest Conference Honorable Mention Award in 1999 and the InternationalSymposium on Quality Electronics Design Best Paper Award in 2011.
