Analysis of a microchannel interconnect basedon the clustering of smart-pixel-device windows

D. R. Rolston, B. Robertson, H. S. Hinton, and D. V. Plant

Adesign analysis of a telecentric microchannel relay system developed for use with a smart-pixel-basedphotonic backplane is presented. The interconnect uses a clustered-window geometry in whichoptoelectronic device windows are grouped together about the axis of each microchannel. A Gaussian-beam propagation model is used to analyze the trade-off between window size, window density,transistor count per smart pixel, and lenslet f-number for three cases of window clustering. The resultsof this analysis show that, with this approach, a window density of 4000 windows@cm2 is obtained for awindow size of 30 µm and a device plane separation of 25 mm. In addition, an optical power model isdeveloped to determine the nominal power requirements of a 32 3 32 smart-pixel array as a function ofwindow size. The power requirements are obtained assuming a complementary metal-oxide semicon-ductor inverter–amplifier and dual-rail multiple-quantum-well self-electro-optic-effect devices as thereceiver stage of the smart pixel. r 1996 Optical Society of America

1. Introduction

Future digital systems, such as asynchronous trans-fer mode switching networks and massively parallelprocessing machines, will have large printed-circuit-board- 1PCB-2 to-printed-circuit-board connectivityrequirements in order to support the large aggregatethroughput demands being placed on these systems.1Current electronic interconnect technology may notbe capable of supporting both the connection densi-ties and the bandwidth required in these systemsbecause of connector limitations at the PCB-to-backplane interface.2 Two-dimensional, free-spaceoptical interconnects represent a potential solutionto the needs of these high-speed, connection-inten-sive digital systems. Faster clock rates associatedwith CPU’s and memory3 and increased parallelismin computer architectures are two features of futuresystems that may benefit from the attributes offree-space optics. When implemented at the PCB-to-PCB level in the form of a photonic backplane, forexample, this technology can potentially provide

When this work was performed, the authors were with theDepartment of Electrical Engineering, McGill University, Mon-treal, Quebec, Canada H3A 2A7. H. S. Hinton is now with theDepartment of Electrical and Computer Engineering, Universityof Colorado, Boulder, Colorado 80309.Received 15 June 1995; revised manuscript received 16 October

1995.0003-6935@96@081220-14$06.00@0r 1996 Optical Society of America

1220 APPLIED OPTICS @ Vol. 35, No. 8 @ 10 March 1996

greater connectivity at higher data rates than cur-rent or future electrical backplanes.4Numerous optical schemes that offer improve-

ments to the metal-based interconnect have beenproposed and demonstrated. Aboard-to-board opti-cal interconnect built by Sakano et al.5 is a prototypeinterconnect that uses bulk optics and light-emittingdiodes to connect 64 processors in a three-dimen-sional mesh. A board-to-board interconnect thatuses diffractive optics and light-emitting-diode ar-rays, built by Dhoedt et al.6 is an example applied tomassively Parallel Processing MPP machines. Inanother system byRedmond and Schenfeld,7 vertical-cavity surface-emitting-lasers and microlens arrayswere used to interconnect cache memory and proces-sors. Vertical-cavity surface-emitting lasers andmetal-semiconductor-metal detectors used by Plantet al. were used to demonstrate a board-to-boardinterconnection in an electronic backplane chassis.8Finally, work on free-space photonic-switching net-works that used field-effect transistor self-electro-optic-effect devices 1FET-SEED’s2 and complemen-tary metal-oxide silicon (CMOS/SEED’s) by McCor-mick et al.9 and Krishnamoorthy et al.,10 respec-tively, have demonstrated the connection-intensivecapability of free-space optics.In this paper we present an analysis of a novel

microchannel-based interconnection scheme devel-oped for photonic-backplane applications. Figure11a2 illustrates the concept of a photonic backplanethat employs a free-space interconnect scheme, mak-

ing use of previously demonstrated techniques ofthrough-chip interconnects.11 In principle, this ap-proach could be extended to through-board intercon-nects. The alignability of this setup will undoubt-edly determine the practicality of this approach, butfor simplicity this subject is not fully addressed here.Previous study in this area has typically concen-

trated on interconnects in which a single opticalbeam is transmitted along each microchannel.12The system presented here uses an alternative tel-ecentric lenslet arrangement that allows multiplesignal beams to be relayed via each microchannel, asshown in Fig. 11b2. The system’s size and physicallayout are in keeping with the size and the geometryof standard electrical backplanes.13 The most criti-cal parameter of this analysis is the channel orwindow density. This is a measure of the number ofpoint-to-point connections made with regard to thephysical space limitations and will have a significantimpact on the amount of data throughput a singleswitching node or parallel machine can have.The interconnect model presented is designed to

operate with smart-pixel arrays in which each smartpixel is capable of electrical-to-optical and optical-to-electrical conversion of digital data. Thus, as shown

1a2

1b2

Fig. 1. 1a2Concept of a double-sided-boardmicrochannel intercon-nect, 1b2 4-f telecentric relay with clustered windows below eachlenslet.

in Fig. 11b2, each smart pixel contains a cluster ofoptical input–output windows capable of transmit-ting and receiving data via a single microchannel.14In addition to optical-to-electrical and electrical-to-optical conversions, the smart pixel can performhigh-speed processing operations at the backplanelevel, such as address recognition or packet routing.An estimate of the aggregate throughput of such a

system can be established with reference to Fig. 11a2.Consider several boards interconnected with 10 opto-electronic chips per PCB, in which each chip containsa 32 3 32 smart-pixel array 11024 smart pixels2.If each pixel operates at 100 megabits per second1Mbps2, the optical interconnect 1or photonic back-plane2 would support greater than a terabit persecond of aggregate data throughput.In this paper we investigate the optical limitations

of this clustered-window interconnection geometryand the effect that it has on smart-pixel design.The first part of the paper describes a Gaussian-beam propagation model that was used to analyzethe dependence of connection density and transistorcount versus window size. A number of physicaldesign constraints based on lenslet f-number 1 f@#2and wiring layout restrictions are also discussed.The model is then used to analyze three differentwindow-cluster geometries in order to determine anoptimum range of interconnect parameters. In thefinal section, an estimate of the optical power re-quired for a specific receiver design and interconnectlayout is given. For the purposes of this work,multiple-quantum-well 1MQW2 symmetric SEED 1S-SEED2 receivers and modulators were assumed;however, this interconnection geometry may be usedwith any optoelectronic device. A circuit model ofthe optical receiver is used to determine the requiredoptical power as a function of optoelectronic devicesize. This verifies that the operating region, sug-gested by the optical analysis, remains valid withrespect to the optical power required.

2. Interconnection Model

A simple Gaussian-beam propagation model wasused to analyze the performance limits of the clus-tered-window geometry. In considering the opticallayout, several assumptions pertaining to the opticalinterconnect geometry were made in order to limitthe number of variable design parameters and pro-vide a tractable solution. For simplicity, it wasassumed that the optical interconnect consisted of asingle 4-f telecentric optical relay. The windowcluster was defined as a regular M 3 N array ofoptical windows positioned symmetrically about theoptical axis of the microchannel. Each optical win-dow 1the active region of an optoelectronic device onthe surface of a chip2 was square with dimensions ofdv 3 dv, and the separation between optical win-dows, ds, was constant across the cluster. Thecluster dimensions were given by lh 3 lv 1Fig. 22.

10 March 1996 @ Vol. 35, No. 8 @ APPLIED OPTICS 1221

The lenslet substrates were assumed to have zerothickness, and the presence of other optical compo-nents, such as beam splitters, was ignored. A pitchof 25 mm between device planes was chosen inaccordance with standard electrical backplane PCBpitches, thereby setting the focal length f of thelenslet arrays at 6.25 mm. The lenslet facets wereassumed to be square with dimensions of DL 3 DL.In addition, it was assumed that the system operatedat a wavelength l of 850 nm.The 1@e2 beamwaist v0 at a device window and the

1@e2 beam radius at the lenslet facet vb are related bythe Gaussian-beam propagation equation 112. Anyclipping of the Gaussian beam as it passes throughthe lenslet relay will alter its propagation character-istics.15 Thus, to minimize clipping effects and tomaintain the initial propagation conditions, it wasdecided to restrict the beam diameter at the windowsto 3v0 5 dv. Similarly, at the lenslet facet, arestriction that the beam diameter be 3vb wasimposed.With the above geometric description of the inter-

connect, a set of equations that describe the relation-ships between various interconnect parameters wasdeveloped. The Gaussian-beam propagation equa-tion and the 3v assumption for the diameter of the

1a2

1b2

Fig. 2. 1a2 Defining parameters of the interconnect model 1frontview2, 1b2 multiple beams passing through a single lenslet 1sideview2.

1222 APPLIED OPTICS @ Vol. 35, No. 8 @ 10 March 1996

beam at the window and the lenslet used in thisanalysis are

vb 5 v031 1 1lf@pv022241@2, 112

dv 5 2r0 5 3v0, 122

2rb 5 3vb, 132

from which it can be shown that

rb 5dv

231 1 19lf@pdv

22241@2, 142

where rb is the effective beam radius at the lensletand r0 is the effective beam radius at the window.In the case of an M 3 N cluster that has the

dimensions of

lh 5 Mdv 1 1M 2 12ds, 152

lv 5 Ndv 1 1N 2 12ds, 162

the longer side of the cluster will govern the dimen-sion of the square lenslet:

l 5 maxclh, lvd. 172

The lenslet size will therefore be

DL 5 l 2 dv 1 2rb. 182

When Eqs. 112–172 are substituted into Eq. 182, anequation for the lenslet size DL, in terms of windowdimensions dv, window separation ds, and size ofwindow array 1M 3 N2 can be derived:

DL 5 f 1M, N, dv, ds2.

Based on the assumption that routing trace linesout of a cluster on a chip will prevent windows frombeing extremely tightly packed, the parameter dswas related toM, N, and the fabrication restrictionsassociated with the chip technology. Although someoptoelectronic integration techniques, such as solder-bump bonding,16 allow optoelectronics to be placeddirectly above silicon circuitry, thereby slightly alter-ing trace-line routing conditions, the assumptionmade here was that the cluster would be too denselypacked to allow logic to be placed between windowsand that trace lines would be the only featurespresent within the cluster.The separation between windows ds was assumed

to be dependent on only five variables: the size ofthe cluster 1M 3 N2, the trace-line width w, thetrace-line separation s, and the number of metallayers on the chip. The trace-line width and separa-tion were chosen to be 4.2 and 3.2 µm, respectively,exactly double the minimum feature size of metal 3for the 0.8-µm CMOSX Vendor Rules.17 Initially weconsidered the case in which the cluster was square1M 5 N2, in which every window consisted of a two-

terminal device and only one type of metal trace lineon the chip was permitted. The trace lines couldthen be routed to only two of the four sides of thecluster, thereby allowing the window separation inone direction to be close to zero and the windowseparation in the other direction 3Fig. 31a24 to be givenby

ds* 5 Mw 1 1M 1 12s. 192

To produce a more general equation for windowseparation, two metal layers were assumed avail-able; in practice, this would be a more likely case.With this assumption, the terminals of the devices

1a2

1b2

Fig. 3. 1a2 Routing out of a cluster with one metal trace line, 1b2Routing out of a cluster with two metal trace lines 1conceptualdrawing2.

could be routed out on all four sides of the cluster,and Eq. 192 could be divided by two 3Fig. 31b24, giving awindow separation in both directions of

ds 5 1ds*@22 5 3Mw 1 1M1 12s4@2. 1102

This description does not exclude other routingstrategies, but does provide a quantitative methodfor obtaining a window separation that depends onchip layout. Under these conditions, the windowseparation cannot be considered as an independentvariable.One of the more critical parameters that must be

taken into account when determining the connectiv-ity and scalability of a free-space system is thewindow density. In this paper the term windowrefers to the active region of any optoelectronicdevice without specifying whether it modulates,emits, or detects light. In this way, any opticalbit-encoding technique 1dual rail, single rail, etc.2 andany optical fan-in or fan-out can be derived from themore general window density. The window densitywas defined as the number of optical windows perunit cross-sectional area of interconnect; based onthis definition, the window density was given by

WDen 5 MN@DL2. 1112

The f@# is an important parameter that governsthe performance of the optical system and is ex-plored here. In the analysis below we define aneffective lenslet f@#:

f@# 5f

Diameter, 1122

where the diameter is given by the farthest possibledistance between the far edges of two beams passingthrough a lenslet 1using the 3v beam waists definedabove2. The diameter is then given by 1Fig. 42

Diameter 5 2rb1 31lh 2 dv22 1 1lv 2 dv2

241@2. 1132

Fig. 4. Diameters given by the far edges of two beams tocalculate the effective f@#.

10 March 1996 @ Vol. 35, No. 8 @ APPLIED OPTICS 1223

This definition differs from the physical f@# of thelenslet, f@Œ2DL, but is more useful as it refers to theregion of the lenslet through which the light actuallypasses.To obtain the maximum allowable number of

transistors per smart pixel as a function of theinterconnect geometry, the size of the lenslet wasassumed to govern the space available for the process-ing electronics associated with each cluster. Thusthe area of the lenslet defined a footprint for theunderlying electronics. Assuming that a typicalchip layout is highly regular and that the smart-pixel logical cell is replicated across the chip, thelenslet will mark the smallest uniquely specifiedarea that can be associated with any one cluster.The number of transistors is then a function of the

area of the lenslet less the area of the cluster.Although, in principle, transistors may be placedwithin and below the cluster, depending on the typeof technology used,16 it was assumed that this wouldbe a region where trace lines would be most denselypacked and hence void of transistors. It followsthat the number of transistors is given by

TxperCluster 5 1DL2 2 lhlv2TxDensity, 1142

where TxDensity is the average number of transistorsper unit area and is technology dependent. Thetransistor density is highly dependent on the chiparchitecture: the Digital Equipment Corporation’sDEC-Alpha 21064 processor that uses a 0.68 µmCMOS has a transistor density of ,900,000transistors@cm2,18 whereas high-speed switchingchips that employ CMOS LSI may have smallerdensities of ,100,000 transistors@cm2,19 which isdue to the less regular arrangement of logic andregisters. For this analysis, a transistor density of100,000 transistors@cm2 is assumed.The equations derived thus far establish a set of

four parameters from which an initial design of anoptical system and an initial electronic chip architec-ture can be developed. Given the optical intercon-nection model described above, the independentvariables associated with this interconnect designwere window size, cluster size, and, to a certainextent, chip and lenslet technology. In Section 3 aset of boundary conditions for these independentvariables is described.

3. Model Results

For the purposes of this analysis, we assumed that asmart pixel required four windows, of which twowindows served as dual-rail encoded input and twowindows served as dual-rail encoded output. Notethat these assumptions were arbitrary, but wererequired in order to define a practical system andplace useful boundaries on the design.Also note that a 32 3 32 smart-pixel array 11024

channels2 that has four windows per smart pixel willcontain a total of 4096 windows. If we assume thatwe are restricted to a 1 cm 3 1 cm chip because of

1224 APPLIED OPTICS @ Vol. 35, No. 8 @ 10 March 1996

packaging considerations, a window density of atleast 4096 windows@cm2 would be required. Thiswould satisfy at least one of the criteria for theabove-mentioned terabit backplane.Three cases of window clustering were analyzed

with the equations derived in the Section 2. Case 1was a 2 3 1 cluster representing 1 bit of optical dataor half a smart pixel, case 2 was a 2 3 2 clusterrepresenting 2 bits of optical data or a single smartpixel, and case 3 was a 4 3 4 cluster representing 8bits of optical data or four smart pixels 1Fig. 52.These cluster sizes were chosen to be compatiblewith the base-2 electronic addressing and data wordsize of almost all electronic architectures. A squarephysical geometry was also assumed for the clusterbecause of the symmetry in both the x and the y axesof the microchannel. Note, however, that any clus-ter geometry could be used for the cluster, and thesecases were chosen only to illustrate the properties ofthe model.Figure 6 shows a plot of the lenslet size versus

window size and provides a means of relating thesize of the chip to the device windows. For example,a very small window would require a large lensletand as a consequence would require a large chiparea. If case 3 is considered, and a 32 3 32 smart-pixel array is used, a 16 3 16 lenslet array would berequired. Assuming the 1 cm 3 1 cm chip dimen-sions described above for the maximum chip size, thelenslet would be 625 µm, and fromFig. 6, aminimumwindow size of ,30 µm would be required. Notealso that cases 1 and 2 give identical results becauseof the application of Eq. 172.From Fig. 6 it can be seen that the lenslet size

reaches a minimum for a given window size; beyondthis window size the lenslet size begins to increase.Physically this is the point where the beam waist atwindow equals the beam diameter on the other sideof the lenslet. As the window size increases beyondthis point, the beam becomes effectively collimatedon the windows and focused between the lenslets.Because this analysis was constrained to operatewith point sources on the windows, the window sizeat which this maximum occurred, dvMAX, was used todefine an upper limit on the window size. Thisparameter was found by the solution of

d3DL1dvMAX24

d1dv25 0, 1152

where DL is given by Eq. 182. This parameter pro-vides the maximum window dimensions as a func-tion of cluster geometry 1Fig. 72 and illustrates thetrade-off between the cluster size and the windowsize.Figure 8 illustrates how the f@# changes with

window size. This result indicates that the f@# ofthe lenslet is very low for very small window sizes.Although it is advantageous to have small devicewindows in order to minimize device capacitance,

1a2

1b2

1c2

Fig. 5. Specific cluster geometries analyzed: 1a2 half a smartpixel, 1b2 one smart pixel, 1c2 four smart pixels.

because of fabrication limits it may not be possible toproduce a low-f@# diffractive lenslet with high opticalefficiency.To investigate the effect of fabrication limits on

low-f@# lenslet designs, we performed an efficiencyanalysis of the two-broad interconnect shown in Fig.9.20 The optical efficiency of the optical componentsused in this analysis are given in Table 1. Thesystem described in Fig. 9 outlines the relevantfeatures of a modulator-based optical interconnect.It is the optical efficiency of this interconnect that is

Fig. 6. Size of lenslet as a function of window size and clustersize.

used in Section 4 to obtain a maximum optical powerrequired for a 32 3 32 smart-pixel array.In this analysis it was assumed that the intercon-

nect used multilevel diffractive lenslet arrays de-signed with a standard analytic-quantization tech-nique.21 These components are relatively easy toproduce as square, contiguous lenslets in large ar-rays by the use of standard photolithographic tech-niques.The minimum feature size of a multilevel diffrac-

tive lenslet, Tmin, is governed by the number of phase

Fig. 7. Maximum window size permitted as a function of clustersize.

10 March 1996 @ Vol. 35, No. 8 @ APPLIED OPTICS 1225

levels used in the design and the specified f@#.Thus, in order for a particular lenslet to be realiz-able,Tmin must be greater than theminimum featuresize that can be fabricated lithographically, d.Equations 1162–1182 relate these variables to theachievable diffraction efficiency h of a multilevellenslet designed with the analytic-quantizationmethod:

Tmin 5 l31 1 12f@#2241@2, 1162

D # Tmin@d, 1172

h 5 3Dp sin1pD242

. 1182

When this fabrication technique is applied to thelenslet arrays in the optical interconnect describedabove, a plot of the normalized incident opticalpower on a receiver as a function of window size isgiven, assuming a minimum feature size of d 5 0.5µm 1Fig. 102. From this result it can be seen that theefficiency of the interconnect decreases rapidly belowa window size of ,10 µm. It was for this reasonthat the lower bound on the f@# was chosen to be 2.5to ensure that as much light as possible will reachthe receiver. This provided yet another lower boundon window size. Because for small window sizeseach of the three cases considered converged towardthe same point and because lenslet fabrication above,f@2.5 was assumed reasonable in terms of effi-ciency, all the cases were independent of the f@#restrictions for window sizes greater than 10 µm.The transistor count as a function of window size

1Fig. 112 provided a general trend to smart-pixelcomplexity. A density of 100,000 transistors@cm2

was chosen, as discussed above, and no transistorswere permitted under the cluster. From this graphit can be seen that it is more desirable to havesmaller windows if more complex smart-pixel archi-tectures are required. An upper bound for a win-dow size of ,50 µm is assumed if at least 250transistors are required per smart pixel.22The window-density figure 1Fig. 122 provided the

Fig. 8. f@# as a function of window size and cluster size.

1226 APPLIED OPTICS @ Vol. 35, No. 8 @ 10 March 1996

largest insight into the optimum clustered-windowgeometry. Because high window densities are nec-essary to satisfy connection-intensive systemswithincertain physical sizes, there exists a definite advan-tage to larger clustering. Case 3 has a significantadvantage in terms of window density over the othertwo cases, andmore importantly, a density of at least4096 windows@cm2 can be achieved with moderatelysmall windows of ,30 µm.One of the problems that will affect the perfor-

mance of free-space microchannel relays is the sensi-tivity of these systems tomisalignment. Even small

Fig. 9. Two-board modulator-based optical interconnect 1seeTable 1 for the definitions of the optical elements used2.

translational and rotational errors can drasticallyreduce the interconnect efficiency and increase thelevel of optical cross talk between neighboring opti-cal communication channels.For simplicity, it is assumed that the lenslet arrays

are accurately prealigned with respect to the smart-pixel arrays. The effect of a translational or arotational misalignment can therefore be deter-mined, to a first approximation, by ignoring diffrac-tion effects and assuming that all the light incidentupon a particular lenslet facet is directed into thecorresponding device window. To illustrate this, letus consider the simple case of a single Gaussianbeam of 1@e2 radius, vb, incident upon a squarelenslet facet of dimensions DL 3 DL, as shown in Fig.131a2. If the beam is misaligned by a distance1Dx, Dy2, the amount of light coupled into the devicewindow, defined as the coupling efficiency CE, isgiven by

CE1Dx, Dy2 5 erf 12DL@2 2 Dx

k, DL@2 2 Dx

k 23 erf 12DL@2 2 Dy

k, DL@2 2 Dy

k 2 , 1192

Fig. 10. Optical power delivered through the optical system forone receiver, for which the efficiency of the lenslet is dependent onthe f@#. A normalized input power of 1 W is used.

Table 1. Nominal Efficiencies for the Optical Components used in theTwo-Board Interconnect of Fig. 9

Numberin Fig. 9 Optical Element Efficiency

1 Fiber —2 Collimating lens 0.943 Binary-phase grating 0.6794 Risley beam steerer 0.925 Focusing lens 0.946 Lenslet array f@# dependent7 Polarized beam splitter 0.9648 Quarter-wave plate 0.949 Lenslet array f@# dependent10 Transmitter plane 0.3@0.611 Lenslet array f@# dependent12 Receiver plane —

where k 5 vb@Œ2 and erf1z1, z22 is the generalizederror function,

erf 1z1, z22 52

Œp ez1

z2

exp12t22dt. 1202

In the case of a clustered-window geometry, thesituation will be more complex. The effect of theoffset of a particular device window with respect tothe microchannel optical axis must also be included.As a result, the window at the extreme corner of acluster will be the most sensitive to any misalign-ment. For a 4 3 4 window cluster 3Fig. 131b24, thedependence of the coupling efficiency on misalign-ment for the far corner window is given by

CE1Dx, Dy2 5 erf 12DL@2 2 sx 2 Dx

k, Dl@2 2 sx 2 Dx

k 23 erf 12DL@22 sy 2 Dy

k, DL@22 sy 2 Dy

k 2 ,1212

where sx and sy are the offsets and are equal to3@21ds 1 dw2.

Fig. 11. Number of transistors per lenslet as a function ofwindow size and cluster size.

Fig. 12. Window density as a function of window size and clustersize.

10 March 1996 @ Vol. 35, No. 8 @ APPLIED OPTICS 1227

The above analysis may be used to compare thealignment tolerances of a clustered window designwith those of a single window per lenslet geometry.As an example, consider a microchannel relay de-signed to interconnect 4096 windows within a 1 cm31 cm area with a single window per lenslet 1corre-sponding to a 32 3 32 smart-pixel array, as dis-cussed above2. This would require a lenslet dimen-sion of 156.25 µm 3 156.25 µm, with a restriction onthe beam radius at the lenslet factor of 3vb 5 DL.Note also that thesemisalignment tolerances are notspecific to either a telecentric relay or a nontelecen-tric relay. The dependence of coupling efficiency ontranslational misalignment Dx for a relay based on asingle lenslet per window geometry is shown inFig. 14.The relationship between the coupling efficiency

and Dx for a 4 3 4 clustered-window geometry hasalso been explored 3Fig. 131b24. The window densityof WDen 5 4096@cm2 was again used and required alenslet length of DL 5 625 µm. This had an associ-ated window size of dv 5 31.75 µm, a windowseparation of ds 5 16.4 µm, and a beam waist at thelenslet of vb 5 160 µm 1Fig. 22. These parameterswere calculated with the interconnect model de-

1a2

1b2

Fig. 13. 1a2 X–Y misalignment of a single window per lenslet, 1b2X–Ymisalignment of a 4 3 4 cluster per lenslet.

1228 APPLIED OPTICS @ Vol. 35, No. 8 @ 10 March 1996

scribed in Section 2. From this result it can be seenthat the 4 3 4 clustered-window arrangement issignificantly less sensitive to translational misalign-ments than the single lenslet per window geometry1Fig. 142.The above model was also used to estimate the

comparative sensitivity of a clustered-window con-figuration and equivalent single lenslet per devicewindow geometry to rotational misalignments.Again, a 32 3 32 array of smart pixels, each contain-ing four optical input–output windows, and a win-dow density of 4096@cm2 were assumed. Thedependence of the coupling efficiency on f, therotational misalignment about the exact center ofthe smart-pixel array, is shown in Fig. 15 for bothcases. From this result it can be seen that the 4 3 4clustered-window geometry is approximately fourtimes less sensitive to rotational misalignments,assuming that a 90% CE is required.From these two calculations, it is possible to

estimate the translational and the rotational align-ment tolerances required for implementing a PCB-to-PCB data link based on a 4 3 4 clustered-windowgeometry. Assuming that the CE must be keptabove 0.9 to minimize the effect of optical cross talk,a rotational misalignment of less than 1.65° and atranslational misalignment of less than 138 µmmust be obtained. Although a challenge, this is

Fig. 14. Coupling efficiency for a misalignment along the x axisfor a single window per lenslet and a 4 3 4 cluster per lenslet.

Fig. 15. Coupling efficiency for an angular misalignment for asingle window per lenslet and a 4 3 4 cluster per lenslet.

within the capabilities of current optomechanicaltechnology.23 A full diffractive-based analysis of thealignment tolerances of a clustered-window relaywill be the subject of a later publication.

4. Optical Power Model

The parameters developed in the sections aboveprovided optical characteristics and numbers of tran-sistors for a preliminary system design, but stilllacked an estimate of the optical power required.In this section, a simple optoelectronic receiver wastheoretically analyzed and simulated for differentwindow sizes and bit rates to estimate the largestwindow permissible with present-day optical powerlimitations.The design of an optical system is highly depen-

dent on the performance of the optoelectronic re-ceiver electronics. The circuit used in the analysisbelow is based on a MQW S-SEED pair.24 Thetransmitter modulator pair was chosen to be adirectly addressable amplified differential modula-tor with a contrast ratio of 2 to 1 1or 60% to 30%reflectivity, depending on applied bias voltage2.25The modulation of the beams had two states, onestate encoded a logical 1 with high–low beams andthe other state encoded a logical 0 with low–highbeams.Two major constraints affected the design of the

receiver. The first was the speed with which itcould change state and is a function of optical powerand device impedance. The second was the receiversensitivity, a parameter that was dependent on thethreshold of the amplifier. The receiver used in thisanalysis was a CMOS SEED design 1Fig. 162 that waschosen because of its simplicity and the relative easewith which the circuit can bemodeled. The receiverwas a simple open-loop amplifier; it used an indepen-dently adjustable diode clamp totem pole, a S-SEEDbiased at DV 5 7.2 V, and a minimum feature size0.8-µm CMOS inverter–amplifier as the front end ofthe optical receiver.

Fig. 16. CMOS SEED receiver circuit.

The initial analysis considered the amplifier with-out any diode clamps at all; the diode clamps areeasily introduced into the model at the end of thederivation and provide an increased bit rate.26,27For this circuit, the impedance seen at node Vx isalmost purely capacitive. The capacitance con-sisted of the gates of the transistors and the capaci-tances of the MQW’s. The P-i-N photodiodes havean assumed responsivity of 0.5A@W.The lumped parameter model of this circuit is

shown in Fig. 17. The total capacitance at the nodeVx is given by

CT 5 CM1 1 CM2 1 Cgn 1 Cgp, 1222

where CM1 and CM2 are the MQW capacitances andCgp and Cgn are the transistor capacitances. Thetotal current into node Vx that is due to the photocur-rent from the MQW diodes is given by

DIMAX 5 Ip1 2 Ip2. 1232

Because this is a first-order circuit that could bemodeled by a current source in parallel with acapacitance, a constant called the slew rate of thevoltage at the node Vx can be determined:

Slew 5 DIMAX@CT, 1242

where the voltage at the node is linear in time:

DVx 5 1Slew2Dt. 1252

The equations above provided the basis for an expres-sion relating the total optical power required by thesystem to the window size. To introduce windowsize as a parameter, the size of the capacitance wasrelated to the window dimensions by a nominal sheetcapacitance for the MQW of 0.1 fF@µm2:

CM1 5 10.1 3 1021521dv22, 1262

CM2 5 10.1 3 1021521dv22. 1272

The gate capacitance of the transistors was fixed at0.1 pF each. It was assumed that the photocurrentdeveloped in the top and the bottom MQW diodes ofthe transmitter dual rail was in a high–low state and

Fig. 17. Lumped parameter model of the CMOS SEED receivercircuit.

10 March 1996 @ Vol. 35, No. 8 @ APPLIED OPTICS 1229

was given by

Ip1 5 10.5210.621heff2PIN, 1282

Ip2 5 10.5210.321heff2PIN, 1292

where heff is the efficiency of the entire optical path1including the lenslet arrays2 and is related to theefficiency model offered in Section 3 1Fig. 102 and PINis the input optical power associated with a singledual-rail optical link.Because themaximumpeak-to-peak voltage swing

DVswing is fixed 1because of clamping or the MQW’sthemselves2 and the bit rate in bits per second 1bps2 isrelated to Dt, i.e.,

Dt 5 1@bps, 1302

an equation that relates input optical power to bitrate, window size, and voltage swing was derivedwith Eqs. 1222–1302:

PIN 51

0.15heff310.2 3 102152dv

2 1 10.2 3 1021224

3 1bps21DVswing2; 1312

the total power required for a cluster would then be,assuming that half the windows are receivers,

PTOTAL 5 1MN

2 2PIN. 1322

Equation 1322 provides the optical power requiredby an M 3 N array as a function of window size,given a fixed bit rate and voltage swing. The exten-sion to this power equation to incorporate diodeclamps involved confining the maximum swing atthe node to the value of the voltage clamping thediodes; this is provided that the clamping voltage isconfined from 0 V to just above turn-on of the diodes1nominally 0.6 V2. Otherwise, the node Vx will notvary significantly from zero, and the amplifier–inverter would not switch logical states.

5. Optical Power Results

To validate the lumped parameter model of thereceiver circuit discussed in the Section 4, a SPICEsimulation of the circuit was performed and theresults were compared with the equation for slewrate. The slew rate equation 1242 was used to plotthe voltage Vx with an incident optical pulse train asinput and a clamping voltage of 0.6 V; this assumedthat the clamping diode nodes, Vcl1 and Vcl2 were setto zero 1Fig. 162.When the theoretical output 3Fig. 181a24 was com-

pared with the SPICE output 3Fig. 181b24 for the nodeVx, the results were similar. However, because theassumptions made for gate capacitance 1Cgn and Cgp2in the lumped parameter model were estimates, thetheoretical slew rate differed slightly from the simu-lated slew rate. The theoretical slew rate was

1230 APPLIED OPTICS @ Vol. 35, No. 8 @ 10 March 1996

238 3 109 V@s and the SPICE model showed ,386 3109 V@s. This difference simply implies that thegate capacitances assumed for the lumped param-eter model were slightly overestimated. Note alsothat the corresponding simulated output voltage ofthe receiver had a 5-V swing compatible with thedigital electronics of the smart pixel, but, for simplic-ity, it is not shown here.Based on the consistent results obtained above for

the node voltage Vx, the subsequent equations foroptical power versus window size were plotted with ahigh degree of confidence in the validity. The opti-cal power versus window size 3Eqs. 1312 and 13224 andthe total optical power versus window size wereplotted for two bit rates: 51 and 155 Mbps 1Fig. 192.The total optical power was calculated assumingthat 4096 windows are required for a 32 3 32smart-pixel array, as discussed above. The opticalpower versus window size was plotted as a semiloggraph over a large range of optical powers. Again, asmall window size is favorable; however, a windowsize of up to 50 µm is still feasible if a total opticalinput power below 1 W is assumed. A 1-W bound-ary would mark the maximum output power realisti-cally available from present-day diode lasers andfiber delivery systems.

1a2

1b2

Fig. 18. 1a2 Plot of a first-order slew rate for which the lumpedparameter model is used, 1b2 SPICE plot of slew rate for the CMOSSEED receiver circuit.

6. Discussion

In this analysis, a Gaussian-beam propagationmodelwas used to formulate the basic parameters of aclustered-window microchannel relay. The modelincorporated rigid assumptions, such as the 25-mmdevice plane separation and a 3v beam waist tominimize clipping. When several less stringent as-sumptions were used, it was possible to reduce thenumber of independent design variables to two:the window size and the cluster size. The variableparameters were the lenslet size, the window den-sity, the f@#, and the transistor count. It was as-sumed that a preliminary design of an optical inter-connect could be done in which one or more of theseparameters was chosen to be optimized.To provide a meaningful set of data for the above

parameters, several present-day technological limita-tions and definitions were imposed. Issues concern-ing the level of sophistication of the chip and thedefinition of a modulator-based smart-pixel arraywere introduced. The ability to produce low-f@#diffractive microlenses with high efficiencies wasalso considered. These imposed design space bound-aries were used to provide meaningful ranges for thebasic parameters. In addition, a photonic back-plane was used as an example application of themodel in order to illustrate how these basic param-eters were to be interpreted.This first-order analysis did not consider a com-

plex optical path. No analysis was done for thebeam propagating through multiple elements, ex-cept for the efficiency degradation of an exampleinterconnect, and diffractive effects and clippingwere not considered. In addition, optomechanicaltolerancing was not incorporated into the model.However, a justification for the telecentric clusteredapproach in terms of translational and rotationalmisalignmentwas offered. This indicates that thesetolerances were at least three times greater thanthose of a single window per microchannel and thatthese tolerances were feasible. The misalignmentanalysis offered here was used as an argument fortelecentric clustered interconnects, but did not con-

Fig. 19. Minimum optical power required for a single receivercircuit and a 32 3 32 smart-pixel array, given bit rates of 51 and155 Mbps.

clude that this interconnect is less sensitive tomisalignment in all cases.The optical power model was introduced to show

that the range of window sizes being explored in thisanalysis corresponded to acceptable levels of inputoptical power. It was based on a simple CMOSreceiver design and showed that a window range ofup to 80 µm for a 32 3 32 smart-pixel array required,1 W of optical power under ideal operating condi-tions. Assuming a more sensitive receiver, the re-sults obtained with this receivermodel can be viewedas worst case in terms of minimum optical powerrequired. It was also assumed in the developmentof the optical receiver model that the system wouldbe perfectly aligned, and any electrical or opticalcross talk was ignored. These nonidealities woulduniformly increase the amount of optical powerrequired over the entire range of window size; hence,a smaller window would be more appropriate 1Fig.192. This would correspond to a large clustering inorder to satisfy some nominal value of windowdensity 1Fig. 122 and thereby lead to additionalsupport for this type of optical interconnect: largeclusters with small windows.

7. Conclusion

With a microchannel interconnect model, an optimalrange for window size and cluster size with referenceto a telecentric microlens interconnect was deter-mined. The model indicated several parametersthat could be optimized when applied to a photonicbackplane. Specifically, the model investigated theeffect of increasing window size for three cases ofcluster size. It was applied to four primary param-eters: the lenslet size, the f@#, the transistor count,and the window density.The analysis resulted in the lenslet-size param-

eter’s providing an upper bound of ,30 µm on thewindow size. This was necessary so that a 32 3 32smart-pixel array could be implemented within a 1cm 3 1 cm chip area. The derivative of lenslet sizeindicated that a maximumwindow size of 70 µmwasattainable for a 4 3 4 cluster, for which the maxi-mum window size decreased with increasing clustersize. The f@# parameter showed that very low-f@#lenslets are required for small windows. This,coupled with the degradation in efficiency of low-f@#diffractive lenslets, provided a lower bound on thewindow size of ,10 µm for any clustering case.The transistor-count parameter provided the

smart-pixel designer with a maximum number oftransistors associated with one smart pixel, assum-ing a LSI-type chip architecture. Alternatively, itindicated that an upper bound on window sizeexisted if a minimum number of transistors wasrequired per smart pixel. The minimum numberwas chosen to be 250 transistors per smart pixel,which implies a maximum window size of ,60 µmfor any clustering geometry.Finally, the most valuable parameter presented in

this analysis was the window density. A goal of

10 March 1996 @ Vol. 35, No. 8 @ APPLIED OPTICS 1231

1024 channels@cm2 14096 windows@cm22was imposedin order to realize a terabit of aggregate data through-put, as discussed in the introduction. The window-density parameter showed that the number of connec-tions as a function of window size increaseddramatically with only a relatively small amount ofwindow clustering. It also showed that a windowdensity of 4000 windows@cm2 could be obtained witha 4 3 4 cluster of moderately small windows of,30 µm.The optical power model was based on a simple

CMOS inverter–amplifier and a MQW S-SEED forthe receiver. It also used a simplified modulator-based two-board interconnect for the optical path.This provided a necessary feasibility check in termsof the total optical power required for a given bitrate. The optical power model showed that withinthe range of window size explored, the optical powerrequired for the system was feasible in terms of thelimits of present-day laser technology.Using these first-order design parameters, a sys-

tem designer can choose which of these parametersis more important and begin a rigorous optimizationaround that parameter. If all parameter are deemedimportant, a range of window sizes can be deter-mined. With regard to the photonic backplane, thewindow size had lower bounds of 10 and 30 µm thatwere due to the f@# and the window density, respec-tively. It had upper bounds of 30, 60, and 70 µm forlenslet size, transistor count, and maximum windowsize of a 4 3 4 cluster, respectively. With thisanalysis, a first-order design of the system can beaccomplished. This could then lead to a rigorousanalysis of the optical interconnect.Finally, this paper showed that, in principle, a

clustered-window approach per microchannel in afree-space optical interconnect has increased connec-tion density and may offer a potential solution formany connection-intensive computing systems.

This work was supported by the Canadian Insti-tute for Telecommunications Research and the BNR-NT@NSERC Chair in Photonics Systems. In addi-tion, D. V. Plant acknowledges support from theNatural Sciences and Engineering Research Council1Canada2 1OPG01551592, Fonds pour la Formation deChercheure et l’Aide a la Recherche 1Quebec2 1NC-14152, and the McGill University Graduate Faculty.

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