Abstract— Embedded temperature sensors based onproportional-to-the-absolute-temperature (PTAT) currentsources have the potential to lay the foundation for low-costtemperature-aware integrated circuit architectures if they meetthe requirements of miniaturization, fabrication process match,and precise estimation in a wide range of temperatures. Thispaper addresses an analytical approach to the minimum-elementPTAT circuit design capitalizing on the physics-based modelingof the heterojunction bipolar transistor (HBT) structures. It isshown that a PTAT circuit can be implemented on only twocore HBT elements with good accuracy. Derived parametricrelations allow a straightforward specification of the thermalgain at the design stage, which affects sensor sensitivity.Further derived current-to-temperature mapping expresses atemperature estimate based on the measured PTAT outputcurrent. Numerical examples indicate attainable estimationaccuracy of 0.43% in case of a measurement instance taken inthe absence of measurement noise.
Index Terms— Bi-complementary metal–oxide–semiconductor(BiCMOS) integrated circuits, bipolar transistors, heterojunction,temperature measurement.
I. INTRODUCTION
REAL-TIME management of temperature and electrother-mal effects has become an important concern for modern
integrated circuits (ICs) characterized by the ultralarge scaleof the number of circuit elements per silicon unit area, 3-Dpackaging structures, etc. Temperature represents a nonlinearfunction of time and the location on the die. It depends onboth the ambient and the intracircuit power dissipation, whichleads to the emergence of strong hotspots at certain IC nodeswhere the power density is high [1]. Embedded temperaturesensors and thermal compensation circuits are seen as one ofthe essential means to realize low-cost temperature-aware ICarchitectures with the built-in self-test and runtime configu-ration capabilities. Information on temperature distribution at
Manuscript received May 6, 2012; revised October 11, 2012; acceptedOctober 17, 2012. Date of publication December 28, 2012; date of currentversion January 31, 2013. This work was supported by the National ResearchFoundation of South Africa under Grant UID:74041. Recommended forpublication by Associate Editor S. Ankireddi upon evaluation of reviewers’comments.
The authors are with the Department of Electrical, Electronic and ComputerEngineering, Carl & Emily Fuchs Institute for Microelectronics, Universityof Pretoria, Pretoria 0002, South Africa (e-mail: [email protected];[email protected]).
Color versions of one or more of the figures in this paper are availableonline at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TCPMT.2012.2226886
tests helps to accomplish the physical design. Digital controlmeans based on the electrothermal models enhance circuitperformance and reliability.
Creation of a simple miniature power-efficient and process-matched on-chip temperature sensor calls for development ofan accurate electrothermal model for a system of transistorelements constituting the sensor circuit. The simplicity require-ment boils down to dc measurements preference to reduce thecomplexity of the measurement setup and to ease integration.The two common approaches to the embedded sensor designcapitalize on differential transducers and the proportional-to-the-absolute-temperature (PTAT) current sources [2]. Thedifferential schemes are known for their sensitivity to thetemperature variations across the IC surface. A number ofrecent works consider differential transducer implementationsbased on at least three bipolar junction transistors (BJTs) [3]–[5]. This class of sensors lacks unification due to their depen-dence on the corresponding IC area layout (and location of thehotspots relative to the transducers). The PTAT current sourcesrepresent highly integrated combinations of BJTs [6]–[8] orfield-effect transistors (FETs) [9]–[12], the output current ofwhich is PTAT at the sensing element location. A related butless common temperature measurement principle was reportedin [13] where PTAT forward voltage drop was measured acrossa Schottky diode. FET-based sensor circuit variants are morewidespread due to the CMOS process standardization, lowerpower consumption, and self-heating avoidance, though theirPTAT accuracy might be inferior in comparison with the BJT-based design. The core of the classic PTAT source consistsof two transistors with distinct transconductance nominals(achieved by using different-size emitter areas in case ofBJTs). Having different physical structures, the transistorsare likely to be susceptible to the process variations andmismatching thermal trends of all main parameters, whichlimits output precision against design expectations. This isexacerbated by a reliance of the sensing circuit theory onthe over-simplified electrothermal models of the componenttransistors which are a poor match to the existing fabricationprocesses. Finally, both PTAT and differential sensors aretraditionally powered by a constant current source, leavingout the voltage supply option discussions in most works onthe topic.
This paper is dedicated to the modeling of the heterojunctionbipolar transistor (HBT) based PTAT current source circuits
GOLOVINS AND SINHA: DESIGN OF PTAT CURRENT SOURCES AND TEMPERATURE SENSORS 263
in a wide range of operating temperatures (in contrast torelatively small temperature ranges reported). The principaldifference from other related findings reported in the literatureis adoption of the realistic physics-based HBT model, i.e.,the high current model (HICUM) [14]. This model featuresbipolar transistor’s inherent scale current and transconductancevariation with temperature and addresses the self-heating effectthat leads to thermal instability and breakdown at high currentdensities [15]. The biasing scheme design is closely related tothe electrothermal model of the transistor. This paper deducesPTAT circuits of a simple minimum-element structure to serveas a temperature sensor core. It presents recommendationsand closed-form analytical relations describing the parameterselection to yield temperature estimates based on the PTAToutput measurements, which is supposed to be followed bythe analogue-to-digital conversion for postprocessing. As theemphasis is on analytical modeling versus a complete sensorcircuit design, the performance metrics feature modeling preci-sion error rather than the commonly adopted sensor sensitivity.
This paper is organized as follows. Section II describes aPTAT output current law in a general formulation. Section IIIhighlights theoretical specifics of the temperature-domainHBT modeling accompanied by an illustrative example.Section IV deals with derivations of the analytical relationsthat serve for the electrothermal characteristics prediction.A closed-form mapping from the measured voltage/current inthe load to the corresponding temperature estimate is solicited.Section V presents several numerical examples with the aimto benchmark the proposed analytical electrothermal relationsversus a comprehensive circuit model simulation.
II. GENERAL PTAT DEFINITION
A traditional approach to the PTAT current mirror (CM)design is the underlying Widlar CM circuit architecture inwhich the output current gain variation with temperature canbe controlled by choosing an emitter degeneration resistancenominal in the mirroring current branch [16]. Depending onthe element transistor properties and the essence of the powersupply (biasing current or voltage) for the CM circuit, the skewof the output temperature–current characteristic may exhibitnonlinearities at different sections. This paper considers amathematical detail of the parametric reasons behind nonlin-earities in the thermal dependence of the output current. Animportant CM design consideration is that the transistors areplaced close enough to each other on the die so that theyshare the same temperature, i.e., they are thermally matchedas a result of the integration.
A broader Widlar CM schematic specifies the commoncircuit elements as in Fig. 1 (n–p–n bipolar transistor basedvariant). The design of the circuit relies on the fact that thetransistor Q1 (master or driving transistor) and the transistorQ2 (slave or mirroring transistor) are selected to have matchedcharacteristics (realistic parametric descriptions of the devicemodels applicable to different scenarios will be detailed inSections III and IV). The output current notation is a functionof the voltage difference across the transistors
IOUT = IC2 ≈ (VBE 1 − VBE 2)
RE(1)
Fig. 1. Widlar CM.
where VBE k denotes the voltage across the base-emitter (BE)junction of the kth transistor, and RE is the emitter degen-eration resistor in the Q2 branch, the nominal of which staysinvariant (or approximately invariant) in the temperature rangeof interest (a package and layout engineering task).
Equation (1) is accurate with the exception of the currentthrough the BE junction of Q2 since it is much (at leastseveral magnitude orders) smaller than the transfer current IC2forming the collector output. The classic theory of the bipolartransistor devices deals with collector current dependence onthe biasing voltage through the proportionality of IC k to theexponential term exp
(η VBE k
/VT
)which also contains the
thermal voltage VT and the nonideality factor η (usually atechnology-specific parameter). The thermal voltage is knownby the expression
VT = kBT
qe(2)
where kB = 1.38 × 10−23 J/K, qe = 1.602 × 10−19 C,and T is the temperature of the transistor that is affectedby the ambient material temperature and the internal powerdissipation observed across the transistor junctions.
Assumption of the equality between the matched (equalor strictly proportional) transistor parameters in a wide tem-perature range would advocate a classic thermal propor-tionality formula obtained from (1) by the substitution ofVBE 1 − VBE 2 = η−1VT ln
(IC 1
/IC2
)which has historically
been used for the PTAT design description [8]
IOUT =(
kB
ηqe REln
IC1
IC2
)T . (3)
Equation (3) would represent an ideal law of the outputcurrent proportionality to the temperature under the conditionof the ratio IC 1
/IC2 being constant across a wide range of
temperatures. However, IC 1/
IC2 is a nonlinear characteristicin temperature and is also technology dependent. The nonex-istence of the exact solution of (3) for IC2 in a strict sensemakes the temperature range uncertainty and the technologydependent factor devalue the empirical results of simulationsand experimental tests (as each technology would define adifferent thermal nonlinearity for IC 1
/IC2).
The invention of realistic physics-based transistor modelshas introduced a potential opportunity to find a closed-formunified expression for the PTAT current source output for a
264 IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY, VOL. 3, NO. 2, FEBRUARY 2013
selected transistor technology. In the following description,a HICUM used for the HBT performance prediction will bescrutinized with the aim to describe the PTAT outputs in awide range of temperatures.
III. THERMAL-DOMAIN HBT DESCRIPTION
BASED ON HICUM/L0
A. HICUM/L0 Theoretical Background
The standard HICUM model of Level 0 or 2 details amethod for computation of the Gummel characteristics for aBJT or an HBT, given the set of fixed technology-specificparameters obtained by the parameter extraction procedures.This section emphasizes description of the model part dealingwith temperature dependences that influence the collector out-put (transfer) current and hence should be taken into accountin the derivation of the CM currents.
The equivalent HICUM/L0 large-signal circuit diagram fea-turing the physics-based vertical n–p–n transistor description isshown in Fig. 2. The HICUM Level 0 model is positioned asa variant of the comprehensive physics-based HBT HICUMLevel 2 model, which is lighter in the computational sensedue to the use of an approximation in the high-current regionof operation instead of an iterative solution of the chargecontrol [17]. The presented model is scrutinized only inthe context of the CM design, hence it omits the signalelements governing operating regimes other than the forwarddc biasing of Q1 and Q2, namely, the parasitic capacitances,tunneling, and avalanche effect included in the full HICUM/L2description [18]. The external emitter, collector, and baseresistances are excluded from the consideration to simplifythe analysis. It is assumed that these resistances can be madeleast thermally dependent in the temperature range of interest.Using the design method with the average-in-temperatureresistance absorption, it is possible to neutralize these parasiticinterconnect resistances, which are known to be quiescent-point independent, by the source reference load connected inseries. The internal base resistance, which is dependent onthe carrier mobility in the neutral base region, is taken intoaccount in the benchmarked simulation model, though it has aminor impact on the output current and hence does not partakein the closed-form temperature estimate derivations (in whichit is assumed that VBEi ≈ VBE). The specifics of the HICUMare such that the influence of the internal collector resistanceis taken into account by the model equations for the transfercurrent and is implicitly incorporated in the derivation process.
Thermal dependence of the main parameters in the HICUMis related to the physical quantities such as the intrinsic chargecarrier density and mobility. The intrinsic carrier densitydefines variation of the transfer current with temperature viathe generalized integral charge-control relation’s (GICCR)constant modeling function
c10(T ) = c10 nom
(T
Tnom
)ζ
exp
[VgB
VT
(T
Tnom− 1
)](4)
where c10 nom is the GICCR constant specified for the ref-erence operating temperature Tnom at which most HICUMparameters are extracted (c10 takes the effective emitter area
Fig. 2. Equivalent HICUM/L0 large-signal circuit for the PTAT analysis.The self-heating effect due to the power dissipation across the BE junction issimulated as an iterative feedback.
into account), VgB is the effective base bandgap voltageextrapolated to T = 0 K and ζ ≡ ζCT is the exponentcoefficient obtained via the extraction procedures that modelsmobility of the minority carriers in the base region.
The hole charge, another implicit parameter affecting thetransfer current, has a much more complex functional depen-dence on temperature. Moreover, it is influenced by thevoltages applied to the BE and the BC junctions (VBEi andVBCi respectively). For the sake of the analysis feasibility, VBCi
impact is omitted from consideration because this dependenceis very weak in case of the forward-biased CM circuit elementswith the diode-connected Q1 (i.e., the BC voltage for Q1is zero at all temperatures). Then the transport-related holecharge at low to medium current densities (desirable thermaldrift region for the quiescent point) can be represented by thesum
QpT = Qp 0 + hjE i QjE i + QfT (5)
where Qp0 describes thermal dependence of the zero-bias holecharge, QjEi is the depletion charge which is stored within theBE junction and which is bias point (VBEi) dependent, hjEiis the BE depletion charge weighting factor (an HBT-specificparameter), and QfT is the minority charge across the entiretransistor constituting the forward transfer current that tends tohave more contribution than the hole and depletion charges atmedium to high current densities. Given the interdependencebetween QfT and the transfer current under the conditions ofVBEi > 0 and VBCi = 0, the bias-dependent hole charge isexpressed in the form of the quadratic equation solution as
QpT(T ) = QpT, j
2+
√(QpT, j
2
)2
+ τ0c10 exp
(VBEi
mCf VT
)
(6)
where QpT, j = Qp0+hjEi QjEi, c10 is given by (4), mCf ≡ 1/η
is the nonideality factor, and the low-current forward transittime τ0 is determined as in [19]
τ0(T ) = τ0 nom
[1 + ατ0(T − Tnom) + kτ0(T − Tnom)2
]. (7)
where the HICUM coefficients τ0 nom = τ0(Tnom), ατ0, andkτ0 are obtained via extraction.
The thermal dependence of the zero-bias hole charge,caused by the base width change with temperature, is
GOLOVINS AND SINHA: DESIGN OF PTAT CURRENT SOURCES AND TEMPERATURE SENSORS 265
described according to the formula
Qp 0(T ) = Qp 0 nom[2 − (VDE i(T )
/VDE i nom)zE i
](8)
where Qp0 nom = Qp0(Tnom) is the zero-bias hole charge,VDE inom = VDE i(Tnom) is the diffusion voltage across theBE junction observed at the reference temperature, zEi is theinternal BE grading coefficient, and
VDE i(T ) = VDE i j(T )
+2VT ln
(0.5+0.5
√1+4 exp[−VDEi j(T )
/VT ]
).
(9)
Here
VDEi j(T ) = VDEi j nomT/
Tnom − mgVT ln(T/
Tnom)
−VgBE(T/
Tnom − 1) (10)
is the auxiliary voltage which depends on the derived HICUMparameters: VgBE is the effective BE bandgap voltage extrap-olated to T = 0 K, mg is the bandgap voltage coefficient, andVDEi j nom = VDEi j(Tnom).
The BE depletion charge in (6), observed at a given biasVBEi > 0, is described as
QjEi(T ) = CjEi 0 nomV zEiDEi nom
(1 − zEi) V zEi−1DEi (T )
×[
1 −(
1 − VBEi
VDEi(T )
)1−zEi]
(11)
where CjEi 0 nom is the internal BE zero-bias depletioncapacitance at T = Tnom.
B. Thermal-Domain HBT Simulation Based on HICUM/L0
For convenience of the analysis scrutiny, each major model-descriptive stage outlined by (4)–(11) is accompanied bynumerical examples of the selected technology. The numericalevaluation of the HICUM/L0 transistor model was done inaccordance with the stable computation methods defined inthe HICUM/L2 manual [18].
In our examples, we refer to the HICUM reference dataextracted from the IBM 5HP technology node, part of which islisted in Table I [20]. Here, only the parameters that influencethe subsequently presented CM derivations are specified (shortlist). To see the rest of the parameter set, the reader is advisedto refer to the HICUM/L2 manual [18].
The operating regions of the HBT used in the exam-ple are shown in Fig. 3. Because of the specific linearityrequirement to the CM output and the analytical descriptionlimitations in the PTAT circuit design, the bias-driven device(master HBT Q1) should be set to operate in the low tomedium current region, i.e., below the critical current (IC K )threshold. This is safely ensured via the choice of bias (supplycurrent or voltage) that sets VBE < 0.95 V for temperaturesnot exceeding the reference temperature Tnom. Fig. 3 alsoshows sufficiency of the HICUM/L0 model choice (versusHICUM/L2) for the task of derivation of a CM operatingin the PTAT mode since the HICUM/L0 accurately covers
Fig. 3. Transfer current regions for the IBM 5HP 0.32 × 16.8 μm2 HBT(plotted for the reference temperature).
device behavior in the medium to high current region whilefeaturing realistic models of the thermal variation of transistorparameters.
It is known that the use of HICUM is not recommendedfor the thermal modeling below 250 K unless the modelparameters have been specifically tested for that temperaturerange [18]. On the other hand, 600 K is found to be thehighest temperature mark available in the reported experi-mental data [18], [21]. These figures are chosen to constitutethe boundaries of the operating temperature range in themodeling presented in this paper, i.e., the dynamic range ofthe temperature sensor under design consideration.
Fig. 4 shows the Gummel plot for a variety of voltage-controlled bias settings defining operation at the low andmedium current densities. It can be seen that the higher biassettings characterized by increased power dissipation may
266 IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY, VOL. 3, NO. 2, FEBRUARY 2013
250 300 350 400 450 500 550
10−15
10−10
10−5
T [K]
I C[A
]
VBE
= 0.1 V
VBE
= 0.2 V
VBE
= 0.3 V
(a)
250 300 350 400 450 500 550
10−8
10−6
10−4
10−2
T [K]
I C[A
]
VBE
= 0.6 V
VBE
= 0.7 V
VBE
= 0.8 V
(b)
Fig. 4. IBM 5HP 0.32 × 16.8 μm2 HBTs collector output current atVBC = −3 V. The thermal dependence of the current is shown for theBE voltages in the range of (a) 0.1–0.3 V and (b) 0.6–0.8 V. The curvesplitting at higher temperatures shows the self-heating effect (upper curvebranches) versus the HICUM/L0 model with disabled self-heating (lowercurve branches).
result in a destructive self-heating situation that might lead to adevice breakdown. The self-heating effect becomes a problemat higher operating temperatures and particularly needs to betaken into account in the PTAT circuit design process. Fig. 4sets an upper limit on VBE at the maximum temperature inthe range, which, for the given transistor example, does notexceed 0.5–0.6 V [it will further be illustrated in the biasingscheme discussion for the CM with the constant voltage supply(CVS)]. In the absence of the self-heating effect, this value canbe up to the medium to high current thresholds as in Fig. 3.
The transconductance is revealed to be a problematic para-meter due to its high fluctuation in a wide temperaturerange. Fig. 5 shows that a nearly constant transconductanceassumption is not suitable for the analysis-based PTAT circuitdesign and calls for accurate models to describe the currentthermal variation. The BE voltage has little impact on thetransconductance at the temperatures below the referencetemperature (298 K). At higher temperatures, the bias-induceddifference becomes more pronounced. Furthermore, saturationin the transconductance thermal characteristic, followed by abreakdown as a result of the self-heating, occurs faster if theBE voltage is higher.
The c10(T ) graph Fig. 6 shows that the thermal variationof the scale current is significant—spanning over 14 orders of
250 300 350 400 450 500 55010
20
30
40
50
60
70
80
90
100
T [K]
β
VBE
= 0.5 V
VBE
= 0.6 V
VBE
= 0.7 V
VBE
= 0.8 V
Fig. 5. IBM 5HP 0.32 × 16.8 μm2 HBTs transconductance variation withtemperature for different BE voltage settings (VBC = −3V ). The curvesplitting at higher temperatures shows the self-heating effect (lower curvebranches with a steep descent) versus the model with disabled self-heating(upper curve branches).
250 300 350 400 450 500 550 600
10−30
10−25
10−20
T [K]
c 10[A
⋅ C]
Fig. 6. GICCR constant as a function of temperature (based on Table I data).
magnitude in the chosen temperature range. Hence, (4) playsa vital role in the thermal modelling of any HBT-based circuit.
In contrast to c10(T ), no major thermal variations areobserved in the hole charge (6) which is the second ther-mally dependent parameter affecting the HBT transfer current.The functional dependence of the inverse hole charge on thetemperature has a linearly declining character for a givenBE voltage in the low current region (VBE < 0.4 V). Thisconforms to a low current density case of the charge (5) whenthe minority charge QfT may be omitted from consideration(its influence is negligible). At higher biases, the decline isfaster and deviates from the linear law due to the QfT impactthat complicates analytical description of the transfer current.The latter reason is another factor dictating restriction of thequiescent point’s thermal drift in the low to medium currentregion for the analysis-based PTAT circuit design.
GOLOVINS AND SINHA: DESIGN OF PTAT CURRENT SOURCES AND TEMPERATURE SENSORS 267
IV. CM WITH CVS
A. Output Current Derivation Based on General TransistorModel
In accordance with the historic terminology, we can definetwo major bipolar transistor parameters: the scale currentIS k = IB k exp(−η VBE k
/VT ) and the transconductance
βk = IC k/
IB k , where IB k is the base current (k = 1, 2).Both of these parameters are technology-specific in their func-tional dependence of the temperature and the voltage acrossthe BE junction (bias point) and have no simple analyticaldescription in the modern physics-based transistor models.Before the functional expansion, we can, however, use themas equation parameters to solve the CM circuit.
The CM with the CVS (CM-CVS) circuit is straightforwardin implementation on the die because it does not require aconstant thermally invariant supply current as shown in Fig. 7.The voltage supply nominal conformance to the thermal driftboundaries of the Q1 quiescent point can be ensured by using asimple voltage divider in most scenarios. The set of equationsdescribing the CM-CVS circuit is as follows:
{VCC = (β1 + 1) Rref IB 1 + Rref IB 2 + VBE 1
VBE 1 = VBE 2 + (β2 + 1) RE IB 2(12)
where VCC is the supply voltage.To solve the first equation of (12) for VBE 1, we intro-
duce substitutions V ∗CC = VCC − Rref IB 2 and IB 1 =
IS 1 exp(η VBE 1/
VT ), so that the equation becomes
exp
(η VBE 1
VT
)= −VBE 1 + V ∗
CC
(β1 + 1) Rref IS 1. (13)
The solution of the nonlinear equation having the formpx = c x + d (p > 0, c �= 0) is known to be x =−W (−c−1 p−d/c ln p)/ln p − d/c, where W is the LambertW function [22]. Hence the solution of (13) can be expressedas
The output current can then be found using (16) as
IOUT, cvs = IC2 = β2 IB 2 = β2 IS 2 exp
(η VBE 2
VT
)
= β2 VT
η R0, cvsW
[η R0, cvs IS 2
VTexp
(η (VCC − V0)
VT
)]
= β2
R0, cvs
VT
η
×W
[ρ W
[η
VT(β1 + 1) Rref IS 1 exp
(η
VTVCC
)]]
(18)
where ρ = [R0, cvs/[(β1 + 1) Rref ]]IS 2/IS 1.If the fabricated transistor devices are a good match in
the temperature range of interest, one can, with a reasonableaccuracy, consider that IS 1 ≈ IS 2 = IS and β1 ≈ β2 = β.Taking into account that β >> 1, (18) is simplified into
IOUT, cvs ≈ 1
(RE + β−1 Rref)
VT
η
×W
[ρ W
[η
VTβ Rref IS exp
(η
VTVCC
)]](19)
where ρ = RE/
Rref + 1/(β + 1).
Referring to (3), for smaller Rref nominals, thenonlinearity in the output current’s temperaturecharacteristic is introduced due to the term ln IC 1/IC2 ≈W [ρ W [(η/VT )β Rref IS exp(ηVCC/VT )]], which is dependenton the thermal voltage, the emitter degeneration resistance,and the transistor parameters IS and β, which are thermallydependent in general.
The disadvantages of (19) are related to the necessityof a relatively accurate specification of IS and β. It isalso apparent that the approximation precision depends onthe RE
/Rref ratio: the condition RE
/Rref >> 1
/(β + 1)
must hold to minimize an effect of inaccurate β specifica-tion or a nonnegligent mismatch between Q1 and Q2 whenβ1 �= β2.
268 IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY, VOL. 3, NO. 2, FEBRUARY 2013
B. Output Current Derivation Based on HICUM/L0 Model
In a simplified theoretical representation, a bipolar transistorcan be seen as an ideal translinear element (TE) characterizedby the thermally invariant scale current and the thermallyinvariant transconductance [23]. Such an assumption underliessome of the earlier large signal transistor models, namely,the Ebers–Moll model and its modifications [24] as well asthe broadly used Gummel–Poon model [25]. If a fabricationtechnology could be selected that would allow the transistorparameters to be invariant in temperature, the CM-CVS outputcurrent description in a wide range of temperatures would bestraightforward by (18) or (19).
Modern compact physics-based transistor models explicitlyor implicitly specify the scale current variation with temper-ature, while the transconductance variation with temperaturerepresents a complex functional case the analysis of which ishampered by multiple factors, e.g., self-heating. This paperconsiders a widely adopted implicit HICUM description forthe thermal variation of the scale current [18]. The completenonlinear model of the CM-CVS output current is subjectedto the second-order Taylor series approximation to derive aclosed-form mapping between the measured voltage/currentacross the sensor load and the temperature estimate. Althoughthe transconductance parameter cannot be specified accuratelyover a wide range of temperatures, we will show that theapproximated model provides quite an accurate output currentdescription.
By ensuring the biasing scheme design that the thermal driftof the quiescent point takes place only in the low to mediumdensity current region, the forward transfer current in HICUMis computed as
iTf = c10(T )
QpT(T, VBE)exp
(η
VTVBE
)(20)
where the thermal variation is stipulated predominantly by thefunctional dependence of the GICCR constant c10 (4) (seeFig. 6) while the transport-related hole charge QpT does notexceed in variation one order of a magnitude for a wide rangeof temperatures (see Fig. 8). The complex QpT descriptionand the dependence on the voltage across the BE junctioncall for using a functional dependence approximation: thelinear function of temperature is viewed as a sufficient variantfor our purposes (the CM output current analysis). Let Tminand Tmax denote the boundaries of the temperature range theCM circuit is subject to during operation. The value of thefunction 1
/QpT(T, VBE) decreases with temperature as shown
in Fig. 8, starting from �0 = 1/
QpT(Tmin, VBE max) whereVBE max denotes the beginning of the high current densityregion at T = Tmin which the quiescent point should notcross (in the particular task of the analysis-based PTAT circuitdesign). The thermal drift of the quiescent point of both Q1and Q2 in the CM results in a steady decrease of VBE i withtemperature, which makes the proposed approximation viable:VBE i is seen as being modulated by T (see Fig. 9). The linear1/QpT(T, VBE) approximation can be written as follows:
1/
QpT ≈ �(T ) = (κ T + − κ Tmin)�0
(21)
250 300 350 400 450 500 550 600
4.5
5
5.5
6
6.5
7
x 1012
T [K]
1/Q
[C
−1 ]
↓ 1/Qp0
↓ 1/Qp(T,V
BE)
↓ 1/Qp(T,V
BE= 0.8 V)
↓ 1/Qp(T,V
BE= 0.2 V)
Fig. 8. Inverse transport-related hole charge (solid line set) as a function ofthe temperature and the BE voltage in 0.1 V steps ranging from 0.1 to 0.9 V(based on Table I data). The “+” markers denote the hole and the depletioncharge contribution without the minority charge effect. The dotted line pointsat the zero-bias hole charge boundary. The dashed line corresponds to thethermal drift of the Q1 quiescent point in the CM-CVS circuit built on theconsidered HBT elements.
where = Tmax − Tmin and the coefficient κ > 0 is assignedby means of empirical evaluation (refer to the subsequentexamples).
Under the normal forward biasing operation conditions, theimpact of the BC junction bias on the (reverse) transfer currentcan be neglected in the collector output current computation.Hence
IC = β IS exp
(η
VTVBE
)≈ iTf
≈ c10(T ) �(T ) exp
(η
VTVBE
). (22)
Substitution of the product β IS ≈ c10(T ) �(T ) into (19)clearly shows that inaccurate specification of the transcon-ductance does not have much impact if RE/Rref >>1/(β + 1). This is the main idea behind reduction of thecritical parameter set governing the CM-CVS output currentdescription
IOUT, cvs ≈ VCC
(RE + β−1 Rref)
T
γcvs
×W
[ρ W
[γcvs
T
c10(T ) �(T ) Rref
VCCexp
(γcvs
T
)]]
= VCC
(RE + β−1 Rref)
T
γcvs
×W[ρ W
[(νζ T ζ + νζ−1T ζ−1) exp
(σ
γcvs
T
)]]
(23)
GOLOVINS AND SINHA: DESIGN OF PTAT CURRENT SOURCES AND TEMPERATURE SENSORS 269
250 300 350 400 450 500 550 600
0.3
0.4
0.5
0.6
0.7
0.8
0.9
T [K]
VB
E[V
]
Rref
= 10 Ω
Rref
= 100 Ω
Rref
= 1 kΩ
Rref
= 10 kΩ
250 300 350 400 450 500 550 600
10−4
10−3
10−2
T [K]
I C[A
]
Rref
= 10 Ω
Rref
= 100 Ω
Rref
= 1 kΩ
Rref
= 10 kΩ
(a)
Fig. 9. Biasing characteristics for the diode-connected transistor Q1 whenQ2 is turned off, i.e., IB 2 = 0 (VCC = 0.95 V). Thermal dependence of(a) BE voltage and (b) collector current.
where
γcvs = ηVCCT/
VT = ηqeVCC
/kB, σ = 1 − VgB
/(η VCC)
νζ = η qec10 nom�0 Rrefκ
kB T ζnom
exp
(qeVgB
kBTnom
)
νζ−1 = η qe c10 nom�0 Rref( − κ Tmin)
kB T ζnom
exp
(qeVgB
kBTnom
)
= (κ−1 − Tmin) νζ .
Note that ζ = 0, σ = 1, νζ = 0, and νζ−1 =η qe c10 nom�0 Rref
/kB in a special case of the TEs.
Let I0, cvs=VCC/(RE + β−1 Rref) and fcvs(T )=(T
/γcvs)
W [ρ W [(νζ T ζ + νζ−1T ζ−1) exp(σ γcvs/
T )]]; then (23) canbe expanded for a Taylor series approximation around thepoint T = T0 as
IOUT, cvs = I0, cvs fcvs(T )
= I0, cvs
[
fcvs(T0) +∞∑
k=1
f (k)cvs (T0)
k! (T − T0)k
]
(24)
where f (k)cvs (T ) = dk/dT k fcvs(T ).
Limiting the series by the second order, one can express
fcvs(T ) ∼= fcvs,2 (T )
= fcvs(T0) + d1,cvs(T0)(T − T0)
+d2,cvs(T0)(T − T0)2 (25)
where
d1, cvs(T ) = d
dTfcvs(T ) =
W(γcvs
/T
)
γcvs
×⎡
⎣1+ c2T 2 + c1T + c0
T (νζ T + νζ−1) [W (γcvs
/T ) + 1] (we + 1)
⎤
⎦
(26)
d2, cvs(T ) = 1
2
d2
dT 2 fcvs(T )
= W (γcvs/
T ) (c2T 2 + c1T + c0)
2γcvsT (νζ T + νζ−1) [W (γcvs/
T ) + 1] (we + 1)
×[
2c2T + c1
c2T 2 + c1T + c0− νζ
νζ T + νζ−1
+ (c2T 2 + c1T + c0)
T 2(νζ T + νζ−1) (we + 1)
×(
1
[W (γcvs/T ) + 1]2 − we
we + 1
)](27)
c0 = −σγcvsνζ−1 (28)
c1 = (ζ − 1)νζ−1 − σγcvsνζ (29)
c2 = ζ νζ (30)
we = W[ρW
[(νζ T ζ + νζ−1T ζ−1) exp(σγcvs
/T )
]].
(31)
In a special case of the TEs
d1, cvs(T ) = W (γcvs/
T )
γcvs
×[
1 − γcvs + T
T [W (γcvs/
T ) + 1] (we + 1)
]
(32)
d2, cvs(T ) = W (γcvs/
T0)
2γcvsT[W (γcvs/T ) + 1
](we + 1)
×[
(γcvs + T )2
T 2(we + 1)
(1
[W (γcvs/
T ) + 1]2
− we
we + 1
)− 1
]. (33)
C. PTAT Tangent and the Maximum Thermal Gain
The skew of the output current thermal characteristic aroundthe observation point T = T0 gives an idea of its proximity tothe ideal PTAT law. It also quantifies the thermal gain of theoutput current, i.e., the current increment with the temperaturein the T = T0 region of the characteristic. The skew is
270 IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY, VOL. 3, NO. 2, FEBRUARY 2013
determined by the tangent at T = T0
fcvs, 1(T ) = fcvs(T0) + d1, cvs(T0) (T − T0)
= W (γcvs/
T0)
γcvs
×[(
1 + c2T 20 + c1T0 + c0
T0 (νζ T0 + νζ−1) [W (γcvs/
T0) + 1] (we0 + 1)
)
T
− c2T 20 + c1T0 + c0
(νζ T0 + νζ−1) [W (γcvs/
T0) + 1] (we0 + 1)
]
(34)
where
we0 = W
[ρ W
[(νζ T ζ
0 + νζ−1T ζ−10
)exp
(σ γcvs
T0
)]].
(35)
If the circuit is made on TEs, (34) becomes
fcvs, 1(T ) = W (γcvs/
T0)
γcvs
×[(
1 − γcvs + T0
T0[W (γcvs/
T0) + 1] (we0 + 1)
)
T
+ γcvs + T0
[W (γcvs/
T0) + 1] (we0 + 1)
]
. (36)
D. Temperature Estimate
Given the measured current at the CM-CVS circuit output,IOUT, cvs, one can determine the corresponding temperature.Let T = T − T0; then the temperature estimate can becalculated using the quadratic equation (25)
d2, cvs(T0) T 2 + d1, cvs(T0) T + fcvs(T0) = IOUT, cvs
I 0, cvs(37)
which results in
Tcvs = T0 − d1, cvs(T0)
2d2, cvs(T0)
+
√d2
1, cvs(T0) − 4d2, cvs(T0) [ fcvs(T0) − IOUT, cvs
/I0, cvs]
2d2, cvs(T0).
(38)
To assess the accuracy of a temperature estimate T obtainedusing (38) or other methods, one can adopt the mean relativeestimation error (MREE) metric
ε = 1
Tmax∫
Tmin
∣∣∣∣∣1 − T
T
∣∣∣∣∣
dT (39)
where = Tmax − Tmin, and Tmin and Tmax denote theboundaries of the temperature range the CM circuit is subjectto during operation.
V. NUMERICAL ANALYSIS
A. Biasing Conditions
A simulation example benchmarking the analytical findingsfrom the preceding section represents the CM-CVS circuitFig. 7 based on the IBM 5HP 0.32 × 16.8 μm2 HBT (whichwas described in Section III). The entire circuit is poweredby the supply voltage VDD = 3.3 V, which is standard forthe selected HBT process. The CM-like load circuit consistsof the matched p–n–p transistors with a symmetric emitterconnection and is terminated by Rload = 50 �.
Biasing of the CM-CVS circuit has to be configured toprevent a thermal drift of the Q1 quiescent point into the self-heating region or the high current region. This is achievedby choosing corresponding settings of the supply voltage VCCand the series reference resistance Rref . At low temperatures(close to 250 K), the current through Q1 is very low, hencethe voltage drop across Rref (IB + IC) Rref << VCC, and theentire supply voltage is actually applied to the BE junction. Asthe current through Q1 and Rref grows with the temperature,the BE voltage decreases as a result of an increasing voltagedrop across the series resistor. This trend is shown in Fig. 9,where a linear variation of VBE with the temperature causesan exponential change in the current through the transistor.Smaller Rref values set a higher current through Q1, whichwould also result in a higher mirroring current through Q2 inthe CM-CVS configuration. However, Rref is bounded frombeneath at the high temperatures (near 600 K) as it shouldbe large enough to enable a sufficient drop in the BE voltagepreventing the self-heating [see Figs. 4(b) and 5].
The thermal drift description from the preceding paragraphallows us to draw a recommendation for the biasing schemedesign. VCC is set first, referring to the Gummel characteris-tics of the transistor at the lowest temperature in the range[Fig. 4(b)]: VCC < VBE max, where VBE max denotes a BEvoltage serving as a self-heating or high currents (compres-sion) boundary. At the second step, the Gummel characteristicsat the highest temperature in the range [Figs. 4(b) and 5]allow us to determine Rref > (VCC − V ∗
BE)/
I ∗C, where V ∗
BEand I ∗
C denote an approximately chosen self-heating boundon the quiescent point at the highest temperature. To achievethe best possible CM efficiency, our example features VCC =VBE max = 0.95 V and Rref ≥ 100 �. According to Fig. 9,the self-heating impact becomes observable at Rref = 10 �and smaller values.
B. Circuit Parameters
The impact of the scale current parameter selection isshown in Fig. 10. Smaller reference resistances necessitatemore accurate specification of the scale current parameter formodeling at higher temperatures. This rule is relevant whenthe CM circuit is assembled on the TEs.
The thermal variation model for the normalized CM-CVSoutput current described by (23) and (24) is shown in Fig. 11.The model is parameterized according to the HICUM/L0specifications (Table I). The characteristic appears to be a veryclose match to the PTAT law, especially at higher temperatures.The linearity of the characteristic is only marginally influenced
GOLOVINS AND SINHA: DESIGN OF PTAT CURRENT SOURCES AND TEMPERATURE SENSORS 271
250 300 350 400 450 500 550 6000
0.01
0.02
0.03
0.04
0.05
0.06
0.07
T [K]
f cvs(T
) =
IO
UT /
I 0
↑ Rref
= 100 Ω
↓ Rref
= 1000 Ω
IS = 10−15 A
IS = 10−13 A
IS = 10−11 A
Fig. 10. Scale current influence on the normalized CM-CVS output current,shown for two reference resistances. Rref = 100 � (top set of curves) andRref = 1 k � (bottom set of curves).
by the Q2 emitter degeneration resistor RE. Increase of REyields a higher thermal gain of the output current. However,the magnitude of the CM output current declines since thenormalizing current I0, cvs is inversely proportional to RE, thusreducing the CM efficiency.
C. PTAT Current Output and Temperature Estimation
Simulation-based benchmarking of the analytical relations(19)–(25) leads to a conclusion that the empirical factor κ(parameter reflecting the thermal drift of the hole and minoritycharge) has no major effect on the HBT-based CM outputcurrent prediction Fig. 12. However κ adjusts precision ofthe PTAT skew, which is important to produce accurate high-temperature estimates. A visible deviation of the approximatedcharacteristic from the simulated one takes place only atlower frequencies (below the reference temperature of 298 K);however no major nonlinearities are observed. A TE-basedCM circuit resorting to the constant scale current fixed at thevalue corresponding to T0 = 425 K exhibits a completelydifferent highly nonlinear thermal trend that sets applicationsof the TE and HBT thermal models apart. HBTs are seen asa particularly good match for the PTAT CM-CVS application.The TE-based CM-CVS output current is quite accuratelydescribed by the analytical approximation (23), which is oneof the special cases of the general solution.
The configuration scenario shown in Fig. 13(a) representsa violation of the approximation validity condition deducedearlier: RE
/Rref >> 1
/(β + 1). The result is a relatively large
deviation of the output current’s analytical description from thesimulated characteristic that is observed for both the circuit onTEs and the circuit on HBTs when κ = 0. At the same time,the linearity of the simulated output current is found to bean almost perfect match to the PTAT law at both lower andhigher temperatures. The approximated characteristic almostcoincides with the PTAT tangent at κ = 6. The trends shown in
250 300 350 400 450 500 550 600
0.05
0.1
0.15
0.2
0.25
T [K]
f cvs(T
) =
IO
UT /
I 0
↑ RE
= 10 Ω
↑ RE
= 100 Ω
↑ RE
= 500 Ω
↑ RE
= 2000 Ω
↑ RE
= 10000 Ω
(a)
250 300 350 400 450 500 550 600
0.01
0.02
0.03
0.04
0.05
0.06
0.07
0.08
0.09
0.1
T [K]
f cvs(T
) =
IO
UT /
I 0
↑ RE
= 100 Ω
↑ RE
= 500 Ω
↑ RE
= 2000 Ω
↑ RE
= 10000 Ω
(b)
Fig. 11. Normalized CM-CVS output current at (a) Rref = 100 � and(b) Rref = 10 k �. The “+” markers denote the second-order approximationand the dashed lines denote PTAT tangents drawn at T0 = 425 K.
Fig. 13(b) resemble those in Fig. 12(b), except for the reducedCM efficiency due to a higher Rref nominal. Comparisonof Figs. 12(b) and 13(b) also reveals that the adjustment ofthe reference resistance Rref in the first instance followed byRE selection might result in a bigger thermal gain than theadjustment of only RE having Rref set to the allowed minimumcorresponding to the maximum CM efficiency.
The MREE of the temperature estimate (38) for the fourconsidered CM-CVS operating schemes is listed in Table II.The output currents were produced by simulating the CM-CVScircuit based on the HBTs (HICUM/L0). The circuit based onthe TEs is not applicable to the PTAT current-driven sensordesign. The temperature estimation error does not exceed anaverage of 1.3% across the wide range from 250 to 600 K.The precision of the estimation deteriorates mainly toward thebeginning of the temperature range.
272 IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY, VOL. 3, NO. 2, FEBRUARY 2013
250 300 350 400 450 500 550 6002
3
4
5
6
7
8
9x 10
−4
T [K]
I OU
T[A
]
↓ TE network
↑ HBT network
TE/HBT network model (sim.)Closed−form math. model (κ ≠ 0)2nd order approximationPTAT tangentClosed−form math. model (κ = 0)
(a)
250 300 350 400 450 500 550 600
1
1.2
1.4
1.6
1.8
2
2.2
2.4
2.6
x 10−5
T [K]
I OU
T[A
]
↓ TE network↑ HBT network
TE/HBT network model (sim.)Closed−form math. model (κ ≠ 0)2nd order approximationPTAT tangentClosed−form math. model (κ = 0)
(b)
Fig. 12. CM-CVS output current at Rref = 100 �. (a) RE = 100 �, κ = 2.(b) RE = 10 k�, κ = 6.
D. Comparison Between CM-CVS and CM With ConstantCurrent Supply as a PTAT Current Source
Fig. 14 shows the comparison between the CM circuits withthe constant voltage and constant current supply (CM-CVSand CM-CCS, respectively) which are configured to produceoutput currents in two ranges with the difference constitutingabout two orders of magnitude. The emitter of Q2 in the CM-CCS circuit is loaded with the optimal resistance enabling themaximum thermal gain. Parameters of the CM-CVS circuitare repeated from the preceding section. The mirrored currentbranch in both types of circuits is powered by VDD = 3.3 V.For comparative purposes, Fig. 14 shows output currents ofthe CM-CVS with the voltage supply from an ideal sourceVDD = VCC = 0.95 V and from a voltage divider connectedto the standard VDD = 3.3 V.
250 300 350 400 450 500 550 600
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6x 10
−5
T [K]
I OU
T[A
]
↓ TE network
↑ HBT network
TE/HBT network model (sim.)Closed−form math. model (κ ≠ 0)2nd order approximationPTAT tangentClosed−form math. model (κ = 0)
(a)
250 300 350 400 450 500 550 600
4
5
6
7
8
9
10
x 10−6
T [K]
I OU
T[A
] ↓ TE network
↑ HBT network
TE/HBT network model (sim.)Closed−form math. model (κ ≠ 0)2nd order approximationPTAT tangentClosed−form math. model (κ = 0)
(b)
Fig. 13. CM-CVS output current at Rref = 10 k�. (a) RE = 100 �, κ = 6.(b) RE = 10 k�, κ = 3.
TABLE II
MREE BY THE THERMAL SENSOR BASED
ON THE CM-CVS CIRCUIT
Circuit ParametersTemperature MREE
Rref RE
100 �100 � 1.13%10 k� 1.30%
10 k�100 � 0.43%10 k� 0.95%
For all current ranges, the CM-CVS circuit exhibits betterPTAT linearity and much higher thermal gain of the outputcurrent than the CM-CCS circuit. As pointed out in thepreceding section, variation of Rref (primary circuit parameter)and RE (secondary circuit parameter) can yield an even higherthermal gain than shown in the figure.
GOLOVINS AND SINHA: DESIGN OF PTAT CURRENT SOURCES AND TEMPERATURE SENSORS 273
250 300 350 400 450 500 550 600
2
3
4
5
6
7
8
9x 10
−4
T [K]
I OU
T[A
]
PTAT with ideal current supply ( IIN
= 1 mA, RE
= 42 Ω)PTAT with ideal voltage supply ( V
DD= 0.95 V, R
ref= 100 Ω, R
E= 100 Ω)
PTAT with voltage divider supply ( RD1
= 30 Ω, Rref
= 100 Ω, RE
= 100 Ω)PTAT with voltage divider supply ( R
D1= 300 Ω, R
ref= 100 Ω, R
E= 100 Ω)
(a)
250 300 350 400 450 500 550 6003
4
5
6
7
8
9
10x 10
−6
T [K]
I OU
T[A
]
PTAT with ideal current supply ( IIN
= 12.5 μA, RE
= 3.36 kΩ)PTAT with ideal voltage supply ( V
DD= 0.95 V, R
ref= 10 kΩ, R
E= 10 kΩ)
PTAT with voltage divider supply ( RD1
= 300 Ω, Rref
= 10 kΩ, RE
= 10 kΩ)PTAT with voltage divider supply ( R
D1= 3 kΩ, R
ref= 10 kΩ, R
E= 10 kΩ)
(b)
Fig. 14. CM-CVS versus CM-CCS at two output current ranges.(a) 200–900 μA in case of Configuration I. (b) 3–10 μA in case ofConfiguration II. The dotted lines denote PTAT tangents.
Design of the voltage divider necessitates RD 1 << Rrefmaintaining a stable VCC voltage across the range of tem-peratures. This condition can easily be fulfilled by setting alarger Rref at the expense of a reduced CM efficiency [as inFig. 14(b)].
VI. CONCLUSION
Analytical derivations presented in this paper showed thatimplementation of an IC-based PTAT thermal sensor is possi-ble with only two HBTs joint into the Widlar CM network andsharing the same ambient temperature. The PTAT thermal gainof the CM circuit powered by the CVS is higher than the gainof the CM circuit powered by the CCS. The CM-CVS solutionproduces an output current in good conformance to the PTATlaw. The CM-CVS output current can be described using anaccurate closed-form expression based on the HICUM physicsprinciples featuring realistic thermal dependences of the mainHBT parameters. Devised approximations substantially limitthe number of HICUM parameters describing the output of
the PTAT circuit model. Thus, the temperature sensor designin the technology dependent CM-CVS circuit variant is rep-resented by only a few analytical relations. Simulation-basedverification of these relations on the IBM 5HP technologynode example established 0.43% achievable accuracy of thetemperature estimates from the PTAT circuit output in thetemperature range from 250 to 600 K.
The presented CM structure and the corresponding analyt-ical methods could also form a theoretical foundation for theanalog thermal compensation circuit design.
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Eugene Golovins (S’07–M’09–SM’11) received theB.S. and M.S. degrees in electrical and computerengineering from Riga Technical University, Latvia,in 2002 and 2004, respectively, and the Ph.D. degreein electrical engineering from the University of CapeTown, Cape Town, South Africa, in 2009.
He held various Research Assistant, TeachingAssistant, and Temporary Lecturer positions from2003 to 2010. He is currently a Post-Doctoral Fellowwith the Carl & Emily Fuchs Institute for Micro-electronics, University of Pretoria, Pretoria, South
Africa. He has authored a book and over 25 publications in peer-reviewedjournals, and international and regional conferences. His research is focusedon millimetre-wave and microwave integrated circuits. His current researchinterests include wireless communication systems and networks, includingbut not limited to baseband digital signal processing, radiowave propagation,channel modelling, cognitive, and adaptive system design.
Dr. Golovins is the Specialist Editor (Communications and Signal Process-ing) of the South African Institute of Electrical Engineers (SAIEE) AfricaResearch Journal. He received the Best Ph.D. Thesis Award in the Faculty ofEngineering and the Built Environment, University of Cape Town.
Saurabh Sinha (S’99–M’01–SM’10) receivedthe B.E. (cum laude), M.E. (cum laude), andPh.D. degrees in electronic engineering from theUniversity of Pretoria, Pretoria, South Africa, in2001, 2005, and 2008, respectively.
He is a Registered Electrical Engineer, aResearcher, and an Educator. He is currently anAssociate Professor with the University of Pretoriaand the Leader of the Electronics and Microelec-tronics Group, Carl & Emily Fuchs Institute forMicroelectronics, where he teaches at the under-
graduate and postgraduate levels, conducts research, and performs associatedmanagement tasks. He has authored or co-authored over 50 publications inpeer-reviewed journals and at international conferences. He is the ManagingEditor of the SAIEE Africa Research Journal. He serves as an IndustrialConsultant for Business Enterprises with the University of Pretoria (Pty) Ltd.
Prof. Sinha was a recipient of the SAIEE Engineer of the Year Award in2007. He received the University of Pretoria Laureate Award in 2010.
