ANFIS BASED ENHANCEMENT OF VOLTAGE GAIN WITH FOUR … · 2018-03-15 · In this paper, a novel...

ANFIS BASED ENHANCEMENT OF VOLTAGE GAIN

WITH FOUR-PHASE INTERLEAVED HIGH STEP-DOWN

REGULATOR FOR RPS APPLICATION

1D.N.S. RaviKumar,

2T.K. Hemnath and

3G Nagarajan

1 Assistant Professor, School of EEE, Sathyabama University, Chennai,Tamil Nadu

2 PG student , School of EEE, Sathyabama University, Chennai, India 3 Associate Professor, School of EEE, Sathyabama University, Chennai,Tamil Nadu

Abstract-In this paper, a unique transformer-

less interleaved four-phase high step-down

conversion ratio dc-dc converter with low switch

voltage stress is proposed. In the proposed

converter, the new capacitors switch circuits are

combined with interleaved four-phase buck

converter in order to induce a high step-down

conversion ratio while not adopting an extreme

short duty ratio. supported the capacitive voltage

division, the main objectives of the capacitors

switching circuits within the converter are each

storing energy in the obstruction capacitors for

increasing the voltage conversion ratio and

reducing voltage stresses of active switches.

This will allow one to decide on lower voltage

rating MOSFETs to reduce both switch and

conduction losses, and also the overall efficiency

is consequently improved. additionally, due to

the charge balance of the blocking capacitor, the

converter features automatic uniform current

sharing characteristic of the interleaved phases

while not adding further circuitry or complex

management methods. ANFIS is implemented

for the proposed converter to maintain voltage

stability

Keywords : Low switch voltage stress, high

step-downconverter, uniform current sharing

characteristic

I .INTRODUCTION

Recently the high-performance dc-dc

converters have been needed the increasing high

step-down ratios with high output current rating

applications, like VRMs of CPU boards and

battery chargers, and distributed power systems

[1]-[3]. For non-isolation applications with low

output current ripple requirement, associate

interleaved buck converter (IBC) has received

plenty of attention as a result of its simple

structure and low control complexity.

Fig 1:Convention System

Fig 2:Proposed System

However, within the conventional

interleaved buck converter owing to active

switches devices sufferfrom the input voltage,

high-voltage devices rated higher thanthe input

voltage ought to be applied. High-voltage-

rateddevices are usually with poor

characteristics like highcost, large on-resistance,

large voltage drop, and severereverse recovery,

International Journal of Pure and Applied MathematicsVolume 119 No. 7 2018, 523-532ISSN: 1311-8080 (printed version); ISSN: 1314-3395 (on-line version)url: http://www.ijpam.euSpecial Issue ijpam.eu

523

etc. These limit the switching frequencyof the

converter and impact the power density

improvement.For high-input and low-output

voltage regulation

applications, following higher power density and

higherdynamics, it's required operational at

higher switchingfrequencies [4] which will

increase each switching andconduction losses.

Consequently, the efficiency is

furtherdeteriorated. Also, it experiences an

especially short duty cycle within the case of

high-input and low-output voltageapplications.

To overcome the drawbacks of the

traditionalinterleaved buck converter (IBC), a

new extended dutyratio multiphase topology has

been proposed [5]-[7]. Extended duty ratio

(ExtD)mechanisms are very efficient input

voltage dividers whichreduce the switching

voltage and associated losses.However, it cannot

reach automatic uniform currentsharing

characteristic of the interleaved four-phase and

also thevoltages stress of switches and diodes

devices are remainsrather high.

In this paper, a novel transformer-less

interleaved four phase high step-down

conversion ratio dc-dc converter with low switch

voltage stress is proposed. In these proposed

converter, they are two capacitors are series-

charged by input voltage and parallel-discharged

by a new four-phase interleaved buck converter

for providing the much higher position of step-

down conversion ratio while not be adopting an

extreme short duty cycle. Based on the

capacitive voltage division, the main objectives

of the new voltage-divider circuit within the

converter are each storing energy within the

blocking capacitors for increasing the step-down

it may be the conversion ratio are reducing to

the voltage stresses of active switches.

In these result, its to a proposed

converter topology prossessesto the low switch

voltage stress characteristic. In this will allow

one to choose lower voltage rating MOSFETs to

reduce the each switching and conduction losses,

and also the overall efficiency is consequently

improved. Moreover, it may thanks to the charge

balance of the block capacitors and the converter

features automatic uniform current with sharing

characteristic of the interleaved phases an while

not adding additional circuitry or complex

control methods.

The remaining contents of this paper

could also be made public as follows. First, the

novel circuit topology and operation principle

are given in section II. Then the corresponding

steady state analysis is created in section III to

provide some basic converter characteristics. A

model is the constructed and experimental

results are then presented in section IV for

demonstrating the merits and validity of the

proposed converter. Finally, some conclusions

are offered in the last section.

1.1 ANFIS

ANFIS Systems Since the moment that

fuzzy systems become popular in industrial

application, the community perceived that the

development of a fuzzy system with good

performance is not an easy task. The problem of

finding membership functions and appropriate

rules is frequently a tiring process of attempt and

error.

This lead to the idea of applying

learning algorithms to the fuzzy systems. In

these neural networks, have the efficient

learning with the algorithms,are to be had been

presented as the alternative under automate or to

be support the development of tuning fuzzy

systems.

II .MODES OF OPERATION

The proposed novel transformer-less

interleaved fourphasehigh step-down converteris

derived from two-phase extended duty ratio

interleavedbuck converter in [7]. so as to further

reduce inputcurrent ripple and output voltage

ripple, the converter isdivided into four-phase

little inductors via interleavedoperation to

minimize those ripples. The one cansee that the

proposed converter consists of four

inductors,four active power switches, four

diodes and four capacitors.The main objectives

of the new voltage-divider circuit aretwofold.

First, they are used to store energy as usual.In

these second, based of the capacitive are to be

International Journal of Pure and Applied Mathematics Special Issue

524

voltage division principlesmay be they are used

to reduce the voltage stress of aactive switchesas

well as increasing the step-down conversion

ratio as willbe obvious from later clarification.

For the theoreticalanalysis, it'll be thought-about

that input and outputvoltages are ripple free, and

all devices are ideal. Thesystem is under steady

state and operative in continuousconduction

mode (CCM) with duty ratio being less than

0.5for high step-down conversion ratio purpose.

because the mainobjective is to obtain same

step-down conversion ratio andautomatic current

sharing characteristics can be achievedwhen the

duty cycle is less than 0.5, the converter

operatingduty ratio D < 0.25 and duty ratio D >

0.25 are often controlled by four-phase

interleaved and twophase interleaved theme

respectively;

Fig 3: Switching waveform's

thus, theillustrations for the operating modes of

the proposedconverter and steady-state analysis

are created as follows forthese two cases,

respectively. referring to the gate signalsthe

corresponding operating modes of theproposed

converter once 0 < D < 0.25.

1)Mode 1:During this operation mode, switch

SI is turned on, switch S2, S3 and S4 stay off.

Hence, Diode D1 becomes turned off and diode

D2, D3 and D4 stay on. The corresponding

equivalent circuit it's seen that the hold on

energy of C1 is discharged to CA, L1, and output

load and current iL2,iL3 and iL4 are freewheeling

through D2, D3 and D4 respectively. The VL2, VL3

and VL4 are equal to -Vco, and hence, iLl.iL3 and

iL4 decrease linearly. The voltage across diode DI

is clamped to VCI minus VCA. The voltage across

switch S3 is clamped to VC2 minus VCB and the

voltage across the switch S2 and S4 are clamped

to VCB and VCI severally.

Fig 4.1: Mode 1 Current flow

2)Mode 2, 4, 6, 8:For this operation mode,

switch S1, S2, S3 and S4 are off. The

corresponding equivalent circuit.one will see

that iLl, iL2, iL3 and iL4 are freewheeling through

D1, D2, D3 and D4 severally.

Fig 4.2: Mode 2,4,6,8 Current flow

All VLI, VL2, VL3 and VL4 are capable -Vco, and

hence, iLl, iLl.iL3 and iL4 decrease linearly. During

this mode, the voltage across S, namely VS1, is

capable the difference of VCI and VCA, and VS2 is

clamped at VCB. Similarly, the voltage across S3,

particularly VS3, is equal to the difference of VC2

and VCB, and VS4 is clamped at VCA.

3)Mode 3:During this mode, D2 becomes

turned off while S2 is turned on. The

corresponding equivalent circuit one can see that

the stored energy of CB is discharged toL2 and

output load and sick, iL3 and iL4 are freewheeling

through D1, D3, and D4 severally. The electrical

device L1, L3, and L4 are releasing energy to

output load. The voltage across diode D2 is

clamped to VCB. The voltage across switch S1 is

clamped to VC1 minus VCA and the voltage

across the switch S3 and S4 are clamped to

VC2and VCA respectively.


525


4) Mode 5:During this mode, D4

becomesturned off whereas S4 is turned on. The

correspondingequivalent circuit is one can see

that the stored energy of CA is discharged to L4

and output load and sick, iL1 and iL2 are

freewheeling through D2, and D3 severally. The

inductor L, L2,and L3 are releasing energy to

output load. The voltageacross diodes D4 is

clamped to VCA. The voltage acrossswitch S1 is

clamped to VC1 minus VCA and also the

voltageacross the switch S2 and S3 are clamped

to VCB and VC2minus VCB severally.

Fig4.4: Mode 5 Current flow

5) Mode 7:During this mode, D3

becomesturned off whereas S3 is turned on. The

correspondingequivalent circuit itis seen that the

stored energy of C2 is discharged to CB,L3, and

output load and iL1, iL2 and iL4 are

freewheelingthrough D1, D2 and D4 severally.

All VLl, VL2 and VL4are equal to -Vco, and

hence, iLl, iLz and iL4 decreaselinearly. The

voltage across diode D3 is clamped to VC2minus

VCB. The voltage across switch S3 is clamped

toYin minus VCA + VCB and also the voltage

across the switch S2and S4 are clamped to VCB

and VCAseverally .


III. SIMULATION RESULTS

3.1 EXISTING SYSTEM

Fig 5: EXISTING SYSTEM CIRCUIT

3.1.1 INPUT VOLTAGE AND CURRENT

Fig 6.1


526

3.1.2 OUTPUT VOLTAGE AND CURRENT

Fig 6.2

3.1.3 POWER COMPARISION

Fig 6.3

3.1.4 EFFICIENCY

Fig 6.4

Fig 6: EXISTING SYSTEM RESULTS

3.2 PROPOSED SYSTEM

Fig 7: EXISTING SYSTEM CIRCUIT


Fig 8.1

3.2.2 OUTPUT VOLTAGE AND CURRNET

Fig 8.2


Fig 8.3

3.2.4 EFFICIENCY

Fig 8.4

Fig 8: PROPSED SYSTEM RESULTS

3.3 PROPOSED SYSTEM WITH CLOSE

LOOP


527

Fig 9: PROPOSED SYSTEM WITH CLOSE

LOOP CIRCUIT


Fig 10.1

3.3.2 OUTPUT VOLTAGE AND CURRENT

Fig 10.2


Fig 10.3

Fig 10: PROPOSED SYSTEM WITH CLOSE

LOOPRESULTS

IV. DESIGN CALCULATION

To facilitate understanding the merits

and serve as a verification of the feasibility of

the proposed converter, a prototype with 24V

input,6V output, rating is constructed. The

switching frequency is chosen to be 20 kHz, the

duty ratios of S1, S2, S3 and S4 equal to 0.24

and the corresponding component parameters

are listed in Table. Due to the low switch

voltage stress of the proposed converter, FOUR

power MOSFETs

Inductor design: As mentioned above

specifications, the voltage conversion ratio is

0.06, as calculated. Next, consider the steady-

state inductor currents the rated output current

is calculated to be 20.83A. Moreover, 12% of

the full-load inductor current, i.e., 2.5A, can be

chosen as peak to peak ripples current.

Therefore, the inductor

operating in the CCM is

According to magnetic powder core data

sheet provided of CSC. Using magnetic design

formulas from data sheet, the design ensures that

the inductor operates in the CCM when the load

is greater than 120W. The fact, a 250uH

inductor is chosen in the implementation.

Output capacitor design: As to output

capacitances Co.the peak-to-peak output voltage


528

ripple is considered to beless than 100 mV, then

the output capacitor is

To ensure sufficient energy and hold-up

time areprovided for the post-stage. Therefore,

the output capacitorof 220uF is selected in the

circuit implementation.

These interleaved structure can be

effectively increase to theswitching frequency

all the reduceto the output ripples as wellas the

size of the energy storage inductors. In

theseFour-phase inductor are current to

waveforms of the experimentalresults. Since

output current is sum of four-phase

inductorcurrent, it is obviously that with four-

phase interleavingcontrol, both output current

ripples and switch conductionlosses can be

reduced.

TABLE 1: COMPONENTS

PARAMETERS SPECIFICATION

COMPONENTS SPECIFICATION

Inductor(L1,L2,L3,L4) 100uH

MOSFET switch IRF540

Blocking capacitors (Cl.

C2)

470uF/63V

Input capacitor (C3,C4) 100uF/25B

Output Capacitor (C5) 470uF/50V

V. HARDWARE RESULTS

5.1 HARDWARE

Fig 11: Hardware implementation and circuits

5.2 INPUT VOLTAGE

Fig 12: Input Voltage

5.3 OUTPUT VOLTAGE

Fig 13: Output Voltage

5.4 Reference and output voltage


529

Fig 14:Displaying Reference and Output

Voltage

5.5 PULSE WAVEFORM FOR S1,S2

Fig 15: DSO Output for S1 and S2

5.6 PULSE WAVEFORM FOR S3,S4

Fig 16: DSO Output for S3 and S4

VI . CONCLUSION

In this paper, a novel transformer-less

interleaved fourphasehigh step-down conversion

ratio dc-dc converterwith low switch voltage

stress is proposed. within the proposedconverter,

the new capacitors switching circuits

arecombined with interleaved four-phase buck

converter inorder to induce a high step-down

conversion ratio withoutadopting associate

extreme short duty ratio. based on thecapacitive

voltage division, the most objectives of

thecapacitors switching circuits within the

converter are eachstoring energy in the blocking

capacitors for increasing thevoltage conversion

ratio and reducing voltage stresses ofactive

switches. In the result, these proposed converter

of the topology possesses at the low switch

voltage stress are characteristic. At this will

permit one to choose Power voltagerating

MOSFETs to reduce each switching and

conductionlosses, and also the overall efficiency

is consequently improved.

In addition, of the charge balance of the

blockingcapacitor,with the converter of the

features automatic from the uniform

currentsharing characteristic must be interleaved

on phases withoutaddinga additional circuitry or

complicated management strategies. In

Theoperating principle are steady-state analyses

of the voltagegain are discussed, ANFIS is

implemented for the proposed converter to

maintain voltage stability

.

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