This paper presents a 6 bit, 11 MS/s time-interleaved pipeline A/D converter design. The specification process, from block levelto elementary circuits, is gradually covered to draw a design methodology. Both power consumption and mismatch between theparallel chain elements are intended to be reduced by using some techniques such as double and bottom-plate sampling, fullydifferential circuits, RSD digital correction, and geometric programming (GP) optimization of the elementary analog circuits(OTAs and comparators) design. Prelayout simulations of the complete ADC are presented to characterize the designed converter,which consumes 12 mW while sampling a 500 kHz input signal. Moreover, the block inside the ADC with the most stringentrequirements in power, speed, and precision was sent to fabrication in a CMOS 0.35 μm AMS technology, and some postlayoutresults are shown.
1. Introduction
The ADC design for a multistandard receiver system hasdifferent ways to be developed seeing that both the involvedstandards and the selected architecture face their own draw-backs and implementation issues. A multistandard receiver isnot only a combination of isolated systems operating undereach of the standards, but a system capable of working inan efficient way under those dynamic conditions. To do that,some desired capabilities are reconfigurable computing andthe possibility of sharing and reusing as many blocks aspossible between the operation modes.
The time-interleaved pipeline architecture is frequentlyused to satisfy the previous requirements in high speed,moderate resolution applications [1–3]. Its main advantageis the flexibility, hence different number of time-interleavedbranches and pipeline stages can be enabled/disabled toconfigure variable resolution and sampling frequency, thusleading to a reconfigurable system. Figure 1 shows a 2-channel, 4-stage version of the architecture, which couldprovide 12 bits @ 2.75 MS/s and 6 bits @ 11 MS/s for aGSM/Bluetooth receiver. There are, however, some draw-backs related to the parallelism of time-interleaved pipeline
ADCs, such as channel offset, gain and timing mismatch.A front-end sample and hold (S&H) circuit is the moststraightforward way to avoid timing skew between channels,as shown in Figure 1 [3]. After this S&H block operatingat the full-sample rate of the converter, input signals arenot anymore continuous. Thus, exact sampling momentsof the first pipeline stages over these new ideally constantinput signals are no longer critical. Additionally, if doublesampling techniques are used, changes between samplingand hold phases are identical for both branches, reducingtiming mismatch [4]. Channel offset and gain mismatchare also diminished by reusing amplifiers, making capacitormismatch the most important error source [5].
This work presents a single-standard version of thetime-interleaved pipeline ADC, which meets Bluetoothspecifications while minimizing power consumption andmismatch issues inherent to the architecture. This simplerdesign allows going deeper into the architecture details aswell as preparing it toward a multistandard implementation.In addition, optimization techniques are also applied andexplored looking for an even lower power consumptionin the most elementary circuits of the A/D converter [6].Finally, as an extended version of [7], this work upgrades the
2 International Journal of Reconfigurable Computing
Sub-ADC
Sub-ADC
Sub-ADC
Sub-ADC
Sub-ADC
Sub-ADC
Sub-ADC
Sub-ADC
Digital correction and multiplexingVin
S & H
Figure 1: Time-interleaved pipeline ADC with S&H.
0 1 2 3
(dB
)
Filter maskGSM profile
Bluetooth profile
0
Baseband filter effect over in-band interferences for each standard
Bluetooth minimum sensitivity
GSM minimum sensitivity
−10
−20
−30
−40
−50
−60
−70
−80
−90
−1000
−1−2−3
Central frequency offset ( f − f0) (MHz)
Figure 2: Blocker profiles for 2 wireless standards.
supporting material for GP and the design strategy. Also, newintermediary results are included to show how the completeADC and the S&H work in pre- and postlayout simulations,respectively.
The architecture of the ADC is described in Sections 2and 3 presents some of the blocks in the topology. Next,design process goes down to a lower hierarchy level, todescribe the OTA and comparator designs using GP inSection 4. Simulation results are presented in Section 5 andfinally, conclusions are drawn in Section 6.
2. System and Architecture Level
The first step in the ADC design is to know the selectedwireless standard. Table 1 shows the main Bluetooth spec-ifications affecting the converter. Albeit general for theentire receiver chain, these specifications can be used insystem level simulations and analysis to determine theADC requirements, as can be seen from Table 2. Resolutionspecification is taken from SNR-BER graphs, along withprofiles of channel adjacent interferences (see Figure 2) anddesign margins. Sampling frequency is derived from system
Table 1: Some specifications for Bluetooth standard.
Parameter Value
Frequency band 2400–2483.5 MHz
Constant amplitude modulation GFSK
Number of channels 79
Channel separation 1 MHz
Maximum bandwidth signal 500 kHz
Sensitivity/BER −70 dBm/10−3
Channel time slot length 625 μs
Packet preamble length 4 μs
level simulations taking into account settling times andpreamble length. Furthermore, linearity requirements (DNLand INL) are defined to guarantee a monotonic converter[3].
As seen from Figure 1, there are 2 variables to playwith in a time-interleaved pipeline architecture: the numberof parallel channels and the resolution of pipeline stages.First, the inverse relation between number of channels and
International Journal of Reconfigurable Computing 3
Table 2: Some design specifications for the ADC.
Parameter Value
Power supply 3.3 V
Maximum input bandwidth 500 kHz
Sampling rate 11 MHz
Resolution 6 bits
Full-scale input voltage (VFS) 2Vpp
INL DNL <0.5 LSB <1 LSB
current consumption of the ADC is mainly due to double-sampling techniques and amplifier reuse. Nevertheless, mis-match issues get worse as the number of branches increase.Furthermore, the less bits every stage resolves, the morestages are needed to provide the required total resolution.This leads to a larger power consumption, yet also to looserspecifications for the comparators into the sub-ADC. On theother hand, each additional bit duplicates the number ofcomparators and divides by two the allowed offset in the sub-ADCs of the pipeline stages. Nonetheless, this also requiresless power consuming MDACs (Multiplying DAC) [5].
After this discussion as well as some parametric analysis,an architecture with 2 channels and 2 pipeline stages isproposed in Figure 3. Each parallel pipeline chain operatesat 5.5 MS/s to get a total sampling rate of 11 MS/s. In spite ofthe first 4 bit complete stage, which includes sub-ADC andMDAC blocks, the second 3 bits stage has only the sub-ADCblock. Moreover, from the 7 output bits, only 6 are effectiveand 1 (from the first stage) is used for Redundant Sign Digit(RSD) correction. The previous task is done with additionaldigital circuitry, which also combines and multiplexes thebits towards a single 6-bit digital output word.
The errors within the pipeline stage may appear infour different points, as shown in Figure 4. The sub-ADCnonidealities produce eADC, while circuit limitations of theS&H, DAC, and residue amplifier add eS&H, eDAC and eGcomponents, respectively. Nonetheless, the previous threecomponents are jointly generated by one single block: theMDAC. By doing so, error sources are identified in Figure 4,as well as the circuit performance parameters to eliminatethose undesired characteristics. Some of these parametersare stage resolution, amplifier gain precision, offset voltagesand noise levels, among others [3]. Therefore, taking intoaccount linearity specifications from Table 2 and errorscaling throughout the pipeline stage gains backwards (1),restrictions in similar forms to (2) can be used to determinethe different stage specifications presented in Table 3.
e2T = e2
1 +(e2
G1
)2
+(
e3
G1 ·G2
)2
+ · · · +
(em∏m−1k=1 Gk
)2
, (1)
Gk · eADC < INL
∣∣∣∣∣for stage k
INL=(1/2)·LSBk+1=(1/2)·(VFS/2nk ).
(2)
Table 3: Specifications for pipeline ADC stages.
SpecInput Stage 1 Stage 2
S&H 4 bits 3 bits
Sub-ADC error eADC (bits)Offset voltage voffset (mV)
166
31.253
125
Gain error eG (%) 1.6 12.5
DAC error eDAC (bits) 6
Noise level (dBc) −34 −34 −25
Clock jitter 226 ps
3. Block Level
Going deeper into the architecture, the block details andfunctions are revealed. Accordingly, Figure 5 shows thedetails of the implemented converter. Not only are the analogblocks presented, which consist of S&H, sub-ADCs, MDACs,buffers, and bias circuits; but the digital circuitry is alsounfolded in clock generation, synchronization, combination,multiplexers, and correction circuits. All of these blocks werefull-custom designed and will be introduced in the next linesas well as some of their design considerations.
The S&H circuit is normally implemented with switchedcapacitors (SCs) architectures including an amplifier as theircentral component. Because of the pure capacitive load, thecentral amplifier employs single-stage topologies (OTAs),which are considered the fastest and most power-efficientones [3, 5]. Though the OTA improves S&H performance,its non-idealities, including finite gain and bandwith, marginphase, slew rate, offset and noise, limit the circuit specifica-tions. During operation, it is required only in the hold phase,thus remaining idle when sample action takes place. Thedouble sampling technique takes advantage of this idle timefor using the amplifier. Despite providing samples at doublespeed, power consumption remains almost unchanged sincethe referred power is dominated by the amplifier, whichnormally uses class A architectures that dissipate power evenwhen idle [5].
The S&H schematic is shown in Figure 6, besides thesignals controlling its operation. This S&H employs bottom-plate sampling with switches S7N(P) − S8N(P) and phasesφ1,2e to reduce the component of charge-injection dependingon the input signal. By using the fully differential archi-tecture, the other constant components of error are alsodiminished. In addition, the shared switches S9N(P) withphase φ at the full sample rate fs eliminate the parallelismat the sampling instant, thus making the S&H timing-skewinsensitive.
To specify the S&H block, a minimum sampling capac-itance is first determined from noise (3), mismatch, andparasitic components requirement. Since input signals arestored into only one pair of capacitors at each samplingmoment, and that OTA also adds thermal noise from itsactive devices (vn,amp
2), total output (and input, because itis a unity gain circuit) referred S&H noise is given by (3),where γ is a channel length dependent noise-excess factor. Ifassumed that OTA design guarantees a minimum input noise
4 International Journal of Reconfigurable Computing
3 bits
3 bits4 bits
4 bits
Vin Multiplexing, combination,and digital correction
5.5 MHz
11 MHz
5.5 MHz
S & H
Figure 3: 2-ch x 2-st ADC for Bluetooth standard.
Gk+
+ +
++
+
Sub-ADCk
Vink
eADC eG
resk
−
S & H
DACk
MDACk
eS & H
Voutk
nk bits
eDAC
Gk = 2(nk−1)
Figure 4: Error model for pipeline stage.
Digital part of the ADC
Iref
Iref
Stage 1
Stage 1
Stage 2
Stage 2
SubADC
SubADC
SubADC
SubADC
MDAC
MDAC
Vref+
Vref−Vin−
Clock
Clo
ck g
ener
atio
n
Synchronization
Synchronization
Combinationdigital correction
Combinationdigital correction
Mux Buffer
6 bits
BIASOTAs
Vin+
4 b 4 b14 b
14 b
3 b
3 b
3 b
6 b
6 b6 b
4 b
4 b
4 b4 b
3 b 7 b
7 b
T > G > B
T > G > B
S & H
Figure 5: Detailed block schematic of the ADC.
International Journal of Reconfigurable Computing 5
VCM
CS2P
CS2N
CS1N
CS1P
S1N
S2N
φ2
φ2
φ2
φ2
φ1
φ2
φ1
φ2
φ
+
+ −
−
Vout−
Vout+
Vin−
Vin+
φ2
φ1
φ1
φ1
φ1
φ1
φ2
φ1
φ1
φ2
φ1
φ1
φ2
φ2
φ1e
φ1e
φ2e
φ2e
S3N
S4N
S7N
S8N
S8P
S7P
S4P
S3P
φ
2T = 2/ f s
φ1e
φ2e
S5P
S6P
S6N
S9N
S9P
S5N
S1P
S2P
φ
T = 1/ fs
Figure 6: SC-S&H block architecture.
6 International Journal of Reconfigurable Computing
Bluetooth operation conditions
−VFS/2
Δt
Vin
VFS/2
dV/dt(max)∗ΔtVmax =
dV/dt(max) = VFS2
VFS
1/ fin = 1/(500 kHz)
t
1/ fs = 1/(500 MHz)
2π fin
(a)
Exponentialsettling time
Slewingtime
Settling time for OTA
tSR tGBW
Vout
VFS
T/2t
(b)
Figure 7: Timing details.
level at S&H operation frequency, its component in (3) maybe considered negligible. As result, sampling capacitors arethe dominant thermal noise source in the S&H.
v2n,out = 2γ
kT
CS+ v2
n,amp. (3)
Once the MOS switches are sized in order to avoiddegrading the frequency response of the amplifier or limitingthe finite-bandwidth input signal [5], OTA specifications canbe described. The combination of the S&H eG specificationin Table 3 and expression (4) gives the DC gain (Ao)requirement for the OTA. The transfer function in rightside of (4) is obtained by applying the charge conservationprinciple in circuit of Figure 6 and assuming that no chargeleakage occurs between phases φ1 and φ2, giving (5) whichcan be approximated as in (6) if Cip is considered negligible:
eG = GS&H−ideal −GS&H−real = 1− 11 + (1/Ao)
= 11 + Ao
,
(4)
QS = QH =⇒ Vout = CS ·Vin
CS · (1 + (1/Ao)) + Cip · (1/Ao), (5)
Vout = Vin
1 + (1/Ao). (6)
When single pole model is used for OTA during holdphase, settling time for a step input voltage is determined bythe unity gain-bandwidth product GBW. This assumption,however, is valid only if OTA is designed in such a way thatits frequency response is close to the single pole response.Consequently, there is one dominant low-frequency pole,while the others poles and zeros lie at much higher fre-quencies [5]. As result, (6) can be re-written as in (7),where pA0 = 2πGBW with p beeing the dominant pole.By applying inverse Laplace transformation, expression (8)
is obtained, where tGBW is the exponential settling time forVout:
Vout = Vin
1 +((
1 +(s/p))/Ao)
� Vin · 11 +
(s/pAo
)
= Vin · 1(1 + (s/(2π ·GBW)))
,
(7)
Vout = Vine−2π·GBW·tGBW . (8)
Right side of Figure 7 shows tGBW and tSR times. Becauseof double sampling, S&H output has to settle before the halfclock period to guarantee the sub-ADC and MDAC in thefirst pipeline stage has enough time to sample it. In addition,it is a good practice to reserve 1/3 of the settling time for theslewing and the rest for the GBW limited part [5]. By usingthe latter ideas, to achieve the DNL and INL requirementafter settling, (9) needs to be satisfied if a single pole systemis guaranteed by means of the OTA frequency response, thatis, the unity gain-bandwidth (GBW) specification
Vin-maxe−2π·GBW·tGBW <
12
LSB
=⇒ VFS
2e−2π·GBW·(2/3)(1/2)(1/ fs ) <
12VFS
2N
=⇒ GBW >3
2πln 2 ·N fs,
(9)
SR = Vstep-max
tSR= Vstep-max
(1/3)(1/2)(1/ fs
) = 6 · fs ·Vstep-max.
(10)
Besides the unity gain-bandwidth, the finite OTA outputcurrent to charge and discharge the capacitive load limits
International Journal of Reconfigurable Computing 7
settling time as well. This prevents OTA outputs to followlarge voltage steps faster than its slew rate. By the way, (10)can be used to find the SR requirement taking into accountthat Vstep-max is the maximum step size at the OTA outputand tSR is shown in the right side of Figure 7. Unlike the verycommon assumption Vstep-max = VFS in the literature [3],this work goes deeper into this specification because of thestrong and direct SR effect on power consumption of theOTA. The previous assumption is valid when S&H circuitapplies a reset between consecutive samples. Nevertheless,S&H of Figure 6 behaves as a track and hold topology, theoutput of which tracks its input during the sampling mode.In addition, the acquisition phase has been suppressed touse double sampling technique, and the S&H operates in avery similar way to a zero-order hold. For the latter kind ofsystem, consecutive samples can be very close in amplitudedepending on fs and fin ratios, as shown in the left sideof Figure 7. Thus, it is evident that there is no possibilitythat OTA output has to follow voltage steps as large as VFS.A more realistic value of Vstep-max can be obtained fromthe maximum derivative of a sinusoidal input signal Vin =(VFS/2)sen(2π fint) times the time slot between consecutivesamples, as illustrated in Figure 7 [7].
The quantization process in each pipeline stage is exe-cuted by low-resolution sub-ADCs. In order to maximize theavailable settling time for S&H/MDAC outputs, so that delaysare reduced as well as signal dependent conversion errors, theflash architecture is chosen for these blocks. The topologyconsists of a comparator bank followed by registers thatsynchronize the output bits with the system, using a carefullyselected VLATCH signal. Furthermore, thermometer outputbits have to be converted into binary codes. Gray codificationis also applied as an intermediate step to diminish spikeerrors from thermometer transitions. Owing to RSD correc-tion, 4-bit sub-ADC in the first stage has 14 comparators(Figure 8), while second stage uses 7 comparators to produce3 bits. The two main comparator specifications, offset andspeed, are derived from eADC in Table 3 and timing (samplingfrequency) in Figure 7, respectively.
The MDAC is the other main block within the pipelinestages, except for the last one in the chain. Its functionis bringing the sub-ADC output back to analog domain,subtracting it from the previously sampled stage input, andthen, amplifying the final residue, which will be used as inputfor the next stage (Figure 5). The MDAC is also based onan SC architecture and has a capacitor bank rather thana single sampling capacitor (Figure 9), so that all the S&Hdesign considerations and analysis are valid, too. Using againthe noise and the other stage specifications from Table 3,the different components of the MDAC architecture can bespecified [5, 8].
The above-mentioned necessity of clock phases gener-ation, bit combination and codification now brings digitalcircuitry into focus. The circuit in Figure 10 generatesthe different clock pases required by the SC circuits ofFigures 6 and 9 and the control signals for the comparatorsand registers in Figure 8 [5]. It is a standard divide-by-2 architecture using a D-flipflop [9] and 2 cross-coupled
NAND gates along with delay chains to control the phaseduty cycles.
Figure 11 shows an arrangement of registers, inverters,and NAND, OR, XOR gates that codes into thermometerrepresentation, synchronizes with an extra stages and finallyapplies RSD to digitally correct the output bits comingfrom the sub-ADC in the pipeline stages. A glitch-freeintermediary Gray coding stage is included as well. RSDcombination was developed with a Carry-Lookahead Adderand static logic gates were used all over the digital block.
4. GP on Circuit Level
GP is applied here to minimize power consumption andoptimize performance under specific requirements, for boththe OTA and comparator design presented as follows.
4.1. Geometric Programming. GP is a special kind ofmathematical optimization problem in which the objectivefunction and restrictions belong to a set of functions witha particular form, thus satisfying some specific conditions.A geometric program is itself a complex nonlinear opti-mization problem, however, it can be turned into a convexproblem through variable changes and transformations ofthe related functions. Then, it can be solved by very efficientalgorithms available from a number of companies andresearch groups working on the matter.
Despite the above benefits, GP is very restrictive aboutits formulation. Just monomial and posynomial expressionscan be part of a geometric program. These function types areshown, respectively in (11) and (12) where ck > 0, ai is anyreal number and x1, . . . , xn are n real and positive variables.It is really important to identify which operations do notmodify the original monomial and posynomial structuresbecause GP is very restrictive in this issue
g(x) = cxa11 xa2
2 · · · xann , (11)
f (x) =K∑k=1
ckxa1k1 x
a2k2 · · · xankn . (12)
A geometric program in standard form is an optimiza-tion problem with the format:
where f0 is called the objective function, fi are inequalityrestrictions and gi are equality restrictions. In a geometricprogram in standard form as described in (13), functionsfi are posynomials, gi are monomials, and xi are theoptimization variables, with the implicit constraint that thevariables be positive (xi > 0). In standard form GP, theobjective must be posynomial (and it must be minimized);the equality constraints can only have the form of monomialequal to one, and the inequality constraints can only have theform of posynomial less than or equal to one [10, 11]. This
8 International Journal of Reconfigurable Computing
Digitaloutput
Th
erm
omet
er to
bin
ary
enco
der
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
++
+−−
−
++
+−−
−
++
+−−
−
++
+−−
−
++
+−−
−
++
+−−
−
++
+−−
−
++
+−−
−
++
+−−
−
++
+−−
−
++
+−−
−
++
+−−
−
++
+−−
−
++
+−−
−
VLATCH
Vin−
Vref+ = VCM + (VFS/4) =
Vin+
φ2
Vref− = VCM − (VFS/4) =
1.65 + 0.5 V = 2.15 V
1.65− 0.5 V = 1.15 V
Figure 8: 4 bit sub-ADC applying RSD.
International Journal of Reconfigurable Computing 9
T1T2T3T4T10T11T12T13T14 T5T6T7T8T9
T1T2T3T4T10T11T12T13T14 T5T6T7T8T9
++ −−
Vref− = 1.15V
Vref+ = 2.15V
Cu
CuCuCuCuCuCuCuCuCuCuCuCuCu
CuCuCuCuCuCuCuCuCuCuCuCuCu
Cu
Vout−
Vout+
VCM = 1.65V
2 Cu
2 Cu
Vin+
Vin−
φ1
φ1
φ1
φ2
φ2
φ2
φ1
φ1
φ2
φ2
φ2
φ1φ1φ1φ1φ1φ1φ1φ1φ1φ1φ1φ1φ1
φ2
φ2
φ1 φ1 φ1 φ1 φ1 φ1 φ1 φ1 φ1 φ1 φ1 φ1 φ1 φ1
φ1e
φ1e
Figure 9: Multiplying DAC architecture.
To alignrising edges
DelayDelay
Externalclock
D
D
Q
Q
Q
Q
D
D
CLK
CLK
Delay
Delay
φ1
φ2φ2eφ
φ1e
VDD
VDD
VDDVDD
VDD
Figure 10: Clock phase generator.
GP solution is based on very efficient algorithms, speciallydesigned for convex optimization.
By developing design via GP, a basic strategy (it requiressome modifications for GP formulation incompatibilities) toobtain optimal circuits can be detailed as follows:
(1) circuit mathematical formulation in GP standardform,
(3) optimization file construction taking models anddesign specifications as inputs,
(4) results verification using a circuit simulator,
(5) new modeling regions identification after GP solu-tion and return to point 2.
4.2. OTA and Comparator Design. In this work, fully-differential folded cascode topology was chosen for the OTAcircuit, as shown in Figure 12. This architecture is preferred
instead of the telescopic one because of its wider inputand output dynamic ranges. These voltage swings are veryimportant for this application because some signals may havemaximum amplitudes as large as VFS, mainly in the S&H.A SC-CMFB circuit controlling the output common-modeVCM,OUT is shown in Figure 12, too [7].
Before applying GP, OTA design space is delimited owingto offset requirements in Table 3. Accordingly, a randomoffset theoretical estimation is made through parametricvariations of the involved transistor sizes shown as.
voff = ΔVth1 +gm3
gm1ΔVth3 +
gm9
gm1ΔVth9 +
VGS1 −Vth1
2ΔK ,
(14)
where ΔVth and ΔK stand for threshold voltage and gainmismatch parameters, respectively, while gm is the transcon-ductance and VGS the gate-source voltage. A prototypedesigned via GP and fabricated in a 0.35 μm technology ispresented in [12] along with some experimental results.
Point 1 in GP methodology requires the main per-formance parameters to be expressed as restrictions for
10 International Journal of Reconfigurable Computing
S1
S2
S3
S4
S5
S6
An extra register stagefor synchronization
D
D
D
D
D
D
D
D
D
D
D
D1
D5
D2
D4
D
D
D
D D
D
D
D
D
D
D
D
D
D
QQ
Q
Q
Q
Q
Q
Q
Q Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
B1
B2
B3
B4U4
B5
B6
B7
Stag
e 1
Stag
e 2
U1
U2
U3
U5
U6
U7
D3
D7
D6
T3
T7
T11
T13
T6
T14
T12
T1
T5
T9
T2
T10
T4
T8
Thermometer−−→gray Gray−−→binary Digital correction
φ2φ2 φ1φ1
Figure 11: Combination and digital correction.
mn1p2
mn2p1mn3p1
mn3p2
M1
M2
M3 M4
M5 M6
M7 M8
M9M10
M11
VB1 VB1
VB2 VB2
VB3VB3
VB4
VCMRF
VPOLAR
mn1p1
mn2p2
VCMFB
φ1
φ2
VDD
C1U
C2U
C1D
C2D
Vout− Vout+
Vin−Vin+
Figure 12: Folded cascode OTA architecture.
International Journal of Reconfigurable Computing 11
Vin+
+
C1 = Cgd1 + Cdb1 + Cgd9 + Cdb9 + Cgs7
C2 = CL + Cgd7 + Cgd5 + Cdb5vod2
vid2
+
+
−
−
−
ro5
ro1
ro3
ro9
ro7
gm1 vid2
vgs7 = −vro9
vs1 = vsb1 = 0V
vgs1vid2
gm7vro9
(gm5 + gmb5)vro3
vgs5 = −vro3
Figure 13: OTA half differential small signal circuit.
minimum values of DC gain in (15), unity gain bandwidthin (16), SR in (17), and an approximation of phase margin in(18), where ρ2, CL,tot and Cd(M9),tot are the nondominant poleand the total capacitances including parasitics at the outputnode and drain terminal of M9(10) in the schematic ofFigure 12, respectively. All these expressions were formulatedfrom the equivalent circuit shown in Figure 13, where thebody effect of transistors M1(2) was ignored since its smallsignal source voltage vs � 0 (ideally balanced differentialpair). A similar simplification was applied to transistorsM7(8) because they are PMOS that can have their ownisolated N-wells in a P-substrate CMOS process. In addition,biasing and devices geometry conditions are also formulatedinto the GP, the objective of which is minimizing OTA powerconsumption established in (19)
gm1(gm5 + gmb5
)−1gds3gds5 + g−1
m7gds7(gds1 + gds9
) ≥ |AVdmin|,(15)
gm1
CL,tot= gm1
CL + Cgd7 + Cgd5 + Cdb5≥ ω0 min, (16)
IM11
CL,tot= IM11
CL + Cgd7 + Cgd5 + Cdb5≥ SRmin, (17)
π − π
2− ω0
ρ2= π − π
2− gm1
CL,tot
Cd(M9),tot
gm7≥ PMmin. (18)
Power = 2 ·VDD · IM9. (19)
A low area, low power dynamic architecture (Figure 14)can be used for the comparators since the RSD correctionloosens the offset restrictions in the sub-ADC [5]. Innerthreshold generation prevents the use of the typical resistanceladder in Figure 8. Even though it suffers from offset, thiscan be tolerated in low-resolution applications, as 3 and 4-bitflash sub-ADCs. Threshold voltage is set by current divisionin the crossed differential pairs. Assuming W3 = W4 =f ·W1 = f ·W2, ID5 = d · ID6, Vin = e ·Vref in Figure 14, andusing large signal models for transistor currents, expression(20) is obtained, with K = μ·Cox as the transistor gain factor.
GP is initially applied to optimize power consumptionand delays in the basic comparator, which needs an externalthreshold voltage. Afterwards, (20) is used to establish thethreshold voltages needed in the sub-ADC by modifying thetransistor size and current ratios:
2de2I6W1
L− Ke4V 2
ref
(W1
L
)2
= 2I6W3
L− KV 2
ref
(W3
L
)2
.
(20)
5. Results
Even though the complete ADC of Figure 5 was designed,only the S&H block reached the silicon fabrication phase sofar. The complete converter needs a longer time to get to itsfinished layout and be sent to chip integration due to thesize and complexity of its architecture. Therefore, this sectionexhibits some prelayout simulations for the Time-InterleavedPipeline ADC from the circuit level up to the top system,and some postlayout results for the Sample and Hold blocktogether with other auxiliary circuits to be introduced later.
First, from the circuit level, comparator yield wassimulated to evaluate whether the offset of the dynamictopology would affect the required resolution. In Figure 15,each point is the result of 100 Montecarlo runs, indicatingthe percentage of right decisions owing to a known inputof the comparator. The closer the input signal is to thethreshold, the lower the yield is. Yield rises over 95% whenthe difference between when the difference between inputand threshold voltages exceeds±voffset. In a different manner,this can be understood as the probability of the comparatorhaving an offset voltage lower than voffset [13]. The offsetvoltage was simulated for the OTA too, as shown in theleft side of Figure 16 together with an input dynamic rangeresult, whose specified value was greater than 1 V and itrequires the amplifier to be simulated in a unity feedbackloop. Offset voltage is given by voffset ≤ μ ± 3 · σ , where μand σ are the mean and the standard deviation in Figure 16,respectively. Consequently, voffset < 7 mV for the S&H OTAsimulated in this case, fulfilling the requirement of Table 3.
12 International Journal of Reconfigurable Computing
M8
M12
M11
M7
M10M9
M2M1
M5 M6
M4
M3
VLatchVLatch
VLatch VLatch
VDD
Vout−Vout+
Vin−Vin+
Vref+
Vref−
Io2Io1
Figure 14: Comparator in the flash subADC.
Com
para
tor
yiel
d (%
)
100
80
60
40
2062.5 187.5 312.5 437.5 562.5 687.5 812.5 937.5
Input voltage (mV)
Comparator for th = 187.5 mVComparator for th = 312.5 mVComparator for th = 437.5 mV
Comparator offset voltage analysis
Comparator for th = 62.5 mV
Δ4b
Figure 15: Comparator threshold simulations.
From the block level, the S&H circuit was simulatedwhile sampling a slow ramp signal in Figure 17. Discreteoutput against analog input are shown, as well as nonidealitydetails and block current consumption. Observed glitchescome from nonlinear variation of CMOS switch resistancesand reduced output resistance in OTA cascode transistors(Figures 12 and 13), since they start working close to theirtriode region when Vin approaches VFS. This is why outputand input DR (see Figure 16) are important specifications forthe OTA design. CMOS bootstrapped switches can be used soas to further reduce those glitches.
Finally, simulations results from the complete ADC areshown in Figures 18 and 19, while sampling a maximum
frequency (500 kHz) input tone using maximum samplingrate (11 MS/s). Time-interleaved pipeline operation can beobserved at digital output word in Figure 19 as result ofmultiplexing the 6-bit outputs from 2 parallel channels,whereas its FFT transform in Figure 18 allows making anestimation of the ADC frequency characteristics. Linearitycan be quantified from curves in Figure 20. Better DNLand INL measures require Montecarlo simulations, yet thatwould take so much longer.
Table 4 shows some results from the prelayout simula-tions, which characterize the designed ADC along with theother specifications presented in Table 2. It is difficult tocompare these prelayout values with other works because
International Journal of Reconfigurable Computing 13
sd = 2.24332 m
10
7.5
5
2.5
−10 −7.5 −5 0 2.5 5−2.5
Montecarlo analysis
Samples
Y0
()
7.5 10
Gauss curve
μ = 443.07μ
N = 100
Offset (E − 3)
(a)
DR IN
Out
IN (V)
3
2.5
2
1.5
1
0.5
0 0.5 1 1.5 2 2.5 3V
(V)
(b)
Figure 16: OTA offset and input DR simulations.
+
+
+
+
2.5
2
1.5
1
−0.5
−1
−1.5
0
0.5
S&H voltages (up) and current (down)
230
220
210
200
1900 1 2 3 4 5
I core OTA
Vout = Vout+
Vout+
−Vout−
Vout−
Time (μs)
Vin = Vin+ −Vin−
I(μ
A)
V(V
)
(a)
++
1
0.9
0.8
0.7
0.6
0.5
0.4
3.5 3.75 4 4.25 4.5
Zoom around +VFS/2Vout = Vout+ −Vout−Vin = Vin+ −Vin−
Time (μs)
V(V
)
.
(b)
Figure 17: S&H operation.
of 2 reasons. The first of them is that these numbers arenot silicon measurements, and the second is that it is reallyhard to find another converter with similar resolution-sampling frequency-technology-architecture characteristicsin the literature, mainly due to the particularity of this
application. In a future work, when the complete ADC is sentto fabrication, it will be worth the comparison.
As previously stated, the S&H block was sent to fabri-cation. Indeed, the complete chip including testing circuitslooks like the schematic in Figure 21, and Figure 22 shows
14 International Journal of Reconfigurable Computing
International Journal of Reconfigurable Computing 15
MIBUFFIBUFF
IBUFF
VSSA
VSSA
CLOCKS
BUFFN
SING2DIFF
DUT
BUFFP
buffer
allsh
Balun
Buffer
INN
INP
OUTSHN
OUTSHP
IN
CLK
VSSA
ISH IBUFF
OUTN
OUTP
VB
SIN
VSSA DN
DP
VSSD
EXTCLK
VD
DA
VSS
A
inshn
inshp
ISH
outshn
outshp
VB
INP
INN
VSSA
OUT
VB
INP
INN
VSSA
OUT
ng = 1
clk gen
φ1N
φ1eN
φ2eN
φ2N
φ1N
φ1eN
φ2eN
φ2N φN
φNφ
1N
φ1eN
φ2eN
φ2N φN
VDDB
VDDB
VDDB
VDDB
VDDD
VDDA
wtot = 2.5 μ
1 = 6 μ
Figure 21: Chip to be fabricated.
VSSA
VB
VSSA
VB
VSSA
VDDA
ISH
VSSA
INN
INP
VSSA
ISH
VDDA
VCMREF
VSSA
VB
SIN
DN
DP
inshn
inshp
outshp
outshn
OUTNOUTN
VDDB
OUT
INP
INN
VDDB
OUT
INP
INN
VDDA
VDDB
PHI1N PHI2N PHI1eN PHI2eN PHIN
SHSI
NG
TO
DIF
F
BU
FFE
RS
CLK
GE
N
Figure 22: Core layout.
Table 4: Prelayout specifications for the ADC.
Parameter Value
Current consumption (rms) 3.64 mA
Latency 5 clock cycles
SNR in the channel up to fs/2 59.4 46.5 dB
the entire layout of the core without pads. As seen in thosefigures, along with the S&H block, four additional circuitswere implemented. First, a clock generator was included
to provide all the phases the sample and hold requiresto function properly. Second, a single-ended to differentialconverter allows the chip input to be single-ended, makingthe test bench simpler. The S&H common mode voltage isalso set by this input converter. Finally, two output buffersmake the S&H capable of driving the measurement probes.
Layout techniques were applied all over the chip ofFigure 22 in order to improve matching characteristics ofthe circuits. All passive component were drawn in commoncentroid arrangements, and when necessary, transistors usedthese structures too. The OTA inside the S&H, whose layout
16 International Journal of Reconfigurable Computing
VD
D
OU
T
VD
DD
IN
VSS
OU
T
VD
D
CL
K
OU
T
OU
T
VD
DD
IN
VSS
D
VD
D
OU
T
VD
DD
IN
VSS
DV
SSV
SSV
SSD
OU
T
VD
D
IN
VSS
DV
SS
OU
T
VD
DD
ININ
ININ
CLK
CLK
OU
T
CLK
VDDA
ISH
VSSA
VD
DD
VD
D
IN
VSS
D
OU
TC
LKC
LK
OU
T
VSS
VD
D
OU
T
VD
DD
IN
VSS
D
OU
TC
LK
VD
D
OU
T
OU
T
VD
DD
IN
VSS
DV
SSV
SS
VD
D
OU
T
VD
DD
IN
VSS
DV
SS
OU
TC
LK
ININ
CLK
CLK
OU
TO
UT
VDDD
IN
VSSD
INOUT
INOUT
INOUT
INOUT
VDDD
IN
VSSD
OUTOUT
VDDD
IN
VSSD
OUT
IN OUT
IN OUT
IN OUT
IN OUT
VDDD
IN
VSSD
OUT
VDDD
IN
VSSD
OUT
IN
IS
VDD
INN
VSS
VC
INO
UT
INO
UT
ININ
ININ
OUTOUTN
HI HI HIHI HI
I
I
OT
A
CM
FB
CLK
CLK
CLK
CLK
CLK CLK
CLKCLK
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
CLK
CLK
VSS
INO
UT
CL
K
VSS
INO
UT
CL
K
VSS
VSS
INO
UT
CL
K
VSS
INO
UT
CL
K
VSS
Figure 23: S&H layout.
Expressions
2.5
2
1.5
1
0.5
0
7
6
5
4
3
2
1
0 2.5 5 7.5 10
Time (us)
/IN (1.576V)
I (m
A)
OUT (557.4 mV)
/CHIP/VDDB (4.59 mA) /CHIP/VDDA (332 μA)
−0.5
−1.5
V(V
)
−1
VT(/CHIP/INP)(2.036V) VT(/CHIP/INN)(1.269V)
Figure 24: S&H postlayout simulations.
is zoomed in Figure 23, was placed in a stacked architectureto improve matching with its bias circuit as well.
Given that the chip has not returned for testing, somepostlayout results are presented instead. Thus, Figure 24shows the sample and hold operation over a 500 kHz single-ended input signal (blue at the top). The input converteramplifies and splits this wave in two differential versions(yellow and purple at the top), which are processed by theS&H and passed through the output buffers to produce theamplitude and time discrete signal in red. This simulation
was executed with the entire chip, including pads andESD structures, after parasitic extraction of the layout. Thebottom panel of Figure 24 shows the separated currentconsumption of the S&H (blue) and testing circuits (red).
This prototype will operate under the same samplingfrequency and bandwidth conditions that it would face aspart of the ADC. The devices under test (S&H + clockgenerator) drive 370 μA from a 3.3 V power supply whilethe testing circuits (single-ended to differential converter andoutput buffers) draw around 4 μA from an auxiliary 3.3 V
International Journal of Reconfigurable Computing 17
power supply. The final layout size including pads is 800 μm× 1400 μm, yet the core is only 500 μm × 255 μm.
6. Conclusions
By carefully deriving key circuit specifications, it is possible toreduce their strong impact on total system power dissipation.Following this idea, a low power time-interleaved pipelineADC for Bluetooth standard was designed. A survey onthe specification process from standard to the elementarycircuits was made to justify the 6-bit, 11 MS/s, 2 time-interleaved channel, 2 pipeline stage topology selection.This is the first step toward a reconfigurable system imple-mentation. Indeed, the skill and architecture knowledgegained from this work will turn, easier and faster, themultistandard application into a power-efficient solution.It is difficult to compare this work results due to its veryspecific characteristics, which do not follow the actual trendsof rising either the sampling rate or the resolution, but meetthe Bluetooth standard requirements, instead.
The main support for this paper contribution is theapplication of GP, seeing that it provides a better knowl-edge and experience of circuit behavior. When designs aredeveloped using GP, it is easier to detect relations and trendsbetween circuit requirements and design variables, allowingidentifying possible optimization focuses for global systemperformance, as in the complete ADC presented here.
As the main contribution of this work over its originalversion in [7], a prototype 11 MHz S&H was designed ina 0.35 μm 3.3 V CMOS process to verify its central OTAdesign via GP. Some testing blocks are also in the chip,yet not intended to influence the S&H performance itself.Over a stacked and common centroid-structure chip layout,future measurements aim to demonstrate the optimizedpower consumption while operating under the highest speedrequirements a block would face into this time-interleavedpipeline ADC.
References
[1] J. Oliveira, J. Goes, M. Figueiredo, E. Santin, J. Fernandes,and J. Ferreira, “An 8-bit 120-MS/s interleaved CMOS pipelineADC based on MOS parametric amplification,” IEEE Transac-tions on Circuits and Systems II, vol. 57, no. 2, pp. 105–109,2010.
[2] N. Petrellis, M. Birbas, J. Kikidis, and A. Birbas, “Asyn-chronous ADC with configurable resolution and binary treestructure,” in Proceedings of the 4th International Symposiumon Communications, Control, and Signal Processing (ISCCSP’10), pp. 1–4, March 2010.
[3] B. Xia, A. Valdes-Garcia, and E. Sanchez-Sinencio, “A 10-bit44-MS/s 20-mW configurable time-interleaved pipeline ADCfor a dual-mode 802.11b/bluetooth receiver,” IEEE Journal ofSolid-State Circuits, vol. 41, no. 3, pp. 530–539, 2006.
[4] B. Xia, Analog-to-digital interface design for wireless receivers[Ph.D. thesis], Texas and A&M University, 2004.
[5] M. Waltari, Circuit techniques for low-voltage and high speedA/D converters [Ph.D. thesis], Helsinki University of Technol-ogy, 2002.
[6] J. Kim, S. Limotyrakis, and C. K. K. Yang, “Multilevel poweroptimization of pipelined A/D converters,” IEEE Transactionson Very Large Scale Integration (VLSI) Systems, vol. 19, no. 5,pp. 832–845, 2011.
[7] W. Carvajal and W. M. V. Noije, “Time-interleaved pipelineADC design: a reconfigurable approach supported by opti-mization,” in Proceedings of the 24th Symposium on IntegratedCircuits and System Design (SBCCI ’11), pp. 17–22, ACM, JoaoPessoa, Brazil, September 2011.
[8] L. Sumanen, Pipeline analog-to-digital converters for wide-bandwireless communications [Ph.D. thesis], Helsinki University ofTechnology, 2002.
[9] J. Yuan and C. Svensson, “New single-clock CMOS latchesand flipflops with improved speed and power savings,” IEEEJournal of Solid-State Circuits, vol. 32, no. 1, pp. 62–69, 1997.
[10] M. Del Mar Hershenson, “Design of pipeline analog-to-digitalconverters via geometric programming,” in Proceedings ofIEEE/ACM International Conference on Computer Aided Design(ICCAD ’02), pp. 317–324, November 2002.
[11] M. Del Mar Hershenson, CMOS analog circuit design viageometric programing, [Ph.D. thesis], Stanford University,1999.
[12] W. Carvajal, E. Roa, and W. M. V. Noije, “A 23 MHzGBW 460 μW folded cascode OTA for a sample and holdcircuit using double sampling technique,” in Proceedings ofthe Conference on Integrated Circuits and Systems (DCIS ’08),Grenoble, France, Novembre 2008.
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