“JTAG Based Board Level Testing How to make it work” · 11/28/2012 · Mandatory Registers TAP...

© GOEPEL electronic 2012

TEST FORUM 2012Nov 27-28, 2012, Snekkersten, Denmark

“JTAG Based Board Level Testing

-

How to make it work”

Presenter: Jan Heiber ([email protected])


NTF 201211/28/2012

1

2

3

Intro

Embedded System Access

How to make it work?

Intro

4 Summary and Outlook

2


NTF 201211/28/2012

GOEPEL electronic GmbH - Profile• Founded: 1991

• Spin-Off JENOPTIC

• Staff: nearly 200 in 2012

• Headquarter: Jena

• Branch Offices:

» USA – Austin

» France – Paris

» UK – Cambridge

» China – Hong Kong

• Business Areas:

» JTAG/Boundary Scan

» Automotive Test Solutions

» Functional Test Systems

» AOI / AXI

» Digital Image Processing

3


NTF 201211/28/2012

2 Embedded System Access

Board Level Access

4


NTF 201211/28/2012

Test Coverage & Fault Isolation Demands

Intrusive Access ICT/MDA

Intrusive Access Flying Prober

Embedded Access Technologies

Test

co

verag

e Q

uali

ty

199x198x 200x 202x201x

Intrusive Board Test Access Era

Static faults

Fault spectrum

Performance faults

Dynamic faults

Boundary Scan + Processor Emulation Test + Chip Embedded Instrumentation + …

55


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Access Strategies

6


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All Applications Under Control

7


NTF 201211/28/2012 GOEPEL Boundary Scan 8

SCANFLEX – Scalable H/W platform

Top Features for the leading JTAG BScan Platform in the Industry

ATE ReadyModularPowerful Flexible more…Scalable Universal


NTF 201211/28/2012 9

System CASCON – Modular S/W platform

Top Features for the leading JTAG BScan Platform in the Industry

Scalable Safe TestIntegrated ModularPowerful Intelligent more…


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Systems for Integration from A to Z

Industry proven integration packages for all leading ATE platforms

AGILENT PXI / PXIe Teradyne more…Digitaltest SPEA Takaya

Seamless and Interactive

Plug-In card for Agilent & Teradyne

Pre-configured integration packages with Software and Hardware

All integration packages are typically OEM approved from native supplier

Free choice of different packages to match performance demands

Support of Flying Probes or ICT nails as virtual BScan cells (Virtual ScanPin™)

Special hardware features for safe and reliable operation in noisy environment

Support of Extended JTAG / Boundary Scan incl. functional Emulation Test


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Chip- and Board- Congruencies

Boards obtain the same physical properties as chips

Chips obtain the same systemic properties as boards


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Current Test Problems

DRAM devices getting continuously higher data rates (DDR2, DDR3…)

Routing of DDR signals during layout is critical to avoid skews (Design Errors)

Boundary Scan is to slow to keep the necessary vector rate

Some processors don‘t have BScan on the Memory Bus pins anymore

Missing access to all Memory signals or non controllable clocks

New Standard IEEE 1581 could solve the problem but is not available yet

12

Memory Test Requirements

Fault coverage for Memory Access on modern boards via IEEE1149.1 is stuck now for several years.

This is caused by use of modern DRAM‘s

200x199x 201x

Average real world BScan Fault coverage Quality for Memory Access

Critical Trend

Situation

Fau

lt

co

verag

e


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Flash Programming Requirements

Rapid growing number of Micro Control Units (MCU) with OCF

Continuously growing Flash size

Standard Boundary Scan can’t program On-Chip Flash

200x

Fla

sh

Siz

e [

Mb

it]

1Kb

10Kb

100Kb

1Mb

#M

CU

wit

h O

CF

MCU with On-Chip Flash (OCF)

µP Core

RAM Flash

I/O


NTF 201211/28/2012 14

Paradigm change for I/F technologies …

Rapid growing GBit bus applications for high speed Communication

Bus speed is doubling every 36 months average

On-Chip Bus I/F with limited low level protocol access and no dot6

External PHY’s typically don’t support dot6

2000 - 2015

Bu

s s

peed

[G

Bit

]

0,1

1

10

100

#G

Bit

ap

plicati

on

s

PCIe 4.0

Thunderbolt

10GigE

USB3.0

PCIe1.0

1GigE

USB2.0


NTF 201211/28/2012

Evolution of ESA Technologies

1990

IEEE1149.1

1993

In-System

Programming

1998

On Chip

Emulation

2000

IEEE1149.4

Market presence threshold

Digital

Boundary Scan

2002

µP Emulation

Test

2004

IEEE1149.6

2008

Chip

Embedded

Instruments

15

Analog

Boundary ScanPLD & Flash

Software

Emulation

At speed Core

Assisted Test

AC Networks

Boundary Scan

2010

FPGA

Assisted

Test/ISP

2012

ESA

Introduction

Embedded

T&M IP

Reconfigurable

T&M IP

15


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Boundary Scan Test

TAP

Controller

Core

Logic

TDI

TMS

TCK

TDO

I/O Pin

Scan cell

16

Structural Test including pin level diagnostics

Prototype Verification, (Mass-) Production, Field

Access to hidden Pins (BGA)

Access to additional resources (BIST)

In-System Programming

Considerations

16


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Processor Emulation Test

On-Chip Resources

JTAG TAP

µP Core

Complex Bus I/F

Legacy Bus I/F

Legacy I/O PortsSystem Bus I/F

External Bus Devices

SRAM / DRAM

Peripheral I/O Ports

Peripheral Bus I/F

Aux Resources

VarioTAP Control System

Access by the native processor debug interface

Conversion of the µP core into an JTAG remote controlled ATE

Use of the design embedded tester with real time speed

No operating system and booting needed

No special Flash image need to be programmed

Considerations

17


NTF 201211/28/2012 18

Chip Embedded Instruments

IEEE1149.1 TAP

Mandatory Registers

TAP Controller

Instrument Control Registers

BScan Register

Control accessInstrument access is IEEE1149.1 mapped

All communications are serial vector based

Open instrument functionality

Devices need a TAP but BScan is an option

Instruments can support validations and tests on chip level and board level

Considerations

Chip-embedded instrument

ChipVORX®

Control System

18


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3 How to make it work?

How To Make It Work

19


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• Don't tie compliance enable pins to GND or VCC (instead, use pull-resistors and make them accessable)

• Don't forget about performance (TCK frequency)

• Avoid using PLL's that cannot be disabled or don't provide a pass-through mode

Board Level DFT – DON’T


NTF 201211/28/2012

• Use Boundary Scan (BScan)

• Make non-BScan devices easily initializable

• Permit non-BScan outputs to be tri-stated

• Use resistors to tie inputs

• Permit enabling/disabling of on-board clocks

• Consider allowing access to all unused pins

• Consider using BIST

• Use test modes offered in non-BScan devices

• Consider using unused BScan pins to improve test coverage

Board Level DFT – DO


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• JTAG Test Bus Connector example:

1064 82

953 71

Board Scan Chain Design – Debug Interfaces

• COP

• Cortex-SWD-10


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• Bypass pads/resistors...

TCK

TMS

/TRST

TDI

TDO

Rtdi

Rtdo

Rbp

TCK

TMS

/TRST

TDI

TDO

Rtms

Bypassing the TAP to exclude a Boundary Scan device from the chain:

Including a Boundary Scan device in the chain:

23

DfT - Board Scan Chain Design


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• Watch out for signal issues:

The extra “clock” ruins the

TAP synchronisation. The system has no chance for

stable

operation.

Board Scan Chain Design


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DFT at Board Level

• Control over (any)enable signals:


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Active non-BScan devices (e.g. controllers)

Example:82371AB PCI ISA IDE Xcelerator (PIIX4)

DFT at Board Level


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DfT - Memory Clusters

• PLL with pass-through mode:

...

...

...

...

TAP

Cor

e Lo

gic

Address bus

Data bus

Control lines

synchronous RAM

Clock PLL

1:1 Mode

Access per BScan available ?

synchronous RAM

27


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DfT - FLASH ISP performance

28


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DfT – FPGA Embedded Instruments

29

• Scan chain DfT rules

• Disable Watchdog/Reset circuitry

• Functional design removed while testing � take care about

circuitry controlled by the FPGA

IEEE1149.1 TAP

Mandatory Registers

TAP Controller

Instrument Control Registers

BScan Register

Control access

Chip-embedded instrument


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DfT – Processor Emulation Test

30

• Depends on µP type & Resources to be tested

• Scan chain DfT rules

• Extra Boot signals

• (internal) memory configurations

• (external) memory design rules

• Interface design rules

On-Chip Resources

JTAG TAP

µP Core

Complex Bus I/F

Legacy Bus I/F

Legacy I/O Ports

System Bus I/F

External Bus Devices

SRAM / DRAM

Peripheral I/O Ports

Peripheral Bus I/F

Aux Resources

• Test people need to communicate with the design people


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Summary & Outlook

4 Summary and Outlook

31


NTF 201211/28/2012

Summary & Outlook

3232

• Access & Fault Coverage

• Control

• Flexibility & Performance

• ESA-Webcast: http://www.goepel.com � Support � Webcasts


NTF 201211/28/2012

Thank you for your attention.

Any questions?

For further information please use

following contact information

Jan Heiber [email protected] www.goepel.com

Scandinavia +45-8748-0608

Germany +49-3641-6896-0

33

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“JTAG Based Board Level Testing How to make it work” · 11/28/2012 · Mandatory Registers TAP...

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