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“Monitoring and Control of Nanoscale Semiconductor
Manufacturing”
Professor Thomas F. EdgarDepartment of Chemical Engineering
University of Texas – Austin
NSF WorkshopFebruary 11-12, 2008
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Systems Tools for Monitoring and Control
• Multiscale Modeling and Control• Recipe Optimization• Multivariable Control• Selection of Sensors• Fault Detection
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1 2
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3r12 = 8.93 Å
r34 = 5.00 Å
MA
dMA
.. . .®
Courtesy Ralph Dammel - Clariant
MPU ½ Pitch (nm) (uncontacted gate) 90 65 45 32 22 18Overlay (nm) 32 23 18 12.8 8.8 7.2MPU gate in resist (nm) 53 35 25 18 13 10MPU gate length after etch (nm) 37 25 18 13 9 7Gate CD control (nm, 3-sigma) 3.3 2.2 1.6 1.2 0.8 0.6Mask CD uniformity (nm, 3σ) (Isolated lines, binary mask)
3.8 2.2 2.0 1.3 0.5 0.4
2004 2007 2010 2013 2016 2018
6590
Manufacturable solutions exist and arebeing optimized
Manufacturable solutions are known
Manufacturable solutions are NOT known
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r34=4.32 Å
r12= 8.69 Å1
2N
BH
FA
Roadmap
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Function Requires the ability to define Arbitrary Shapes and precision placement of those shapes
Function Requires the ability to define Arbitrary Shapes and precision placement of those shapes
!
Transistor
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Unit operations in microelectronics manufacturing are characterized by:
1. Physical/chemical complexity2. Inability to measure directly many
process variables3. High sensitivity to process changes4. Multiple inputs/multiple outputs
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Plasma Etching Sensors
• Tool measurements (~80)• Optical Emission Spectroscopy (~1200)• SEERS (~10)• VI – probe (~40)• Total possible sensors > 1300• Need sensor selection methodologies
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Observations About Plasma Etching from Semicon Korea (2008)
• PE will be an enabling tool for making novel devices in the future
• Nanodevice requirements include precise etch rate, high etch selectivity, and no damage or residue
• Trench bottom roughness and leakage current can be controlled by plasma chemistry and ion energy
• Profile simulator for dielectric etch can predict “necking” of sidewall in contact hole etching
• Neutral beam etching is not capable of atomic layer resolution because etching is too rapid
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Atomic Layer Etching Steps
• Absorb reactant molecules onto substrate surface (does not spontaneously etch surface)
• Purge excess reactant• Irradiate surface with energetic beam, causing
chemical etching of surface atoms bonded to reactants
• Purge reaction products
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Profile Simulator (Lam Research)
• Monte Carlo transport module calculates fluxes of ions and neutrals to surface and angular distribution from plasma
• Mass balance model calculates surface reaction rates
• Profile is calculated from evolution of surface• Operating strategy needed to prevent necking,
bowing, and profile distortion
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MultiscaleMultiscale Modeling of Modeling of NanoengineeringNanoengineering
Time (sec): 10-12 10-9 10-6 10-3 100
Length (m): 10-9 10-8 10-7 10-6
Its success will offer tremendous opportunities for guiding the rational design and fabrication of a variety of nanosystems!
Quantum Mechanics
Molecular Dynamics
Statistical Mechanics
ContinuumMechanics
PhysicalProperties
Atomistic behaviors
physical understanding
quantitative prediction
Fundamental processes,Atomic structures, Energetics, ….
Shape, Size distribution,Spatial distribution,Interface structures, ….
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Ultrashallow Junction Overview
• Requirements– Shallow junction depth– Box-like dopant profile – High dopant activation
Year of Production: 2002 2005 2008 2011 2014
Junction depth (nm): 25-43 20-33 16-26 11-19 8-13
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Multiscale Modeling
• Goal: Develop a predictive multiscale model of the As-doped ultrashallow junction formation process
prediction
validation
• Density functional theory[short time (< nsec)]
Atomic-scale calculation
fundamental data
Mesoscale simulation• Kinetic Monte Carlo• Continuum model
[long time (>1 sec)]
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Arsenic Junction Formation
• Anomalous annealing behavior– Dopant electrical inactivation– Transient enhanced dopant diffusion
Provided by Seiko-Epson
After Annealing
Before Annealing
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The SFIL ProcessThe SFIL Processtemplate
etch barrier
UV Cure
transfer layer
Dispense
Expose
Separate
release treatment
Imprint
Breakthrough Etch
Transfer Etch
Residual layer
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Schematic of Grand Challenge
Machine & Process Design
ImprintSFILnTP
Proximity
EmbossingVisco
plastic solids
DirectedSelf-Assembly
Functionalnanoparticles on
patterned surface
Large Area, Long-Ranged Order Manufacturing Processes
High Speed Physical Processes
Liquid Carrier DeliveryPressing
DispersionCuring/Solidification
Alignment
FunctionalizedNanostructured
Surfacese.g., Solar panels,Photonic sheets,
High density memory
Goal: Development and Integration of MultiscaleComputational Tools to Deliver Reliable Quantities of Interest
Creation ofMaster,Web
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Grand Challenge and Its Goals
• Integrated Computationally Aided Engineering of Nanopatterning Processes- Provide suite of computational tools to enable the
in-silico design and optimization of high throughput,large area, low defect processes to produce functionalized nanostructured surfaces
- Provide means to turn laboratory nanopatterninginto true (practical) manufacturing processes
- Quantum jump in US competitiveness in thenanomanufacturing arena
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Modeling / Simulation Challenges
• Multi-scale- Length scales 10-9 to 10-1 m- Time scales 10-3 to 101 s
• Multi-physics- Fluid-solid interfaces and interphases- Multi-phase- Phase changes- Phase boundaries- Microstructure evolution- Non-continuum effects/sub-grid models
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Cyberinfrastructure Challenges
• Solvers, scalability, and data flows negatively affected by multi-scale, multi-physics, large aspect ratios
• Verification and uncertainty quantification• Validation and uncertainty quantification (data)
