APA2057A

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Copyright ANPEC Electronics Corp.Rev. A.1 - Aug., 2007

www.anpec.com.tw 1

ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, andadvise customers to obtain the latest version of relevant information to verify before placing orders.

2.4W Stereo Audio Power Amplifier (with Gain Setting) & Capfree Headphone Driver

APA2057A

The APA2057A is a monolithic integrated circuit, whichcombines a stereo power amplifier and a stereo outputcapacitor-less headphone amplifier. The stereo power amplifier provides 19-steps gain setting for flexibleapplication. The headphone amplifier is ground-refer-ence output, and no need the output capacitors for DCblocking. The advantages of eliminating the output ca-pacitor are saving the cost, PCBs space and componentheight.

Both the de-pop circuitry and the thermal shutdownprotection circuitry are integrated in the APA2057A,which reduces pops and clicks noise during power on/off and in shutdown mode. Thermal shutdown protectsthe chip from being destroyed by over-temperaturefail ure. To simpl ify the audio system design in notebookcomputer applications, the APA2057A provides the in-ternal gain setting, and these features can minimizecomponents and PCB area.

The APA2057A is avai lable in both TSSOP-28P andTQFN5x5-28 packages. Both packages are character-

ized by space saving and thermal efficiency.

Features General Description

Applications

Note book PCs LCD monitor

Operating Voltage HV DD= 3.0~3.6V

V DD= 4.5~5.5V

No Output Capacitor at Headphone Amplifier Required

Meeting VISTA Requirement Low Distortion

AMP mode THD+N=56dB, at V DD = 5V, R L = 4 , P O=1.5W THD+N=64dB, at V DD = 5V, R L = 8 , P O=0.9W

HP mode THD+N=73dB, at HV DD=3.3V, R L=16 P O=125mW

THD+N=77dB, at HV DD=3.3V, R L=32 ,P O=88mW

THD+N=85dB, at HV DD=3.3V, R L=10k , VO=1.7Vrms

Output Power at 1% THD+N 1.9W, at V DD = 5V, AMP mode, R L = 4 1.2W, at V DD = 5V, AMP mode, R L = 8

at 10% THD+N 2.4W at V DD = 5V, AMP mode, R L = 4 1.5W at V DD = 5V, AMP mode, R L = 8

Depop Circuitry Integrated Internal 19-steps Gain Setting for Flexible Applica-

tion

Thermal Shutdown Protection and Over CurrentProtection Circuitry

High Supply Voltage Ripple Rejection Surface-Mount Packaging

TSSOP-28P (with enhanced thermal pad) TQFN5x5-28 (with enhanced thermal pad)

Lead Free Available (RoHS Compliant)

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Ordering and Marking Information

Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully

compliant with RoHS and compatible with both SnPb and lead-free soldering operations. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JED EC J STD-020C for MSL classification at lead-free peak reflow temperature.

Pin Configurations

Absolute Maximum Ratings (Note 1)

Symbol Parameter Rating Unit

VDD Supply Voltage (PVDD, CVDD, VDD) V

HVDD, Supply Voltage (HVDD)-0.3 to 6

VSS Supply Voltage (VSS) +0.3 to -6 V

VSET , V AMP_EN , VHP_EN Input Voltage 0 to V DD+0.3V

T A Operating Ambient Temperature Range -40 to 85 CTJ Maximum Junction Temperature 150 C

(Over operating free-air temperature range unless otherwise noted.)

APA2057A

Handling Code

Temperature Range

Package Code

Package CodeR : TSSOP-28P QB : TQFN5x5-28

Operating Ambient Temperature RangeI : -40 to 85 C

Handling CodeTR : Tape & Reel

Lead Free CodeL : Lead Free Device

APA2057A R : APA2057A

XXXXX XXXXX - Date Code

XXXXX - Date Code

Lead Free Code

APA2057A QB : APA2057AXXXXX

= ThermalPad (connected the ThermalPad to GND plane for better heat dissipation)

INR_A 3

INR_H 4

LOUT- 9

LOUT+ 8

INL_A 5

PVDD 10

CVDD 11

CGND 13

APA2057A

15 CVSS

16 HVSS

VDD 1

GND 2

17 HP_R

18 HP_L

21 ROUT-

19 HVDD

20 PVDD

22 ROUT+

23 PGND

24 HP_EN

25 BIAS

INL_H 6

PGND 7

CP- 14

CP+ 12

28 BEEP

27 AMP_EN

26 SET

(Top view)

(TSSOP-28P)

(Top view)(TQFN5x5-28)

APA2057A

20 HP_EN

17 ROUT-

15 HVDD

16 PVDD

18 ROUT+

19 PGND

21 BIAS

2 4 B E E P

2 5 V D D

2 6 G N D

2 7 I N R

_ A

2 8 I N R

_ H

2 2 S E T

2 3 A M P

_ E N

LOUT- 5

LOUT+ 4

PGND 3

INL_A 1

PVDD6

CVDD 7

INL_H 2

C P -

1 0

C G N D 9

C P + 8

C V S S 1 1

H V S S 1 2

H P

_ R 1 3

H P

_ L 1 4

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Absolute Maximum Ratings (Cont.) (Note 1)

Symbol Parameter Rating Unit

TSTG Storage Temperature Range -65 to +150 CTSDR Maximum Lead Soldering Temperature 260, 10 seconds CP D Power Dissipation Internally Limited W

(Over operating free-air temperature range unless otherwise noted.)

Note 1 : Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Exposure to absolute maximum ratingconditions for extended periods may affect device reliability.

Recommended Operating Conditions

Thermal Characteristics (Note 2)Symbol Parameter Value Unit

JA Thermal Resistance - Junction to Ambient (Note 2)

TSSOP-28PTQFN5x5-28

4543

oC/W

Note 2 : 3.42 in 2 printed circuit board with 2OZ trace and copper through 10 vias of 15mil diameter vias. The thermal pad on the TSSOP-28P & TQFN-28packages with solder on the printed circuit board.

Min. Max. Unit

Supply voltage, V DD 4.5 5.5 V

Supply voltage, HV DD 3.0 3.6 VHigh level threshold voltage, V IH AMP_EN, HP_EN 2 V

Low level threshold voltage, V IL AMP_EN, HP_EN 0.8 V

for Amplifier V DD-1 VCommon mode input voltage, Vicm

for Headphone Amplifier HV DD-1 V

Shutdown 0.8

Gain Setting 2 4.2 VInput Voltage (V SET )

Fix Gain 4.5 V

Electrical Characteristics

APA2057A Symbol Parameter Test Condition

Min. Typ. Max. Unit

VDD Supply Voltage 4.5 5.5 V

HVDD Headphone Amplifier supply voltage 3.0 3.6 V

IVDD VDD Supply Current 17.5 29

IHVDD HVDD Supply Current

Only Speaker mode,

AMP_EN = HP_EN = 0V 0.15 1

IVDD VDD Supply Current 12 20


Only Headphone mode,

HP_EN = AMP_EN = 5V 3 5

IVDD VDD Supply Current 20 35


All Enable, HP_EN=5V and AMP_EN = 0V

3 5

mA

VDD = 5V, HV DD = 3.3V, GND = PGND = CPGND = 0V, T A= 25 C (unless otherwise noted).

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Electrical Characteristics (Cont.)

APA2057ASymbol Parameter Test Condition

Min. Typ. Max. Unit

ISD(HVDD) HVDD Shutdown Current 50 90

ISD(VDD) VDD Shutdown CurrentSET = 0V

1 10 A

I AMP_EN Input current AMP_EN 1 AIHP_EN Input current HP_EN, 10 15 A

Speaker mode

THD+N =1%, F in =1KHzRL =4 RL =8 1.0

1.91.2

P O Output Power THD+N =10%, F in =1KHzRL =4 RL =8 1.3

2.41.5

W

VOS Output Offset Voltage RL =8 , Gain =10.5dB 10 mV

THD+N Total Harmonic Distortionplus Noise

F in =1KHzP O = 1.5W, R L =4 P O = 0.9W, R L =8

0.150.06

%

F in =1KHz, C B=2.2 F, R L=8 , P O=0.92W 80Xtalk Channel Separation

F in =1KHz, C B=2.2 F, R L =4 , P O=1.5W 83dB

PSRR Power Supply RejectionRatio CB =2.2 F, R L =8 , F in =120Hz 70 dB

S/N P O =0.8W, R L =8 , A-weighted Filter 90 dB

Vn Noise Output Voltage Gain =10.5dB, R L =8 , C B =2.2 F 80 V(rms)Headphone mode

THD+N = 1%, F in =1KHzRL = 16 RL = 32 100

160120

Po Output Power THD+N = 10%, F in =1KHzRL =16 RL =32 150

200165

mW

THD+N=10% 2.9Vo Output Voltage Swing RL =10K

THD+N=1% 2.4 Vrms

Vos Output Offset Voltage RL =32 -10 +10 mV

THD+N Total Harmonic Distortionplus Noise

F in = 1KHzP O = 125mW, R L =16 P O = 88mW, R L =32 VO=1.7Vrms, R L=10k

0.020.02

0.005

%

F in =1KHz, R L =16 , P O =125mW 80F in =1KHz, R L =32 , P O =88mW 85Xtalk Channel Separation

F in =1KHz, R L=10K , VO =1.7Vrms 105dB

PSRR Power Supply RejectionRatio CB = 2.2 F, R L=32 ,F in =120Hz 80 dB


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Electrical Characteristics (Cont.)

APA2057ASymbol Parameter Test Condition

Min. Typ. Max. Unit

Headphone mode (Cont.)

S/N

With A-weighted Filter

P O = 70mW, R L =32 VO =1.2Vrms, R L=10k

95

92

dB

Vn Noise OutputVoltage C B =2.2 F 30V

(rms)

Rf Input FeedbackResistance 38 40 42 k

Charge Pump

Fosc Switching frequency 460 540 620 KHz

CVSS Charge DumpOutput Voltage(CVSS)

No load -0.98VDD V

ReqCharge pumprequirementresistance

9 12

Beep

Vbeep Beep trigger level 3 V PP

TRES Beep response time 4 ms

Attenuation

R L = 32 , VO = 1.1Vrms, F in = 1KHz 115 dB Att(HP_EN)

HP disableattenuation R L = 10K , VO = 1.1Vrms, F in = 1KHz 85 dB

R L = 8 , VO = 2Vrms, F in = 1KHz 112 dB Att(AMP_EN)

AMP disableattenuation R L = 4 , VO = 2Vrms, F in = 1KHz 112 dB

Att_SD(HP_EN) Shutdown activeR L = 10K on the Headphone Mode,VO = 1.1Vrms, F in = 1KHz

90 dB

Att_SD(AMP_EN) Shutdown activeR L = 8 on the AMP Mode, V O = 1Vrms,F in = 1KHz

100 dB

Headphone to Speaker Crosstalk

AMP_EN = 0V, R L = 8 Xtalk Channel Separation HP_EN = 5V, R L = 16 , F in = 1KHz,

P O = 125mW

85 dB

Speaker to Headphone Crosstalk

HP_EN = 5V, R L = 10K Xtalk Channel Separation AMP_EN = 0V, R L = 4 , F in = 1KHz,

P O = 1.5W

80 dB

Amplifier Start up Time

Tstart-up Start up time 120 msec


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Gain Setting Table _AMP Mode

Input Voltage (V SE T )Gain (dB)Low (V) High (V)

Hysteresis (mV) Recommended Voltage(V )

-70 0 2.00 SD 0.00

-7 2.04 2.12 47 2.08

-5 2.15 2.24 36 2.20

-3 2.28 2.35 41 2.31

-1 2.39 2.47 41 2.43

1 2.51 2.58 35 2.54

3 2.62 2.70 41 2.66

4 2.74 2.81 48 2.78

5 2.86 2.92 43 2.89

6 2.97 3.04 47 3.01

7 3.09 3.15 45 3.12

8 3.21 3.27 54 3.24

9 3.33 3.39 59 3.36

10 3.45 3.51 64 3.48

11 3.56 3.62 53 3.59

12 3.68 3.73 59 3.70

13 3.80 3.85 66 3.82

14 3.92 3.96 69 3.94

15 4.02 4.07 64 4.05

16 4.15 4.17 76 4.16

10.5 4.26 5.00 94 5.00

Gain (dB) R1 (1%) R# (1%)

-70 10K 0

-7 18K 13K

-5 20K 16K

-3 18K 16K

-1 16K 15K

1 15K 16K

3 13K 15K

4 24K 30K

5 13K 18K

6 13K 20K

7 13K 22K

8 16K 30K

9 13K 27K

10 13K 30K

11 15K 39k

12 13K 39K

13 13K 43K

14 13K 50K

15 15K 68K

16 13K 68K

10.5 10K >90K

(VDD=5V)

Recommend Resistances Value for Gain Setting

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T H D + N ( % )

Output Power (W) Output Power (W)

T H D + N ( % )

C r o s s

t a l k ( d B )

T H D + N ( % )

THD+N vs. Output Power

Frequency (Hz) Frequency (Hz)


THD+N vs. Frequency Crosstalk vs. Frequency

O u t p u

t N o i s e

V o l

t a g e

( V r m s )

Frequency (Hz)

Output Noise Voltage vs. Frequency

G a i n

( d B )

Frequency Response

P h a s e

( d e g

)

Frequency (Hz)

Typical Operating Characteristics

0.05

10

0.1

1

0 30.5 1 1.5 2 2.5

VDD =5VF in=1KHzC in=2.2 FBW

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T H D + N ( % )

Output Power (W) Frequency (Hz)

T H D + N ( % )

O u t p u

t N o i s e

V o l

t a g e

( V r m s )

C r o s s

t a l k ( d B )



THD+N vs. Frequency

Crosstalk vs. Frequency Output Noise Voltage vs. Frequency

G a i n

( d B )

Frequency (Hz)

Frequency Response

C r o s s

t a l k ( d B )

Crosstalk vs. Frequency

Frequency (Hz)

P h a s e

( d e g

)

Typical Operating Characteristics (Cont.)

0.05

10

0.1

1

0.01 50.1 1

VDD =5VR L=8 C in=2.2 FBW

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A M P A t t e n u a t

i o n

( d B )


A M P A t t e n u a t

i o n

( d B )

S h u t d o w n A

t t e n u a t

i o n

( d B )

S h u t d o w n A

t t e n u a t

i o n

( d B )

AMP Attenuation vs. Frequency


AMP Attenuation vs. Frequency

Shutdown Attenuation vs. Frequency Shutdown Attenuation vs. Frequency

O u t p u

t V o l

t a g e

( V r m s )

Input Voltage (Vrms)

Input Voltage vs. Output Voltage

O u t p u

t V o l

t a g e

( V r m s )




-120

+0

-110

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

20 20k100 1k 10k

VDD =5VRL=4 C in=2.2 FVO=2Vrms(F in=1KHz, AMP enable)

AMP mode (disable)

-120

+0

-110

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

20 20k100 1k 10k

VDD =5VRL=8 C in=2.2 FVO=2Vrms(F in=1KHz,AMP enable)

AMP mode (disable)

-120

+0

-110

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

20 20k100 1k 10k

VDD =5VRL=4 C in=2.2 FVO=1Vrms(F in=1KHz)Shutdown active

AMP mode

-120

-110

-100

20 20k100 1k 10k

VDD =5VRL=8 C in=2.2 FVO=1Vrms(F in=1KHz)Shutdown active

AMP mode

+0

-90

-80

-70

-60

-50

-40

-30

-20

-10

3.5

0.5

1

1.5

2

2.5

3

0 1.50.3 0.6 0.9 1.2

VDD =5VRL=4C in=2.2 FF in=1KHz

AMP mode

0

4

0.5

1

1.5

2

2.5

3

3.5

1.50.3 0.6 0.9 1.2

VDD =5VR L=8C in=2.2 FF

in=1KHz

AMP mode

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T H D + N ( % )

Output Voltage (Volt) Output Power (W)

T H D + N ( % )

T H D + N ( % )

T H D + N ( % )

THD+N vs. Output Voltage



THD+N vs. Output Power THD+N vs. Frequency

C r o s s

t a l k ( d B )

Frequency (Hz)

Crosstalk vs. Frequenc y

O u t p u

t N o i s e

V o l

t a g e

( V

r m s )


Frequency (Hz)


0.001

10

0.01

0.1

1

30.5 1 1.5 2 2.50

TT

RL=10K

RL=300

RL=32

RL=16

VDD =5VHVDD=3.3VF in=1KHzC in=3.3 FBW

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G a i n (

d B )

Frequency (Hz) Output Power (W)

T H D + N ( % )

T H D + N ( % )

T H D + N ( % )

Frequency Response



THD+N vs. Output Power THD+N vs. Frequency

C r o s s

t a l k ( d B )

Frequency (Hz)


O u t p u

t N o i s e

V o l

t a g e

( V )


Frequency (Hz)

P h a s e

( d e g

)


+170

+190

+175

+180

+185

-0.2

+0.2

-0.1

-0

+0.1

10 200k100 1k 10k 100k

Gain

Phase

VDD=5VHVDD=3.3VRL=16 R in=39K C in=3.3 FP O=28mWHP mode

0.01

10

0.1

1

1m 200m10m 100m

F in=20KHz

F in=20Hz

F in=1KHz

VDD=5VHVDD=3.3VRL=32 R in=39K C in=3.3 FBW

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G a i n

( d B )

Frequency (Hz) Output Voltage (Vrms)

T H D + N ( % )

C r o s s

t a l k ( d B )

T H D + N ( % )

Frequency Response



THD+N vs. Frequency Crosstalk vs. Frequency

O u t p u

t N o i s e

V o l

t a g e

( V r m s )

Frequency (Hz)


G a i n

( d B )

Frequency Response

Frequency (Hz)

P h a s e

( d e g

)

P h a s e

( d e g

)


+170

+190

+175

+180

+185

-0.2

+0.2

-0.1

-0

+0.1

10 200k100 1k 10k 100k

VDD =5VHVDD=3.3VRL=32 R in=39K C in=3.3 FP O=13mWHP mode

Gain

Phase

0.001

10

0.01

0.1

1

0 30.5 1 1.5 2 2.5

F in=20Hz

F in=20KHz

F in=1KHz

VDD=5VHVDD=3.3VRL=300 R in=39K C in=3.3 FBW

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T H D + N ( % )

Output Voltage (Volt) Frequency (Hz)

T H D + N ( % )

O u t p u

t N o i s e

V o l

t a g e

( V r m s )

C r o s s

t a l k ( d B )



THD+N vs. Frequency

Crosstalk vs. Frequency Output Noise Voltage vs. Frequency

G a i n

( d B )

Frequency (Hz)

Frequency Response

C r o s s

t a l k ( d B )


Frequency (Hz)


P h a s e

( d e g

)

0.001

10

0.01

0.1

1

0 30.5 1 1.5 2 2.5

F in=20Hz

F in=20KHz

F in=1KHz

VDD =5VHVDD=3.3VRL=10K R in=39K C in=3.3 FBW

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H P a t

t e n u a t

i o n

( d B )


H P a t

t e n u a t

i o n

( d B )

S h u t d o w n a t

t e n u a t

i o n

( d B )

S h u t d o w n a

t t e n u a t

i o n

( d B )

HP attenuation vs. Frequency


HP attenuation vs. Frequency

Shutdown attenuation vs. Frequency Shutdown attenuation vs. Frequency

O u t p u

t V o l

t a g e

( V r m s

)



O u t p u

t V o l

t a g e

( V r m s

)




-120

+0

-110

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

20 20k100 1k 10k

VDD =5VHVDD=3.3VRL=32 C in=3.3 FVO=1Vrms(F in=1KHz HP enable)HP mode (disable)

Right channel

Left channel

-100

+0

-90

-80

-70

-60

-50

-40

-30

-20

-10

20 20k100 1k 10k

VDD =5VHVDD=3.3VRL=10K C in=3.3 FVO=1Vrms(F in=1KHz HP enable)HP mode (disable)

Left channelRight channel

-140

+0

-130

-120

-110

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

20 20k100 1k 10k

VDD =5VHVDD=3.3VRL=32 C in=3.3 FVO=1Vrms(F in=1KHz)Shutdown activeHP mode

Left channel

Right channel-130

+0

-120

-110

-100

-90

-80-70

-60

-50

-40

-30

-20

-10

20 20k100 1k 10k

VDD =5VHVDD=3.3VRL=10K C in=3.3 FVO=1Vrms(F in=1KHz)Shutdown activeHP mode

Left channel

Right channel

0

2.5

0.5

1

1.5

2

0 2.50.5 1 1.5 2

Stereo, inphase

Mono

VDD =5VHVDD=3.3VRL=16

R in=39K C in=3 FF in=1KHzHP mode

0

3

0.5

1

1.5

2

2.5

0 30.5 1 1.5 2 2.5

VDD =5VHVDD=3.3VRL=32

R in=39K C in=3 FF in=1KHzHP mode Stereo, in

phase

Mono

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O u t p u

t V o l

t a g e

( V r m s )

Input Voltage (Vrms) Input Voltage (Vrms)

O u t p u

t V o l

t a g e

( V r m s )

Input Voltage vs. Output Voltage Input Voltage vs. Output Voltage

PSRR vs. Frequency PSRR vs. Frequency

P S R R ( d B )

Frequency (Hz)

PSRR vs. Frequency

P S R R ( d B )

PSRR vs. Frequency

Frequency (Hz)

P S R R

( d B )

P S R R

( d B )



0

3

0.5

1

1.5

2

2.5

0 30.5 1 1.5 2 2.5

Mono &Stereo, in phase

VDD =5VHVDD=3.3VRL=10K R in=39K C in=3 FF in=1KHzHP mode

-100

+0

-90

-80

-70

-60

-50

-40

-30

-20

-10

20 20k100 1k 10k

Right channel

Left channel

VDD=5VRL=4C in=2.2 FVrr=200mVrms

AMP mode

Vrr: Ripple Voltage on V DD

20 20k100 1k 10k

VDD =5VRL=8 C in=2.2 FVrr=200mVrms

AMP mode

Right channel

Left channel

-100

+0

-90

-80

-70

-60

-50

-40

-30

-20

-10

Vrr: Ripple Voltage on V DD

-100

+0

-90

-80

-70

-60

-50

-40

-30-20

-10

20 20k100 1k 10k

Left channel

Right channel

VDD =5VHVDD=3.3VRL=32 R

in=39K

C in=3.3 FVrr=200mVrmsHP mode

Vrr: Ripple Voltage on HV DD-100

+0

-90

-80

-70

-60

-50

-40

-30

-20

-10

20 20k100 1k 10k

VDD =5VHVDD=3.3VRL=10K

R in=39K C in=3.3 FVrr=200mVrmsHP mode

Left channel

Right channel Vrr: Ripple Voltage on HV DD

0

3

0.5

1

1.5

2

2.5

0 30.5 1 1.5 2 2.5

Stereo,in phase

Mono

VDD =5VHVDD=3.3VRL=300 R in=39K C in=3 FF in=1KHzHP mode

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APA2057A

S u p p l y

C u r r e n t

( m A )

Supply Voltage (Volt) Supply Voltage (Volt)

S h u t d o w n

C u r r e n t

( A )

Supply Current vs. Supply Voltage Shutdown Current vs. Supply Voltage

Power Dissipation vs. Output Power Power Dissipation vs. Output Power

Output Power vs Load ResistanceOutput Power vs Load Resistance &

Charge Pump Capacitance

P o w e r

D i s s

i p a t

i o n

( W )

P o w e r

D i s s i p a t

i o n

( m W )

Output Power (W) Output Power (mW)

O u t p u

t P o w e r

( m W )

O u t p u

t P o w e r

( m W )

Load Resistance ( ) Load Resistance ( )


24

6

8

10

12

14

16

18

20

3.0 3.5 4.0 4.5 5.0 5.5

No Load

HP Mode

AMP Mode

*HP Mode disableHVDD=3.3VIHVDD=0.15mA

**AMP Mode disableVDD=5VIVDD=12mA

0

10

20

30

40

50

3.0 3.5 4.0 4.5 5.0 5.5

Amp modeHP modeNo Load

ISD(VDD)

ISD(HVDD)

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

0.0 0.5 1.0 1.5 2.0

VDD =5VTHD+N

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APA2057A

Output Transient at Turn Off

Output transient at Shutdown ReleaseOutput Transient at Turn On

Output transient at Shutdown Active

Operating Waveforms

AMP_Out

((Out+)-(Out-))

VDD

HP_Out

5V/div

10mV/div

20mV/div

SD

HP_Out

AMP_Out

((Out+)-(Out-))

5V/div

10mV/div

20mV/div

VDD

HP_Out

AMP_Out

((Out+)-(Out-))

5V/div

10mV/div

20mV/div AMP_Out

((Out+)-(Out-))

HP_Out

5V/div

10mV/div

20mV/div

SD

20ms/div

200ms/div

20ms/div

20ms/div

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APA2057A

TSSOP-28 TQFN-28

NO. NO.Name Function Description

1 25 VDD Power supply for control section

2 26 GND Ground

3 27 INR_A Right channel input terminal for speaker amplifier

4 28 INR_H Right channel input terminal for headphone driver

5 1 INL_A Left channel input terminal for speaker amplifier

6 2 INL_H Left channel input terminal for headphone driver

7,23 3,19 PGND Power ground

8 4 LOUT+ Left channel positive output for speaker

9 5 LOUT- Left channel negative output for speaker

10,20 6,16 PVDD Power amplifier power supply11 7 CVDD Charge pump power supply

12 8 CP+ Charge pump flying capacitor positive connection

13 9 CGND Charge pump ground

14 10 CP- Charge pump flying capacitor negative connection

15 11 CVSS Charge pump output, connect to the HVSS

16 12 HVSS Headphone amplifier negative power supply

17 13 HP_R Right channel output for headphone

18 14 HP_L Left channel output for headphone

19 15 HV DD Headphone amplifier positive power supply

21 17 ROUT- Right channel negative output for speaker

22 18 ROUT+ Right channel positive output for speaker 24 20 HP_EN Headphone driver enable pin, pull high to enable headphone mode

25 21 BIAS Bias voltage generator

26 22 SETIt has 19 steps gain setting control from 2.0~4.2V; pull high to 5V is 10.5dB fixgain and pull low to 0V, the APA2057A enter shutdown mode. I SD = 80 A

27 23 AMP_EN Speaker driver enable pin, pull low to enable speaker mode

28 24 BEEP PC BEEP Trigger signal input

Pin Descriptions

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APA2057A

Block Diagram

ChargePump

SPK EN

HP EN

INR_A

INL_A

INR_H

INL_H

SET

BIAS

CP+

CP-

CVSS

HP_R

HP_L

AMP_EN

HP_EN

SET

HVSS

*40k

*40k

HVDD

Power Mamagement PVDD

VDD

CVDD

Internal gainsetting

CGND

PGND GND

ROUT-

ROUT+

LOUT-

LOUT+

* The internal Rf's value has10% variation by process

R f(HP_R)

R f(HP_L)

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APA2057A

Typical Application Circuit

R#: For the gain setting of speaker driver thatyou need, refer to the Gain Setting Tablesrecommended voltage, and setting this voltageat SET pins voltage =5R #/(R #+10K).

Ring

Headphone Jack

Sleeve

Tip

R_CH

R_ch

for AMP

L_ch

for AMP

R_ch

for HP

39K

2.2 F

2.2 F

4

ChargePump

SPK EN

HP EN

INR_A

INL_A

INR_H

INL_H

SET

BIAS

CP+

CP-

CVSS

HP_R

HP_L

AMP_EN

HP_EN

SET

HVSS

*40K

*40K

HVDD

Power Management PVDD

VDD

CVDD

Internalgain

setting

CGND

PGND GND

ROUT-

ROUT+

2.2 F

3.3 F

L_ch

for HP

39K 3.3 F

1F

1F

L_CH

4

LOUT-

LOUT+

1F

0.1 F

0.1 F

10 F

0.1 F

C i(AMP_R)

C i(AMP_L)

C i(HP_R)

C i(HP_L)

R i(HP_R)

R i(HP_L)

R f(HP_R)

R f(HP_L)

CCPB CCPF

CCPO

10nF

VDD(5V)

10K

R#Shutdown

VDD(5V)

VDD(5V) HVDD(3.3V)

VSS

51k

4.7nF

Recommended for de-pop

C B

SET Pull-high HP_EN to enableheadohone driver

R1

CS(VDD)

CS(PVDD) CS(HVDD)

CVDD

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APA2057A

Amplifier Mode OperationThe APA2057A has two pairs of operational amplifiersinternally, which allows different amplifier configurations.

Figure 1: APA2057A internal configuration(each channel)

The OP1 and OP2 are all differential drive configurations.The differential drive configurations doubling the voltageswing on the load. Compare with the single-endingconfiguration, the differential gain for each channel is 2X

(Gain of SE mode).

By driving the load differentially through outputs OUT+and OUT-, an amplifier configuration commonly referredto all differential mode is established. All differential modeoperation is different from the classical single-ended SEamplifier configuration where one side of its load is con-nected to ground.

A differential ampli fier design has a few distinct advan-tages over the SE configuration, as it provides differentialdrive to the load, thus it is doubling the output swingfor a specified supply voltage. The output power can be4 times greater than the SE amplifier working under thesame condition. A differential configuration, similar as theone used in APA2057A, also creates a second advantageover SE amplifiers. Since the differential outputs, ROUT+,ROUT-, LOUT+, and LOUT-, are biased at half-supply,there is no need for DC voltage across the load. Thiseliminates the need for an output coupling capacitor whichis required in a single supply, SE configuration.

The APA2057As headphone amplifiers uses a chargepump to invert the positive power supply (CV DD) to negativepower supply (CV SS ), see Figure2. The headphone am-plifiers operate at this bipolar power supply (HV DD & VSS ),and the outputs reference refers to the ground. This fea-ture eliminates the output capacitor that is using in con-ventional single-ended headphone amplifier. The head-phone amplifier internal supply voltage comes from HV DDand V SS . For good AC performance, the HV DD connected to3.3V is recommended. It can avoid the output over volt-age for line out application.

Charge Pump Flying Capacitor The flying capacitor (C CPF ) affects the load transient of thecharge pump. If the capacitors value is too small, thenthat will degrade the charge pumps current driver capa-bility and the performance of headphone amplifier.

Increasing the flying capacitors value will improve theload transient of charge pump. It is recommend to usethe low ESR ceramic capacitors (X7R type is recommended)above 1 f.

Figure 2: Cap-free Operation

Pre-amplifier Output signal

Vbias

OP1

OP2

-

+

-

+OUT+

OUT-DIFF_AMP_CONFIG

Headphone Mode Operation

Application Information

HVDD

HVDD/2

GND

VOUT

HVDD

VSS

GNDVOUT

Conventional Headphone amplifier

Cap-free Headphone amplifier

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APA2057A

The HP_EN will detect the voltage. If the voltage isless than 0.8V, the headphone amplifiers will be disabled;if greater than 2V, then the headphone amplifier will beenabled.

In Figure 3, phone-jack with the control pin is used andconnected to HP_EN input from control pin. When aheadphone plug is inserted, the HP_EN will pull highinternally which enables headphone amplifiers; with-out headphone plug, the HP_EN is pulled to GND.

Operation Mode

The APA2057A amplifier has two pairs of independentamplifier. One for stereo speaker is BTL structure, andthe other for headphone is cap-less structure. Each pair has independent input pin; INR_A and INA_L are for ste-reo speaker drivers, and INR_H and INL_H are for stereo headphone drivers.

Amplif ier mode operat ion: Pull low the AMP_ENcontrol pin can enable the stereo speaker driver.

Headphone mode operation: Pull high the HP_ENcontrol pin can enable the cap-less headphone

drive.

Both amplifier and headphone ON mode: Pull lowthe AMP_EN and pull high the HP_EN control pins,then turn on both speaker drivers and headphonedrivers

Both amplifier and headphone OFF mode: Pullhigh the AMP_EN and pull low the HP_EN controlpins, then turn off both speaker drivers and head-phone drivers

If the AMP_EN and HP_EN are connected together, thenthis pin will be connected to headphone jacks controlpin (Figure 3), the APA2057A is switchable between Am-plifier mode (Headphone mute), or Headphone mode(Amplifier mute).

Gain Setting

The gain for speaker drivers can be adjustable by apply-ing DC voltage to SET pin. The APA2057A control con-sists 19 step gain settings from 2.0V~ 4.2V, and the gainis from -7dB to 16dB. Each gain step corresponds to aspecific input voltage range, as shown in Gain SettingTable . To minimize the effect of noise on the gain settingcontrol, which can affect the selected gain level, hyster-

esis and clock delay are implemented. For the highestaccuracy, the voltage shown in the recommended volt-age column of the table is used to select a desired gain.This recommended voltage is exactly halfway betweenthe two nearest transitions. The amount of hysteresiscorresponds to half of the step width, as shown in Fig-ure 4. Apply 0V to SET pin will place the APA2057A intoshutdown mode, and when SD =5V, it allows the speaker driver at a fixed gain (A V=10.5dB).

Figure 3 HPD configurations

Charge Pump Output Capacitor

The output capacitor (C CPO )s value affects the power ripple directly at CV SS (VSS ). Increasing the value of outputcapacitor reduces the power ripple. The ESR of outputcapacitor affects the load transient of CV SS (VSS ). Lower ESR and greater than 1 f ceramic capaci tor (X7R typeis recommended) is recommendation.

Charge Pump Bypass Capacitor

The bypass capacitor (C CPB ) relates with the charge pumpswitching transient. The capacitors value is same asflying capacitor (1 f). Place it close to the CV DD and PGND.

Headphone Detection Input

Application Information (Cont.)

Figure 4: APA2057A Gain setting vs. SET pin Voltage

DC Volume (V)

G a i n

( d B )

0.0 1.0 2.0 3.0 4.0 5.0-70

-60

-50

-40

-30

-20

-10

0

10

20

Forward

Backward

Ring

Headphone Jack with swich

Sleeve

Control pin

Tip

HP_ENHPD_Switch

HP_L

HP_R

1K

1K

Headphone Detection

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APA2057A

HP Mode Gain Setting Table for ReferenceR i(HP) ,external

(k)*Rf(HP) ,internal

(k) HP OUT (V/V) HP Gain(dB)

62 40 0.65 -3.850 40 0.80 -1.939 40 1.03 0.2

30 40 1.33 2.524 40 1.67 4.420 40 2.00 6.0

*The internal Rf's value has 10% variation by process.

Consider to input resistance variation, the C i is 1.6 F, so

one would likely choose a value in the range of 2.2 Fto 3.3 F. A further consideration for this capacitor isthe leakage path from the input source through the inputnetwork (R i+R f , C i) to the load. This leakage currentcreates a DC offset voltage at the input to the amplifier that reduces useful headroom, especially in high gainapplications. For this reason, a low-leakage tantalum or ceramic capacitor is the best choice. When polarizedcapacitors are used, the positive side of the capaci tor should face the amplifier input. As the DC level is heldat V DD/2, which is likely higher than the source DC level.

(2)

Please note that it is important to confirm the capaci-tor polarity in the application.

Note: The headphone dirvers input is ground reference,so please check the C

i(HP)s polarized at design.

Effective Bias Capacitor, C B

As with any power amplifier, proper supply bypassing iscritical for low noise performance and high power supplyrejection.

The capacitor location on both the bypass and power supply pins should be as close to the device as possible.

The effect of a larger bypass capacitor is improved PSRRdue to increased 1.8V bias voltage stability. Typicalapplications employ a 5V regulator with 2.2 F and a0.1 F bypass capacitor, which aids in supply filtering.This does not eliminate the need for bypassing thesupply nodes of the APA2057A. The selection of by-pass capacitors, especia lly C B, is thus dependent upondesired PSRR requirements and click-and-popperformance.

Power Supply Decoupling, C s

The APA2057A is a high-performance CMOS audio amplifier that requires adequate power supply decoupling toensure the output tot al harmonic distortion (THD+N)is as low as possible. Power supply decoupling al soprevents the oscillations causing by long lead lengthbetween the amplifier and the speaker. The optimumdecoupling is achieved by using two different typesof capaci tor that target on different types of noise on thepower supply leads. For higher frequency transients,spikes, or digital hash on the line, a good low equivalent-series-resistance (ESR) ceramic capacitor, typically0.1 F, is placed as close as possible to the device V DDlead works best (the pin1 (V

DD) and pin2 (GND)s capaci-

tor must short less than 1cm). For filtering lower-frequencynoise signals, a large aluminum electrolytic capacitor of 10 F or greater is placed near the audio power amplifier is recommended.

Shutdown Function

In order to reduce power consumption while not in use,the APA2057A contains a shutdown pin to externally turnoff the amplifier bias circuitry. This shutdown featureturns the amplifier off when a logic low is placed on the


Input Capacitor, C i

In the typical application, an input capacitor, C i, is requiredto allow the amplifier to bias the input signal to the proper DC level for optimum operation. In this case, C i and theminimum input impedance Ri from a high-pass filter withthe corner frequency are determined by the following

equation:

The value of Ci is important to consider as it directlyaffects the low frequency performance of the circuit.Consider the example where R i is 10k and thespecification calls for a flat bass response down to10Hz. Equation is reconfigured as below:

For headphone driver, the internal feedback resistor is40k (R f(HP) external, 10% variation by process), so theheadphone drivers gain is set by the input resistor (R i(HP)external), the Table 1 lists the reference gain settingswith external resistor for headphone driver (HP Mode).

Table 1: Gain Setting Table for Reference

Gain Setting (Cont.)

)CR(21

=(highpass)Fii(MIN)

C

(1)

Fc)R(21

=Ci

i

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APA2057A

(5)

(7)

(6)

Shutdown Function (Cont.)

(4)

Table 1 calculates efficiencies for four different output

PsupPOEfficiency = (3)

4V R

R

2V*V/

2R )V*(V

PsupP

DD

L

L

PDD

L

PPO =

=

L

PP

L

OOO 2R

)V*(VR

rmsV*rmsVP ==

Where:

2

VrmsV PO =

R2V

*V=(AVG)I*V=PsupL

PDDDDDD

Efficiency of a Differential configuration:Since the APA2057A is a dual channel power amplifier,the maximum internal power dissipation is 2 times thatboth of equations depending on the mode of operation.Even with this substantial increasing in power dissipation,the APA2057A does not require extra heatsink. The

A final point to remember about linear amplifiers is howto manipulate the terms in the efficiency equation toutmost advantage when possible. Note that in equation,VDD is in the denominator. This indicates that as V DD goesdown, efficiency goes up. In other words, using the effi-ciency analysis to choose the correct supply voltageand speaker impedance for the application.

Power Dissipation

Whether the power amplifier is operated in BTL or SEmodes, power dissipation is a major concern. Equation 8states the maximum power dissipation point for a SEmode operating at a given supply voltage and driving aspecified load.

SE mode:

In BTL mode operation, the output voltage swing isdoubled as in SE mode. Thus the maximum power dissipation point for a BTL mode operating at the samegiven conditions is 4 times as in SE mode.

BTL mode:

R2V

=PL

2DD

MAXD, (8)

Rp24V

=PL

2

2DD

MAXD,(9)


SET pin. The trigger point between a logic high and logiclow level is typically 2.0V. It is the best to switch be-tween ground and the supply V DD to provide maximumdevice performance.

By switching the SET pin to low, the amplifier enters alow-current consumption state, I DD

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APA2057A

Thermal Considerations

Linear power amplifiers dissipate a significant amountof heat in the package under normal operating conditions.

In the Power Dissipation vs. Output Power graph, the APA2057A is operating at a 5V supply and a 4 speaker that 2W output power peaks are available. The verticalaxis gives the information of power dissipation (P D) inthe IC with respect to each output driving power (P O) onthe horizontal axis.

This is valuable information when attempting to estimatethe heat dissipation of the IC requirements for theamplifier system.

Using the power dissipation curves for a 5V/4 system,the internal dissipation in the APA2057A and maximumambient temperatures is shown in Table 3.


For TSSOP-28 package with thermal pad, the thermalresistance ( JA) is equal to 45 oC/W.

Since the maximum junction temperature (T J,MAX) of APA2057A is 150 C and the ambient temperature (T A) isdefined by the power system design, the maximum power

dissipation that the IC package is able to handle can beobtained from equation10. Once the power dissipation isgreater than the maximum limit (P D,MAX), either the supplyvoltage (V DD) must be decreased, the load impedance(R L) must be increased or the ambient temperatureshould be reduced.

Thermal Pad Considerations

The thermal pad must be connected to ground. Thepackage with thermal pad of the APA2057A requiresspecial attention on thermal de sign. If t he thermal de-

sign issues are not properly addressed, the APA2057A4 will go into thermal shutdown when driving a 4 load.The thermal pad on the bottom of the APA2057A shouldbe soldered down to a copper pad on the circuit board.Heat can be conducted away from the thermal pad throughthe copper plane to ambient. If the copper plane is not onthe top surface of the circuit board, 8 to 10 vias of 15 mil or smaller in diameter should be used to thermally couplethe thermal pad to the bottom plane. For good thermalconduction, the vias must be plated through and solder filled. The copper plane used to conduct heat away from

the thermal pad should be as large as practical.If the ambient temperature is higher than 25 C, a larger copper plane or forced-air cooling will be required to keepthe APA2057A junction temperature below the thermalshutdown temperature (150 C).

In higher ambient temperature, higher airflow rate and/or larger copper area will be required to keep the IC out of thermal shutdown. See Demo Board Circuit Layout asan example for PCB layout.

power dissipation from equation 9, assuming a 5V-power supply and an 8 load, must not be greater thanthe power dissipation that results from the equation 9:

(10)JA

AMAXJ,MAXD,

T-T =P

Power Dissipation (Cont.)

15 mil

12mil

Via diameter

=25mil X4Via diameter =15mil X10

Ground plane for ThermalPAD

70 mil 70 mil180 mil120 mil

2 4 0 m

i l

Exposed for thermalPAD connected

Figure 5: TSSOP-28P layout recommendation

Max. T A (C)Peak outputpower (W)

Averageoutput

power (W)

Power dissipation(W/channel) With thermal pad

2 1.95 1.25 37

2 1.17 1.25 37

2 0.74 1.19 43

2 0.43 1.05 55

2 0.19 0.8 78

Table 3: APA2057A Power information, 5V/4 , Stereo, Differential mode

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APA2057A

Thermal Considerations (Cont.)

Table 3 shows that for some applications, no airflow isrequired to keep junction temperatures in the specifiedrange. The APA2057A is designed with a thermal shut-down protection that turns the device off when the junctiontemperature surpasses 150 C to prevent IC from

damage. The information in table 3 was calculated for maximum listen volume with limited distortion. Whenthe output level is reduced, the numbers in the tablechange significantly. Also, using 8 speakers will dra-matically increase the thermal performance by increasingamplifier efficiency.


150 - 45(0.8*2) = 78 C (with thermal pad)NOTE: Internal dissipation of 0.8W is estimated for a 2W system

with 15-dB headroom per channel.

P-T=T DJAMaxJ,Max A, (11)

This parameter is measured with the recommendedcopper heat sink pattern on a 2-layer PCB, 23cm 2

in 5.7mm *4mm in PCB, 2oz. Copper, 100mm 2

coverage. Airflow 0 CFM the maximum ambient tem-perature depends on the heat sink ability of the PCBsystem.

To calculate maximum ambient temperatures, firstconsiderati on is that the numbers from the dissipationgraphs are per channel values, so the dissipation of theIC heat needs to be doubled for two-channel operation.

Given JA , the maximum allowable junction temperature(TJ,Max ), and the total intemal dissipation (P D), the maximumambient temperature can be calculated with the followingequation. The maximum recommended junctiontemperature for the APA2057A is 150 C. The internaldissipation figures are taken from the Power Dissipation

vs. Output Power graph.

Package JA

TSSOP-28 45 C/WTQFN -28 43 C/W

Table 4: Thermal resistance Table

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APA2057A

Package Information

TSSOP-28P

Note : 1. Followed from JEDEC MO-153 AET.2. Dimension "D" does not include mold flash, protrusions

or gate burrs. Mold flash, protrusion or gate burrs shall notexceed 6 mil per side.

3. Dimension "E1" does not include inter-lead flash or protrusions.Inter-lead flash and protrusions shall not exceed 10 mil per side.

S YMB

OL MIN. MAX.

1.20

0.05

0.09 0.20

9.60 9.80

0.15

A

A1

c

D

E

e

L

MILLIMETERS

b 0.19 0.30

0.65 BSC

TSSOP-28P

0.45 0.75

0.026 BSC

MIN. MAX.

INCHES

0.047

0.002

0.007 0.012

0.004 0.008

0.378 0.386

0.169 0.177

0.018 0.030

0

0.006

A2 0.80 1.05

4.30 4.50E1

6.40 BSC 0.252 BSC

0.031 0.041

3.30D1 0.130

E2 1.50 0.059

7.00

4.00

0.276

0.157

INCHES

8 0 80

0VIEW A

0 . 2 5

SEATING PLANEGAUGE PLANE

SEE VIEW A

E 1

E

b c

A 2 A

e

A 1 L

E 2EXPOS

ED PAD

D1

D

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APA2057A

Package Information

TQFN5x5-28

AD

E

A1

A3

Pin 1Corner

E 2

L

D2

e

b

S YMBOL MIN. MAX.

0.80

0.00

0.18 0.30

3.50 3.80

0.05

3.50

A

A1

b

D

D2

E

E2

e

L

MILLIMETERS

A3 0.20 REF

TQFN5x5-28

0.35 0.45

3.80

0.008 REF

MIN. MAX.

INCHES

0.031

0.000

0.007 0.012

0.138 0.150

0.138

0.014 0.018

0.70

0.150

0.028

0.002

5.00 BSC 0.197 BSC

5.00 BSC 0.197 BSC

0.50 BSC 0.020 BSC

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APA2057A

Application A H T1 C d D W E1 F

330.0 2.00 50 MIN. 16.4+2.00-0.0013.0+0.50

-0.20 1.5 MIN. 20.2 MIN. 16.0 0.30 1.75 0.10 7.5 0.10

P0 P1 P2 D0 D1 T A0 B0 K0TSSOP-28P

4.0 0.10 8.0 0.10 2.0 0.10 1.5+0.10-0.00 1.5 MIN.0.6+0.00

-0.406.90 0.20 10.2 0.20 1.50 0.20

Application A H T1 C d D W E1 F

330.0 2.00 50 MIN. 16.4+2.00-0.0013.0+0.50

-0.20 1.5 MIN. 20.2 MIN. 12.0 0.30 1.75 0.10 5.5 0.10

P0 P1 P2 D0 D1 T A0 B0 K0TQFN5x5-28

4.0 0.10 12.0 0.10 2.0 0.10 1.5+0.10-0.00 1.5 MIN.0.6+0.00

-0.405.30 0.20 5.30 0.20 1.30 0.20

(mm)

Carrier Tape & Reel Dimensions

Package Type Unit QuantityTSSOP- 28P Tape & Reel 2000TQFN5x5-28 Tape & Reel 2500

Devices Per Unit

A

E 1

AB

W

F

T

P0OD0

B A0

P2

K0

B 0

SECTION B-B

SECTION A-A

OD1

P1

H

T1

A

d

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Test item Method DescriptionSOLDERABILITY MIL-STD-883D-2003 245 C, 5 secHOLT MIL-STD-883D-1005.7 1000 Hrs Bias @125 CPCT JESD-22-B,A102 168 Hrs, 100 %RH, 121 CTST MIL-STD-883D-1011.9 -65 C~150 C, 200 CyclesESD MIL-STD-883D-3015.7 VHBM > 2KV, VMM > 200VLatch-Up JESD 78 10ms, 1 tr > 100mA

Reflow Condition (IR/Convection or VPR Reflow)

Classification Reflow ProfilesProfile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly

Average ramp-up rate(TL to T P)

3C/second max. 3 C/second max.Preheat

- Temperature Min (Tsmin)- Temperature Max (Tsmax)- Time (min to max) (ts)

100 C150 C

60-120 seconds

150 C200 C

60-180 seconds

Time maintained above:- Temperature (T L)- Time (t L)

183 C60-150 seconds

217 C60-150 seconds

Peak/Classification Temperature (Tp) See table 1 See table 2Time within 5 C of actualPeak Temperature (tp) 10-30 seconds 20-40 seconds

Ramp-down Rate 6C/second max. 6 C/second max.Time 25 C to Peak Temperature 6 minutes max. 8 minutes max.

Notes: All temperatures refer to topside of the package. Measured on the body surface.

t 25 C to Peak

tp

Ramp-up

tL

Ramp-down

tsPreheat

Tsmax

Tsmin

TL

TP

25

T e m p e r a t u r e

Time

Critical ZoneTL to T P

Reliability Test Program

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Table 2. Pb-free Process Package Classification Reflow Temperatures

Package ThicknessVolume mm 3

2000

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