Copyright ANPEC Electronics Corp.Rev. B.1 - Apr., 2003

APA3541/4

www.anpec.com.tw1

ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advisecustomers to obtain the latest version of relevant information to verify before placing orders.

Class AB Stereo Headphone Driver with Mute

Ordering and Marking Information

Features

The APA3541/4 is an integrated class AB stereoheadphone driver contained in an SO-8 or a DIP-8plastic package with Mute feature . Besides the com-mon Mute feature , the APA3541/4 further integratesa voltage divider inside the chip . Thus , the externalresistors can be eliminated . The APA3541 has a fixedgain of 0dB and the APA3544 has a fixed gain of 6dBso that external gain setting is unnecessary. The de-vice is fabricated in a CMOS process and has beenprimarily developed for portable digital audio appli-cations .

High Signal-to-Noise Ratio

High Slew Rate

Low Distortion

Large Output Voltage Swing

Flexible Mute Function

Excellent Power Supply Ripple Rejection

Low Power Consumption

Short-circuit Elimination

Wide Temperature Range

No Switch ON/OFF Clicks

Integrated Voltage Divider (VDD/2) to Eliminate

External Resistors

Applications

Portable Digital Audio

General Description

A PA 3541/4 P ackage C ode J : P D IP - 8 K : S O P - 8

Y : C h ip F romT em p. R ange I : - 40 to 85 CH and ling C ode T U : Tube T R : T ape & R ee l

H and ling C ode

T em p. R ange

P ackage C ode

A P A 3541/4 J : A P A 3541/4X X X X X

X X X X X - D a te C ode

A P A 3541/4 K : A P A 3541/4X X X X X X X X X X - D a te C ode

Copyright ANPEC Electronics Corp.Rev. B.1 -Apr., 2003

APA3541/4

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Symbol Parameter Rating Unit

VDD Supply Voltage 7 V

tSC(O) Output Short-circuit Duration, at TA=25C, Ptot=1W 20 S

TA Operating Ambient Temperature range -40 to 85 C

TJ Maximum Junction Temperature 150 C

TSTG Storage Temperature Range -65 to +150 C

TS Soldering Temperature,10 seconds 300 C

VESD Electrostatic Discharge -3000 to 3000 *1 V

Pin Name I/O Function Description

Out A O A channel output pin

Mute I Chip disable control input, low active and high for normal operating

Input A I A channel input terminal

VSS Power ground pin

Input B I B channel input terminal

BIAS I Right channel bias input pin

OUT B O B channel output pin

VDD Power input pin

Absolute Maximum Ratings

Note: 1. Human body model : C=100pF, R=1500, 3 positive pulses plus 3 negative pulses

Function Pin Description

Block Diagram

Input B

Out B

BIAS

Mute

Out A

Input A BIAS

+

A B

+

1

2

3

4VSS 5

6

7

8 VDD

M UTE

0dB(6dB)

0dB(6dB)

180k(90k )

180k(90k )

* The values in parenthessis are for the APA3544.

Copyright ANPEC Electronics Corp.Rev. B.1 -Apr., 2003

APA3541/4

www.anpec.com.tw3

Symbol Parameter Rating UnitRTHJA Thermal Resistance from Junction to Ambient in Free Air

DIP-8 SOP-8

108210

K/W

RTHJC Thermal Resistance from Junction to Case DIP-8 SOP-8

4540

K/W

Electrical CharacteristicsV

IN=0dBV, V

CC=5V, T

A=25C, f=1kHz, R

L=32 (unless otherwise noted)

APM3541/4Symbol Parameter Test Condition

Min. Typ. Max.Unit

VDD Supply Voltage 3.0 5.0 6.0 V

IQ Quiescent Current VIN= 0 Vrms 3.5 5 mA

Imute Mute Current 200 A

VTM Mute Terminal Voltage 0.3 0.7 1.6 V

GVCLDifferential Channel

Voltage Gain-0.5 0 0.5 dB

Vin=1Vrms,f= 1kHz,RL=32 APA3541 -2 0 2GVCL Voltage Gain

Vin=0.5Vrms, f=1kHz,Rl=32 APA3544 4 6 8dB

THDTotal Harmonic Channel

Distortion FactorBW

Copyright ANPEC Electronics Corp.Rev. B.1 -Apr., 2003

APA3541/4

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Test and Application Circuit

+

B IAS

5 7

M UTE

6 8

VDD

0dB(6dB)

B

A

APA3541

(APA3544)

220F

1F

1F

100F

220F

1 0F

1F

100kV

INA

VDDOut BInput B BIAS

VINB

VMUTE

H : Speaker ActionL : M ute on

Out AM uteVSS

+

Input A

4 3 2 1

0dB(6dB)

Copyright ANPEC Electronics Corp.Rev. B.1 -Apr., 2003

APA3541/4

www.anpec.com.tw5

Typical Characteristics

Figure 1 : Supply Voltage : VDD

(V)

Quie

scent C

urr

ent :

I Q (m

A)

Figure 2 : Supply Voltage : VDD

(V)B

ias

DC

Volta

ge :V

bia

s (V

)

0

1

2

3

4

5

6

7

8

0 2 4 6 7531

MUTE : OFF

MUTE : ON

RL=32

0

1

2

3

4

5

0 2 4 6 71 3 5

RL=32

Figure 3 : Mute Control Voltage : VTM

(V)

Outp

ut V

olta

ge :

VO

UT (

dB

V)

Figure 4 : Frequency :f (Hz)

Volta

ge G

ain

: G

VC

(dB

)

10 100k100 1k 10k-12

+8

-10

-8

-6

-4

-2

+0

+2

+4

+6 APA3541

VDD

=5V

VIN

=0dBv

-80

-70

-60

-50

-40

-30

-20

-10

0

10

0 0.4 0.8 1.2 1.6 2

VDD

=5V

VIN

=0dBv

f =1 kHz

RL=32

Copyright ANPEC Electronics Corp.Rev. B.1 -Apr., 2003

APA3541/4

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-40 +10-30 -20 -10 +00.01

10

0.02

0.05

0.1

0.2

0.5

1

2

5

Typical Characteristics Cont.

Figure 7 : Output Voltage : VOUT

(dBv)

Tota

l Harm

onic

Dis

tort

ion :

TH

D+

N (

%)

Figure 8 : Output Voltage : VOUT

(dBv)

Tot

al H

arm

onic

Dis

tort

ion

: TH

D+

N (

%)

-40 +10-30 -20 -10 +00.01

10

0.02

0.05

0.1

0.2

0.5

1

2

5

f =10kHz

f =1kHz , 100Hz

VDD

= 3V

RL=16

BW< 80kHz

-40 +10-30 -20 -10 +00.01

10

0.02

0.05

0.1

0.2

0.5

1

2

5 VDD

= 5V

RL=16

BW< 80kHz

f =10kHz

f =1kHz , 100Hz

Figure 5 : Output Voltage : VOUT

(dBv)

Tota

l Harm

onic

Dis

tort

ion :

TH

D+

N(%

)

f =1kHz , 100Hz

f =10kHz

Output Voltage : VOUT

(dBv)Figure 6 :T

ota

l Harm

onic

Dis

tort

ion :

TH

D+

N

(%)

-40 +10-30 -20 -10 +00.01

10

0.02

0.05

0.1

0.2

0.5

1

2

5 VDD

= 3V

RL=32

BW< 80kHz

f =10KHz

f =1KHz , 100Hz

VDD

= 5V

RL=32

BW< 80kHz

Copyright ANPEC Electronics Corp.Rev. B.1 -Apr., 2003

APA3541/4

www.anpec.com.tw7

Typical Characteristics Cont.

Figure 11 : Supply Voltage : VDD

(V)

Rip

ple

Reje

ctio

n :

RR

(dB

)

fRR

=100Hz

VRR

=-20dBv

-1 0 0

-9 0

-8 0

-7 0

-6 0

-5 0

-4 0

-3 0

-2 0

-1 0

0

0 2 4 6 7531

Figure 9 : Frequency :f (Hz)

Cha

nnel

Sep

arat

ion

: CS

(dB

)

100k10 100 1k 10k-120

+0

-100

-80

-60

-40

-20V

DD=5V

RL=32

Figure 10 : Frequency :f (Hz)

Mute

Atte

nuatio

nt :

AT

T(d

B)

10 100k50100 1k 10k100

+0

-90

-80

-70

-60

-50

-40

-30

-20

-10 VDD=5V

VIN

=0dBv

RL=32

Copyright ANPEC Electronics Corp.Rev. B.1 -Apr., 2003

APA3541/4

www.anpec.com.tw8

Application Note

Input Capacitor , Ci

In the typical application an input capacitor , Ci , isrequired to allow the amplifier to bias the input signalto the proper DC level for optimum operation . In thiscase , the external capacitor Ci and the internal re-sistance Ri form a high-pass filter with the corner fre-quency determined in the follow equation:

fc (highpass)= 1/ (2RiCi) (1)The value of Ci is important to consider as it directlyaffects the low frequency performance of the circuit.Consider the APA3541 where Ri is 180k andAPA3544 is 90k internal fixed . Equation isreconfigured as follow:

Ci= 1/(2*180k*fc) for APA3541 Ci= 1/(2*90k*fc) for APA3544 (2)And the ceramic capacitor is recommanded.

Bias Capacitor , Cb

As with any power amplifier , proper supply bypass-ing is critical for low noise performance and highpower supply rejection . The capacitor location onboth the bypass and power supply pins should be asclose to the device as possible . The effect of a largerhalf supply bias capacitor is improved PSRR due toincreased half-supply stability . Typical applicationsemploy a 5V regulator with 10F and a 0 . 1F biascapacitors which aid in supply filtering .

This does not eliminate the need for bypassing thesupply nodes of the APA3541/4 . The selection ofbias capacitors , especially Cb , is thus dependentupon desired PSRR requirements , click and pop per-formance . The capacitor is fed from a 95k sourceinside the amplifier . To keep the start-up pop as lowas possible , the relationship shown in equation shouldbe maintained .

1/(Cb*95k) 1/{Ci*Ri} (3)As an example , consider a circuit where Cb is4.7F, Ci is 1F and APA3541 Ri is 180k Insertingthese values into the equation we get 2.24 5.55which satisfies the rule . Bias capacitor , Cb , valuesof 2.2F to 10F ceramic or tantalum low-ESR ca-

pacitors are recommended for the best THD andnoise performance .

Output Coupling Capacitor, Cc

In the typical single-supply SE configuration , an out-put coupling capacitor (Cc) is required to block theDC bias at the output of the amplifier thus preventingDC currents in the load . As with the input couplingcapacitor , the output coupling capacitor and imped-ance of the load form a high-pass filter governed byequation .

fc(highpass)= 1/(2RLCc) (4)

For example , a 220F capacitor with an 32speakerwould attenuate low frequencies below 22Hz . Themain disadvantage , from a performance standpoint, is the load impedance is typically small , which drivesthe low-frequency corner higher degrading the bassresponse . Large values of Cc are required to passlow frequencies into the load .

Optimizing Depop Circuitry

When the amplifier is in mute mode , both of the out-put stage and input bypass continues to be biased .And no pop noise will be heard during the transitionout of mute mode .

Power Supply Decoupling, Cs

APA3541/4 is a high-performance CMOS audio am-plifier that requires adequate power supply decouplingto ensure the output total harmonic distortion (THD)is as low as possible . Power supply decoupling alsoprevents the oscillations causing by long lead lengthbetween the amplifier and the speaker . The optimumdecoupling is achieved by using two different typecapacitors that target on different type of noise onthe power supply leads . For higher frequency tran-sients , spikes , or digital hash on the line , a goodlow equivalent-series-resistance (ESR) ceramiccapacitor, typically 0.1F placed as close as possibleto the device V

DD lead works best . For filtering lower-

frequency noise signals , a large aluminum electro-lytic capacitor of 10F or greater placed near the audiopower amplifier is recommended .

Copyright ANPEC Electronics Corp.Rev. B.1 -Apr., 2003

APA3541/4

www.anpec.com.tw9

Packaging Information

1

D

E1

A2

A1

A

L

e2

e 3

e 1

E

E3

1

PDIP-8 pin ( Reference JEDEC Registration MS-001)

Millimeters InchesDimMin. Max. Min. Max.

A 5.33 0.210A1 0.38 0.015A2 2.92 3.68 0.115 0.145D 9.02 10.16 0.355 0.400e1 2.54BSC 0.100BSCe2 0.36 0.56 0.014 0.022e3 1.14 1.78 0.045 0.070E 7.62 BSC 0.300 BSCE1 6.10 7.11 0.240 0.280E3 10.92 0.430L 2.92 3.81 0.115 0.150 1 15 15

Copyright ANPEC Electronics Corp.Rev. B.1 -Apr., 2003

APA3541/4

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Packaging Information

Mill imeters InchesDim

Min. Max. Min. Max.

A 1.35 1.75 0.053 0.069

A1 0.10 0.25 0.004 0.010

D 4.80 5.00 0.189 0.197

E 3.80 4.00 0.150 0.157

H 5.80 6.20 0.228 0.244

L 0.40 1.27 0.016 0.050

e1 0.33 0.51 0.013 0.020

e2 1.27BSC 0.50BSC

1 8 8

HE

e1 e2

0.0

15

X4

5

D

AA1

0.004max.

1

L

SOP-8 pin ( Reference JEDEC Registration MS-012)

Copyright ANPEC Electronics Corp.Rev. B.1 -Apr., 2003

APA3541/4

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Physical Specifications

Reflow Condition (IR/Convection or VPR Reflow)

Pre-heat temperature

183 C

Peak temperature

Time

tem

pera

ture

Classification Reflow Profiles

Convection or IR/Convection

VPR

Average ramp-up rate(183C to Peak) 3C/second max. 10 C /second max.Preheat temperature 125 25C) 120 seconds maxTemperature maintained above 183C 60 150 secondsTime within 5C of actual peak temperature 10 20 seconds 60 secondsPeak temperature range 220 +5/-0C or 235 +5/-0C 215-219C or 235 +5/-0CRamp-down rate 6 C /second max. 10 C /second max.Time 25C to peak temperature 6 minutes max.

Package Reflow Conditions

pkg. thickness 2.5mmand all bgas

pkg. thickness < 2.5mm andpkg. volume 350 mm

pkg. thickness < 2.5mm and pkg.volume < 350mm

Convection 220 +5/-0 C Convection 235 +5/-0 CVPR 215-219 C VPR 235 +5/-0 CIR/Convection 220 +5/-0

C IR/Convection 235 +5/-0 C

Terminal Material Solder-Plated Copper (Solder Material : 90/10 or 63/37 SnPb)Lead Solderability Meets EIA Specification RSI86-91, ANSI/J-STD-002 Category 3.

Reference JEDEC Standard J-STD-020A APRIL 1999

Copyright ANPEC Electronics Corp.Rev. B.1 -Apr., 2003

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Test item Method Description

SOLDERABILITY MIL-STD-883D-2003 245 C , 5 SEC

HOLT MIL-STD-883D-1005.7 1000 Hrs Bias @ 125 CPCT JESD-22-B, A102 168 Hrs, 100 % RH , 121 C

TST MIL-STD-883D-1011.9 -65C ~ 150C , 200 Cycles

ESD MIL-STD-883D-3015.7 VHBM > 2KV, VMM > 200VLatch-Up JESD 78 10ms , I

tr > 100mA

Reliability test Program

Carrier Tape & Reel Dimensions

A

J

B

T2

T1

C

t

Ao

E

W

Po P

Ko

Bo

D1

D

F

P1

Application A B C J T1 T2 W P E

330 1 62 +1.5 12.75+0.15 2 0.5 12.4 0.2 2 0.2 12 0. 3 8 0.1 1.750.1

F D D1 Po P1 Ao Bo Ko tSOP- 8

5.5 1 1.55 +0.1 1.55+ 0.25 4.0 0.1 2.0 0.1 6.4 0.1 5.2 0. 1 2.1 0.1 0.30.013

Copyright ANPEC Electronics Corp.Rev. B.1 -Apr., 2003

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Cover Tape Dimensions

Anpec Electronics Corp.Head Office :

5F, No. 2 Li-Hsin Road, SBIP,Hsin-Chu, Taiwan, R.O.C.Tel : 886-3-5642000Fax : 886-3-5642050

Taipei Branch :7F, No. 137, Lane 235, Pac Chiao Rd.,Hsin Tien City, Taipei Hsien, Taiwan, R. O. C.Tel : 886-2-89191368Fax : 886-2-89191369

Customer Service

Application Carrier Width Cover Tape Width Devices Per ReelSOP- 8 12 9.3 2500

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