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Xilinx FPGA Design Flow

Ping-Liang Lai ()

Digital System

8/3/2019 Appendix 2-FPGA Design Flow

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Outline of FPGA Design Flow

Project Navigator I: Schematic

(Project)

(Schematic)

(Functional Simulation)

» Testbench» :Modelsim Simulator 

» Implementation Constraints File

» Implementation Design

» (Timing Simulation) :Modelsim Simulator 

» Configuration

»

II: Verilog

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Project Navigator (1/2)

Source

Process

Source

Transcript

Multi-document Interface

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Outline of FPGA Design Flow

Project Navigator I: Schematic

(Project)

(Schematic)

(Functional Simulation)

» Testbench» :Modelsim Simulator 

» Implementation Constraints File

» Implementation Design

» (Timing Simulation) :Modelsim Simulator 

» Configuration

»

II: Verilog

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(1/8)

Step 1: File New Project

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(2/8)

FPGA: Spartan 3 XC3S200-FT256

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(3/8)

Step 2: Source Schematic

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(4/8)

New Source Summary

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(5/8)

We only need one Source, so Next.

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(6/8)

We don¶t need and have any Existing Sources, so Next.

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(7/8)

New Project Summary

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(8/8)

1.

Source

,

Device2.

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Outline of FPGA Design Flow

Project Navigator I: Schematic

(Project)

(Schematic)

(Functional Simulation)

» Testbench» :Modelsim Simulator 

» Implementation Constraints File

» Implementation Design

» (Timing Simulation) :Modelsim Simulator 

» Configuration

»

II: Verilog

8/3/2019 Appendix 2-FPGA Design Flow

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Schematic (1/5)

Schematic

Add wireAdd  Net  Name

Add I/O Maker 

Add Symbol

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Schematic (2/5)

Step 3: Add Symbol and Wire.

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Schematic (3/5)

Step 4: Add IO Maker.

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Schematic (4/5)

Step 5: Add Net name.

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Schematic (5/5)

Step 6: Tool Check schematic, and check no error and Save.

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Outline of FPGA Design Flow

Project Navigator I: Schematic

(Project)

(Schematic)

(Functional Simulation)

» Testbench» :Modelsim Simulator 

» Implementation Constraints File

» Implementation Design

» (Timing Simulation) :Modelsim Simulator 

» Configuration

»

II: Verilog

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(1/12)

Step 7: Source for Behavioral Simulation fa (fa.sch)add new source fa_tbw

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(2/12)

We only have one source, so Next.

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(3/3)

New Source Summary

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(4/12)

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(5/12)

Step 8: inputn inputs 2n input combinations.

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Step 9: Modelsim Simulator  Simulate Behavioral Model (Double click mouse left key 2 times).

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Modelsim Simulator You can see ³ Error Loading ´.

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Step 10: Select work  Compiler A ND2, OR3, and XOR2. (file path:C://Xilinx/9.2i/ISE/verilog/src/unisims)

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Step 11: In fa_tbw, Right click  Simulate

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Step 12: Right Click ³fa_tbw

´to select Add  To Wave  All items in

region.

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(11/12)

Behavioral Waveform Window

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Step 14: Run all, and Step 15: Zoom fit.

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Outline of FPGA Design Flow

Project Navigator I: Schematic

(Project)

(Schematic)

(Functional Simulation)

» Testbench» :Modelsim Simulator 

» Implementation Constraints File

» Implementation Design

» (Timing Simulation) :Modelsim Simulator 

» Configuration

»

II: Verilog

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Implementation Constraints File (1/8)

Step16: Sources for ³ Synthesis/Implementation ³ Step 17: fa.schProject New Source

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Implementation Constraints File (2/8)

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Implementation Constraints File (3/8)

Step 18: fa.ucf User Constraints  Assign Package Pins.

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Implementation Constraints File (4/8)

Xilinx PACE

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Implementation Constraints File (5/8)

Step 19:Package ViewDesign Browser  I/O Pins

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Implementation Constraints File (6/8)

Step 20: Spartan-3 FPGA XC3S200-FT256 Datasheet Slide Switches

LEDs

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Implementation Constraints File (7/8)

File Save

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Implementation Constraints File (8/8)

Edit Constraints (Text)

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Outline of FPGA Design Flow

Project Navigator I: Schematic

(Project)

(Schematic)

(Functional Simulation)

» Testbench» :Modelsim Simulator 

» Implementation Constraints File

» Implementation Design

» (Timing Simulation) :Modelsim Simulator 

» Configuration »

II: Verilog

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Implement Design (1/6)

Step 21: Implement Design

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Implement Design (2/6)

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Implement Design (3/6)

Place & Route View/Edit Routed Design (FPGA Editor) LUT

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Implement Design (4/6)

FPGA (Design Summary Summary)

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Implement Design (5/6)

Pinoout Report (Design Summary Pinout Report)

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Implement Design (6/6)

: Generate Post-Place & Route Static Timing AnalyzePost-Place & Route Static Timing.

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Outline of FPGA Design Flow

Project  Navigator  I: Schematic

(Project)

(Schematic)

(Functional Simulation)

» Testbench» :Modelsim Simulator 

» Implementation Constraints File

» Implementation Design

» (Timing Simulation) :Modelsim Simulator 

» Configuration »

II: Verilog

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(Timing Simulation)

Functional Simulation

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Outline of FPGA Design Flow

Project  Navigator  I: Schematic

(Project)

(Schematic)

(Functional Simulation)

» Testbench» :Modelsim Simulator 

» Implementation Constraints File

» Implementation Design

» (Timing Simulation) :Modelsim Simulator 

» Configuration »

II: Verilog

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Configuration (1/2)

Step 22: Generate Programming File

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Configuration (2/2)

Configure Device (iMPACT) Step 22: iMPACT Configure devices using Boundary-Scan

(JTAG) Automatically «

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Outline of FPGA Design Flow

Project  Navigator  I: Schematic

(Project)

(Schematic)

(Functional Simulation)

» Testbench» :Modelsim Simulator 

» Implementation Constraints File

» Implementation Design

» (Timing Simulation) :Modelsim Simulator 

» Configuration »

II: Verilog

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II: Verilog

From Step 2 to choose a Verilog Module, and repeat Step3 ~ Step 22. Design example: 4-bit Ripple Carry Counter 

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reset ck qn qn+1

1 * 1 0

1 * 0 0

0 0 1

0 1 0

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