Apple 1 32K and 20K Memory Upgrade Wendell Sander updated November 24, 2012 This document describes memory upgrades for an Apple 1 or Clone Board. The first design was used on my board in about 1980 and represents the type of modification that was common for hobbyists of that era. Many Apple 1 boards were modified because they were intended for hardware and software tinkerers. 32K Board Mod This design supports the installation of 16 16K DRAMS in the memory positions on the Apple 1 board. The memory chips must be the 3 power supply variety, not the single 5 volt parts. Figure 1 shows the cuts that were made on the board for this modification. Figure 1
Transcript
Apple 1 32K and 20K Memory UpgradeWendell Sander updated November 24, 2012
This document describes memory upgrades for an Apple 1 or Clone Board. The first design was used on my board in about 1980 and represents the type of modification that was common for hobbyists of that era. Many Apple 1 boards were modified because they were intended for hardware and software tinkerers.
32K Board Mod
This design supports the installation of 16 16K DRAMS in the memory positions on the Apple 1 board. The memory chips must be the 3 power supply variety, not the single 5 volt parts. Figure 1 shows the cuts that were made on the board for this modification.
Figure 1
If you don’t have the nerve to make cuts on a $300,000 collectable board the same result can be accomplished by lifting pins 13 and 15 on all 16 DRAMS then connect all pin 13’s together and then connect all pin 15’s on each row together. This is not very esthetically pleasing when looking at the top of the Board but no cuts are needed. Figure 2 illustrates the Schematic of the modification.
Figure 2Three IC’s need to be added, a 74S32 or 74F32, 74LS21, and a 74S253 or 74F253. The 253 multiplexer needs to be a fast part to assure Address set-up time to /CAS. The extra S32 gate is used to add delay to the /CAS signal for added margin but is not required, the S32 is needed to provide good drive to the /CAS lines. This design maps the DRAM memory from $0000 to $6FFF with no breaks and $E000 to $EFFF.
This design provides the maximum flexibility for address remapping for peripherals using the /CS connections. The bottom view of the board is shown in Figure 3, no sign of the modification is seen on the top of the board except for the added parts in the BB space. The interconnection style using wire wrap wire stretched tight is very similar to Woz’s assembly style.
74S211/2
74S211/2
S0 S1 E
14 2 15
74F253
10111213
I0b
I1b
I2b
I3b
Zb9
1/474S32
+1/4
74LS32
+
1/474LS32
+
1/474S32
+
9101213
CS0CS1CS2CS3
CS4CS5CS6CSE
From CSSelects
CASB6-12
V4
A12
A13
A15
B6-1D10-11
Addr MUXRfsh
D9-14
B9-22
B9-23B9-20
CASA
CASB109
8
1312
11
45
6
12
3DRAMs -Pin 13
DRAMs Row A-Pin 15
DRAMs Row B-Pin 15
WW
XX
Figure 3
A simpler version is shown in Figure 4. This solution only requires 2 added parts a 74S or 74F251 and 74S or 74F32 and uses spare parts from the Apple 1 Board.
Figure 4
This version uses the /CAS to multiplex the address. This works well for the MK 4116 because it has a negative Address Setup time to /CAS. This was a change
1/474S32
+
1/474S32
+
D9-18
B9-20CASA
CASB910
8
45
6DRAMs Row A-Pin 15
DRAMs Row B-Pin 15
WW
XX
1/474S32
+21
3A15A14
B9-21
CSE
CS7
B9-16
B9-8
12
32
131 12
C15
C6A14
1/4 74S32
+1312CASB6-12
S0S1
1110
S29
74S251
2115141312
3I0I1I2I3
Z
4
DRAMs - Pin 13
OE
I4I5I6I7
7
5
V4
A12A13
B9-22B9-23
V4D9-14
D9-18
CASB6-12CSEB9-16RFSH RFSH
11
from the MK4096 which had a zero set-up time. That change was made based on input from the DRAM users. Also the /CAS goes through two gate delays whereas the Address goes through one gate delay. The RFSH is taken from the Enable on the enable on the 74154 which is the complement of RF on the connector because VMA is wired high.
20K Board Mod
A 20K version of the circuit of Figure 4 requires only the 74F or 74S253 and 74F or 74S32. Only the DRAMs in Row B are 16K in this case. Figure 5 shows the schematic for this implementation.
Figure 5
This 16K of added memory is mapped from $0000 to $3FFF with no breaks. The 4K bank of DRAMS in Row A would normally be mapped to $E000 to $EFFF.
