appliedVHDLV1

Aim: Capture, simulate, implement appliedVHDLV1 SystemSupports GUI r/w access from/to FPGA CSR block

This document contains:• EE427 submission / demonstration instructions• appliedVHDL project overview • appliedVHDLV1 Context Diagram (CD) • appliedVHDLV1 Context Diagram Data Dictionary (DD) • appliedVHDLV1 Data Flow Diagram (DFD) • appliedVHDLV1 System elements• appliedVHDLV1 System hierarchy

Assignment steps• P2.1 CSRBlk Design • P2.2 IOCSRBlkV1 Design • P2.3 NUIGProjectV1 Design• P2.4 appliedVHDLV1 Design• P2.5 Implementation on FPGA

EE427 Phase 2 Assignment : Contents

appliedVHDLV1Context Diagram

Aim: Capture, simulate, implement appliedVHDLV1 SystemSupports GUI r/w access from/to FPGA CSR block

appliedVHDLV1

• clk : system strobe (50MHz oscillator)

• rst : asynchronous system reset (high asserted). Clears(or sets) registers

• RxD : serial port data received by appliedVHDL system from host

• TxD : serial port data transmitted to host by appliedVHDLsystem

• seg7L(6:0), dpL : 7-segment display data signals. Assertion (low)lights LEDS on the Digilent Spartan-3 hardwaredevelopment system

• anL(3:0) : anode control signals (asserted low), e.g., upper 7-seg display segment 0 will light when anL(3)=’0’and seg7L(0)=’0’

• ld(7:0) : 8 leds. Assertion (H) lights leds

Context Diagram Data Dictionary

appliedVHDLV1

UART

TxD RxD

rxDat(7:0)rxDatValid

txDat(7:0)

txDatValid

csr(7)(7:0) csr(6)(7:0) csr(5)(7:0) csr(4)(7:0) csr(3)(7:0) csr(2)(7:0) csr(1)(7:0) csr(0)(7:0)

csrOut(7:0)

rxDatAck

txDat(7:0)

CSR register assignment

Visual Basic Host Interface GUI

sequentialcombinational

keyCSR contents

element names

RX : ser2Par

TX :par2Ser

4x7-seg displays

8 LEDs

dpLdisplayCtrlrdpIn(3:0)

rxDat(7:0)

seg7L(6:0)

anL(3:0)appliedVHDL Top Level Data Flow Diagram [F Morgan, Ph.D] V07_1

seg73In(3:0)seg72In(3:0)

seg71In(3:0)seg70In(3:0)

ld(7:0)

txDat(7:0)

txDat(3:0)

ldIn(7:0)rxDat(7:0)

IOCtrlr State Machine

IOCtrlrFSM V1

cmdRegV1csrAdd(2:0)

enCSRWr

CSRBlk

csrOut(7:0)

NUIGProjectV1 (DFD 1.0) is a combination of these two blocks

CSR register assignment

rxDat(7:0)

CSR Add decode

CSR data wr on enableassertion

CSR rden

rxDat(6:4, 1)

4

regCSRInfo, clrCSRInfo

2.0

3.0

datCtrlrV1

IOCSRBlkV1

1.1.2

1.1

1.2

1.1.1IOCtrlrFSM&CmdRegV1

NUIGProjectV1

Supports CSR r/w access

DFD 1.1 V1

DFD 3.0

DFD 2.0

NUIGProjectV1

Data Flow Diagram (DFD 0.0)

appliedVHDLV1

Project Element Activity (ref glossary)

IOCSRBlkV1 contains CSRBlk: Control and Status Register (CSR) block C, S, I IOCtrlrV1: I/O controller Finite State Machine (FSM, Parses host

GUI commands and data from UART), register command C, FSM, S, I

datCtrlrV1 Simply connects CSROut(7:0) to txDat(7:0) C, S, IRefer to DFD 0.0

appliedVHDLV1 (top level): C, S, I

NUIGProjectV1: contains IOCSRBlkV1 and datCtrlrV1

UART Xilinx UART component Provided

displayCtrlr: Multiplexed 7-segment display and LED controller Completed (phase 1)

System Elements

Glossary : FSM : Finite State Machine C : VHDL Capture S : Simulation I : Implementation

BFM: VHDL Bus Functional Model

appliedVHDLV1

Use the active links to browse the design hierarchy and documentation ISE Project : appliedVHDLV1.ise (provides access to all of constituent files)

appliedVHDLV1

displayCtrlr NUIGProjectV1 UART

IOCSRBlkV1: includes IOCtrlrFSMV1, cmdReg & CSRBlk (component)

datCtrlrV1

CSRBlk

DFD1.0 V1

DFD1.1 V1

P2.3

P2.4

DFD1.1.2P2.1

NUIGPackage

DFD2.0P2.4

DFD3.0

System Hierarchy

cascadedBCDCntrAndDisplay

CD, DFD1.0 V1

P2.3

P1.1 / P2.4

P1.2

P2.2

appliedVHDLV1

• rxDat(7:0) : byte-wide data generated by UART from serial byte received from host. rxDat is validated by assertion (h) ofrxDatValid

• rxDatValid :assertion (h) validates rxDat(7:0). Signal remains asserteduntil assertion of rxDatAck

• rxDatAck : assertion by FPGA acknowledges receipt of a valid rxDatbyte. Signal asserts for one clock period only

• txDat(7:0) : byte-wide data generated by FPGA and transferred to UARTfor serialisation and transfer to host PC. txDat is validatedby assertion (h) of txDatValid

• txDatValid : assertion (h) validates txDat(7:0)

DFD 0.0 Incremental Data Dictionary

appliedVHDLV1

Assignment instructions continued P2. 1 CSRBlk

– Capture, simulate and synthesise the CSRBlk

appliedVHDLV1

Assignment instructions continued P2. 2 IOCSRBlkV1 level

– Review/verify/complete IOCSRBlkV1.vhd

– Decodes UART control/data byte sequence. Handshakes with host via UART byte interface CSR access : provides Control and Status Register (CSR) R/W access (8 byte-wide CSRs)

– Includes IOCtrlr FSM process(es), CSRBlk component instance and cmdReg process. – Check VHDL code syntax, synthesise and view RTL schematic. Confirm correctness.– Simulation is not required at this level

appliedVHDLV1

IOCtrlrV1 FSM description Refer to course notes on

VHDL Finite State Machine Description

Refer to FSM flowchart• Finite State Machine (FSM) detects and processes

control or data byte (rxDat) from UART (on assertion of rxDatValid signal).

• Decodes :– CSR access :

• Registers csrAdd(2:0) and csrTask flag• write : requires a further data byte (on rxDat)

from UART• read : provides CSR data byte (csrOut) to

UART on txDat

• Validates byte data transmission to UART (txDatValid assertion)

• Acknowledges receipt of byte data (rxDat) from UART (rxDatAck assertion)

chkTask

rxDatValid

csrRd

Flowchart Key :

i/ps :clk, rstrxDatValidrxDat(7:0)

o/ps (all default to ‘0’)rxDatAcktxDatValidldCSRAddenCSRWr

N

Y

IOCtrlrFSMV1 (DFD 1.1.1) Flowchart© F Morgan, 2005

rxDat(1)

rxDat(0)

csrWr

rxDatValid

N

Y

Y

N

N

Y

txDatValid

rxDatAckenCSRWr

ldCSRAdd

rxDatAck

Note : all signals indicated onflowchart paths are asserted ‘1’

appliedVHDLV1IOCtrlrV1 FSM : Synthesised RTL Schematic

appliedVHDLV1

DFD 1.1.1 (IOCtrlrV1 FSM & cmdReg Testbench Block Diagram

appliedVHDLV1Assignment instructions continued

P2.3 NUIGProjectV1 level– Review/verify/complete NUIGProjectV1.vhd.

– Includes IOCSRBlkV1 and datCtrlrV1 elements (VHDL code is provided)– Check VHDL code syntax, synthesise and view RTL schematic. Confirm correctness.– Review the NUIGProjectV1_TB.vhd VHDL testbench code and modelsim macro files– Simulate NUIGProjectV1_TB.vhd fully, review the timing waveform and verify correct VHDL model operation.

P2. 4 appliedVHDLV1 level– Review/verify/complete appliedVHDLV1.vhd.

Includes NUIGProjectV1, UART and displayCtrlr components (VHDL code is provided)– Check VHDL code syntax, synthesise and view RTL schematic. Confirm correctness.– Review the appliedVHDLV1_TB.vhd VHDL testbench code and modelsim macro files– Simulate appliedVHDLV1_TB.vhd fully, review the timing waveform and verify correct VHDL model operation

P2.5 Implement on FPGA – Review appliedVHDLV1.ucf (provided) for pinout– Implement appliedVHDLV1 on the Spartan 3 development system and test

appliedVHDLV1

Testbench structure