Ar ion implant damage gettering of generation impurities in silicon employing voltage ramping and nitrogen backscattering Indexing terms: B. Golja and A.G. Nassibian Annealing, Carrier lifetime, Elemental semiconductors, Ion implantation, Metal-insulator- semiconductor structures, Minority carriers, Silicon Abstract: The effects of Ar-ion implant gettering has been investigated using the linear voltage ramp applied to m.o.s. capacitors. A comparison is made with control (not implanted) samples and N + -ion Rutherford backscattering is used to examine the precipitation of generation impurities by the damaged layers. The gettering anneals were carried out over the temperature range 950°C-1100°C and for various times from 15min to 120min. It is shown that long gettering anneal times and high anneal temperatures both have a detrimental effect on minority-carrier lifetime. 1 Introduction To minimise the generation charge in m.o.s. devices it is necessary to getter the generation impurities by producing lattice disorder at the back surface of the silicon wafer. The gettering of undesirable impurities has been carried out to a certain extent by phosphorus diffusion at the back surface of the silicon wafer. 1 " 4 lon-implant-damage gettering in silicon photodiode arrays, resulting in a reduction in the incidence of the type of white video defects and a reduction of dark current, has been reported; 5 ion-implant-damage gettering has also been studied using the Rutherford backscattering method. 6 ' 7 Seidel et al. 1 have used the Rutherford backscattering technique to investigate the gettering of gold by damaged layers produced by Ar, 0, P, Si, As, and B ion implant, and compared it to gettering by phosphorus diffusion. The influence of Ar and 0 ion-implant-damage gettering on the generation lifetime has been reported recently by Nassibian et al. s The transient response of a m.o.s. capaci- tor at room temperature was used to determine the generation lifetime of carriers, and an increase from 1 — 15 jus to as high as 200 us was observed. Such investigations are relevant to c.c.d.s where a packet of signal charge is stored in a surface potential well and transferred from one well to the other along the oxide/silicon interface. These devices employ m.o.s capacitor transfer elements, and any undesir- able deep-lying generation centres such as Au, Cu, Fe etc. can generate spurious charge which can be stored in the potential well with the input packet of charge, resulting in the degradation of the output signal. It is the aim of this paper to present a detailed study of Ar-implant gettering. The nonequilibrium response of m.o.s. capacitors to a linear voltage ramp, based on a recent theory by Board and Simmons 9 and experimental studies by Nassibian et al., 10> n has been used to extract the lifetime of carriers. Paper T416s, first received 26th March and in revised form 19th June 1979 Dr. Nassibian and Dr. Golja are with the Department of Electrical & Electronic Engineering, University of Western Australia, Nedlands, Western Australia 6009 2 Sample preparation 2.1 Oxidation The wafers were w-type, 8 Hem polished silicon of (100) orientation. The back surface of each wafer was chemically etched and free from any mechanical damage. After a standard RCA cleaning procedure, 12 a 0-15 /um gate oxide was grown at 1080° C in dry oxygen followed by a 15 min nitrogen anneal. The resistivity of the materials was measured using the four-point probe technique prior to oxidation. 2.2 Imp Ian t and anneal The oxidised wafers were then divided into two equal parts; the oxide was etched off the back surface of the wafers and one half of each wafer was sent to the AERE, Harwell, for Ar-ion implant. The implant was done on a Lintott ion implanter at 180keV. The dosage was 10 16 cm" 2 at 200 fiA. Under these conditions the projected range of Ar ions in silicon is 0-21 /urn. The other half-wafers on which no implant was done were the control wafers. Both control and implant wafers were then given standard RCA cleaning, 12 and annealed in dry nitrogen. 2.3 Low-temperature anneal and Al evaporation The m.o.s. capacitors were made by evaporating Al contacts. All the samples were heat-treated at 450° C in forming gas ambient, for 30 min before and after the evaporated Al contacts were made, to reduce the density of fast-interface states. 3 Basis of the nonequilibrium linear-voltage-ramp method The principal results in this work on the dynamic properties of bulk generation centres are obtained by the nonequilib- rium response of m.o.s. devices subjected to a linearly varying voltage. This technique involves applying a linear voltage ramp, V = V n +oct SOLID-STATE AND ELECTRON DEVICES, SEPTEMBER 1979, Vol. 3, No. 5 0) 127 0308-6968/79/050127 + 06 $01-50/0
Transcript
Ar ion implant damage gettering of generationimpurities in silicon employing voltage ramping and
Abstract: The effects of Ar-ion implant gettering has been investigated using the linear voltage ramp appliedto m.o.s. capacitors. A comparison is made with control (not implanted) samples and N+-ion Rutherfordbackscattering is used to examine the precipitation of generation impurities by the damaged layers. Thegettering anneals were carried out over the temperature range 950°C-1100°C and for various times from15min to 120min. It is shown that long gettering anneal times and high anneal temperatures both have adetrimental effect on minority-carrier lifetime.
1 Introduction
To minimise the generation charge in m.o.s. devices it isnecessary to getter the generation impurities by producinglattice disorder at the back surface of the silicon wafer. Thegettering of undesirable impurities has been carried out to acertain extent by phosphorus diffusion at the back surfaceof the silicon wafer.1"4 lon-implant-damage gettering insilicon photodiode arrays, resulting in a reduction in theincidence of the type of white video defects and a reductionof dark current, has been reported;5 ion-implant-damagegettering has also been studied using the Rutherfordbackscattering method.6'7 Seidel et al.1 have used theRutherford backscattering technique to investigate thegettering of gold by damaged layers produced by Ar, 0, P,Si, As, and B ion implant, and compared it to gettering byphosphorus diffusion.
The influence of Ar and 0 ion-implant-damage getteringon the generation lifetime has been reported recently byNassibian et al.s The transient response of a m.o.s. capaci-tor at room temperature was used to determine thegeneration lifetime of carriers, and an increase from 1 — 15 justo as high as 200 us was observed. Such investigations arerelevant to c.c.d.s where a packet of signal charge is storedin a surface potential well and transferred from one well tothe other along the oxide/silicon interface. These devicesemploy m.o.s capacitor transfer elements, and any undesir-able deep-lying generation centres such as Au, Cu, Fe etc.can generate spurious charge which can be stored in thepotential well with the input packet of charge, resulting inthe degradation of the output signal.
It is the aim of this paper to present a detailed study ofAr-implant gettering. The nonequilibrium response of m.o.s.capacitors to a linear voltage ramp, based on a recenttheory by Board and Simmons9 and experimental studies byNassibian et al.,10> n has been used to extract the lifetimeof carriers.
Paper T416s, first received 26th March and in revised form 19thJune 1979Dr. Nassibian and Dr. Golja are with the Department of Electrical &Electronic Engineering, University of Western Australia, Nedlands,Western Australia 6009
2 Sample preparation
2.1 Oxidation
The wafers were w-type, 8 Hem polished silicon of (100)orientation. The back surface of each wafer was chemicallyetched and free from any mechanical damage. After astandard RCA cleaning procedure,12 a 0-15 /um gate oxidewas grown at 1080° C in dry oxygen followed by a 15 minnitrogen anneal. The resistivity of the materials wasmeasured using the four-point probe technique prior tooxidation.
2.2 Imp Ian t and anneal
The oxidised wafers were then divided into two equal parts;the oxide was etched off the back surface of the wafers andone half of each wafer was sent to the AERE, Harwell, forAr-ion implant. The implant was done on a Lintott ionimplanter at 180keV. The dosage was 1016 cm"2 at 200 fiA.Under these conditions the projected range of Ar ions insilicon is 0-21 /urn. The other half-wafers on which noimplant was done were the control wafers. Both controland implant wafers were then given standard RCAcleaning,12 and annealed in dry nitrogen.
2.3 Low-temperature anneal and Al evaporation
The m.o.s. capacitors were made by evaporating Al contacts.All the samples were heat-treated at 450° C in forming gasambient, for 30 min before and after the evaporated Alcontacts were made, to reduce the density of fast-interfacestates.
3 Basis of the nonequilibrium linear-voltage-rampmethod
The principal results in this work on the dynamic propertiesof bulk generation centres are obtained by the nonequilib-rium response of m.o.s. devices subjected to a linearlyvarying voltage.
This technique involves applying a linear voltage ramp,
V = Vn+oct
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to the m.o.s. device via an HP 3310B function generator,and recording the corresponding displacement current,
/ = OLC (2)
using a Keithley 616 electrometer and an X-Y recorder. Inthese equations, a. is the ramp rate, / is time, Vo is thestarting voltage of the ramp, and C is the capacitance of them.o.s. device.
If a is made sufficiently large, the device is driven intononsteady state and, provided that the interface density ofstates is low, the resulting I/V characteristics reflect thedynamic properties of the bulk traps. The device can alsobe driven into nonsteady state by sufficiently lowering thetemperature. In the present work, measurements werecarried out over a temperature range 250K-300K, in anaccurately controlled cryostat filled with dry nitrogen.
The curve in Fig. 1 shows the I/V characteristic of adevice in nonequilibrium. Only the section abode of thecurve is in nonequilibrium. The rest of the characteristic isin quasiequilibrium.
During the negative-going voltage ramp, from 0 to—12-5 V, the portion ab of the curve is traced. The currentIf flowing in the device consists of the current Id discharg-ing the donor centres at the edge of the depletion regionand the generation current, 7^:
If = -Id~Ig (3)
Upon reversal of the voltage sweep, Ig continues to flow inthe same direction, but Id reverses since the donor centresat the edge of the depletion region now start refilling. Thecurrent Ir is now given by
Therefore, immediately on reversal of the voltage sweep,the current drops abruptly, as shown by be on the curve,and then at the positive-going sweep, from —12-5 to 0 V,increases positively as indicated by cd on the curve. Ir = 0when the curve crosses the voltage axis (i.e. Id = Ig).
When the bulk Fermi level EFB lines up with the Fermilevel at the surface EFS, the current rises almost verticallyuntil it reaches quasiequilibrium, giving the portion de ofthe curve. The device is now in strong inversion.
The theory of the above behaviour has recently beenpresented by Board and Simmons.9 The relevant equationsfor generating various sections of the I/V curve had pre-viously been developed.9' n The equations describing the
I/V response during both the forward and reverse sweep11
contain the variable Z described by
z = (5)
where Xd is the time-dependent depletion width, Xo thedepletion width at start of generation, given by
Xn =2e.(EF-Et)
1/2
(6)
LE the normalised steady-state depletion width, given by
T -E ~
Et is the energy level of bulk traps, and ND is the donorconcentration. For the special case of a depleted region,such as exists when a deep-depleting voltage step ordepleting voltage ramp is applied to a m.o.s. structure, theelectron and hole carrier concentrations (n and p, respect-ively) are reduced well below their equilibrium concen-trations.
From Shockley-Hall-Read statistics, Ug is described by
V* =
2 coshkT
2TO(8)
where rg is defined as the generation lifetime.Thus the process by which an m.o.s. capacitor subjected
to a depleting voltage relaxes to equilibrium is characterisedby the generation lifetime, given by
coshkT
ovthNt(9)
Herein lies the essence of the technique. In generatingtheoretical curves using the parametric variable Z of eqn. 5to correspond with experimentally determined I/Vcharacteristics, an appropriate choice has to be made of thetrap parameters ovthNt and Et, and the lifetime can beextracted from eqn. 9. The parameterND can be determinedfrom high-frequency C/V measurements and four-point-probe resistivity measurements.
4 Results and discussion
4.1 Nonequilibrium linear-voltage-ramp study
The I/V characteristics are strongly dependent on thetemperature and voltage sweep rates. The displacementcurrent 7 is dependent on a, therefore all the measurementswere carried out with a set to 0-25 V s"1, so that I/Vcharacteristics could be compared between devices and atdifferent temperatures.
It should be emphasised at this point that differentsilicon materials were used in various sets of experiments,e.g. the results presented in Table 1 and Fig. 3 are obtainedfrom silicon material different to that which provided thedata presented in Table 2 and Fig. 4, unless otherwisespecified. In this manner several different materials wereinvestigated simultaneously, with different control lifetimes.
128 SOLID-STATE AND ELECTRON DEVICES, SEPTEMBER 1979, Vol. 3, No. 5
The results obtained from wafers 1 and 2 (Table 1), havebeen presented in Fig. 2. The I/V curves for a control (C)and an implant gettered (I) device, at a temperature of258 K, are shown in Fig. 2a. The I/V characteristics of thesame two devices at 245 K and 233 K are shown in Figs. 2band 2c, respectively. The control and implant devices havebeen shown at the same temperatures to make directcomparison easier. The Figures have been separated intothree simply for reasons of clarity. Theoretical plots areshown by the dashed lines in Figs. 2a, b and c. Theparameters used to generate the theoretical curves whereND = 4-6 x 1014 cm"3, Et = 0-015 eV above the intrinsiclevel, and avthNtc = 3-65 x 106 s"1 for the control device;ND=4-6x 1014cm~3 (same as control), Et = 0eV (atmidgap) and avthNti = 4 x 10s s"1 for the implant device.Ntc and Nti are the bulk-generation-centre densities forcontrol and implant devices, respectively.
Table 1: Results of generation lifetime of Ar-implanted samplesafter annealing at 1050°C for various times
u -
-2
-U
233K
1 1 1
12 -8 -A 0gate voltage, V
Fig. 2 Current/voltage curves for control (C) and implant (I)devices at various temperatures
Table 1 (wafers 3—9) outline the gettering-anneal-timeresults for several sets of experiments with anneal timesranging from 15 min to 120 min at a temperature of1050°C. The wafers 3—9 are quarters cut from two 50 mmdiameter silicon slices of the same material, and the wafers1 and 2 are from a different material and reflect the variationin results that can be obtained between different materials.8
Minority-carrier lifetime has been obtained from the I/Vresponse, and the lifetime giving the best general fit over arange of measurement temperatures is shown plotted againstanneal time in Fig. 3. It is evident that gettering annealtimes between 15 and 60 min result in an improvement inlifetime compared with the control devices. For the longeranneal time of 120 min, the minority-carrier lifetimedegraded markedly, approaching that of the original controlsample.
The effectiveness of different gettering anneal tempera-tures on implanted devices was also investigated. The results
15
(/)
| 10
oa
1
anneal temperature = 1050°C
implant •
control (average)
= theoretical
SOLID-STATE AND ELECTRON DEVICES, SEPTEMBER 1979, Vol. 3, No. 5
0 15 30 45 60 75 90 105 120time.min
Fig. 3 Generation lifetime against gettering anneal time
Anneal temperature = 1050°C
129
Table 2: Results of generation lifetime of Ar-implanted samplesafter annealing for 60 min at various temperatures
obtained from this study are presented in Table 2 and Fig.4, which shows the lifetime giving the best overall fit to theI/V curve against anneal temperatures ranging from 950° to1100°C. The results, obtained from two 50 mm siliconslices of the same material, clearly indicate that the mosteffective anneal temperatures lie between 1000°C and1050°C. Above 1050°C the effect of gettering is greatlyreduced, and lifetime drops sharply, tending towards thevalue of the control wafer.
In another experiment, successive gettering heattreatments at 1050°C on one Ar-implanted wafer wereinvestigated. The silicon wafer was divided into quarterswhich were inserted into the furnace. After a 15 min heattreatment, the wafers were brought to the cold zone of thefurnace and allowed to cool. One wafer was removed, andthe remaining three reinserted for an additional 15 min,when the second wafer was removed. The remaining twowere given an additional 30 min heat treatment. When thethird wafer had been removed, the fourth was given a
7
i/i 6
3.a/
§ s
c Ao
anneal t ime=60mm
950 1000 1050temperature,°C
1100
further 60 min anneal. Table 3 presents the varioussuccessive heat-treatment times, and the generation lifetimeobtained in each case. These results clearly show that thelifetime of Ar-implanted wafers is continually degraded bysuccessive gettering heat treatments, indicating that thegettering anneal must be the final process in devicemanufacture. It suggests that the damage produced by theion implant is annealed out after the first heat treatmentand cooling-off process, resulting in a fall of getteringefficiency and redissolving of generation impurities into thebulk of the material in successive treatments.
4.2 In terface sta te effec ts
A requirement of the nonequilibrium method for deter-mining dynamic properties of silicon is a low density ofinterface states. This can be confirmed by the high-frequencyC/V method, and by the quasiequilibrium linear-voltage-ramp technique of generating I/V curves. The I/V curves aregenerated by applying the linear voltage ramp at a suf-ficiently slow rate or at a temperature high enough for thedevice to remain in quasiequilibrium.11
Table 3: Results of generation lifetime of Ar-implanted samplesafter successive heat treatments at 1050°C
generationlifetime
wafer successive heat treatment total heattimes treatment
1st 2nd 3rd 4th
60
control average over all times
1234
mm15151515
151515
3030
mm153060
120
MS3-330-526
<0-35<0-35
0-36
Fig. 4 Generation lifetime against gettering anneal temperature
Anneal time = 60 min
Both these measurements have been carried out, andyielded a value of Q^/q of the order of 1-22 x 1010 cm"2
for all the devices measured.The capacitance-transient measurements have also been
carried out to ascertain that the presence of low interfacestates is negligible, and to establish the validity of the dataderived from the linear-voltage-ramp technique. To this end,the devices are pulsed from accumulation into deepdepletion and from strong inversion into deep depletion.The high-frequency capacitance as a function of time istraced on the X-Y recorder as the sample is released toquasiequilibrium. In the former case, generation throughinterface states will occur, but in the latter case, interfacegeneration is suppressed. If the interface-generation ratesare significant, then the two plots cannot be identicallysuperimposed if they are pulsed the same amount into deepdepletion.
The results of these measurements on wafers 1 and 2from Table 1 are shown in Fig. 5. The measurements forboth control and implant devices are done at 250 K and arepulsed from +5V to —25V (accumulation to deepdepletion), and from — 5V to —25V (inversion to deepdepletion). It can be seen that the recovery times tf andthe shape of the curves are almost identical for both devices,indicating that the interface-state generation in thesedevices is in fact negligible.
It is important to note that, if there was a generationeffect from the interface states, it would not have been
130 SOLID-STATE AND ELECTRON DEVICES, SEPTEMBER 1979, Vol. 3, No. 5
possible to fit theoretical curves to experimental results, asdemonstrated by nonequilibrium curves in Figs. 1 and 2.
The capacitance-transient measurements can also be usedto derive independently the generation lifetime of theminority carriers.13'14 The values obtained from thistechnique are rc = 2-57 x 10"7 s and r,- = 2-42 x 10"6 s forcontrol and implant devices, respectively, which is in verygood agreement with the values extracted from the I/Vcurves.
•30
•20 2
Cf
Ci
/
f
control
T=25OK
-10
Cf
c,
120 240times
implant
360
T=25OK
30
20 u.
a10 a
120 time,sb
240 360
Fig. 5 Capacitance/time curves of control and implant samplespulsed 25 V into deep depletion
= accumulation -*• deep depletioni
p= inversion -»• deep depletion
4.3 Rutherford backscattering
Rutherford backscattering7 using 14N+ ions was applied toboth implanted and control wafers, to investigate thenature of the generation impurities. The ^NT-ion back-scattering was done at the AERE at Harwell, on the Van deGraaff accelerator, with a beam energy of 3-5 MeV. A30-40/nm layer was etched off half the back surface ofeach implanted wafer, and backscattering measurementswere done on each half of the wafer. Thus, on the implantedsamples, measurements were carried out on the implant-damaged surface and also some 30 //m into the bulk of thematerial. The control samples also had 30 nm etched off the
back so that the measurements reflected the bulk propertiesof the wafer.
The results of the backscattering are presented in Table4. The impurities identified by backscattering, with theirmass numbers, are listed. They fall into several massgroupings. Mass numbers M= 40-65 are Ar, Fe, and Cu;M = 80 ± 5 can be Br, Se and Kr; M = 124 ± 6, Sb and Te;M= 197 ±5 is Au.
4.4 Discussion
4.4.1 M.O.S. devices: The results presented indicate thatthe improvements in minority-carrier lifetime achieved byAr-ion implant gettering have been as high as an order ofmagnitude. The spread in lifetime appearing across thewafer and among wafers may be due to the silicon material.Crystalline imperfections and stacking faults will play asignificant role and cannot be annealed out by getteringtechniques.
Annealing in anonreactive nitrogen ambient suggests thatthe gettering mechanism is associated with implant damageand not with ambient effects. The solubility of generationimpurities in crystallographically damaged areas of siliconresults in a redistribution of any generation impuritiespresent in the wafer with the introduction of such adamaged layer. The gettering process in an ion-implantedlayer is very similar to that associated with phosphorus-diffusion gettering, as it involves the precipitation ofgeneration impurities into the lattice damage brought aboutby ion implantation on the back surface. For the getteringto be efficient, it is necessary both that the damaged layerappears as an infinite sink for any generation impuritiespresent, and that impurities are gettered into the layer asfast as they arrive.
The results obtained indicate that a short gettering-annealtime (around 15min) is sufficient to getter generationimpurities. No marked improvement was observed for 30and 60min anneal times, whereas with the longer annealtime of 120 min, a degradation in minority-carrier lifetimewas clearly evident. This suggests that, after the damagedlayer has been saturated, annealing for an appreciable timebeyond this point results in generation impurities annealingout and redissolving into the bulk silicon.
The most improvement (with anneal temperature as thevariable) was observed in the range 1000°C-1050°C.Annealing at the higher temperature (1100°C) had a similareffect to annealing for a longer time, i.e. deterioration inlifetime.
The effects observed after successive heat treatments(Table 3) support the conclusion that a short anneal timeis adequate for gettering impurities. It is also evident thatproducing lattice disorder via ion implantation, and thenproceeding through the various stages associated withdevice manufacture, does not increase the effect orefficiency of gettering but decreases it significantly. Thisdecrease in minority-carrier lifetime resulting from repeatedheat treatments also suggests the possibility of generationimpurities redissolving into the bulk material.
4.4.2 Backscattering: Energy levels of generation impuritiesdepend on how well these impurities fit the electronic andperiodic pattern of the silicon lattice. There is also atendency to form compounds and precipitates upon cooling,resulting in various concentrations of electrically active andinactive species.
SOLID-STATE AND ELECTRON DEVICES, SEPTEMBER 1979, Vol. 3, No. 5 131
wafer
Table 4: Concentration of various deep impurities in silicon determined using the Rutherford backscattering technique
implant orcontrol
anneal time annealtemperature
areaexamined
= 197 (Au) M = 40 (Ar)toM = 56 (Fe)
M = 63 (Cu)
implant
implant
control
mm1515606015
C10501050105010501050
surfacebulksurfacebulkbulk
cm8X 10'°
< 7 X 109
1-2X 10"1-5 X 10'°5-4 X 10'°
cm5X 10"2X 101
5X 10'4 X 10'5 X 10'
cm< 2 X 1012
< 2 X 10 n
< 2 X 1012
' < 4 X 10 n
< 5 X 1012
Gold has been studied extensively as a very effectivelifetime-control impurity in silicon,15 and generationthrough the 0-54 eV acceptor level will dominate theresponse to the nonequilibrium linear voltage ramp. In thebackscattering measurements, gold appears in low concen-trations in these materials and is very effectively getteredby the Ar-ion-implant-damaged layer. In the bulk of thecontrol material (wafer 3 in Table 4), the density of residualgold scattering centres is 5-4 x 1010 cm"2. In the implant-damaged surface layers of wafers 1 and 2, the density ofgold scattering centres has increased to about 1011 crrf2,and in the bulk of the same samples it has decreased toabout 1010 cm"2.
The Ar40, Fe56 and Cu63 fall under a broad backscat-tering spectrum; they overlap the silicon edge and could notbe resolved. It has been established by Seidel et al.l that Arremains in the silicon after the anneal. In the presentinvestigations, the Ar-ion implant concentration was1016 cm"2, and therefore Ar will dominate the 2-5 x 1014
cm"2 concentration of impurities with mass numbersbetween 40 and 56 measured by 14N+ ion backscattering.
Iron has a donor level 0-40 eV from the valence band,but two additional donor levels, 0-14 eV and 051 eV fromthe valence band, have also been observed.15 Cu63, whichhas three acceptor levels at 0-52 eV, 0-37 eV and 0-24 eVfrom the valence band,15 could not be resolved, and anestimate of its density is < 2 x 1012cm"2. It is clear,therefore, that Fe in concentrations of 1014 cm"2 shouldact as a recombination centre. However, the electricalmeasurements using the nonequilibrium linear voltage rampdo not reflect the presence of generation centres of thesemagnitudes. Therefore, Fe56 cannot be acting as an effectivegeneration centre at this concentration level. It is alsopossible that Fe can form compounds in silicon of electri-cally inactive species. Then results also suggest that the0-51 eV donor level of Fe is either absent or has very lowdensity.
It can, therefore, be concluded from the impuritiesanalysed by backscattering that gold is the generationcentre that is playing the most effective role in the gener-ation mechanism of these devices, and the removal of thegold from the bulk by the Ar-implant damage layer is thedominating influence in the increase in generation lifetimeobserved in the present investigations.
5 Conclusion
It has been demonstrated by the linear-voltage-ramptechnique that Ar-ion implant is effective in achieving anincrease in generation lifetime. The evidence also indicates
that prolonged gettering anneals and high-temperatureanneals (1100°C) have a deleterious rather than beneficialeffect on the lifetime. It was also discovered that successiveheat treatments result in a degradation of minority-carrierlifetime, suggesting that in dsvice manufacture the getteringanneal should be the final high-temperature process associ-ated with the device.
6 Acknowledgments
The authors wish to thank the Australian Research GrantsCommittee for financial assistance for this work.
7 References
1 GOETZBERGER, A., and SHOCKLEY, W.: 'Metal precipitates insilicon p-n junctions', J. Appl. Phys., I960, 31, pp. 1821-1824
2 WALDNER, M., and SILVO, L.: 'Lifetime preservation in dif-fused silicon',/. Electrochem. Soc, 1960, 107, pp. 298-301
3 ING, S.W., MORRISON, R.E., ALT, L.L., and ALDRICH, R.W.:'Gettering of metallic impurities from planar silicon diodes', ibid.,1963, 110, pp. 533-537
4 MURRAY, L.A., and KRESSEL, H.: 'Improvement in minoritycarrier lifetime in silicon diodes', Electrochem. Technol. 1967, 5,pp. 406-407
6 BUCK, T.M., PICKAR, K.A., POUTE, J.M., and HSIEH, CM.:'Gettering rates of various fast diffusing metal impurities in ion-damaged layers on silicon', ibid., 1972, 21, pp. 485-487
7 SEIDEL, T.E., MEEK, R.L., and CULLIS, A.G.: 'Direct compari-son of ion-damage gettering and phosphorus-diffusion getteringof Au in Si', ibid., 1975, 46, pp. 600-609
8 NASSIBIAN, A.G., BROWNE, V.A., and PERKINS, K.D.:'Generation lifetime investigations of ion-damage gettered siliconusing MOS structure', ibid., 1976, 47, pp. 992-996
9 BOARD, K., and SIMMONS, J.G.: 'Non-equilibrium response ofMOS devices to a linear voltage ramp - I. Bulk discrete traps',Solid-State Electron., 1978, 20, pp. 859-867
10 NASSIBIAN, A.G., FARAONE, L., and SIMMONS, J.G.: 'Non-equilibrium response of MOS devices to linearly varying voltages',Appl. Phys. Lett., 1978, 32, pp. 444-445
11 NASSIBIAN, A.G., FARAONE, L., and SIMMONS, J.G.: 'Non-steady-state studies on MOS devices subject to a linear voltageramp',/ Appl. Phys., 1979, 50, pp. 1439-1444
12 KERN, W., and POUNTIEN, D.A.: 'Cleaning solutions based onhydrogen peroxide for use in silicon semiconductor technology',RCA Rev., 1970, 31, pp. 187-206
13 ZERBST, M.: 'Relaxationseffekte an Halblcitcr-Isolator-Grenzflachen', Z. Angew. Phys., 1970, 22, pp. 30-33
14 SCHRODER, D.K., and GULDBERG, J.: 'Interpretation ofsurface and bulk effects using the pulsed MIS capacitor', Solid-State Electron., 1971, 14, pp. 1285-1297
15 MILNES, A.G.: 'Deep impurities in semiconductors' (JohnWiley and Sons, 1973) pp. 11-25
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