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FPGA IMPLEMENTATION:

SEVEN SEGMENT INTERFACING

September 2014

ABSTRACT:

The paper presents a simple design and implementation of a Seven-Segment Displays Designs

on BASYS 2 Board. Seven segments are used to display the input data at the input terminal;

input as well as the output data is displayed at the receiver terminal. The input fed into any

processing unit is in the form of analog signals and are converted into the digital data and is

processed. Then the output data is converted form digital to analog form for displaying the

processed output data.

This paper is for basic implementation in “BASYS2 Board” which may be applied in the study to

connect the board using computer and get solution to the problems of digits binary used their

equivalents in hexadecimal.

The purpose of this paper is to practice implementation Verilog codes and performing

simulations on various counter designs and implement designs on FPGA utilizing switches,

LEDs, and seven-segment displays. The power consumption and the delay of this unit is

estimated using the synthesizer „Xilinx‟ and is simulated using „ModelSim‟.

Author: Pallavi Atha Sr. Technical Marketing Engineer

(Assisted by Tripti Singh-Intern)

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INTRODUCTION:

Every unit in digital circuit has certain applications to be performed in them using the data fed as

an input to the unit. Numerals and alphabets are displayed using the seven segment display unit.

The seven segment display unit plays a major role in providing the data display effectively when

compared to the other display units. The seven segment displays are placed almost with equal

size in the shape of hexagons. In the seven segments display unit each and every segment is fixed

with the LED's and are made to trigger based on the input voltage fed to the particular segment

to be enabled.

In this paper, the input to the LED's in the display unit are triggered by switching the form of

digital input signal from 0's to 1's using the conventional logic gates. The expression for

triggering each and every segment is obtained using the truth table and is simplified for Boolean

expressions usingK-map. In order to select the particular unit in the seven segments display unit

the corresponding logic combinations are to be enabled respectively. The gates used for this

design implementation

SEVEN SEGMENT DISPLAY:

A seven-segment display (SSD), or seven-segment indicator, is a form of electronic display

device for displaying decimal numerals that is an alternative to the more complex dot-matrix

displays.

To implement any display unit, seven segments display unit is the best approach. Seven segment

display unit requires very less wiring, low cost and easily available in the market. In this

proposed module, the seven segment display unit is implemented by using the Boolean

expression so as to reduce the number of gates used. The reduction in thenumber of gates

reduces the latency and the power consumption of the display unit.

The seven segments in the display unit are named as A, B, C, D, E, F and G as shown in fig.1.

each and every segment in the display unit is attached with the active component LED‟s which

emit light on the particular segment at once the input voltage is fed to the desired segment. In

case of the input signal with the desired threshold value is not attained the LED‟s are turned off.

The switching ON and switching OFF of any segment in the display unit is done by feeding 0‟s

(0v) or 1‟s (threshold voltage to switch ON the LED) at the anode of the LED terminal

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FPGA – Field Programmable Gate Array:

Field Programmable Gate Array (FPGA) is a kit which is made up of several Programmable

Logic Arrays. The FPGA enables the implementation of any logic functions with reduced cost,

high performance, space and reduced power dissipation. Spartan 3E FPGAs offer the ideal

combination of performance and flexibility to address requirements for high resolution, video

analytics, and increased channels in video Surveillance system.

The Xilinx tool is used to implement the logic functions efficiently in the Spartan 3E kit

(BASYS 2 Diligent ).The power supply required for the FPGA is comparatively very low. It is a

programmable analog and digital peripherals, some control the regulation and load switches in

the battery powered system. In this proposed module the seven segment display unit is

performed using the FPGA kit which effectively utilizes low power for the implementation and

with minimum latency. The selection of each and every segment in the display unit is performed

digitally. Boolean expression is the simplified form used to perform the logic in the FPGA kit.

INTERFACING SEVEN SEGMENTWITH FPGA:

Figure 1 : INTERCONNECTION WITH FPGA

The Spartan-3 Kit board has a four-character, seven

segment LED display controlled by FPGA user-I/O

pins. Each digit shares eight common control signals

to light individual LED segments. Each individual

character has a separate anode control input.

The pin number for each FPGA pin connected to the

LED display appears in parentheses. To light an

individual signal, drive the individual segment

control signal Low along with the associated anode

control signal for the individual character.

A Low value lights the individual segment, a High

turns off the segment. A Low on the A input signal,

lights segment „a‟ of the display. The anode controls

for the remaining characters, AN[2:0] are all High,

and these characters ignore the values presented on A

through G and DP.

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Figure 2 : SEVEN SEGMENT DISPLAY TABLE

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CONCEPT FOR INTERFACING SEVEN SEGMENT WITH

FPGA:

Seven-segment displays may use a liquid crystal display (LCD) or arrays of light-emitting diodes

(LEDs). In a simple LED package, which is the type of display that we will be working with,

typically all of the cathodes (negative terminals) or all of the anodes (positive terminals) of the

segments are connected together and brought out to a common pin; these devices are referred

to as „common cathode‟ or „common anode‟ devices respectively. The other terminals are used

to control the segments via a seven-segment decoder.

TOOLS & EQUIPMENTS USED:

1. XILINX SPARTAN 3E FPGA Board (Basys2 Digilent)

2. XILINX 13.1 SUITE

3. ISE Impact (0.76xd)

4. Adept Software (FPGA)

5. Connecting leads and wires

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BASIC IMPLEMENTATION OF SEVEN SEGMENT :-

Display : 0 to 9 & A to F using UP & Down Counter:

Brief Explanation:

In our Basys2 FPGA Board we have 4 seven segment display. We would display 0 to 9 and A to

F in all the seven segment at same time frame. We have a UP_DOWN counter – if UP is selected

then we would increment from 0 to F – if DOWN is selected we would move in reversed

direction is F to 0.

Flow Chart :

initialization

•Input : Clk, Reset, Up_down counter

•Output : a,b,c,d,e,f,g, an1,an2,an3,an0

•Output reg : Cout

Delay

•Declare Clock/Frequency divider to reduce speed of the board : for display

Functioning

•All anode = 0 (As display is on all seven segments )

•Depending on Up or Down - counter will work

•Depending on counter - Combination will be displayed on respective cathodes.(refer table)

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Output On FPGA:

Figure 3 : OUTPUT OF UP & DOWN COUNTER

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Figure 4 : VIEW OF XILINX – SYNTHESISE RESULT

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Display : Name of Company – “teva”

Brief Explanation:

In our Basys2 FPGA Board we have 4 seven segment display, Hence We would display only

four alphabets i.e., “teva” in respective seven segment at same time frame.

Flow Chart :

Output On FPGA:

Figure 5: OUTPUT OF FPGA : DISPLAY : TEVA

initialization

•Input : Clk, Reset

•Output : a,b,c,d,e,f,g, an1,an2,an3,an0

•Output reg : Cout

Delay

•Declare Clock/Frequency divider to reduce speed of the board : for display (We may not declare also as its a single display)

Functioning

•Declare are the respective letters to be 0 and rest as 1 with specific individul delay

•Combination for "teva" will be displayed on respective cathodes.(refer table)

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Display Increment Counter in Binary

Brief Explanation:

In our Basys2 FPGA Board we would display Binary Increment counter,which states as follows:

i.e 0 to 9 in binary pattern(BIN). In this we have to change control signal of Anode

Flow Chart :

initialization

•Input : Clk, Reset

•Output : a,b,c,d,e,f,g, an1,an2,an3,an0

•Output reg : Cout , X , Y

Delay

•Declare Clock/Frequency divider to reduce speed of the board : for display

•Two streaching loops are used for display different numbers simultaneously in all the seven segments

Functioning

•Two loops are used for display with minute delay: Display Numeric numbers & Choose the Seven segment to be displayed in every increment

•Binary values are displayed from 0 to F in seven segment

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Output On FPGA:

Figure 6: OUTPUT OF BINARY SEQUENCE AS SHOWN IN TABLE

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PROCESS FOR INTERFACING SEVEN SEGMENT

DISPLAY WITH FPGA:

I. Concept implementation using HDL (Verilog/VHDL).

II. New project is created using Xilinx ISE Design Suite 13.3

III. Specifications:

family as Spartan3E

device as XC3S500E,

package as FG320 and

Speed as -4.

IV. Create implementation constraints file( .ucf ) and properly map all the input/output ports to

the pins of Spartan3E FPGA board.

V. Synthesize and implement design and Generate bit/ programming file.

VI. Open Adept software for FPGA

VII. Browse the bit file For FPGA

VIII. Plug on Board with USB cable and switch it on

IX. Select program to be executed.

X. Output will be displayed in FPGA.

Figure 7 TOOL USED FOR FPGA

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CONCLUSION:

The seven segments of a display unit have been proposed by using the Boolean expression and is

implemented in the FPGA kit in the Xilinx synthesizer. The main result is done for “Basys2

FPGA Board” by connection by computer and get solution to the problems of digits binary used

their equivalents in hexadecimal.

The purpose of this paper is to learn how to connect simple input and output devices to an FPGA

chip and implement a circuit that uses these devices. We will use the switches SW 9−0 on the

FPGA board as inputs to the circuit. We will use light emitting diodes (LEDs) and 7-segment

displays as output devices

“Basys2 FPGA Board” is important for many applications, so the practice is important to get

knowledge about implementation Verilog codes and performing simulations on various counter

designs and implement designs on FPGA board utilizing switches, LEDs, and seven-segment

displays and digital electronics Systems