+ All Categories
Home > Documents > Architectural Aspects in Design and Analysis of SOT- based ... · PDF fileOutline Motivation...

Architectural Aspects in Design and Analysis of SOT- based ... · PDF fileOutline Motivation...

Date post: 14-Mar-2018
Category:
Upload: vuongdien
View: 221 times
Download: 4 times
Share this document with a friend
30
KIT University of the State of Baden-Wuerttemberg and National Research Center of the Helmholtz Association INSTITUTE OF COMPUTER ENGINEERING (ITEC) CHAIR FOR DEPENDABLE NANO COMPUTING (CDNC) www.kit.edu Architectural Aspects in Design and Analysis of SOT- based Memories Rajendra Bishnoi, Mojtaba Ebrahimi, Fabian Oboril & Mehdi Tahoori
Transcript
Page 1: Architectural Aspects in Design and Analysis of SOT- based ... · PDF fileOutline Motivation SOT based MRAM STT-MRAM & Limitations Basics of SOT-MRAM Simulation tool flow Results For

KIT – University of the State of Baden-Wuerttemberg and

National Research Center of the Helmholtz Association

INSTITUTE OF COMPUTER ENGINEERING (ITEC) – CHAIR FOR DEPENDABLE NANO COMPUTING (CDNC)

www.kit.edu

Architectural Aspects in Design and Analysis of SOT-based Memories

Rajendra Bishnoi, Mojtaba Ebrahimi, Fabian Oboril & Mehdi Tahoori

Page 2: Architectural Aspects in Design and Analysis of SOT- based ... · PDF fileOutline Motivation SOT based MRAM STT-MRAM & Limitations Basics of SOT-MRAM Simulation tool flow Results For

Outline

Motivation

SOT based MRAM

STT-MRAM & Limitations

Basics of SOT-MRAM

Simulation tool flow

Results

For various memory technologies

System-level

Summary & Conclusion

ASPDAC-2014 2 Mehdi Tahoori --- Architectural Aspects in Design and Analysis of SOT-MRAM

Page 3: Architectural Aspects in Design and Analysis of SOT- based ... · PDF fileOutline Motivation SOT based MRAM STT-MRAM & Limitations Basics of SOT-MRAM Simulation tool flow Results For

Outline

Motivation

SOT based MRAM

STT-MRAM & Limitations

Basics of SOT-MRAM

Simulation tool flow

Results

For various memory technologies

System-level

Summary & Conclusion

ASPDAC-2014 3 Mehdi Tahoori --- Architectural Aspects in Design and Analysis of SOT-MRAM

Page 4: Architectural Aspects in Design and Analysis of SOT- based ... · PDF fileOutline Motivation SOT based MRAM STT-MRAM & Limitations Basics of SOT-MRAM Simulation tool flow Results For

Memory Hierarchy

ASPDAC-2014 4 Mehdi Tahoori --- Architectural Aspects in Design and Analysis of SOT-MRAM

SRAM

DRAM

FLASH

DISK

High Performance &

Endurance

High Capacity

A Universal Memory Required to overcome these limitations

Non Volatile Magnetic RAM is promising candidate

High Leakage, Scalability Issue

and Radiation Vulnerable

Refresh, Scalability Issue and

Destructive read

Endurance, Scalability Issue

and Radiation Vulnerable

Page 5: Architectural Aspects in Design and Analysis of SOT- based ... · PDF fileOutline Motivation SOT based MRAM STT-MRAM & Limitations Basics of SOT-MRAM Simulation tool flow Results For

Motivation

STT-MRAM has

potential to become

universal memory

technology

However, obstacles are

High write current & time

“Read Disturb”

Addressed using Spin

Orbit Torque (SOT)

ASPDAC-2014 5 Mehdi Tahoori --- Architectural Aspects in Design and Analysis of SOT-MRAM

Spin Orbit

Torque

Spin Transfer

Torque

Perpendicular

Anisotropy

Separate

Read & Write

current Path

Results in

Low Write Current

Low Switching Time

Avoid Read Disturb

Page 6: Architectural Aspects in Design and Analysis of SOT- based ... · PDF fileOutline Motivation SOT based MRAM STT-MRAM & Limitations Basics of SOT-MRAM Simulation tool flow Results For

Outline

Motivation

SOT based MRAM

STT-MRAM & Limitations

Basics of SOT-MRAM

Simulation tool flow

Results

For various memory technologies

System-level

Summary & Conclusion

ASPDAC-2014 6 Mehdi Tahoori --- Architectural Aspects in Design and Analysis of SOT-MRAM

Page 7: Architectural Aspects in Design and Analysis of SOT- based ... · PDF fileOutline Motivation SOT based MRAM STT-MRAM & Limitations Basics of SOT-MRAM Simulation tool flow Results For

Basics of Spin Transfer Torque (STT)

Two ferromagnetic layers seperated by a oxide barrier layer

Magnetic Tunneling Junction (MTJ) Cell is a storing device

Value stored as a resistance state

ASPDAC-2014 7 Mehdi Tahoori --- Architectural Aspects in Design and Analysis of SOT-MRAM

Free Layer

Barrier Oxide Layer, MgO

Reference Layer

Parallel Magnetisation (P)

Low Resistance Anti- Parallel Magnetisation (AP)

High Resistance

Page 8: Architectural Aspects in Design and Analysis of SOT- based ... · PDF fileOutline Motivation SOT based MRAM STT-MRAM & Limitations Basics of SOT-MRAM Simulation tool flow Results For

Bit-cell using STT based MTJ cell

Bit-cell has three terminals:

Bit-Line

Word-Line

Source-Line

Read current is unidirectional

Write current is bidirectional

Possible “Read Disturb”

Same path for read and write

ASPDAC-2014 8 Mehdi Tahoori --- Architectural Aspects in Design and Analysis of SOT-MRAM

Source-Line

Word-Line

Read & Write

Current Path

Page 9: Architectural Aspects in Design and Analysis of SOT- based ... · PDF fileOutline Motivation SOT based MRAM STT-MRAM & Limitations Basics of SOT-MRAM Simulation tool flow Results For

Merits & Demerits of STT

Merits:

High Density

Non-Volatility

Scalability

CMOS Compability

ASPDAC-2014 9 Mehdi Tahoori --- Architectural Aspects in Design and Analysis of SOT-MRAM

Low Read Latency

High Endurance

High Retention

Radiation Immune

Demerits:

High Write Power

High Write Latency

Aditional Layer requires

Read Disturb

Page 10: Architectural Aspects in Design and Analysis of SOT- based ... · PDF fileOutline Motivation SOT based MRAM STT-MRAM & Limitations Basics of SOT-MRAM Simulation tool flow Results For

In-Plane Vs Perpendicular Anisotropy

ASPDAC-2014 10 Mehdi Tahoori --- Architectural Aspects in Design and Analysis of SOT-MRAM

Parameters In-Plane Magnetic

Anisotropy

Perpendicular

Magnetic Anisotropy

Diagram

Ratio of critical switching

current to thermal stability, IC

𝛼

𝜂× 1 +

Hd

2Hk

where, 𝛼= damping constant,

𝜂=STT efficiency, Hd =

demagnetization field, Hk=in-plane

anisotropy field

𝛼

𝜂

switching current High Low

switching time More Less

Perpendicular magnetic anisotropy

Low switching current

Less switching time

“Read Disturb“ still remains challenge

Page 11: Architectural Aspects in Design and Analysis of SOT- based ... · PDF fileOutline Motivation SOT based MRAM STT-MRAM & Limitations Basics of SOT-MRAM Simulation tool flow Results For

Spin Orbit Torque

Separate read and write current paths

One additional terminal

No read disturb

Need not to maintain ratio of IRead

IWrite

Less current required to flip due to parallel magnetization

Fast switching

ASPDAC-2014 11 Mehdi Tahoori --- Architectural Aspects in Design and Analysis of SOT-MRAM

Word-Line

Source-Line

Read

Current

Path Write

Current

Path

Page 12: Architectural Aspects in Design and Analysis of SOT- based ... · PDF fileOutline Motivation SOT based MRAM STT-MRAM & Limitations Basics of SOT-MRAM Simulation tool flow Results For

STT-MRAM VS SOT-MRAM

ASPDAC-2014 12 Mehdi Tahoori --- Architectural Aspects in Design and Analysis of SOT-MRAM

Parameter STT-MRAM SOT-MRAM

Bit-cell Terminals

(1T1MTJ type)

3 4

Access Transistor 8F 2F

Current (uA) 750 100

Write Current Period (ns) 11 0.3

Read Disturb High Probability Almost Nil

Read Energy (pJ) 1.8 1.8

Write Energy (pJ) 3.9 (reset)/3.4(set) 0.1

Switching Behavior Asymmetrical Almost Symmetrical

Magnetic Anisotropy In-Plane Perpendicular

Page 13: Architectural Aspects in Design and Analysis of SOT- based ... · PDF fileOutline Motivation SOT based MRAM STT-MRAM & Limitations Basics of SOT-MRAM Simulation tool flow Results For

Tool Simulation Flow

ASPDAC-2014 13 Mehdi Tahoori --- Architectural Aspects in Design and Analysis of SOT-MRAM

SOT

Model SPICE

CMOS

Model

NVSIM

GEM5

Memory

Configuration

Processor

Configuration

Circuit-Level

Memory

Architecture-Level

System-Level

Bit-Cell Characteristics

1

Page 14: Architectural Aspects in Design and Analysis of SOT- based ... · PDF fileOutline Motivation SOT based MRAM STT-MRAM & Limitations Basics of SOT-MRAM Simulation tool flow Results For

Basic Memory Architecture

ASPDAC-2014 14 Mehdi Tahoori --- Architectural Aspects in Design and Analysis of SOT-MRAM

Word-line drives the access transistor of bit-cell

Write Enable =1, for write operation

Write Enable =0, for read operation

Page 15: Architectural Aspects in Design and Analysis of SOT- based ... · PDF fileOutline Motivation SOT based MRAM STT-MRAM & Limitations Basics of SOT-MRAM Simulation tool flow Results For

Simulation models

STT-MTJ

SPICE modelling framework presented in [ W. Guo,

JAP-2010]

SOT-MTJ

Compact Verilog-A framework presented in [ K. Jabeur,

IJESE-2013]

CMOS

General purpose TSMC 65nm models.

ASPDAC-2014 15 Mehdi Tahoori --- Architectural Aspects in Design and Analysis of SOT-MRAM

Page 16: Architectural Aspects in Design and Analysis of SOT- based ... · PDF fileOutline Motivation SOT based MRAM STT-MRAM & Limitations Basics of SOT-MRAM Simulation tool flow Results For

Tool Simulation Flow

ASPDAC-2014 16 Mehdi Tahoori --- Architectural Aspects in Design and Analysis of SOT-MRAM

SOT

Model SPICE

CMOS

Model

NVSIM

GEM5

Memory

Configuration

Processor

Configuration

Circuit-Level

Memory

Architecture-Level

System-Level

Memory Characteristics

2

Page 17: Architectural Aspects in Design and Analysis of SOT- based ... · PDF fileOutline Motivation SOT based MRAM STT-MRAM & Limitations Basics of SOT-MRAM Simulation tool flow Results For

NVSIM flow

ASPDAC-2014 17 Mehdi Tahoori --- Architectural Aspects in Design and Analysis of SOT-MRAM

Hierarchy Reports

for given Memory

Configuration

Architecture related Information like

Type of Memory

Capacity

Data Width

Local & Global Wire Type

Routing Type

Optimization Type

Array Organization

Design Constraint

Switch for CACTI assumption

Cell related Information like

Cell Type

Cell Area & Aspect Ratio

On & Off Resistance

Read power

Set & Reset Current

Set & Reset time

Set & Reset Energy

Access transistor Width

Following modification done:

Cell information

Memory architecture information

Enable the asymmetrical write behavior

Page 18: Architectural Aspects in Design and Analysis of SOT- based ... · PDF fileOutline Motivation SOT based MRAM STT-MRAM & Limitations Basics of SOT-MRAM Simulation tool flow Results For

Tool Simulation Flow

ASPDAC-2014 18 Mehdi Tahoori --- Architectural Aspects in Design and Analysis of SOT-MRAM

SOT

Model SPICE

CMOS

Model

NVSIM

GEM5

Memory

Configuration

Processor

Configuration

Circuit-Level

Memory

Architecture-Level

System-Level

Performance Number

3

Page 19: Architectural Aspects in Design and Analysis of SOT- based ... · PDF fileOutline Motivation SOT based MRAM STT-MRAM & Limitations Basics of SOT-MRAM Simulation tool flow Results For

Input & Output Parameters

ASPDAC-2014 19 Mehdi Tahoori --- Architectural Aspects in Design and Analysis of SOT-MRAM

Input

Parameters

Output

Parameters

GEM5 Simulator

Processor

Configuration Applications

Memory

design data

Performance

• Access numbers

• Hit/Miss rate

• Instruction-per-

cycle

Runtime

Dynamic

Energy

Per Access

Energy

Access

Numbers

NVSim GEM5

Static

Energy

Leakage

Power Runtime

Extended GEM5 to support MRAM

Changed uniform read- write latency to non-uniform

Page 20: Architectural Aspects in Design and Analysis of SOT- based ... · PDF fileOutline Motivation SOT based MRAM STT-MRAM & Limitations Basics of SOT-MRAM Simulation tool flow Results For

Outline

Motivation

SOT based MRAM

STT-MRAM & Limitations

Basics of SOT-MRAM

Simulation tool flow

Results

For various memory technologies

System-level

Summary & Conclusion

ASPDAC-2014 20 Mehdi Tahoori --- Architectural Aspects in Design and Analysis of SOT-MRAM

Page 21: Architectural Aspects in Design and Analysis of SOT- based ... · PDF fileOutline Motivation SOT based MRAM STT-MRAM & Limitations Basics of SOT-MRAM Simulation tool flow Results For

Comparison of various Memory Technologies

Values are extracted using NVSim for

512 Kbyte capacity

Latency optimization

ASPDAC-2014 21 Mehdi Tahoori --- Architectural Aspects in Design and Analysis of SOT-MRAM

Parameters SRAM NAND

FLASH

STT-

MRAM

SOT-

MRAM

PC-

RAM

R-

RAM

Area [mm2] 2.8 0.2 1.6 1.5 0.3 0.7

Read Latency [ns] 2.2 565 1.2 1.13 0.6 1.2

Write Latency [ns] 2.0 2× 105 11.2 1.4 150 21

Read Energy [pJ] 587 3921 260 247 363 193

Write Energy [pJ] 355 6902 2337 334 63670 592

Leakage [mW] 932 77 387 254 153 115

Page 22: Architectural Aspects in Design and Analysis of SOT- based ... · PDF fileOutline Motivation SOT based MRAM STT-MRAM & Limitations Basics of SOT-MRAM Simulation tool flow Results For

Area Comparison for various memory sizes

ASPDAC-2014 22 Mehdi Tahoori --- Architectural Aspects in Design and Analysis of SOT-MRAM

SRAM is better

Voltage sense amplifier used for SRAM

High current drivers for STT and SOT

SOT built on STT framework with different access transistor size

STT & SOT are better with capacity increase

Page 23: Architectural Aspects in Design and Analysis of SOT- based ... · PDF fileOutline Motivation SOT based MRAM STT-MRAM & Limitations Basics of SOT-MRAM Simulation tool flow Results For

Read & Write Latency Comparison

ASPDAC-2014 23 Mehdi Tahoori --- Architectural Aspects in Design and Analysis of SOT-MRAM

SRAM varies linearly with capacity increase

STT & SOT, remain almost flat with capacity increase

Page 24: Architectural Aspects in Design and Analysis of SOT- based ... · PDF fileOutline Motivation SOT based MRAM STT-MRAM & Limitations Basics of SOT-MRAM Simulation tool flow Results For

Energy Comparison

ASPDAC-2014 24 Mehdi Tahoori --- Architectural Aspects in Design and Analysis of SOT-MRAM

SOT has almost same read & write access energy

Page 25: Architectural Aspects in Design and Analysis of SOT- based ... · PDF fileOutline Motivation SOT based MRAM STT-MRAM & Limitations Basics of SOT-MRAM Simulation tool flow Results For

Leakage Comparisons

ASPDAC-2014 25 Mehdi Tahoori --- Architectural Aspects in Design and Analysis of SOT-MRAM

SRAM varies linearly with capacity increase

STT & SOT, leakage is due to periphery circuits

Page 26: Architectural Aspects in Design and Analysis of SOT- based ... · PDF fileOutline Motivation SOT based MRAM STT-MRAM & Limitations Basics of SOT-MRAM Simulation tool flow Results For

System-Level Evaluation

ASPDAC-2014 26 Mehdi Tahoori --- Architectural Aspects in Design and Analysis of SOT-MRAM

Configuration details for Experiments:

Processor : single core, 3 GHz

L1-Cache : 32 Kbyte with 64B Data Width

L2-Cache : 512 Kbyte with 64B Data Width

Application (MiBench):

BasicMath, BitCnt, Qsort, Dijkstra, Patricia, StrSearch, SHA, CRC, FFT

Page 27: Architectural Aspects in Design and Analysis of SOT- based ... · PDF fileOutline Motivation SOT based MRAM STT-MRAM & Limitations Basics of SOT-MRAM Simulation tool flow Results For

Comparisons with Various Cache conf.

ASPDAC-2014 27 Mehdi Tahoori --- Architectural Aspects in Design and Analysis of SOT-MRAM

SRAM+SOT is best area combination.

SOT+SOT is best energy configuration

Page 28: Architectural Aspects in Design and Analysis of SOT- based ... · PDF fileOutline Motivation SOT based MRAM STT-MRAM & Limitations Basics of SOT-MRAM Simulation tool flow Results For

Benchmark Analysis

ASPDAC-2014 28 Mehdi Tahoori --- Architectural Aspects in Design and Analysis of SOT-MRAM

SOT only solution is best for low power.

For runtime, the best combination is SRAM+SOT.

Page 29: Architectural Aspects in Design and Analysis of SOT- based ... · PDF fileOutline Motivation SOT based MRAM STT-MRAM & Limitations Basics of SOT-MRAM Simulation tool flow Results For

Outline

Motivation

SOT based MRAM

STT-MRAM & Limitations

Basics of SOT-MRAM

Simulation tool flow

Results

For various memory technologies

System-level

Summary & Conclusion

ASPDAC-2014 29 Mehdi Tahoori --- Architectural Aspects in Design and Analysis of SOT-MRAM

Page 30: Architectural Aspects in Design and Analysis of SOT- based ... · PDF fileOutline Motivation SOT based MRAM STT-MRAM & Limitations Basics of SOT-MRAM Simulation tool flow Results For

Summary & Conclusion

Developed hybrid memory architecture based on

SOT-MRAM

A cell-level information is extracted using SPICE

simulations

NVSim tool is explored to estimate the design data

Many applications run using GEM5 simulator

SOT is the best solution for low power

Overall best is hybrid memory architecture

SRAM+SOT

ASPDAC-2014 30 Mehdi Tahoori --- Architectural Aspects in Design and Analysis of SOT-MRAM


Recommended