ARM CPU Internal I

Prof. Taeweon SuhComputer Science Education

Korea University

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Overview

• For the sake of your understanding, we simplify the CPU and its system structure

2

CPU

North Bridge

South Bridg

e

Main Memor

y(DDR)

FSB (Front-Side Bus)

DMI (Direct Media I/F)

Real-PC system

Memory(Instruction,

data)

ARM CPU

Address Bus

Data Bus

Simplified

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Actual ARM Connection

• ARM CPU has separate connections to memory (caches)

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ARM CPU core

InstructionCache

Address Bus

Data Bus

Instruction fetch

Data access

Address Bus

Data Bus

Data Cache

Memory

Instruction/Data access

Address Bus

Data Bus

ARM920T

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Overview

• Microarchitecture is composed of datapath and control Datapath operates on words of data

• Datapath elements are used to operate on or hold data within a processor• Datapath elements include the register file, ALU, muxes, and memory

Control tells the datapath how to execute instructions• Control unit receives the current instruction from the datapath and tells the

datapath how to execute that instruction• Specifically, the control unit produces mux select, register enable, ALU

control, and memory write signals to control the operation of the datapath

• Essential ARM instructions Data processing instructions: add, sub, cmp, and, or Memory access instructions: ldr, str Branch instructions: b, bl

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Instruction Execution in CPU

• Generic steps of the instruction execution in CPU Fetch uses the program counter (PC) to supply the instruction

address and fetch instruction from memory Decoding decodes instruction and reads operands

• Extract opcode: determine what operation should be done• Extract operands: register numbers or immediate from fetched instruction

Execution• Use ALU to calculate (depending on instruction class)

Arithmetic or logical result Memory address for load/store Branch target address

• Access memory for load/store

Next Fetch• PC target address or PC + 4

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ARM CPU coreAddress Bus

Data Bus Instruction/Data

Memory

Fetch with PC

ExecuteAddress Bus

Data Bus

Decode

PC = PC +4

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ARM CPU core

Instruction Fetch

6

PC

Memory

Address Out

Add

4

32-bit register (flip-flops)

Increment by 4 for the next

instruction

32

instruction

resetclock

• What is PC on reset in ARM? PC = 0x0000_0000

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Memory

• Memory is classified into RAM (Random Access Memory) and ROM (Read-Only Memory) RAM is classified into DRAM (Dynamic RAM) and SRAM

(Static RAM) DDR is a kind of DRAM

• DDR is a short form of DDR (Double Data Rate) SDRAM (Synchronous DRAM)

• DDR is used as main memory in modern computers

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Simple ARM Test Code

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assemble

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Instruction Decoding

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• Instruction decoding separates the fetched instruction into the fields Opcode determines which operation the instruction

wants to do• Control logic should be designed to supply control signals to

datapath elements (such as ALU and register file) Operands

• Register numbers in the instruction are sent to the register file

• Immediate field is either sign-extended or zero-extended depending on instructions*

*It seems immediate is zero-extended in ARM case. If you write “add r1, r2, #-12”, assembler generates “sub r1, r2, 12”. The shifter operand could be “logical (or arithmetic) shift right a register by immediate. In this case, the register is zero-filled or signed-filled in the shifted vacant bits

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ARM CPU

Schematic with Instruction Decoding

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Memory

AddressOut

32

instruction

PC

Add4

resetclock

Register File

Inst[15:12] (=Rd)

Inst[19:16] (=Rn)

Inst [3:0] (=Rm)

Rn32

Rm32

wd32

RegWrite

R0R1R2R3

R14R15 (PC)

…

Control Unit

Opcode

8 32zero-

extended

imm

RegWrite

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Instruction Execution #1

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• Arithmetic and logical instructions Examples: add, adc, sub, sbc, cmp, mov, and, or … Two source operands

• One is always a register• The other has two basic forms: Immediate or register (optionally shifted)

sub r1, r2, r3 # r1 = r2 – r3

add r1, r2, r3 # r1 = r2 + r3

sub opcode: 0010

add opcode: 0100

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Data Processing Instruction Formats

12Source: ARM Architecture Reference Manual

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ARM CPU

Schematic with Instruction Execution #1

13

Memory

AddressOut

32

instruction

PC

Add4

resetclock

Register File

Inst[15:12] (=Rd)

Inst[19:16] (=Rn)

Inst [3:0] (=Rm)

Rn32

Rm32

wd32

RegWrite

R0R1R2R3

R14R15 (PC)

…

Control Unit

opcode

8 32zero-

extended

imm

ALU

mux

ALUSrc

ALUSrcRegWrite

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Instruction Execution #2

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• Memory access instructions ldr, str instructions

ldr R1, [R2, #4] // R1 <= [R2 + 4]

str R1, [R2,R3] // [R2 + R3] <= R1

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Memory Access Instruction Formats

15Source: ARM Architecture Reference Manual

• Load and Store Word or Unsigned Byte instructions

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ARM CPU

Schematic with Instruction Execution #2

16

Memory

AddressOut

32

instruction

PC

Add4

resetclock

Register File

Inst[15:12] (=Rd)

Inst[19:16] (=Rn)

Inst [3:0] (=Rm)

Rn32

Rm32

wd32

R0R1R2R3

R30R31

…

Control Unit

opcode

8 32zero-

extended

imm

ALU

mux

ALUSrc

Memory

Address

ReadData

WriteData

MemWriteALUSrcRegWrite

MemWrite

MemtoReg

MemtoReg

mux

ldr R1, [R2, #4] // R1 <= [R2 + 4]str R1, [R2, R3] // [R2 + R3] <= R1

Rd

8-or-12

12

8-or-12

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Instruction Execution #3

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• Execution of the branch and jump instructions b, bl instructions

b target (offset)

Destination = (PC + 8) + sign-extend (imm << 2)

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ARM CPU

Schematic with Instruction Execution #3 (B)

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Memory

AddressOut

32

instruction

Register File

Inst[15:12] (=Rd)

Inst[19:16] (=Rn)

Inst [3:0] (=Rm)

Rn32

Rm32

wd32

R0R1R2R3

R14R15 (PC)

…

Control Unit

opcode

12 32zero-

extendedimm

ALU

mux

ALUSrc

Memory

Address

ReadData

WriteData

MemWrite

MemtoReg

mux

Note that Branch Destination = (PC+8) + (sign-extend) (imm << 2)}

32

branch

24imm Sign extension

<<2

8-or-12

Rd

PC

Add4

resetclock

Addmux

branch