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ASIC 120: Digital Systems and Standard-Cell ASIC Design

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ASIC 120: Digital Systems and Standard-Cell ASIC Design. Tutorial 1: Introduction to Digital Circuits October 11, 2005. Outline. Digital Systems Combinational Logic NOT, AND, OR, XOR, NAND, etc. mux, half-adder, full-adder Sequential Logic flip-flop/register, shift register, counter - PowerPoint PPT Presentation
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ASIC 120: Digital Systems and Standard- Cell ASIC Design Tutorial 1: Introduction to Digital Circuits October 11, 2005
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Page 1: ASIC 120: Digital Systems and Standard-Cell ASIC Design

ASIC 120: Digital Systems and Standard-Cell ASIC Design

Tutorial 1: Introduction to Digital Circuits

October 11, 2005

Page 2: ASIC 120: Digital Systems and Standard-Cell ASIC Design

Outline

• Digital Systems• Combinational Logic

– NOT, AND, OR, XOR, NAND, etc.– mux, half-adder, full-adder

• Sequential Logic– flip-flop/register, shift register, counter– state machines

Page 3: ASIC 120: Digital Systems and Standard-Cell ASIC Design

Digital Systems

• Analog vs. Digital– continuously varying vs. discrete– imprecise vs. precise– 0..1 vs. 0 or 1

• Digital systems excel at…– repetitive calculations– large amounts of data– reproducible results

Page 4: ASIC 120: Digital Systems and Standard-Cell ASIC Design

The Big Picture

Page 5: ASIC 120: Digital Systems and Standard-Cell ASIC Design

The Big Picture

FreescalePowerPC

microprocessor(PPC)

MPC850 family

RAMXilinx

Spartan-IIXC2S30FPGA

AlteraPLD

Ethernet Connector

Page 6: ASIC 120: Digital Systems and Standard-Cell ASIC Design

Combinational and Sequential Logic

• We can break a digital system into two types of logic

• Combinational– computation happens

in a linear fashion• Sequential

– computation involves a feedback loop (memory)

In Out

CombinationalInput Output

In Out

CombinationalInput Output

Feedback

Page 7: ASIC 120: Digital Systems and Standard-Cell ASIC Design

Combinational Logic: NOT

A X0 1

1 0

Input Output

Truth Table

Page 8: ASIC 120: Digital Systems and Standard-Cell ASIC Design

Combinational Logic: AND

A B X0 0 00 1 01 0 0

1 1 1

Page 9: ASIC 120: Digital Systems and Standard-Cell ASIC Design

Combinational Logic: OR

A B X0 0 00 1 11 0 1

1 1 1

Page 10: ASIC 120: Digital Systems and Standard-Cell ASIC Design

Combinational Logic: XOR

A B X0 0 00 1 11 0 1

1 1 0

Page 11: ASIC 120: Digital Systems and Standard-Cell ASIC Design

Combinational Logic: NAND

A B X0 0 10 1 11 0 1

1 1 0

Page 12: ASIC 120: Digital Systems and Standard-Cell ASIC Design

Combinational Logic: NOR, XNOR

A B X0 0 10 1 01 0 01 1 0

A B X0 0 10 1 01 0 01 1 1

Page 13: ASIC 120: Digital Systems and Standard-Cell ASIC Design

Building Combinational CircuitsA B C X

0 0 0 00 1 0 01 0 0 1

1 1 0 10 0 1 00 1 1 11 0 1 01 1 1 1

Page 14: ASIC 120: Digital Systems and Standard-Cell ASIC Design

Combinational Logic: MUX(multiplexer)

A B C X0 0 0 00 1 0 01 0 0 1

1 1 0 10 0 1 00 1 1 11 0 1 01 1 1 1

Page 15: ASIC 120: Digital Systems and Standard-Cell ASIC Design

Half AdderA B S C

0 0 0 00 1 1 01 0 1 0

1 1 0 1

Page 16: ASIC 120: Digital Systems and Standard-Cell ASIC Design

Full Adder

Page 17: ASIC 120: Digital Systems and Standard-Cell ASIC Design

Full Adder

Page 18: ASIC 120: Digital Systems and Standard-Cell ASIC Design

What I’ve Skipped

• Gates with more than two inputs• Boolean algebra• Karnaugh maps• Quine-McCluskey method• Binary arithmetic, base conversions• Practical digital circuits have more than 0s

and 1s• Transmission gates, tri-state buffers

Page 19: ASIC 120: Digital Systems and Standard-Cell ASIC Design

Sequential Logic

In Out

CombinationalInput Output

In Out

CombinationalInput Output

Feedback

Page 20: ASIC 120: Digital Systems and Standard-Cell ASIC Design

Basic Feedback Element: SR latch

S R Q Qnext

0 0 0 00 0 1 10 1 0 0

0 1 1 01 0 0 11 0 1 11 1 0 N/A1 1 1 N/A

Page 21: ASIC 120: Digital Systems and Standard-Cell ASIC Design

D Flip-Flop or RegisterD Clk Q Qnext

0 0 0 00 0 1 11 0 0 0

1 0 1 10 01 0 00 01 1 01 01 0 11 01 1 1

Page 22: ASIC 120: Digital Systems and Standard-Cell ASIC Design

Synchronous vs. Asynchronous

• Synchronous– circuit operation governed by a clock– currently more popular and practical

• Asynchronous– circuit operation independent of a clock– potentially faster than synchronous– lower power consumption– difficult to design

Page 23: ASIC 120: Digital Systems and Standard-Cell ASIC Design

Sequential Constructs

• Shift register• Counter• State Machines

Page 24: ASIC 120: Digital Systems and Standard-Cell ASIC Design

State Machines

• Useful abstract constructs for more complex sequential logic

Page 25: ASIC 120: Digital Systems and Standard-Cell ASIC Design

What I’ve Skipped

• Other flip-flops (RS, T, JK)• Other interesting sequential circuits (barrel

shifters, etc.)

Page 26: ASIC 120: Digital Systems and Standard-Cell ASIC Design

Hardware Description Languages (HDLs)

• HDL describes in text a digital circuit• Examples

– VHDL (we will look at this next time)– Verilog– AHDL– JHDL

Page 27: ASIC 120: Digital Systems and Standard-Cell ASIC Design

Hardware Description Languages (HDLs)

• schematics are useful for…– drawing high level diagrams– manually working out simple pieces of logic

• HDLs are useful for…– describing complex digital systems

• HDLs are not...– software programming languages (C, Java,

assembly, etc.)

Page 28: ASIC 120: Digital Systems and Standard-Cell ASIC Design

Summary

• Digital Systems• Combinational Logic

– NOT, AND, OR, XOR, NAND, etc.– mux, half-adder, full-adder

• Sequential Logic– flip-flop/register, shift register, counter– state machines

Page 29: ASIC 120: Digital Systems and Standard-Cell ASIC Design

UW ASIC Design Team

• www.asic.uwaterloo.ca• reference material

– Bryce Leung’s tutorials (UW ASIC website)– Michael Goldsmith’s tutorials (UW ASIC

website)– your course notes

• my contact info:Jeff Wentworth,

[email protected]


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