ASIC buck converter prototypes for LHC upgrades
S.MichelisS.Michelis1,31,3, C. Azra, C. Azra33,, B.AllongueB.Allongue11, G.Blanchot, G.Blanchot11, , F.FaccioF.Faccio11, C.Fuentes, C.Fuentes1,21,2, S.Orlandi, S.Orlandi11
11CERN – PH-ESECERN – PH-ESE22UTFSM, Valparaiso, ChileUTFSM, Valparaiso, Chile
33EPFL, LausanneEPFL, Lausanne
S.Michelis CERN/PH 2Twepp09, Paris
OutlineOutline
IntroductionIntroduction AMIS2AMIS2
FeaturesFeatures PinoutPinout WaveformsWaveforms EfficiencyEfficiency Radiation resultsRadiation results Noise performancesNoise performances
IHP1IHP1 FeaturesFeatures
ConclusionsConclusions
2
S.Michelis CERN/PH 3Twepp09, Paris
Power distribution scheme
3
Power supply 10-12V
DC/DC converter requirements:- Vin= 10-12V- Vout= 1.8-2.5V- Switching frequency ~ MHz
due to magnetic field- Rad-hard design
250Mrd, 2∙1015 n/cm2
Buck converter is the chosen topology:- high efficiency- small number of external components
Det
ect
or
DC/DC
1.8-2.5V
S.Michelis CERN/PH 4Twepp09, Paris 4
FEATURES•VIN and Power Rail Operation from +3.3V to +24V •Includes basic building blocks•External oscillator Programmable from 250kHz to 3MHz •External voltage reference •Vertical HV transistors are used as power switches
PROBLEMS•Low efficiency due to overlap between gate signals for power mosfet.
First ASIC: AMIS1First ASIC: AMIS1
S.Michelis CERN/PH 5Twepp09, Paris 5
FEATURES•VIN and Power Rail Operation from +3.3V to +12V •Internal oscillator fixed at 1Mhz, programmable up to 2.5MHz with external resistor•Internal voltage reference •Programmable delay between gate signals•Integrated feedback loop with bandwidth of 20Khz•Different Vout can be set: 1.2V, 1.8V, 2.5V, 3V, 5V•Lateral HV transistors are used as power switches•Enable pin
Second ASIC: AMIS2Second ASIC: AMIS2
+-
Vin
Vo
VI
VFS2
D2
IND
BT
ST
R
+-
driver
Cout
L
CBTSR
VDD (for control)
VSS
SUB
2.5
V
1.8
V
5V
En
ab
le fr
eq
Rf
Enable delay
R delay
VF
VI
VDD2 (for drivers)
Sawtooth generator
En_BNGPVref
SW1
SW2
SW
1
SW
2Vref
Vre
f
IPTA
T
ENABLE
VR
AM
P
S.Michelis CERN/PH 6
AMIS2 circuit details (1)
Phase
Cout
L
Vout
SW2
Vin
SW1GateSW1
SW1 off
Sw1 on
Sw1 on
3.3V
Input signal
Bootstrap capacitor
Bootstrap circuit needed to drive the high side switch (SW1) whose source is floatingAn external bootstrap capacitor is needed
Cboot > CgSW1 x10 CgSW1=7.5nF (W=0.15m)
GateSW1
time
Vo
ltag
e
Phase
S.Michelis CERN/PH 7Twepp09, Paris
AMIS2 circuit details (2)
Bandgap provides a constant reference voltage over temperature variations and radiation effect
S.Michelis CERN/PH 8Twepp09, Paris
AMIS2 circuit details (3)The integrated control loop guarantees the stability for input and load variations
S.Michelis CERN/PH 9Twepp09, Paris
AMIS2 chip layout
9
+-
Vin
Vo
+-
driver
Cout
L
CBTSR
Sawtooth generator
Bandgap
SW1
SW2
SW1
SW2
CONTROL
Sawtooth generator
Bandgap
Drivers
EA ComparatorDriver logic+bootstrap
•The chip size is 3x3 mm•The biggest part is reserved to power transistors
S.Michelis CERN/PH 10Twepp09, Paris
S2
S2
S2
S2
S2
S2
Vdd2
SUB
Enable
Enable delay
R delay
S2
D1 D1 D1 D1 D1 D1 D1 D1 IND IND IND
IND
IND
IND
IND
IND
IND
BTSTR
S2
OUT
V5V25
V18
En_B
ND
GP
En_freq
R_freq
IPT
AT
SW
1PA
D
SW
2PA
D
VFVI
VR
AM
P
VR
EF
Vss
Vdd
IND
AMIS2 pinoutAMIS2 pinout
•Several pins for power transistors.
•Red pins for the control circuit for testing
•QFN48 for testing•QFN32 for system level
test
POWER
CONTROL
10
7 mm
7 mm
Package QFN48
5 mm
5 mm
Package QFN32
D1 D1 D1 D1 D1 D1 D1
IND
IND
IND
IND
IND
D1
S2
S2
S2
S2
S2
S2
Vdd2
SUB
Enable
Enable delay
R delay
OUT
V25
V18
En_freq+S2
R_freq
VREF
Vss
Vdd
BTSTR
S.Michelis CERN/PH 11Twepp09, Paris 11
AMIS2 WaveformsAMIS2 WaveformsWaveforms of the input and output voltage, the voltage at the inductor node (Phase) and the gate signal for SW1.
-1.5 -1 -0.5 0 0.5 1
x 10-6
-2
0
2
4
6
8
10
time (s)
V
Phase
Gate SW1
Vin
VoutSW1 off
Sw1 on
Sw1 on
S.Michelis CERN/PH 12Twepp09, Paris 12
AMIS2 efficiencyAMIS2 efficiency•The measured efficiency goes up to 82%, depending on load current and frequency.•Conductive losses are the major contribution of inefficiency. •Resistance along the current path is much higher than the one expected for the power
transistors alone. This is due to on-chip routing and bondings.
Mos resistance
Silicon RSi=30mΩ
Metals RM=50mΩ
Package QFN48
Bonding RBond=80mΩ
Total resistance Rtot=RSi+RM+RBond=160mΩ (more than RSi x 5)Big impact of bondings and metal routingQFN32 will reduce a bit the bonding resistance Final integration maybe with flip chip. It can drastically reduce the conductive losses
S.Michelis CERN/PH 14Twepp09, Paris 14
AMIS2 Radiation resultsAMIS2 Radiation resultsThe X-ray radiation tests shows a decrease of the efficiency mostly due to the radiation induced leakage current , compensated by the threshold voltage shift.
V bandgap vs TID
1.255
1.26
1.265
1.27
1.275
1.28
1.285
1.00E+04 1.00E+05 1.00E+06 1.00E+07 1.00E+08 1.00E+09 1.00E+10 1.00E+11
TID (rad)
V b
andg
ap (
V)
V bandgap
Pre rad Annealing3 days
Annealing7 days
Leakage (sat)
1.E-12
1.E-11
1.E-10
1.E-09
1.E-08
1.E-07
1.E-06
1.E-05
1.E-04
1.E-03
1.E+02 1.E+03 1.E+04 1.E+05 1.E+06 1.E+07 1.E+08
TID (rad)
Lea
kag
e (A
)
A3
A2
A1
C1
Vth (linear)
0.4
0.45
0.5
0.55
0.6
0.65
0.7
0.75
1.E+02 1.E+04 1.E+06 1.E+08
TID (rad)
Vth
(V
)
A3
A2
A1
C1
S.Michelis CERN/PH 15Twepp09, Paris 15
RF=6.8KOhm
538nH
22uF
IND
100nFVdd
Vdd2
VIN
LIN REGULATOR3.3V out
1uF
1uF
Vdd2
Vdd
22uF
12nH
22uF 22uF
12nHVin
Out
Typical applicationTypical application
π filter
π filter
Linear Regulator
AMIS2
S.Michelis CERN/PH 16Twepp09, Paris
Noise tests with AMIS2
The AMIS2 power ASIC was mounted on 3 different prototypes: same schematic, different layouts.
PCB and Coilcraft coils were tested. Several placements were exercised.
CM, DM and LISN figures were acquired. The reference setup was used. Load = 0.9A x 2.5V, Switch frequency = 1.55 MHz.
S.Michelis CERN/PH 17Twepp09, Paris
AMIS2 Tests: Layout
AMIS2 V1 AMIS2 V2 AMIS2 V3
In/Out on opposite sides
Filters on opposite sides
In/Out on corner sides
Coil along Y axis
In/Out on corner sides
Coil along X axis
Filters close together Filters further closer
With inductors
S.Michelis CERN/PH 18Twepp09, Paris
Best noise performances
18
CM DM
Best noise performance of AMIS2
Proto2 Proto3 Proto5
Evolution of noise performance of prototype with commercial components
CM CM CM
S.Michelis CERN/PH 19Twepp09, Paris 19
We moved on a 0.25um technology from IHP.Tests shows that this technology has better performance • for radiation tolerance for TID and displacement damage
(see talk of F. Faccio during Power WG) • for efficiency (lower on-resistance and capacitance)A new buck design has been submitted in May 2009 and chip will be back this
week
Third ASIC: IHP1Third ASIC: IHP1
FEATURES•VIN and from +2.5V to +12V •Internal oscillator fixed at 2Mhz, programmable •External voltage reference •Adaptive logic for optimum gate delay•External feedback loop with bandwidth of 20Khz•Enable pin•Package QFN48
S.Michelis CERN/PH 20Twepp09, Paris
Conclusions
AMIS 2 has been tested and it shows good performances in term of Efficiency: up to 82% Noise: compliant with class A CISPR 11
standards and close to class B limit. Radiation: after annealing only 2% of efficiency
is lost in the worst case (Vin=10V and TID=300Mrd)
We have now moved to a 0.25um technology and first prototype has been delivered this week
20
