Asic Tape Out

C-DAC All Rights Reserved

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C-DAC/TVM/HDG/Aug’12

ASIC Tape Out:Designers’

Perspective


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2/60C-DAC/TVM/HDG/Aug’12

SoC Design Process

Specification Realization Verification Fabrication Testing


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Know the Specifications

Functionality Speed Area Power Cost Time to market.


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Realizing the Functionality

High Level Design Design Capture in C, C++,

SystemC or SystemVerilog

RTL Design Verilog / VHDL

Schematic Design

FFgates

FF


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Realizing the Functionality

PROCESSINGLOGIC

ADC

FLASH

RAM

ROM

PLL

PERIPHERAL

OUTPUTINPUT

clock


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Verifying the Functionality

Simulation, Debugging of the RTL

Confirms the realized functionality against the required functionality

Generation of Golden RTL

VCS, NCSIM, Modelsim


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Implementing the Functionality “Mapping to Hardware logic”

Primitives Simple Gates, Flip flops, Complex gates etc.

Hard macros Memories, PLLs, Analog/RF IPs

Where to get all these hardware logic?


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Choosing the Resources

Foundry Semiconductor fabrication plant (fab) is a factory where

Integrated circuits are manufactured Accepts the design as GDSII and delivers the IC in die form.

IP Cores : Any reusable unit of logic, cell, or chip layout design

EDA Tools Category of software tools for designing electronic systems

such as Printed Circuit Boards and Integrated Circuits


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The Foundry Menu

Technology Feature size of the smallest length that can be

manufactured with that particular technology (usually gate length)

“The masks for different layer have grids of squares that are either "on" or "off“, the size of each square will be half of the

specified size”. Process

Nominal High speed Low power


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Choosing from Foundry Menu Follow your Specification

Frequency of Operation Area Operating voltage Power requirement Yield

Seek the availability of the required Third party IPs

Cost


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Semiconductor Technology selection

5V 5V

Vt = 1V

VOUT2


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MOSFET Structure


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Propagation Delay of Digital Abstraction


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Propagation Delay of Digital Abstraction


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Impact of Technology Scaling

Speed of operation

Area of Chip

Power consumption


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Selecting the Process

Regular process High speed process

Propagation delay will be minimum Power consumption higher

Low power process Multi Vt transistors

Leakage power consumption low Propagation delay will be high

Multi voltage transistors Reduced dynamic power


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MOSFET as a Switch

Digital circuits : MOSFET as a switch.

VGS >= VT : Switch is ON

VGS < VT : Switch is OFF


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MOSFET as a Switch

MOSFET: Not an Ideal switch since RON ≠ ‘0’


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MOSFET switch behavior

VS = 5V, VT = 1V, RON = 1K RL= 15K


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The “Static Discipline” Need for Static Discipline : Ensures proper switching action

VS VS

M1 M2

To Switch ON the MOSFET

VIN >= VT


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Increasing the Device Speed

Reduce RL ??


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CMOS Technology


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CMOS Technology


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Process Finalizing

Reduce VT LOW VT CELLS

The device won’t turn off abruptly when VGS drops below VT

High VT cells consumes less leakage power but operates at lower speed.


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Foundry / IP Vendor Deliverables For Hardware Mapping Primitive Cell Behavioral Models (Verilog)

Describes the functionality of the Cell. Primitive Cell Abstract Timing Models (.Lib)

Describes the functionality, propagation delay & power consumption of the cells.

Primitive Cell Abstract layout (LEF) Describes the pin position for ASIC layout


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Need for Abstract Models

outputinput


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Mapping to Hardware : Synthesis Golden Register Transfer level (RTL)

Functionality to be implemented Timing libraries (.Lib)

Mapping to Foundry supported primitive cells Design Constraints (.sdc)

Speed, Power, Area Synopsys “Design compiler” , Cadence “RTL

Compiler”


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Logical DRC Constraints

Max Transitions (Max Trans) Maximum allowable slew for the gates

Max Capacitance (Max Cap) Maximum allowable load capacitance for the

gates Max Fan-out

Maximum number of fan-out for a gate.


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Constraints (SDC)

Speed Clock frequency

Power Area


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How the synthesis tool Infer hardware Infers the Input /Output pins Infers the registers Infer the combinational gates Clock treated as Ideal clock Splits the entire design into 4 groups

Input 2 Register (I2C) Register 2 Register (C2C) Register 2 Output (C2O) Input 2 Output (I2O)

Maps the cells according to the constraints


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Synthesized Logic for 800 MHz

A BC


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Static Timing Analysis

A

B

C

C L K8 0 0 M H z

D e la y o f F lipFlo p

D e la y o f A ND g a te

S e tu p t im e fo r FF

C L K


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Static Timing analysis (set-up violation)

A

B

C

C L K1 G H z

D e la y o f FlipFlo p

D e la y o f A ND g a te

S e tu p t im e fo r FF

C L K


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Synthesized Logic for 1 GHz


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Timing Library

Models cell delay as function of “input slew” and “output load”

Models cell power Switching power as function of “input slew” and

“output load”

Leakage power


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Synthesis Place and Route Mapped Netlist

Mapped to a specific foundry library Constraints

SDC LEF

Layout of the cells in Abstract form Details of Metals and Via

Timing Library .lib


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P&R :Floorplanning

Arranging all the modules and macros

Objectives Minimize area Reduce wirelength Maximize routability Determine shapes of flexible

blocks Constraints

Shape of each block Area of each block Pin locations for each block Aspect ratio


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Floor plan


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Hard macros and Soft macros


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Placement The process of arranging circuit components

on a layout surface Inputs : Set of fixed modules, netlist Output : Best position for each module based

on various cost functions Cost functions include wirelength, wire

routability, performance


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Good placement vs Bad placement

Good placement No congestion Shorter wires Less metal levels Smaller delay Lower power dissipation

Bad placement Congestion Longer wire lengths More metal levels Longer delay Higher power dissipation


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Placement


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Routing Connect the various standard cells using

wires Objective

100% connectivity of a system Minimize area Minimize wirelength

Constraints Number of routing layers Design rules Timing (delay)


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Global Routing vs Detailed Routing


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Detailed routing - Encounter


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Clock Routing & Power Routing


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Clock Tree Synthesis Why Clock needs buffering?


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Maximum fan-out of a gate


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Clock Tree Network


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Clock Tree Routing


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Clock Skew


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Synchronous Counter

FF1

FF2


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Setup Timing

Skew

CLK FF1

CLK FF2

FF2_in

FF1_in

T in_to_FF1_out + T FF1_out_to_FF2_in + T set_up_FF2 = < TCLK + TSKEW


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Hold Timing

CLK FF1

CLK FF2

FF2_in

FF1_in

T in_to_FF1_out + T FF1_out_to_FF2_in >= Thold_FF2 + TSKEW


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Setup & Hold Timing

Hold Violation is Independent of Clock Frequency


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Power Routing Creation of power grid to ensure Power Integrity


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Final layout


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Physical Verification: Design Rule Check Determines whether the physical layout of a particular chip layout

satisfies a series of recommended parameters called Design Rules


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Tape out


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Semiconductor Manufacturing Yield Percentage ratio of “good dies” over total dies manufactured


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Appendix: Inside a Semiconductor foundry


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Appendix: Semiconductor Technology Nodes

10 µm — 1971 3 µm — 1975 1.5 µm — 1982 1 µm — 1985 800 nm (.80 µm) — 1989 600 nm (.60 µm) — 1994 350 nm (.35 µm) — 1995 250 nm (.25 µm) — 1998 180 nm (.18 µm) — 1999 130 nm (.13 µm) — 2000 90 nm — 2002 65 nm — 2006 45 nm — 2008 32 nm — 2010 22 nm — 2012

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