Assembly and Packaging TWG

What has changed in the last 12 months?

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What Has Changed In The Last 12 Months?

With the continuous shrinking of device features and the emergence of new device types everything is changing. A

few key changes in the last 12 months are the focus of this presentation.

– Change dictated by Moore’s Law scaling– Copper wire bonding moving toward volume leadership– Heterogeneous integration for SiP – 2.5D moves the interposer into volume manufacturing– 3D integration– Thinning– Photonics getting closer to the transistors– Requirements for packaging MEMS devices

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Single Chip Package Technology Requirement

• Challenges still remain for conventional single chip packaging

• The continuous drive to reduce cost remains one of the most challenging requirements

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Year of Production 2016 2017 2018 2019 2020 2021 2022 2023 2024 2025

Cost per Pin Minimum for Contract Assembly (Cents/Pin)

Low-end, Low-cost package .20-.32 .20-.30 .2-.29 .2-.27 .2-.26 .19-.25 .19-.25 .19-.25 .19-.25 .17-.24

Mobile Device Package 0.34 0.33 0.32 0.31 0.3 0.29 0.28 0.27 0.26 0.25

Memory 0.21 0.21 0.21 0.21 0.21 0.21 0.2 0.2 0.19 0.19

Cost-performance .44 - .75 .42 - .71 .39 - .68 .37 - .64 .35 - .61 .33-.58 0.32-0.55 0.31-0.52 0.30-0.50 0.29-0.48

High-performance 1.15 1.09 1.04 0.99 0.94 0.89 0.85 0.81 0.77 0.75

Harsh .20 - 1.40 .20 - 1.33 .20 - 1.26 .20 - 1.20 .20 - 1.14 .19-1.08 .19-1.03 .19-1.01 .19-.99 0.18-.97

Copper Wire Bonding Is Taking Over

Driven by:•Strong mechanical properties•Better heat dissipation•Increases power ratings •Thinner wire diameters •It is cheaper than gold

Improved process control in now delivering•No reliability issues•No yield issues •Some vendors don’t yet have this process control

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Evolution Of Heterogeneous Integration: 2.5D a bridge to 3D

WLCSPWLCSP

IC

IC

IC

IC

Wirebond BGA FC BGA

Stacked Die PoP EPS 2.5D IC (Si Interposer)

3D IC 3D IC die stackdie stack

FO-WLPFO-WLP

MEMs &MEMs & Wireless

FO-WLP SiPFO-WLP SiP

TimeTime

WLCSPWLCSP

Heterogeneous Integration

Assembly + Substrate

Heterogeneous Integration

IC + Assembly

The Vision Of Complex Sip Is Finally Entering The Market

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5 Layers in the stack• Processor• Wide IO SDRAM• 2 mobile DRAM• Silicon spacer between the 2 mobile DRAM

Sony’s CXD5315GG Package in PlayStation Vita

Packaging is the enabling tool for “More than Moore”. It allows consumer products that are ever smaller, more powerful, cheaper, require less power and reliability ensuring a useful life that meets the expectation of the customer.

Why Has 3D TSV Taken So Long?

The typical response is:– Cost– Competition from existing technology– Technical inertia– Supply chain maturity

“Truth is” it has not been slow. – flip chip 30 years– copper wire bond 30 years – 3D-TSV 6 years assuming 2013 for volume

production

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Why Has 3D TSV Been So Fast?

It has been driven by:– CMOS shrinking can no longer keep up the pace of

progress– Enabling packaging technologies are available

• Interposers• TSV

– Performance advantages are compelling• Reduced power• Reduced latency• Increased bandwidth• Reduced size

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SnAg bumps for FC Interconnects and Cu pillar bumps for board assembly

Silicon Interposerdeals with a wide IO interface between devices e.g logic, memory, Fan-out interface from device to package/board high re-routing capability and TSV interconnects

Interposers Are Now In Production• Interposer substrate has more than 10,000 routing connections Interposer substrate has more than 10,000 routing connections • Compared with standard I/O connections it provides:Compared with standard I/O connections it provides:

– > 100X die-to-die bandwidth per watt > 100X die-to-die bandwidth per watt – one-fifth the latency one-fifth the latency – Uses no high-speed serial or parallel I/O resources.Uses no high-speed serial or parallel I/O resources.

3D Integration - TSV

3D Products Are Sampling Today

Four layer stacks are sampling today. •The industry is getting ready for high volume with the next generation.

– Greater density– Lower latency– Higher bandwidth

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We Are Thinning EverythingWhat is driving this change?

•Thinning is delivering what the consumer wants– Thinner devices and products– Flexible devices and products– Increases functional density– Stacking needs it– It is the key to low cost TSV– High yield cost effective thinning processes are

available

Packaging challenges remain for cost effective Packaging challenges remain for cost effective handling of thinned die and wafershandling of thinned die and wafers

We Are Thinning EverythingWhat is being thinned?

– Wafers and die– Die attach layers– Lead frames– Underfill– Package substrates– Mold caps

Example: Total package height for BGA counting solder Total package height for BGA counting solder balls is 400um down from 500um a year ago.balls is 400um down from 500um a year ago.

Optical IO In-to And Out-of Package• There is a drive to move photonics as close to the

transistors as possible to increase bandwidth and reduce power requirement

• The challenges increase with each node due to large size of E to O and O to E conversion

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Year 2014 2015 2016 2017 2018 2019 2020

Max Package I/O Data Rate, Gb/s - - - - - - -

Max IO Power dissipation, watts 40 40 40 40 40 40 40

Optical media; fiber, waveguide, optical viaFiber/Wavegui

deFiber/Waveguid

eFiber/Waveguid

eFiber/Waveguid

eFiber/Waveguid

eWaveguide/So

me fiberWaveguide/Some

fiber

Optical wavelength 850/1350/1550 850/1350/1550 850/1350/1551 850/1350/1552 850/1350/1553 850/1350/1550 850/1350/1551

Max Data rate/Optical Channel, Gb/s 25 25 25 25 25 40 40

max # wavelengths/waveguide 4 4 4 4 4 4 4

Max Data rate/Optical IO, Gb/s 100 100 100 100 100 160 160

Optical #I/O per package 0 0 0 0 0 0 0

Wavelength spacing, nm NA NA NA NA NA 20 20

Optical power, mw/wavelength 0.1 to 1.0 0.1 to 1.0 0.1 to 1.1 0.1 to 1.2 0.1 to 1.3 0.1 to 1.0 0.1 to 1.1

Optical mode; multi/singlemultimode/sing

lemodemultimode/singl

emodemultimode/singl

emodemultimode/singl

emodemultimode/singl

emodemultimode/sing

lemodemultimode/single

mode

Light Source; VCSEL, laser, in-chip, etc. VCSEL/hybrid VCSEL/in-chip VCSEL/in-chip VCSEL/in-chip VCSEL/in-chip VCSEL/in-chip VCSEL/in-chip

Physical Modulation Method (direct or secondary)

direct direct direct direct directdirect

modulatorsdirect modulators

MEMS Are Now Shipping For Diverse Applications

Current state of the art production

•MEMS oscillators

•Sensors with ten degrees of freedom– 3-axis gyro– 3-axis magnetometer– 3-axis accelerometer– Pressure sensor

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These products have unique packaging These products have unique packaging challenges and new solutions are being challenges and new solutions are being

developed. developed.

Package cost is often greater than 50% of Package cost is often greater than 50% of product cost and cost remains a factor product cost and cost remains a factor

restraining broader adoption of MEMS solutionsrestraining broader adoption of MEMS solutions

Thank YouThank You

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