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Verilog HDL Verilog HDL ASIC DESIGN USING FPGA BEIT VII KICSIT Sep 4 2012 Lecture 5
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Verilog HDLVerilog HDLVerilog HDLVerilog HDL
ASIC DESIGN USING FPGA
BEIT VII
KICSIT
Sep 4 2012 Lecture 5
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Abstraction Levels Abstraction Levels
Sep 4 2012
• There are four levels of abstraction• Switch level
• Gate level• RTL (Dataflow) level • Behavioral or algorithmic level
Lecture 5
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Modeling Techniques Modeling Techniques
Sep 4 2012
• Switch-Level Modeling
The lowest level of abstraction is the switch or transistor Level Modeling. (It is rarely used)
• Gate Level Modeling
It is feasible for small circuits.
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Modeling Techniques Modeling Techniques
Sep 4 2012
• Dataflow Modeling
The level of abstraction higher than the gate level.
• Behavioral Modeling
In more complex digital designs, priority is given to the performance and behavior of the algorithm.
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Modeling Techniques Modeling Techniques
Sep 4 2012
• Verilog allows the designer to mix and match all four levels of abstractions in a design.
• In the digital design community, the term register transfer level (RTL) is frequently used for a Verilog description that uses a combination of behavioral and dataflow constructs and is acceptable to logic synthesis tools.
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Modeling Techniques Modeling Techniques
Sep 4 2012
• Normally, the higher the level of abstraction, the more flexible and technology-independent the design.
• As one goes lower toward switch-level design, the design becomes technology-dependent and inflexible.
• A small modification can cause a significant number of changes in the design in Low level abstration.
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Module Module
Sep 4 2012
• The Module Concept
• The module is the basic building block in Verilog
• Modules are:• Declared• Instantiated
• Modules declarations cannot be nested
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Module Module
Sep 4 2012
• Modules can be interconnected to describe the structure of your digital system
• Modules start with keyword module and end with keyword endmodule• Modules have ports for interconnection with other modules
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Module Module
Sep 4 2012
•Everything you write in Verilog must be inside a module exception: compiler directives
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Module Module
Sep 4 2012 Lecture 5
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Components of a Verilog ModuleComponents of a Verilog Module
Sep 4 2012 Lecture 5
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Components of a Verilog ModuleComponents of a Verilog Module
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Components of a Verilog ModuleComponents of a Verilog Module
Sep 4 2012 Lecture 5
• Stimulus and Design blocks can also be instantiated in a Dummy Top level module
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Module Ports Module Ports
Sep 4 2012
• Similar to pins on a chip
• Provide a way to communicate with outside world.
• Ports can be input, output or inout
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Port Assignments Port Assignments
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Hierarchical Design Hierarchical Design
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Module Instances Module Instances
Sep 4 2012
• Verilog design models consist of a hierarchy of module instances.
• Like in C++ : modules are classes and instances are objects.
• The process of creating objects from a module template is called instantiation.
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Module Instances Module Instances
Sep 4 2012
• As an example a top-level block ripple_crry_counter creates four instances from the T-flipflop (T_FF) template.
• Each T_FF instantiates a D_FF and an inverter gate.
• Each instance must be given a unique name.
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Module Instances Module Instances
Sep 4 2012 Lecture 5
