AstroLab1 (1)

NTUEE GIEE

Computer-Aided VLSI System DesignPlace & Route Lab 1: Astro

Objectives:

In this lab, you will learn:

1. How to use Astro to run a timing driven P&R

Environment Setup:

1. Copy the default .cshrc file into your home directory:

cp /home/raid1_1/.cshrc ~/

Note: If you already have a .cshrc file and you do not want to overwrite it,

you can add only the CAD tools related lines that you miss into your

own .cshrc file.

2. Source the default .cshrc file:

source ~/.cshrc

3. Remember to setup XWindow Environment mentioned in Verilog Lab2.

Copy Files from CSDTA Directory

1. Copy all the files into your working directory:

cp –r ~cvsd/06F/Astro/Lab1 .

2. Check if you have these files

filename Description

CHIP.vg Scan-inserted gate level Verilog code (with IO pads added) for the simple ALU

CHIP.sdc Timing Constraint Files

io.tdf I/O placement constraint file

For technology file preparation, you need several files. Following the above

commands to put them into your working directory:

cp -R /home/raid1_1/cic/CBDK018_UMC_Artisan/CIC/Astro/umc18* .

cp /home/raid1_1/cic/CBDK018_UMC_Artisan/CIC/Astro/stout.map .

cp /home/raid1_1/cic/CBDK018_UMC_Artisan/CIC/Astro/tluplus/* .

source /usr/cad/synopsys/CIC/astro.csh

NTU GIEE Computer-Aided VLSI System Design 1/18

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Verilog I/O Pad Insertion

1. After the synthesis, you need to pack your verilog module with input/output

pad. The I/O pads are inserted in the verilog file “CHIP.vg” here. A new top

module “CHIP” is added into the design, and its input and output pin are

assigned with the input or output of the I/O pads as shown in following code:

dmodule CHIP ( P_alu_out, P_instruction, P_inputA,

P_inputB, P_clk, P_reset,

P_test_si, P_test_se );

output [7:0] P_alu_out;

input [3:0] P_instruction;

input [7:0] P_inputA;

input [7:0] P_inputB;

input P_clk, P_reset, P_test_si, P_test_se;

wire [7:0] alu_out;

wire [3:0] instruction;

wire [7:0] inputA;

wire [7:0] inputB;

wire clk, reset, test_si, test_se;

ALU ALU_final ( alu_out, instruction, inputA, inputB,

clk, reset, test_si,

test_se );

// Output PADs

P8A

OPAD_OUT_alu_out_0( .A(alu_out[0]), .P(P_alu_out[0]),.Y

(), .ODEN(1'b1), .OCEN(1'b1), .PU(1'b1), .PD(1'b0), .CE

N(1'b1), .CSEN(1'b0));

P8A



N(1'b1), .CSEN(1'b0));

P8A



N(1'b1), .CSEN(1'b0));

……


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// Input PADs

P2A IPAD_IN_instruction_0

(.P(P_instruction[0]), .Y(instruction[0]), .A(1'b0), .O

DEN(1'b0), .OCEN(1'b0), .PU(1'b1), .PD(1'b0), .CEN(1'b1

), .CSEN(1'b0) );

P2A IPAD_IN_instruction_1

(.P(P_instruction[1]), .Y(instruction[1]), .A(1'b0), .O

DEN(1'b0), .OCEN(1'b0), .PU(1'b1), .PD(1'b0), .CEN(1'b1

), .CSEN(1'b0) );

……

// Core Power + PAD DC Power

supply1 VDD;

supply0 GND;

// core VDD, GND

PVDDC COREVDD(.VDD(1'b1));

PVSSC COREGND(.GND(1'b0));

// PAD VDD, GND

PVDDR PADVDD();

PVSSR PADGND();

PCORNER cornerLL();

PCORNER cornerUL();

PCORNER cornerUR();

PCORNER cornerLR();

endmodule

2. The input pad we used here is the pad “P2A”, and the output pad we used

here is the pad “P8A”. You should examine the CHIP.vg to know further

about how to insert the I/O pads.

Invoke Astro

1. Open the GUI of SE at your working directory:

source /usr/cad/synopsys/CIC/astro.csh


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Astro &

Data Preparation

1. Create Library

1.1. “ToolsData Prep”

1.2. “LibraryCreate …”

Library Name CHIP

Technology File Name umc18_CIC.tf

Set Case Sensitive On

Hierarchy Separator .

Click “OK”

There might be some warning. They are due to the cell library

mismatch. You can ignore them now, but you should check them while

you are making the chip in the future.

2. Add Reference Lib

2.1. “Library add Ref”

Library Name CHIP

Ref Library Name umc18_fram, click “Apply”

Ref Library Name umc18io3v5v_5lm, click

“Apply”

Click “Cancel”

3. Verilog In

3.1. “Netlist In Verilog In”

Verilog File Name CHIP.vg

Library Name CHIP

Tech File Name umc18_CIC.tf

Net NAME for 1’b0 GND

Hierarchy Separator .

Set Case Sensitive On

No Backslash Insertion to avoid Hier Name

Collisions On

Click “OK”

4. Expand Netlist

4.1. “Netlist in Expand”

Library Name CHIP

Unexpanded Cell Name CHIP.NETL

Expanded Cell Name CHIP.EXP

4.1.1 Click “Global Net Options”

Net Name VDD


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Port Pattern VDD, Click “Apply”

Net Name GND

Port Pattern GND, Click “Apply”, “Hide”

Click “OK”

5. Open Library

5.1. “Tools Astro”

5.2. “Library Open”

Library Name “CHIP”

Click “OK”

6. Create Cell

6.1. “Cell Create”

Cell Name “CHIP”

Click “OK”

7. Bind Netlist

7.1. “Design Setup Bind Netlist”

Net Name CHIP.EXP

Click “OK”

Now you can press “f” in the cell view window. And them you’ll see

the basic shape of your chip.

8. Specify Global Net Connections

8.1. “PreRoute Connect Ports to P/G”

Net Name VDD

Port Pattern VDD

Net Type Power

Net Sub Type Core, Pad

Cell Types Macro, Std/Module Cell, Pad, Cover

Click “Apply” and “OK” for popped out window

Net Name GND

Port Pattern GND

Net Type Ground

Net Sub Type, Cell Types No Change

Update Tie Up/Down On

Click “OK” and “OK” for popped out window

9. Save Your Design

9.1. “Cell Save”

9.2. “Cell Save As”

CHIP Name CHIP_connpg

Overwrite Enable


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Click “OK”

10. Load TDF File

10.1. “Design Setup Load TDF”

TDF File Name io.tdf

Click “OK”

Floor Planning

1. Setup Floorplan

1.1. “Design Setup Set Up Floorplan”

Control Param aspect ratio

Core Utilization 0.8

Row/Core Ratio 1

Core Aspect Ratio (H/W) 1

Double Back On

Flip First Row On

Core To Left, Core To Right, Core To Bottom,

Core To Top 35

Click “OK”

2. Create P/G Rings

2.1. “PreRoute Rectangular Rings”

Net Name(s) VDD, GND

L-Width, R-Width, B-Width, T-Width 15

L-Layer, R-Layer 52 52:met4

B-Layer, T-Layer 50 50:met3

Offsets

Are Absolute

Left, Right, Bottom, Top 2

Click “OK”

3. Create P/G Straps

3.1. “PreRoute Straps”

Vertical Start X 480

Net Name(s) VDD, GND

Width 5

Layer 52 52:met4

Click “OK”

4. PreRoute Macros & Pads

4.1. “PreRoute Macros/Pads”

Select Pins Automatically and Route


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Only those on pin layer On 50 50:met3

Click “Apply”

Only those on pin layer On 52 52:met4

Click “Apply”

Click “Cancel”

5. Add Pad Filler

5.1. “PostPlace Add Pad Fillers”

Filler PFILL, PFILL_9, PFILL_1, PFILL_01

Overlap Filler PFILL_01

Click “OK”

6. Save Your Design



Cell Name CHIP_fr

Overwrite On

Click “OK”

Timing Setup

1. Attach TLU+

1.1. “Tools Data Prep”

1.2. “Tech Files ITF to TLU+”

Library Name CHIP

Nom CapTable File mixed18.tluplus

Nom ITF File mixed18.itf

Star-RCXT Mapping File mixed18.map

Click “Sanity Check” to see if there’s any problem?

If no, click “OK”; else if yes, check the problems and click “Update

MW-Tech” to accept those problems

2. Load Constraints


2.2. “Timing Constraints: Load SDC…”

SDC File Name CHIP.sdc

SDC File Hierarchy Separator .

Click “OK”

3. Timing Setup

3.1. “Timing Astro Time: Timing Setup…”

Environment Page

Include Non Propagated Nets On


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Ignore clock uncertainty Off

Ignore propagated clock On

Enable ideal Network Delay On

Click “Apply”

Parasitics Page Capacitance Model TLU+

Click “Apply”

Model Page Operating Cond: Max, Nom, Min

Net Delay Model: Delay Model: Medium

Effort

Click “Load”, then “Apply”

Click “Hide”

4. Timing Check

4.1. Type “astCheckDesign” in command window, decide the output file

name yourself. Then see the output file if the timing is met or not?

5. Save Your Design



Cell Name CHIP_fr_t

Overwrite on

Click “OK”

Placement

1. Trace Scan chain and detach it

The scan chains are considered as standard cell if we don’t trace them out.

After placement, the un-traced scan chains are placed disorderly. So we

should reorder the scan chain and do ATPG again after P&R to get the

correct test pattern.

1.1. “PrePlace ScanChain: Trace Scan Chain…”

Start Port Name Y

Of cell instance

Instance Name IPAD_IN_test_si

Allow Buffers On

Buffer Master Name(s) .*INV.*, .*BUF.*

Specify Chain End On

End Port Name SI

Of cell instance


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End Instance Name ALU_final.alu_out_reg_7_

Click “OK”

How many edges does Astro traced out? 28

1.2. Detach scan chain

“PrePlace ScanChain: Optimize/Delete Scan Chain…”

Click “Default”

Delete Only On

Click “OK”, then wait for a moment

2. Set Placement Options

2.1. “In-Place Placement Common Options…”

Optimization Mode: Timing On

Click “OK”

3. Pre-Placement Optimization

3.1. “PrePlace Pre-Placement Optimization…”

Remove Buffer On

Click “OK”

Remember to check your timing with “astCheckDesign”

4. Connect Ports to P/G


Net Name VDD

Port Pattern VDD

Net Type Power



Update Tie Up/Down OFF


Net Name GND

Port Pattern GND

Net Type Ground




5. PreRoute Standard Cells

5.1. “PreRoute Standard Cells”

Default Settings then click “OK”

6. Placement

6.1. “InPlace AstroPlace: Design Placement…”

Look in to “mode” to see if it is “congestion+timing”


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In-Placement Optimization On

Click “OK” and wait until it ends

7. Save Your Design



Cell Name CHIP_placed

Overwrite On

Click “OK”

8. Search and Refine Violations

8.1. Execute this if there is any violation

8.2. “InPlace AstroPlace: Search and Refine…”

Click “OK”

9. Post-Placement Optimization Phase1 (PPOP1)

9.1. Use this to fix the setup time violations

9.2. “PostPlace Optimization: Post-Place Optimization Phase1…”

Use Global Routing On

Setup Fixing On

Hold Fixing Off

Design Rule Fixing On

Fix Tran/Cap On

Click “OK”

9.3. Check timing again, and try to fix the setup time violations.

10. Save Your Design



Cell Name CHIP_PPOP1

Overwrite On

Click “OK”

Now have a rest. Use “Tools Quit” to quit. Keep the LAB files until next

week. We’ll start from the clock tree synthesis and post-placement optimizations next

week.


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Clock Tree Synthesis & Post Place Optimizations

1. Reopen the Library


1.2. “Library Open…”

Library Name CHIP

Click “OK”

1.3. “Cell Open…”

Cell Name CHIP

Click “OK”

And then you’ll see your cell in the lab last time.

2. Set Clock Options

2.1. “Clock Clock Common Options.”

Clock Nets P_clk

Buffer/Inverters CLKBUFXL, CLKBUFX1,

CLKBUFX2, CLKBUFX3, CLKBUFX4, CLKBUFX8,

CLKBUFX12, CLKBUFX16, CLKBUFX20

Delay Cells DLY1X1, DLY2X1, DLY3X1, DLY4X1

Click “OK”

3. Clock Tree Synthesis

3.1. “Clock Clock Tree Synthesis”

Use default settings and click “OK”

4. Timing Setup Options for Post-CTS

4.1. “Timing Astro Time: Timing Setup.”

Environment Page Ignore Clock Uncertainty On

Ignore Propagated Clock Off

Enable ideal Network delay Off

Click “Apply”

Model Page Operating Cond: Max, Nom, Min

Net Delay Model High Effort

Click “Load”, “Apply”, then “Hide”

5. Connect Scan Chain and Reorder Scan Chain

5.1. “PrePlace Scan Chain: Optimized/Delete Scan Chain”

Mode Optimize

Click “OK”

6. Post-Place Optimization Phase 2

6.1. “PostPlace Optimization: PostPlace Optimization”


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Default Settings, and click “OK”

7. Save Your Design



Cell Name CHIP_PPOP2

Overwrite on

Click “OK”

8. Clock Tree Optimization

8.1. “Clock Clock Tree Optimization: Clock Tree Optimization”

Click “OK”



Net Name VDD

Port Pattern VDD

Net Type Power



Update Tie Up/Down Off


Net Name GND

Port Pattern GND

Net Type Ground







11. Save Your Design again



Cell Name CHIP_cts

Overwrite On

Click “OK”

Routing

1. Setup routing options

1.1. “Route Setup Route common options”


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Global Routing: Timing Driven On

Global Routing: Clock Routing balanced

Track Assign: Timing Driven On

Library Cells and Design Rules: Same Net Notch

check and fix

Click “OK”

2. Route Clock Net

2.1. “Route Route Net Group”

Net Name(s) From: All clock nets

Click “OK”

3. Route nets (Auto Route)

3.1. “Route Auto Route”

Search Repair Loop 5

Click “OK”

Check if there is any DRC or timing violations

4. Change delay model

4.1. “Timing Astro Time: Timing Setup”

Model Page Delay Model High Effort

Click “Apply”

5. Search and Repair violations

5.1. “Route Detail Route: Search and Repair”

Search & Repair Loop 50

Click “OK”

6. Post Route Optimization for clock skew

6.1. “Clock Clock tree optimization: Post Route CTO”

Buffer Sizing On

Gate Sizing On

Click “OK”

7. Post-CTO ECO Routing: Setting the options

7.1. “Route Setup Route Common Options”

Global Routing: Timing Driven Off

Track Assign: Timing Driven Off

CTS nets minor change only

Click “OK”



Net Name VDD


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Port Pattern VDD

Net Type Power



Update Tie Up/Down Off


Net Name GND

Port Pattern GND

Net Type Ground







10. Post-CTO ECO Routing

10.1. “ECO ECO Route: Design ECO…”

Phase: Global and track assign Off

Phase: detail On

Dangling wires utilize

Reroute modified nets first, others later

Click “OK”

11. Save Your Design



Cell Name CHIP_eco

Overwrite On

Click “OK”

12. Post Route Optimization

12.1. “Route Detail Route: Detail Route Placement/Detail Route

Optimization …”

ECO Search & Repair On

Click “OK”



Net Name VDD

Port Pattern VDD

Net Type Power


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Net Name GND

Port Pattern GND

Net Type Ground







15. Save Your Design again



Cell Name CHIP_routed

Click “OK”

Design for Manufacturing

1. Add Core Filler

1.1. “PostPlace Add Core Filler”

Master Cell Name(s) without Metal FILL64,

FILL32, FILL16, FILL8, FILL4, FILL2, FILL1

Respect hard placement blockage On

Respect soft placement blockage On

Between std cells only On

Connect to Power Net VDD

Connect to Ground Net GND

Click “OK”

2. Slot Wire

2.1. “PreRoute Slot Wires”

Specified Net Name(s) VDD, GND

RouteLayer

CutWidth 20

CutLength 30

Width 2

Length 10

SideSpace 10


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EndSpace 10

SideClearance 10

EndClearance 10

Click “OK”

3. Save slot wired design



Cell Name CHIP_slotwire

Overwrite On

Click “OK”

4. Fill Notches and Gaps

4.1. “Route Utility Fill Gap/Notch”

Click “OK”

5. Verify DRC

5.1. “Verify DRC”

List Error Summary Immediately On

Click “OK”

Check DRC violations

6. Verify LVS

6.1. “Verify LVS”

List Error Summary Immediately On

Click “OK”

Check LVS violations

7. Save your design for manufacturing



Cell Name CHIP_dfm

Overwrite On

Click “OK”

8. SDF Out

8.1. “Timing SDF Out”

Flatten Format On

Version 2.1 On

SDF Design Name CHIP

SDF CellType Name CHIP

SDF Instance Name CHIP

File Name CHIP.SDF

Click “OK”


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9. Stream Out GDSII

9.1. “Tools Data Prep”

9.2. “Output Stream Out”

Stream File Name CHIP.gds

Library Name CHIP

Layer File stout.map

Child Extraction Depth 20

Convert Specified Cell

Cell Name CHIP

Fill Enable only “Fill”

Click “Pin/Net Options”

Output Pins As Text

Pin Name Magnification 1.0

Output Net As Text

Click “Hide”

Click “OK” and check if the fill data are translated , and the CHIP.gds

is produced.

10. Post-Sim Verilog Out

10.1. “Output Verilog Out”

Library Name CHIP

Cell Name CHIP

Verilog Out Data File CHIP_pr_sim.vg

No Corner Pad Instances On

No Pad Filler Cell Instances On

No Ports Connected to Pad Filler Cell Instances

On

No Core Filler Cell Instances On

No Unconnected Instances On

No Unconnected Ports On

No Diode Ports On

Output 1’b1 for Power(VDD, vdd, …) and 1’b0 for

Ground (VSS, gnd, …) On

Output Bus As Individual Bus Off

Reference Top NETL Cell To Output Bus CHIP.NETL

Click “OK”

11. LVS Verilog Out

11.1. “Output Verilog Out”


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Library Name CHIP

Cell Name CHIP

Verilog Out Data File CHIP_pr_lvs.vg

No Corner Pad Instances Off

No Pad Filler Cell Instances Off

No Ports Connected to Pad Filler Cell Instances

Off

No Core Filler Cell Instances Off

No Unconnected Instances Off

No Unconnected Ports Off

No Diode Ports Off

Output 1’b1 for Power(VDD, vdd, …) and 1’b0 for

Ground (VSS, gnd, …) Off

Output Bus As Invidividual Bus Off

Reference Top NETL Cell To Output Bus CHIP.NETL

Click “OK”

11.2. LVS

12. Done! Check your Verilog Files and GDSII File.

13. Prepare for Calibre!

1st Edtion: Yu-Lin Chang, 2005

2nd Edition: Yu-Lin Chang, 2006


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AstroLab1 (1)

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