Async03 Tut Demo

1

Petrify: Method and Tool for Synthesis of Asynchronous Controllers and

Interfaces

Jordi Cortadella (UPC, Barcelona, Spain), Mike Kishinevsky (Intel Strategic CAD Labs, Oregon), Alex Kondratyev (Berkeley Cadence Research Labs, CA), Luciano Lavagno (Politecnico di Torino, Italy ),Alex Yakovlev (University of Newcastle, UK)

ASYNC2003 - Tutorial on Petrify Method and Tool 2

Outline

• Part 1: The Petrify Method– Overview of the Petrify synthesis flow– Specification: Signal Tranistion Graphs– State graph and next-state functions– State encoding– Implementation conditions– Speed-independent circuits

• Complex gates

• C-element architecture


Specification(STG)

State Graph

SG withCSC

Next-state functions

Decomposed functions

Gate netlist

Reachability analysis

State encoding

Boolean minimization

Logic decomposition

Technology mapping

Design flow


x

y

z

x+

x-

y+

y-

z+

z-

Signal Transition Graph (STG)

xy

z

Specification


x

y

z

x+

x-

y+

y-

z+

z-

Token flow


x+

x-

y+

y-

z+

z-

xyz000

x+

100y+z+

z+y+

101 110

111

x-

x-

001

011y+

z-

010

y-

State graph


x z x y ( )

y z x

z x y z

Next-state functionsxyz000

x+

100y+z+

z+y+

101 110

111

x-

x-

001

011y+

z-

010

y-


x

z

y

Gate netlist

x z x y ( )

y z x

z x y z


Specification(STG)

State Graph

SG withCSC



Gate netlist


State encoding


Logic decomposition

Technology mapping

Design flow


VME bus

DeviceLDS

LDTACK

D

DSr

DSw

DTACK

VME BusController

DataTransceiver

BusDSr

LDS

LDTACK

D

DTACK

Read Cycle


STG for the READ cycle

LDS+ LDTACK+ D+ DTACK+ DSr- D-

DTACK-

LDS-LDTACK-

DSr+

LDS

LDTACK

D

DSr

DTACK

VME BusController


Choice: Read and Write cycles

DSr+

LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK- DTACK-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

DSw-

LDS-

LDTACK-DTACK-



DTACK-

DSr+

LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

DSw-

LDS-

LDTACK-DTACK-



DTACK-

DSr+

LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

DSw-

LDS-

LDTACK-DTACK-


Circuit synthesis

• Goal:– Derive a hazard-free circuit

under a given delay model andmode of operation


Speed independence

• Delay model– Unbounded gate / environment delays

– Certain wire delays shorter than certain paths in the circuit

• Conditions for implementability:– Consistency

– Complete State Coding

– Persistency


Specification(STG)

State Graph

SG withCSC



Gate netlist


State encoding


Logic decomposition

Technology mapping

Design flow


STG for the READ cycle


DTACK-

LDS-LDTACK-

DSr+

LDS

LDTACK

D

DSr

DTACK

VME BusController


Binary encoding of signals

DSr+

DSr+

DSr+

DTACK-

DTACK-

DTACK-

LDS-LDS-LDS-

LDTACK- LDTACK- LDTACK-

D-

DSr-DTACK+

D+

LDTACK+

LDS+


Binary encoding of signals

DSr+

DSr+

DSr+

DTACK-

DTACK-

DTACK-

LDS-LDS-LDS-

LDTACK- LDTACK- LDTACK-

D-

DSr-DTACK+

D+

LDTACK+

LDS+

10000

10010

10110 01110

01100

0011010110

(DSr , DTACK , LDTACK , LDS , D)


QR (LDS+)QR (LDS+)

QR (LDS-)QR (LDS-)

Excitation / Quiescent Regions

ER (LDS+)ER (LDS+)

ER (LDS-)ER (LDS-)

LDS-LDS-

LDS+

LDS-


Next-state function

0 1

LDS-LDS-

LDS+

LDS-

1 0

0 0

1 1

1011010110


Karnaugh map for LDS

DTACKDSrD

LDTACK 00 01 11 10

00

01

11

10

DTACKDSrD

LDTACK 00 01 11 10

00

01

11

10

LDS = 0 LDS = 1

0 1-0

0 0 0 0 0 0/1?

1

111

-

-

-

---

- - - -

-

- ---

- - -


Specification(STG)

State Graph

SG withCSC



Gate netlist


State encoding


Logic decomposition

Technology mapping

Design flow


Concurrency reduction

LDS-LDS-

LDS+

LDS-

1011010110

DSr+

DSr+

DSr+


Concurrency reduction


DTACK-

LDS-LDTACK-

DSr+


State encoding conflicts

LDS-

LDTACK-

LDTACK+

LDS+

10110

10110


Signal Insertion

LDS-

LDTACK-

D-

DSr-

LDTACK+

LDS+

CSC-

CSC+

101101

101100


Specification(STG)

State Graph

SG withCSC



Gate netlist


State encoding


Logic decomposition

Technology mapping

Design flow


Complex-gate implementation

)(csccsc

csc

csc

LDTACKDSr

LDTACKD

DDTACK

DLDS


Implementation conditions

• Consistency– Rising and falling transitions of each signal

alternate in any trace

• Complete state coding (CSC)– Next-state functions correctly defined

• Persistency– No event can be disabled by another event

(unless they are both inputs)


Implementation conditions

• Consistency + CSC + persistency

• There exists a speed-independent circuit that implements the behavior of the STG

(under the assumption that ay Boolean function can be implemented with one complex gate)


Persistency

100 000 001a- c+

b+ b+

a

cb

a

c

b

is this a pulse ?

Speed independence glitch-free output behavior under any delay

a+

b+

c+

d+

a-

b-

d-

a+

c-a-

0000

1000

1100

0100

0110

0111

1111

1011

0011 1001

0001

a+

b+

c+

a-

b-

c-

a+

c-

a-

a-

d-d+

0000

1000

1100

0100

0110

0111

1111

1011

0011 1001

0001

a+

b+

c+

a-

b-

c-

a+

c-

a-

a-

d-d+

abcd 00 01 11 10

00

01

11

10 1

1 1 11

10

0 000

ER(d+)

ER(d-)

abcd 00 01 11 10

00

01

11

10 1

1 1 11

10

0 000

caadd

0000

1000

1100

0100

0110

0111

1111

1011

0011 1001

0001

a+

b+

c+

a-

b-

c-

a+

c-

a-

a-

d-d+

Complex gate


Implementation with C elements

CR

S z

• • • S+ z+ S- R+ z- R- • • •

• S (set) and R (reset) must be mutually exclusive

• S must cover ER(z+) and must not intersect ER(z-) QR(z-)

• R must cover ER(z-) and must not intersect ER(z+) QR(z+)

abcd 00 01 11 10

00

01

11

10 1

1 1 11

10

0 000

0000

1000

1100

0100

0110

0111

1111

1011

0011 1001

0001

a+

b+

c+

a-

b-

c-

a+

c-

a-

a-

d-d+

CS

Rdc

ca

0000

1000

1100

0100

0110

0111

1111

1011

0011 1001

0001

a+

b+

c+

a-

b-

c-

a+

c-

a-

a-

d-d+

CS

Rdc

ca

but ...

0000

1000

1100

0100

0110

0111

1111

1011

0011 1001

0001

a+

b+

c+

a-

b-

c-

a+

c-

a-

a-

d-d+

CS

Rdc

ca

Assume that R=ac has an unbounded delay

Starting from state 0000 (R=1 and S=0):

a+ ; R- ; b+ ; a- ; c+ ; S+ ; d+ ;

R+ disabled (potential glitch)

abcd 00 01 11 10

00

01

11

10 1

1 1 11

10

0 000

0000

1000

1100

0100

0110

0111

1111

1011

0011 1001

0001

a+

b+

c+

a-

b-

c-

a+

c-

a-

a-

d-d+

CS

Rdc

cba

Monotonic covers


C-based implementations

CS

Rdc

cbaC

d

ab

c

a

b

cd

weak

a

cd

generalized C elements (gC)

weak


Speed-independent implementations

• Implementation conditions– Consistency– Complete state coding– Persistency

• Circuit architectures– Complex (hazard-free) gates– C elements with monotonic covers– ...


Synthesis exercise

y-

z- w-

y+ x+

z+

x-

w+

1011

0111

0011

1001

1000

1010

0001

0000 0101

0010 0100

0110

y-

y+

x-

x+w+

w-

z+

z-

w-

w-

z-

z-y+

y+

x+

x+

Derive circuits for signals x and z (complex gates and monotonic covers)


Synthesis exercise

1011

0111

0011

1001

1000

1010

0001

0000 0101

0010 0100

0110

y-

y+

x-

x+w+

w-

z+

z-

w-

w-

z-

z-y+

y+

x+

x+

wxyz 00 01 11 10

00

01

11

10

-

-

-

-

Signal x

1

0

1

1

1

1

1

0 0

0

0

0


Synthesis exercise

1011

0111

0011

1001

1000

1010

0001

0000 0101

0010 0100

0110

y-

y+

x-

x+w+

w-

z+

z-

w-

w-

z-

z-y+

y+

x+

x+

wxyz 00 01 11 10

00

01

11

10

-

-

-

-

Signal z

1

0 0

0

0

11 1

0

0 0

0


A simple filter: specification

y := 0;loop x := READ (IN); WRITE (OUT, (x+y)/2); y := x;end loop

RinAin

Aout Rout

ININ

OUTOUT

filter


A simple filter: block diagram

x y+

controlRin

Ain

Rout

Aout

Rx AxRy Ay Ra Aa

ININOUTOUT

• x and y are level-sensitive latches (transparent when R=1)• + is a bundled-data adder (matched delay between Ra and Aa)• Rin indicates the validity of IN• After Ain+ the environment is allowed to change IN• (Rout,Aout) control a level-sensitive latch at the output


A simple filter: control spec.

x y+

controlRin

Ain

Rout

Aout

Rx AxRy Ay Ra Aa

ININOUTOUT

Rin+

Ain+

Rin-

Ain-

Rx+

Ax+

Rx-

Ax-

Ry+

Ay+

Ry-

Ay-

Ra+

Aa

+Ra-

Aa-

Rout+

Aout+

Rout-

Aout-


A simple filter: control impl.

Rin+

Ain+

Rin-

Ain-

Rx+

Ax+

Rx-

Ax-

Ry+

Ay+

Ry-

Ay-

Ra+

Aa+

Ra-

Aa-

Rout+

Aout+

Rout-

Aout-

C

Rin

Ain

Rx Ax RyAy AaRa

Aout

Rout


Control: observable behavior

Rx+

Rin+

Ax+ Ra+ Aa+ Rout+ Aout+ z+ Rout- Aout- Ry+

Ry- Ay+Rx-Ax-Ay-

Ain-

Ain+

Ra-

Rin-

Aa-z-

C

Rin

Ain

Rx Ax RyAy AaRa

Aout

Rout

z


Following slides borrowed from Ran Ginosar, Technion (VLSI Architectures course) with thanks


Generalized C Element

ab C

+

-cz set(z) = ab

reset(z) = b'c'

z

reset

setb

a

c

b

z

a

b

c

z

reset

setb

a

c

b

a

b

cset

reset

DYNAMIC (Pseudostatic) STATIC

z

b c

b a

From Ran Ginosar’s course


STG Rules

• Any STG:– Input free-choice—Only inputs may control the choice)– Bounded—Maximum k (given bound) token per place– Liveness—every signal transition can be activated

• STG for Speed Independent circuits:– Consistent state assignment—Signals strictly alternate

between + and –– Persistency—Excited non-input signals must fire,

namely they cannot be disabled by another transition

• Synthesizable STG:– Complete state coding—Different markings must

represent different states


• We use the following circuit to explain STG rules:

req

ack

REQ

ACK


1-Bounded (Safety)

• STG is safe if no place or arc can ever contain more than one token

• Often caused by one-sided dependency

STG is not safe: If left cycle goes fast and right cycle lags, then arc ack+ REQ+ accumulates tokens. (REQ+ depends on both ack+ and ACK- )

Possible solution: stop left cycle by right cycle

REQ+ ACK+

REQ-ACK-

req+ ack+

req-ack-


Liveness

• STG is live if from every reachable marking, every transition can eventually be fired

• The STG is not live: • Transitions reset, reset_ok cannot be repeated.

• But non-liveness is useful for initialization

reset_ok-reset- req+ ack+

req-ack-


Consistent state assignment

• The following subgraph of STG makes no sense:

a+ a+

a- a-


Persistency

• STG is persistent if for all non-input transitions once enabled the transition cannot be disabled by another transitions. Non-persistency may be caused by arbitration or dynamic conflict relations – STG must have places

STG is not persistent: there is a place between req+ andack+ in which a token is needed in order to fire REQ+ . So there is some sort ofnondeterminism – either REQ+ manages to fire before ack+ or not

Possible solution: introduce proper dependence of the left cylce on the right one (e.g., an arc from req+ to REQ+, and from REQ+ to ack+)

REQ+ ACK+

REQ-ACK-

req+

ack+req-

ack-

60

Complete State Coding

• STG has a complete state coding if no two different markings have identical values for all signals.

REQ+ ACK+

REQ-ACK-

ack- req+

ack+req-

1000 1010req,ack,REQ,ACK:

1011

100110001100

0100

0000

00

01

00 01 11 10cd\ab

11

10

Disaster!


Complete State Coding

• Possible solution: Add an internal state variable

x- x+

req,ack,REQ,ACK,x:

REQ+ ACK+

REQ-ACK-

ack- req+

ack+req-

10000 10100

1000111001


A faster STG?

• Does it need an extra variable?

ack-

req+

ack+

req-

ACK-

REQ+

ACK+

REQ-


STG specification in .astg format.model simple_buffer.inputs r A.outputs a R.graph# left handshake (r,a)r+ a+a+ r-r- a-a- r+# right handshake (R,A)R+ A+A+ R-R- A-A- R+# interaction between handshakesr+ R+A+ a-.marking{<a-,r+><A-,R+>}.end


Drawn by draw_astg

65

The SGreq,ack,REQ,ACK:

0000

r+1000a+ R+

1100 1010r-

0100

R+

1110a+ A+

1011A+

1111a+r-

0110

R+a-

a- A+

0111r-

0011a-

R-

1001R-

1101a+

R-

0101r-

0001a-R-

A-

1000A-

1100a+

A-

0100r-

a-A-1011

r+

1001r+R-

A-1111

a+

R-

1101a+

A-0111

r-

R-

0101r-

A-

a-

a-

66

The SGreq,ack,REQ,ACK:

0000

r+1000a+ R+

1100 1010r-

0100

R+

1110a+ A+

1011A+

1111a+r-

0110

R+a-

a- A+

0111r-

0011a-

R-

1001R-

1101a+

R-

0101r-

0001a-R-

A-

1000A-

1100a+

A-

0100r-

a-A-1011

r+

1001r+R-

A-1111

a+

R-

1101a+

A-0111

r-

R-

0101r-

A-

a-

a-

R+

R+

R+

CSC-conflict states are highlighted


Drawn by write_sg & draw_astg


Extra states inserted by petrify


Rearranged STG

ack-

req+

ack+

req-

c1-

c1+

c0-

ACK-

REQ+

ACK+

REQ-

c2-

c2+

c0+

Initial Internal State: c0=c1=c2=1


The new State Graph…


The Synthesized Complex Gates Circuit

INORDER = r A a R csc0 csc1 csc2;

OUTORDER = [a] [R] [csc0] [csc1] [csc2];

[a] = a (csc2 + csc0) + csc1';

[R] = csc2 (csc0 (a + r) + R);

[csc0] = csc0 (csc1' + a') + R' csc2;

[csc1] = r' (csc0 + csc1);

[csc2] = A' (csc0' (csc1' + a') + csc2);


Technology MappingINORDER = r A a R csc0 csc1 csc2;OUTORDER = [a] [R] [csc0] [csc1] [csc2];[0] = R'; # gate inv: combinational[1] = [0]' A' + csc2'; # gate oai12: combinational[a] = a csc0' + [1]; # gate sr_nor: asynch[3] = csc1'; # gate inv: combinational[4] = csc0' csc2' [3]'; # gate nor3: combinational[5] = [4]' (csc1' + R'); # gate aoi12: combinational[R] = [5]'; # gate inv: combinational[7] = (csc2' + a') (csc0' + A'); # gate aoi22: combinational[8] = csc0'; # gate inv: combinational[csc0] = [8]' csc1' + [7]'; # gate oai12: combinational[csc1] = A' (csc0 + csc1); # gate rs_nor: asynch[11] = R'; # gate inv: combinational[12] = csc0' ([11]' + csc1'); # gate aoi12: combinational[csc2] = [12] (r' + csc2) + r' csc2; # gate c_element1:asynch


The Synthesized Gen-C CircuitINORDER = r A a R csc0 csc1 csc2;

OUTORDER = [a] [R] [csc0] [csc1] [csc2];

[0] = csc0' csc1 (R' + A);

[1] = csc0 csc2 (a + r);

[2] = csc2' A;

[R] = R [2]' + [1]; # mappable onto gC

[4] = a csc1 csc2';

[csc0] = csc0 [4]' + csc2; # mappable onto gC

[6] = r' csc0;

[csc1] = csc1 r' + [6]; # mappable onto gC

[8] = A' csc0' (csc1' + a');

[csc2] = csc2 R' + [8]; # mappable onto gC

[a] = a [0]' + csc1'; # mappable onto gC


Petrify Environment

STG

EQNdraw_astg

ps

write_sg

SG

libpetrify


Petrify

• Unix (Linux) command line tool• petrify –h for help (flags etc.)• petrify –cg for complex gates• petrify –gc for generalized C-elements• petrify –tm for tech mapping• draw_astg to draw• write_sg to create state graphs• Documented on line, including tutorial


References

• See the attached Practical Exercise manual for various design examples using Petrify commands

• Additional references:– Petrify and all documentation can be downloaded from:

http://www.lsi.upc.es/~jordic/petrify/petrify.html

– J. Cortadella, M. Kishinevsky, A. Kondratyev, L. Lavagno and A. Yakovlev, Logic Synthesis of Asynchronous Controllers and Interfaces, Springer, Berlin, 2002, ISBN3-540-43152-7

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