Asynchronous Machine

Types of Asynchronous Sequential Machines

Pulse-Mode

Pulse will not occur simultaneously on two or more inputs

Memory Element transitions are initiated by input pulses

Input variables are used only in the uncomplemented or complemented forms, but not both

y1 Yryr Y1

Flip-Flopmemory

Combinational logic

Pulse Mode circuit model

x1 z1

xn zm


Fundamental Mode

Level inputs and unclocked memory element

Assume delay is lumped and equal (t)

In reality often not necessary

Only one input is allowed to change at any instant of time

y1 Yryr Y1

Delay, t

Combinational logic

Fundamental Mode circuit model

x1 z1

xn zm


In all types: State must be stable before input can be change

Behavior is unpredictable (nondeterministic) if circuit not allowed to settle

Stable State

PS = present state

NS = next state

PS = NS = Stability Machine may pass through none or more intermediate

states on the way to a stable state

Desired behavior since only time delay separates PS from NS

Oscillation Machine never stabilizes in a single state

Races

A Race Occurs in a Transition From One State to the Next When More Than One Next State Variables Changes in Response to a Change in an Input

Slight Environment Differences Can Cause Different State Transitions to Occur

Supply voltage

Temperature, etc.

Races

Desired Next State: NS

if Y1 changes

first

if Y2 changes

first01

Present State : PS (Y1Y2)

11 00

10

Types of Races

Non-Critical

Machine stabilizes in desired state, but may transition through other states on the way

Critical

Machine does not stabilize in the desired state

Races

Desired Next State: NS

if Y1 changes

first

if Y2 changes

first01

Present State : PS (Y1Y2)

11 00

1000

Non-Critical Race

Critical Race

Asynchronous FSM Benefits

Fastest FSM

Economical

No need for clock generator

Output Changes When Signals Change, Not When Clock Occurs

Data Can Be Passed Between Two Circuits Which Are Not Synchronized

In some technologies, like quantum, clock is just not possible to exist, no clocks in live organisms.

Asynchronous FSM Example

next

statepresent

state y1

y2

input

Next State Variables

1 1 2 1 1 2 2

1 1 2 2

2 1 2 2

2 1

, ,

, ,

Y x y y x y x y y x y

x y x y y x y

Y x y y y x y

y x y

Asynchronous State Tables

States are either Stable or Unstable.

Stable states encircled with symbol.

Present

state

Next state, output

x=0 x=1

Q0 Q0,0 Q1,0

Q1 Q2,0 Q1,0

Q2 Q2,0 Q3,1

Q3 Q0, 0 Q3,1

Oscillations occur if all states are unstable for an input value.

Total State is a pair (x, Qi)

Constraints on Asynchronous Networks

If the next input change occurs before the previous

ones effects are fed back to the input, the machine

may not function correctly.

Thus, constraints are needed to insure proper

operation.

Fundamental Mode Input changes only when the machine is in a stable state.

Normal Fundamental Mode A single input change occurring when the machine is in a stable state produces a single output change

Analysis Pulse-Mode Asynch. Circuit

Assumptions

Pulse do not occur simultaneously on two or more input lines

State transition only occurs only if an input pulse occurs

All devices trigger on the same edge of each pulse


Q

QSET

CLR

S

R

x1

x2

z

y

y

States:

y = 0 = A

y = 1 = B

Inputs:

[x1,x2] = 00 = I0[x1,x2] = 10 = I1[x1,x2] = 01 = I2

yxR

yxS

yxz

2

1

1


States:

y = 0 = A

y = 1 = B

Inputs:

[x1,x2] = 00 = I0[x1,x2] = 10 = I1[x1,x2] = 01 = I2 yxR

yxS

yxz

2

1

1

x1

x2

y

S

R

z


States:

y = 0 = A

y = 1 = B

Inputs:

[x1,x2] = 00 = I0[x1,x2] = 10 = I1[x1,x2] = 01 = I2 yxR

yxS

yxz

2

1

1

y\x1x2 00 01 11 10

0 0 0 - 1

1 0 0 - 0

S

y\x1x2 00 01 11 10

0 0 0 - 0

1 0 1 - 0

R

y\x1x2 00 01 11 10

0 0 0 - 0

1 0 0 - 1

z


y\x1x2 00 01 11 10

0 00 00 - 10

1 00 01 - 00

SR

y\x1x2 00 01 11 10

0 0 0 - 1

1 1 0 - 1

Y

y\x1x2 00 01 11 10

0 0/0 0/0 - 1/0

1 1/0 0/0 - 1/1

Y/z

y\x1x2 00 01 11 10

0 0 0 - 1

1 0 0 - 0

S

y\x1x2 00 01 11 10

0 0 0 - 0

1 0 1 - 0

R

y\x1x2 00 01 11 10

0 0 0 - 0

1 0 0 - 1

z


Q

QSET

CLR

S

R

x1

x2

z

y

y

States:

y = 0 = A

y = 1 = B

Inputs:

[x1,x2] = 00 = I0[x1,x2] = 10 = I1[x1,x2] = 01 = I2

yxR

yxS

yxz

2

1

1

y\x1x2 00 01 10

0 0/0 0/0 1/0

1 1/0 0/0 1/1

Y/z Present State

I0 I2 I1

A A/0 A/0 B/0

B B/0 A/0 B/1

Present State

x1 x2

A B/0 A/0

B B/1 A/0

Exercise

Q

QSET

CLR

D

x z

y1

Q

QSET

CLR

Dy2

21

212

2111

,

,

yxyz

xCyD

xyCyD

Inputs:

I0 = no pulse on x

I1 = pulse on x

States (y1, y2)

A = 00

B = 01

C = 10

D = 11

Assume A as initial state

Exercise Complete the timing diagram for 4 pulse on x

21

212

2111

,

,

yxyz

xCyD

xyCyD

Inputs:I0 = no pulse on x

I1 = pulse on x

States (y1, y2)

A = 00

B = 01

C = 10

D = 11

x

y1

y2

D1=D2

C1

C2

z

0

0

0 0

0

0

1

1

1 1

Exercise

We need to construct the K-map for the State Table.

DFF clock input will see a transition 1 to 0 if the input pulse occurs

From the DFF Characteristics equation and this observation, the next state equations are:

Q

QSET

CLR

D

x z

y1

Q

QSET

CLR

Dy2

21

212

2111

,

,

yxyz

xCyD

xyCyD

1 1 1 1 1

1 2 1 2

1 2 1 1 2

2 2 2 2 2

1 2

( )

Y D C y C

y xy y x y

xy y xy y y

Y D C y C

xy xy

Exercise

y1y2\x 0 1

00 1 1

01 1 1

11 0 0

10 0 0

D1y1y2\x 0 1

00 0 0

01 0 1

11 0 1

10 0 0

C1y1y2\x 0 1

00 10 10

01 10 11

11 00 01

10 00 00

D1C1

y1y2\x 0 1

00 1 1

01 1 1

11 0 0

10 0 0

D2y1y2\x 0 1

00 0 1

01 0 1

11 0 1

10 0 1

C2y1y2\x 0 1

00 10 11

01 10 11

11 00 01

10 00 01

D2C2

22222

11111

CyCDY

CyCDY

y1y2\x 0 1

00 0 0

01 0 1

11 1 0

10 1 1

Y1

y1y2\x 0 1

00 0 1

01 1 1

11 1 0

10 0 0

Y2

Exercise

y1y2\x 0 1

00 00 01

01 01 11

11 11 00

10 10 10

Y1Y2 21

22222

11111

yxyz

CyCDY

CyCDY

y1y2\x 0 1

00 0 0

01 0 1

11 1 0

10 1 1

Y1

y1y2\x 0 1

00 0 1

01 1 1

11 1 0

10 0 0

Y2y1y2\x 0 1

00 00/0 01/0

01 01/0 11/0

11 11/0 00/1

10 10/0 10/0

Y1Y2/z

y1y2\x I0 I1

00 00/0 01/0

01 01/0 11/0

11 11/0 00/1

10 10/0 10/0

Y1Y2/z

y1y2\x x

00 01/0

01 11/0

11 00/1

10 10/0

Y1Y2/z

Exercise

Q

QSET

CLR

D

x z

y1

Q

QSET

CLR

Dy2

y1y2\x I0 I1

A A/0 B/0

B B/0 D/0

C C/0 C/0

D D/0 A/1

Y1Y2/z

A B

D C

I0/0

I1/0

I0/0

I0/0

I0/0I1/0

I1/1

I1/0

Design of Pulse-Mode Circuit

Step 1. Derive state diagram or state table

Step 2. Minimize the state table

Step 3. Choose state assignment and generate the transition output table

Step 4. Select type of latch or flip-flop to be used and determine excitation equation

Step 5. Determine the output equation

Step 6. Draw the circuit

Do it yourself

Design a pulse-mode circuit having two input lines x1 and x2, and one output line z. The circuit should produce an output pulse coincide with the last input pulse in the sequence x1-x2-x2. No other input sequence should produce an output pulse. (Sequence detector x1-x2-x2)

Use T-FF: T = 1, C acts as input

Step 1

States

A : indicates that the last input was x1 B : indicates that the sequence x1-x2 occurs

C : indicates that the sequence x1-x2-x2 occurs

Present State

x1 x2

A A/0 B/0

B A/0 C/1

C A/0 C/0

A B

C

x1/0

x2/0

x1/0

x2/0

x2/1x1/0

Step 2 and 3

Step 2. State table is minimize as given

Step 3. State assignment A=00, B=01, and C=10

y1y2 x1 x2

00 00/0 01/0

01 00/0 10/1

10 00/0 10/0

Y1Y2/z

Step 4 and 5

Use T-FF: T = 1

y1y2 x1 x2

00 00/0 01/0

01 00/0 10/1

10 00/0 10/0

Y1Y2/z

y1y2 x1 x2

00 0 0

01 0 1

11 d d

10 0 1

Y1

y1y2 x1 x2

00 0 0

01 0 1

11 d d

10 1 0

C1

y1y2 x1 x2

00 0 1

01 0 0

11 d d

10 0 0

Y2

y1y2 x1 x2

00 0 1

01 1 1

11 d d

10 0 0

C2

y1y2 x1 x2

00 0 0

01 0 1

11 d d

10 0 0

z

22

12212

22111

yxz

yxyxC

yxyxC

Step 6

22

12212

22111

yxz

yxyxC

yxyxC

z

y1

y2

TQ

Q

TQ

Q

x1

x2

1

1

Do it yourself

Design a pulse-mode circuit with inputs x1,x2, x3 and output z. The output must change from 0 to 1 iff the input sequence x1-x2-x3 occurs while z = 0. The output must change from 1 to 0 only after an x2 input occur.

Use SR Latch

Step 1

Moore machine because output must remain high between pulses

Present State

x1 x2 x3 z

A B A A 0

B B C A 0

C B A D 0

D D A D 1

A/0 B/0

D/1 C/0

x2,x3x1

x1

x1

x3

x2

x3

x2

x2

x1,x3

Step 2 and 3

Step 2. State table is minimize as given

Step 3. State assignment A=00, B=01, C=11, and D =10

y1y2 x1 x2 x3 z

00 01 00 00 0

01 01 11 00 0

11 01 00 10 0

10 10 00 10 1

Y1Y2

Step 4

Use SR Latch

y1y2 x1 x2 x3

00 0 0 0

01 0 1 0

11 0 0 1

10 1 0 1

Y1

y1y2 x1 x2 x3 z

00 01 00 00 0

01 01 11 00 0

11 01 00 10 0

10 10 00 10 1

Y1Y2

y1y2 x1 x2 x3

00 1 0 0

01 1 1 0

11 1 0 0

10 0 0 0

Y2

y1y2 x1 x2 x3

00 0 0 0

01 0 1 0

11 0 0 d

10 d 0 d

S1

y1y2 x1 x2 x3

00 d d d

01 d 0 d

11 1 1 0

10 0 1 0

R1

y1y2 x1 x2 x3

00 1 0 0

01 d d 0

11 d 0 0

10 0 0 0

S2

y1y2 x1 x2 x3

00 0 d d

01 0 0 1

11 0 1 1

10 d d d

R2

12211

2121

yxyxR

yyxS

3121

112

xyxR

yxS

Step 5

y1y2 x1 x2 x3 z

00 01 00 00 0

01 01 11 00 0

11 01 00 10 0

10 10 00 10 1

Y1Y2

21yyz

Step 6

12211

2121

yxyxR

yyxS

3121

112

xyxR

yxS

21yyz

Q

QSET

CLR

S

R

Q

QSET

CLR

S

R

x1

x2

x3

z

Analysis Fundamental-Mode Asynch. Circuit

Assumptions

Fundamental Mode Input changes only when the machine is in a stable state.

Normal Fundamental Mode A single input change occurring when the machine is in a stable state produces a single output change

This type of circuit is most difficult to analyze

Introduction to Fundamental mode

x=(x1, , xn) : input state

y =(y1, , yr) : secondary state

z=(z1, , zm) : output state

Y=(Y1, , Yr) : excitation state

(x,y) : total state

y1 Yryr Y1

Delay, t

Combinational logic

Fundamental Mode circuit model

x1 z1

xn zm

ttt

ttt

ttt

Yy

yxhY

yxgz

),(

),(

Example

Set of equations

Delay

dt

x1

x2z

ttt

tt

tttttttt

Yy

zY

yxxxyxxgz

22121 ),,(

x1

x2

y

z=Y

t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15

Unstable at t3 (y Y)

Tabular Representation

Excitation Table

Excitation state and output

It is a function of total space (x1, ,xn, y1, , yr)

K-map of

Row of secondary state

Column of unique input state

ttt

tt

tttttttt

Yy

zY

yxxxyxxgz

22121 ),,( y\x1x2 00 01 11 10

0 0/0 0/0 1/1 0/0

1 1/1 0/0 1/1 1/1


Flow Table

Replace the secondary state and excitation state by letters or nonbinary characters

It represents the behavior of the circuit but does not specify the realization of the circuit

y\x1x2 00 01 11 10

0 0/0 0/0 1/1 0/0

1 1/1 0/0 1/1 1/1

y\x1x2 00 01 11 10

a a/0 a/0 b/1 a/0

b b/1 a/0 b/1 b/1


Flow Table Can be used to determine

the output behavior given an input sequence

Input change produce horizontal movement

State changes produce vertical movement

y\x1x2 00 01 11 10

a a/0 a/0 b/1 a/0

b b/1 a/0 b/1 b/1

x1

x2

y

z=Y

t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15

t1 t2t3

t4t5

t6t7

Analysis of Fundamental-Mode Asynch. Circuit

Determine the excitation and output equations from the circuit diagram

Plot the excitation and output K-map for Y and z and from these K-map construct the excitation table

Locate and circle all stable state in the excitation table

Assign a unique nonbinary symbol for each row of the excitation table.

Construct the flow table

Example

Step 1

1

12

21

yxz

yxY

yxY

Delay

dt

x z

Delay

dt

Y2

Y1

y2

y1

Example

Step 2

y1y2\x 0 1

00 1 0

01 0 0

11 0 0

10 1 0

Y1y1y2\x 0 1

00 0 1

01 0 1

11 0 0

10 0 0

Y2y1y2\x 0 1

00 0 0

01 0 0

11 1 0

10 1 0

z

y1y2\x 0 1

00 10/0 01/0

01 00/0 01/0

11 00/1 00/0

10 10/1 00/0

Y1 Y2/z

y1y2\x 0 1

1 3/0 2/0

2 1/0 2/0

4 1/1 1/0

3 3/1 1/0

Y1 Y2/z

y1y2\x 0 1

1 3/0 2/0

2 1/0 2/0

3 3/1 1/0

4 1/1 1/0

Y1 Y2/z

1

12

21

yxz

yxY

yxY

y1y2\x 0 1

00 10/0 01/0

01 00/0 01/0

11 00/1 00/0

10 10/1 00/0

Example

Timing Diagram

y1y2\x 0 1

00 10/0 01/0

01 00/0 01/0

11 00/1 00/0

10 10/1 00/0

Y1 Y2/z

Y1 Y2/z

x

y1

y2

Y1

Y2

z

dt dt

Start from (2) and input changes from 1 to 0

State (2) 1 (3)

Example

Step 1

Let Q0 be state when y1 = 0 and Q1 be state when y1 = 1.

12

111

1221112

1121121

)(

)())((

yz

yxz

yxxxyxx

yxxyxxY

x1 z1

Delay

dt

z2

Y1y1

x2

Example

Step 2 through 5

Let Q0 be state when y1 = 0 and Q1 be state when y1 = 1.

y1\x1 x2 00 01 11 10

0 0 0 0 1

1 1 0 0 1

Y1

y1\x1 x2 00 01 11 10

0 0 0 0 0

1 1 1 1 1

z1

y1\x1 x2 00 01 11 10

0 1 1 0 0

1 0 0 0 0

z2

Present State

Input x1,x2

00 01 11 10

Q0 Q0,10 Q0,10 Q0,00 Q1,00

Q1 Q1,01 Q0,01 Q0,01 Q1,01

z1z2

x1 z1

Delay

dt

z2

Y1y1

x2

Do it Yourself

Analyze this circuit!

Q

QSET

CLR

S

R

Q

QSET

CLR

S

R

x1

x1

x1

x1x2

x1x2

x1

z

Q1

Q2

Example (Excitation Table)

1 1 2

1 1 2

2 1 2 1

1 1 2 1 1

S x Q

R x Q

S x x Q

R x x x Q

1 2 1 2z QQ xQ

Present State (Q1Q2)

Excitation(S1R1,S2R2)

Output(z)

Inputs State (x1x2) Inputs State (x1x2)

00 01 10 11 00 01 10 11

00 00,01 00,01 10,00 10,00 0 0 1 1

01 00,01 00,01 01,00 01,00 0 0 0 0

10 00,01 00,10 10,00 10,00 1 1 1 1

11 00,01 00,10 01,00 01,00 0 0 0 0

Example (Transition Table)


Next State(Q+1Q

+2)

Output(z)


00 01 10 11 00 01 10 11

00 00 00 10 10 0 0 1 1

01 00 00 01 01 0 0 0 0

10 10 11 10 10 1 1 1 1

11 10 11 01 01 0 0 0 0

Example (State Table)


Next State(Q+1Q

+2)

Output(z)


00 01 10 11 00 01 10 11

00 A A A C C 0 0 1 1

01 B A A B B 0 0 0 0

10 C C D C C 1 1 1 1

11 D C D B B 0 0 0 0

Example (Flow Table)


Next State(Q+1Q

+2)

Output(z)


00 01 10 11 00 01 10 11

A A A C C 0 0 - -

B A A B B - - 0 0

C C D C C 1 - 1 1

D C D - B - 0 - -

Tables, tables and tables.

Excitation table

Transition Table

State Table

Flow Table

Careful with unreachable state because input is restricted

Output only at stable state

Design of Fundamental-Mode Circuit

Step 1. Construct a primitive flow table from word description of the problem

Step 2. Derive a reduced primitive flow table

Step 3. Make secondary state assignment

Step 4. Construct excitation table and output table

Step 5. Determine the logic equations for each state variable and output state variable

Step 6. Realize the logic equation with the appropriate logic devices

A primitive flow table is a flow table that contains only one stable state per row

Example

A two input (x1,x2) and one output (z) asynchronous sequential circuit is to be designed to meet the following specifications. 1. Whenever x1 = 0, z = 0.

2. The first change to input x2 that occurs while x1 = 1 must cause the output to become z = 1.

3. A z = 1 output must not change to z = 0 until x1 = 0.

A typical input-output response of the desired circuit is shown below.

x1

x2

z

Example

Step 1. Create a primitive table that satisfy the requirement of the circuit.

Note:

Given only one stable state then we can only have 2 other unstable state and one unspecified state.

x1

x2

z

Example

Possible input x1x2 = 00

Since the circuit is operating on fundamental mode, then there must be a stable state at x1x2 = 00

Create a state a in the next state at 00 column.

Circle it because it must be stable.

Since z = 0 when x1 = 0, then the output is set to 0

Present State

Next State, Output

00 01 10 11

a a,0

Example At state (a),

Since there can be only one stable state in each row, this implies that x1x2 = 11 can not follow x1x2 = 00.

Place -,- at column x1x2 = 11

When x1x2 = 01, the next state must be an

unstable state, named b with output.

We must add a new row for state b, where b is stable for x1x2 = 01

Since z = 0 for x1 = 0 then the output is zero

Present State

Next State, Output

00 01 10 11

a a,0 b,- c,- -,-

b b,0

c c,0


unstable state, named c with output.

We must add a new row for state b, where c is stable for x1x2 = 10

For x1 = 1, x2 must change thus the output is 0

Example At state (b),

x1x2 = 10 can not follow x1x2= 01.


When x1x2 = 00,

the next state must be an unstable state

For x1x2 = 00, we already have a stable state (a). We must consider this.

From specification, z=0 when x1 = 0, thus go to a with - output

Present State

Next State, Output

00 01 10 11

a a,0 b,- c,- -,-

b a,- b,0 -,- d,-

c c,0

d d,0


unstable state, named d with output.

We must add a new row for state d, where d is stable for x1x2 = 11

For x1 = 1, x2 must change thus the output is 0

Example At state (c),

x1x2 = 01 can not follow x1x2 = 10. Place -,- at column x1x2 = 01

When x1x2 = 00, From specification, z=0 when x1

= 0, thus go to a with - output

When x1x2 = 11, Already have a stable state (d),

we must consider this. For x1 = 1, x2 changes from 0 to 1

thus the output must be 1. Thus we can not go to state (d)

the next state must be a new unstable state, named e with output.

We must add a new row for state e, where e is stable for x1x2 = 11 and the output is 1

Present State

Next State, Output

00 01 10 11

a a,0 b,- c,- -,-

b a,- b,0 -,- d,-

c a,- -,- c,0 e,-

d d,0

e e,1

Example At state (d),

x1x2 = 00 can not follow x1x2 = 11. Place -,- at column x1x2 = 00

When x1x2 = 01, From specification, z=0 when x1

= 0, thus go to b with - output

When x1x2 = 10, Already have a stable state (c),

we must consider this. For x1 = 1, x2 changes from 1 to 0

thus the output must be 1. Thus we can not go to state (c)

the next state must be a new unstable state, named f with output.

We must add a new row for state f, where f is stable for x1x2 = 10 and the output is 1

Present State

Next State, Output

00 01 10 11

a a,0 b,- c,- -,-

b a,- b,0 -,- d,-

c a,- -,- c,0 e,-

d -,- b,- f,- d,0

e e,1

f f,1

Example At state (e),

x1x2 = 00 can not follow x1x2 = 11.


When x1x2 = 01, From specification, z=0 when

x1 = 0, thus go to b with -output

When x1x2 = 10, Already have a stable state (c)

and (f), we must consider this.

For x1 = 1, x2 changes from 1 to 0 thus the output must be 1. Thus we can not go to state (c)

the next state must be unstable state f with output.

Present State

Next State, Output

00 01 10 11

a a,0 b,- c,- -,-

b a,- b,0 -,- d,-

c a,- -,- c,0 e,-

d -,- b,- f,- d,0

e -,- b,- f,- e,1

f f,1

Example At state (f),

x1x2 = 01 can not follow x1x2 = 10.


When x1x2 = 00, From specification, z=0 when

x1 = 0, thus go to a with -output

When x1x2 = 11, Already have a stable state (d)

and (e), we must consider this.

For x1 = 1, x2 changes from 0 to 1 thus the output must be 1. Thus we can not go to state (d)

the next state must be unstable state e with output.

Present State

Next State, Output

00 01 10 11

a a,0 b,- c,- -,-

b a,- b,0 -,- d,-

c a,- -,- c,0 e,-

d -,- b,- f,- d,0

e -,- b,- f,- e,1

f a,- -,- f,1 e,-

Example

Step 2. Reduce primitive flow table

It is an incompletely specified machine.

Start with implication chart to produce compatible pairs

Determine maximal compatibles

Determine minimal collection of maximal compatibles

Reduction of input-restricted flow table

Dashed entries are allowed to take different values

Implication chart

Find compatible pairs

Present State

Next State, Output

00 01 10 11

a a,0 b,- c,- -,-

b a,- b,0 -,- d,-

c a,- -,- c,0 e,-

d -,- b,- f,- d,0

e -,- b,- f,- e,1

f a,- -,- f,1 e,-

cf

cf

cf

b

c

d

e

f

de

de

de

cfde

cf

de

a b c d e

Implication chart

Determine Maximal Compatible

cf

cf

cf

b

c

d

e

f

de

de

de

cfde

cf

de

a b c d e

Column List of Compatible Classes

e {e,f}

d {e,f}

c {e,f}

b {e,f}, {b,d}

a {e,f}, {b,d},{a,b},{a,c}

No single state is added since

every state already appear at least

once.

Implication chart

Determine minimal collection of maximal compatible

Apply the concept of prime-implicant to reduce flow table

Column List of Compatible Classes

e {e,f}

d {e,f}

c {e,f}

b {e,f}, {b,d}

a {e,f}, {b,d},{a,b},{a,c}

a b c d e f

{a,b} x x

{a,c} x x *

{b,d} x x *

{e,f} x x *

Minimal collection of MC is {a,c} {b,d} {e,f}

Constructing Minimal Row Flow Table

Present State

Next State

00 01 10 11

{a,c} : ,0 ,- ,0 ,-

{b,d} : ,- ,0 ,- ,0

{e,f} : ,- ,- ,1 ,1

Present State

Next State, Output

00 01 10 11

a a,0 b,- c,- -,-

b a,- b,0 -,- d,-

c a,- -,- c,0 e,-

d -,- b,- f,- d,0

e -,- b,- f,- e,1

f a,- -,- f,1 e,-

Secondary State Assignment

Step 3. State Assignment

The goal is to avoid race

Present State

Next State

00 01 10 11

{a,c} : ,0 ,- ,0 ,-

{b,d} : ,- ,0 ,- ,0

{e,f} : ,- ,- ,1 ,1

State Assignment Possibility

(,) (,) (,)

Choose!

(,) (,)

y1\y2 0 1

0

1

Assignment

: 00

: 11

: 10

Constructing State Transition Table (Step 4)

Replace all stable state with its assignment

Present State

Next State

00 01 10 11

{a,c} : ,0 ,- ,0 ,-

{b,d} : ,- ,0 ,- ,0

{e,f} : ,- ,- ,1 ,1

Assignment

: 00

: 11

: 10

Present State

Next State

00 01 10 11

: 00 00,0 00,0

: 11 11,0 11,0

: 10 10,1 10,1

Constructing State Transition Table

Now we need to replace the unstable states

Present State

Next State

00 01 10 11

{a,c} : ,0 ,- ,0 ,-

{b,d} : ,- ,0 ,- ,0

{e,f} : ,- ,- ,1 ,1

Assignment

: 00

: 11

: 10

Present State

Next State

00 01 10 11

: 00 00,0 00,0

: 11 10,- 11,0 11,0

: 10 00,- 10,1 10,1

Remember if a state changes

more than 1 bit at a time we have a race

Input 00:

Total State (00,11) (00,00)

Create a cycle

(00,11) (00,10) (00,00)



Present State

Next State

00 01 10 11

{a,c} : ,0 ,- ,0 ,-

{b,d} : ,- ,0 ,- ,0

{e,f} : ,- ,- ,1 ,1

Assignment

: 00

: 11

: 10

Present State

Next State

00 01 10 11

: 00 00,0 10,- 00,0

: 11 10,- 11,0 11,0

: 10 00,- 11,- 10,1 10,1



Input 01:

Total State (01,00) (01,11)

Create a cycle

(01,00) (01,10) (01,11)



Present State

Next State

00 01 10 11

{a,c} : ,0 ,- ,0 ,-

{b,d} : ,- ,0 ,- ,0

{e,f} : ,- ,- ,1 ,1

Assignment

: 00

: 11

: 10

Present State

Next State

00 01 10 11

: 00 00,0 10,- 00,0

: 11 10,- 11,0 10,- 11,0

: 10 00,- 11,- 10,1 10,1



Input 10:

Total State (10,11) (10,10)

No problem here!

Only 1 bit need to change



Present State

Next State

00 01 10 11

{a,c} : ,0 ,- ,0 ,-

{b,d} : ,- ,0 ,- ,0

{e,f} : ,- ,- ,1 ,1

Assignment

: 00

: 11

: 10

Present State

Next State

00 01 10 11

: 00 00,0 10,- 00,0 10,-

: 11 10,- 11,0 10,- 11,0

: 10 00,- 11,- 10,1 10,1



Input 11:

Total State (11,00) (11,10)

No problem here!

Only 1 bit need to change

Constructing State Transition Table (variant 1)

Used the unused state 01

Present State

Next State

00 01 10 11

{a,c} : ,0 ,- ,0 ,-

{b,d} : ,- ,0 ,- ,0

{e,f} : ,- ,- ,1 ,1

Assignment

: 00

: 11

: 10

Present State

Next State

00 01 10 11

: 00 00,0 00,0

: 11 01,- 11,0 11,0

: 10 00,- 10,1 10,1

01 00,-

Input 00:

Total State (00,11) (00,00)

Create a cycle

(00,11) (00,01) (00,00)


Used the unused state 01

Present State

Next State

00 01 10 11

{a,c} : ,0 ,- ,0 ,-

{b,d} : ,- ,0 ,- ,0

{e,f} : ,- ,- ,1 ,1

Assignment

: 00

: 11

: 10

Present State

Next State

00 01 10 11

: 00 00,0 01,- 00,0 10,-

: 11 01,- 11,0 10,- 11,0

: 10 00,- 11,- 10,1 10,1

01 00,- 11,-

Input 01:

Total State (01,00) (01,11)

Create a cycle

(01,00) (01,01) (01,00)

All other inputs are the same as

before!


Create non-critical race

Present State

Next State

00 01 10 11

{a,c} : ,0 ,- ,0 ,-

{b,d} : ,- ,0 ,- ,0

{e,f} : ,- ,- ,1 ,1

Assignment

: 00

: 11

: 10

Present State

Next State

00 01 10 11

: 00 00,0 00,0

: 11 00,- 11,0 11,0

: 10 00,- 10,1 10,1

01 00,-

Input 00:

Total State (00,11) (00,00)

Non critical race

(00,11) (00,01) (00,00)

(00,11) (00,10) (00,00)


Create non-critical race

Present State

Next State

00 01 10 11

{a,c} : ,0 ,- ,0 ,-

{b,d} : ,- ,0 ,- ,0

{e,f} : ,- ,- ,1 ,1

Assignment

: 00

: 11

: 10

Present State

Next State

00 01 10 11

: 00 00,0 11,- 00,0 10,-

: 11 00,- 11,0 10,- 11,0

: 10 00,- 11,- 10,1 10,1

01 00,- 11,-

Input 01:

Total State (01,00) (01,11)

Non critical race

(01,00) (01,01) (01,11)

(01,00) (01,10) (01,11)

All other input are the same!

Constructing State Transition Table (output)

Now we need to set the output of the unstable states

If for some stable state the output is 0 and after input changes the resulting stable state the output is 0, then all unstable state that might be encountered during the time between the two stable state must have an output of 0.

The same for stable state with output of 1.

Present State

Next State

00 01 10 11

: 00 00,0 10,0 00,0 10,-

: 11 10,0 11,0 10,- 11,0

: 10 00,0 11,0 10,1 10,1

The unstable state (01,00) is

reachable from (00,00) having an

output 0 and eventually reaches

(01,11) which also have an output

of 0 then (01,00) must have an

output of 0.

The same for (00,11), (00,10) and

(01,10)

Constructing State Transition Table (output)

What about the others?

Consider (11,11) (10,11) (10,10) (11,11) have an output of 0

(10,10) have an output of 1

The output of (10,11) can be left unspecified (dont care) as it provides more flexibility in implementation as it does not violates that no more than a single output can change.

Present State

Next State

00 01 10 11

: 00 00,0 10,0 00,0 10,-

: 11 10,0 11,0 10,- 11,0

: 10 00,0 11,0 10,1 10,1

Note: no more than a single output

can change at a time!

You can do the same for variant 1

and 2

Determine Logic Equations (Step 5)

Present State y1y2

Next State Y1Y2,z

00 01 10 11

: 00 00,0 10,0 00,0 10,-

: 11 10,0 11,0 10,- 11,0

: 10 00,0 11,0 10,1 10,1

y1y2\x1x2 00 01 11 10

00 0 1 1 0

01 - - - -

11 1 1 1 1

10 0 1 1 1

Y1

y1y2\x1x2 00 01 11 10

00 0 0 0 0

01 - - - -

11 0 1 1 0

10 0 1 0 0

Y2

y1y2\x1x2 00 01 11 10

00 0 0 - 0

01 - - - -

11 0 0 0 -

10 0 0 1 1

z

11221 yxyxY 121222 yxxyxY

211 yyxz

Realize logic equation (Step 6)

11221 yxyxY

121222 yxxyxY

211 yyxz

Delay

dt

Delay

dt

Y2

Y1

y1

y2

x1

x2

z


With SR Latch?

11221 yxyxY

121222 yxxyxY

211 yyxz

SR Excitation Property

00 SR 0d

01 SR 10

10 SR 01

11 SR d0

Present State y1y2

Next State Y1Y2,z

00 01 10 11

: 00 00,0 10,0 00,0 10,-

: 11 10,0 11,0 10,- 11,0

: 10 00,0 11,0 10,1 10,1

Present State y1y2

Next State (S1R1,S2R2),z

00 01 10 11

: 00 (0d,0d),0 (10,0d),0 (0d,0d),0 (10,0d),d

: 11 (d0,01),0 (d0,d0),0 (d0,01),d (d0,d0),0

: 10 (01,0d),0 (d0,10),0 (d0,0d),1 (d0,0d),1


Present State y1y2


00 01 10 11

: 00 (0d,0d),0 (10,0d),0 (0d,0d),0 (10,0d),d

: 11 (d0,01),0 (d0,d0),0 (d0,01),d (d0,d0),0

: 10 (01,0d),0 (d0,10),0 (d0,0d),1 (d0,0d),1

y1y2\x1x2 00 01 11 10

00 0 1 1 0

01 d d d d

11 d d d d

10 0 d d d

S1

21 xS

y1y2\x1x2 00 01 11 10

00 d 0 0 d

01 d d d d

11 0 0 0 0

10 1 0 0 0

R1

2211 yxxR


Present State y1y2


00 01 10 11

: 00 (0d,0d),0 (10,0d),0 (0d,0d),0 (10,0d),d

: 11 (d0,01),0 (d0,d0),0 (d0,01),d (d0,d0),0

: 10 (01,0d),0 (d0,10),0 (d0,0d),1 (d0,0d),1

y1y2\x1x2 00 01 11 10

00 0 0 0 0

01 d d d d

11 0 d d 0

10 0 1 0 0

S2

1212 yxxS

y1y2\x1x2 00 01 11 10

00 d d d d

01 d d d d

11 1 0 0 1

10 d 0 d d

R2

22 xR


21 xS

2211 yxxR

1212 yxxS

22 xR

211 yyxz

Q

QSET

CLR

S

R

Q

QSET

CLR

S

R

zx1

x2

Do it yourself

Design a two input (x1, x2) and two output (z1,z2) circuit where,

z1z2 =00 when x1x2=00

Output 10 will be produced following the occurrence of 00-01-11 input sequence, and the output goes back to 00 after a 00 input.

Output 01 will be produced following the occurrence of 00-10-11 input sequence, and the output goes back to 00 after a 00 input.

Step 1: Construct Primitive Flow Table

Present State

Input State (x1 x2)

00 01 11 10

a a/00 b/-- -/-- c/--

b a/-- b/00 d/-- -/--

c a/-- -/-- e/-- c/00

d -/-- f/-- d/10 g/--

e -/-- h/-- e/01 i/--

f a/-- f/10 d/-- -/--

g a/-- -/-- d/-- g/10

h a/-- h/01 e/-- -/--

i a/-- -/-- e/-- i/01

Present State

Input State (x1 x2)

00 01 11 10

a a/00 b/00 -/-- c/00

b a/00 b/00 d/-0 -/--

c a/00 -/-- e/0- c/00

d -/-- f/10 d/10 g/10

e -/-- h/01 e/01 i/01

f a/-0 f/10 d/10 -/--

g a/-0 -/-- d/10 g/10

h a/0- h/01 e/01 -/--

i a/0- -/-- e/01 i/01

It might be easier if we assigned the output of the unstable states.

So that we correctly reduced the flow table.

Step 2: Construct Implication chart

Present State

Input State (x1 x2)

00 01 11 10

a a/00 b/00 -/-- c/00

b a/00 b/00 d/-0 -/--

c a/00 -/-- e/0- c/00

d -/-- f/10 d/10 g/10

e -/-- h/01 e/01 i/01

f a/-0 f/10 d/10 -/--

g a/-0 -/-- d/10 g/10

h a/0- h/01 e/01 -/--

i a/0- -/-- e/01 i/01

e

f

g

h

i

a b c d e f g h

d

c

b

de

Step 2: Find Maximal Compatibles

e

f

g

h

i

a b c d e f g h

d

c

b

de

column List of Maximal Compatible

h {h,i}

g {h,i}

f {h,i}{f,g}

e {e,h,i}{f,g}

d {e,h,i}{d,f,g}

c {e,h,i}{d,f,g}{c,h}

b {e,h,i}{d,f,g}{c,h}{b,g}

a {e,h,i}{d,f,g}{c,h}{b,g}{a,b}{a,c}

Step 2: Merger Diagram

column List of Maximal Compatible

h {h,i}

g {h,i}

f {h,i}{f,g}

e {e,h,i}{f,g}

d {e,h,i}{d,f,g}

c {e,h,i}{d,f,g}{c,h}

b {e,h,i}{d,f,g}{c,h}{b,g}

a {e,h,i}{d,f,g}{c,h}{b,g}{a,b}{a,c}

a

b

c

d

ef

g

h

i

Minimal cover : {e,h,i}{d,f,g}{a,b}{a,c}

Reassignment: {a,b}

{d,f,g}

{a,c}

{e,h,i}

Step 2: Reduced Flow Table

Reassignment: {a,b}

{d,f,g}

{a,c}

{e,h,i}

Present State

Input State (x1 x2)

00 01 11 10

/00 /00 /-0 /00

/-0 /10 /10 /10

/00 /00 /0- /00

/0- /01 /01 /01

Row 1 includes two states and .

Any unstable state could go to either one of them.

Present State

Input State (x1 x2)

00 01 11 10

a a/00 b/00 -/-- c/00

b a/00 b/00 d/-0 -/--

c a/00 -/-- e/0- c/00

d -/-- f/10 d/10 g/10

e -/-- h/01 e/01 i/01

f a/-0 f/10 d/10 -/--

g a/-0 -/-- d/10 g/10

h a/0- h/01 e/01 -/--

i a/0- -/-- e/01 i/01

Step 3: Secondary State Assignment

Assignment: 00

01

10

11Present State

Input State (x1 x2)

00 01 11 10

/00 /00 /-0 /00

/-0 /10 /10 /10

/00 /00 /0- /00

/0- /01 /01 /01

Look at row 4 column 1,

transition from (11 00)

Need to change (11 10)

0 1

0

1

Present State

Input State (x1 x2)

00 01 11 10

/00 /00 /-0 /00

/-0 /10 /10 /10

/00 /00 /0- /00

/0- /01 /01 /01

Step 4: Constructing Transition Table

Assignment: 00

01

10

11PS (y1 y2)

Input State (x1 x2)

00 01 11 10

00 00/00 00/00 01/-0 10/00

01 00/-0 01/10 01/10 01/10

10 10/00 00/00 11/0- 10/00

11 10/0- 11/01 11/01 11/01

0 1

0

1

Present State

Input State (x1 x2)

00 01 11 10

/00 /00 /-0 /00

/-0 /10 /10 /10

/00 /00 /0- /00

/0- /01 /01 /01

Step 4: Constructing Excitation and Output Table

PS (y1 y2)

Next State (Y1 Y2)

00 01 11 10

00 00 00 01 10

01 00 01 01 01

10 10 00 11 10

11 10 11 11 11

Output (z1 z2)

00 01 11 10

00 00 -0 00

-0 10 10 10

00 00 0- 00

0- 01 01 01

Step 5: Next State and Output Equations

y2

y1

00 01 11 10

00

01

11

10

0 0 0 1

0 0 0 0

1 1 1 1

1 0 1 1

x 1x

2y2

y1

00 01 11 10

00

01

11

10

0 0 1 0

0 1 1 1

0 1 1 1

0 0 1 0

x 1x

2

Y1

Y2

y2

y1

00 01 11 10

00

01

11

10

0 0 d 0

d 1 1 1

0 0 0 0

0 0 0 0

x 1x

2

z1

y2

y1

00 01 11 10

00

01

11

10

0 0 0 0

0 0 0 0

d 1 1 1

0 0 d 0

x 1x

2

z2

1 1 2 1 1 2 1 1 2 2

2 1 2 1 2 2 2

Y y y x y x y x x y

Y x x x y x y

1 1 2

2 1 2

z y y

z y y

Date post:	21-Nov-2015
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