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Atrenta's Solution for Power Formats Kiran Vittal July 26, 2009
Atrenta's Solution for Power Formats
Kiran Vittal
July 26, 2009
Introduction
What is the problem?
Examples of correspondence between CPF and UPF
Atrenta’s Solution for Power Aware Design
Case Study: Customer Scenario
2
What is the Power Problem?
What the end user wants:Power intent verification for all tool flows
IP YRTLX Bridge?tool flows
What the EDA industry has delivered so far:
Y
Front-endD i
PointTools
X g
Two formats, at least five total dialects: CPF 1.0, CPF 1.0e, CPF 1.1, UPF 1.0, IEEE P1801 (“UPF
RTL Signoff
DesignX
YBridge?
2.0”)
Is it like “Blu-ray vs. HD DVD”? Or like “VHDL vs
Howbridge?
RTL SignoffThis ProblemIs a LOT more
DifficultDVD ? Or like VHDL vs. Verilog”? Back-end
Implement
Y
DifficultThan it looks!
And the target
3
Y And the targetKeeps moving!
Correspondence Between CPF and UPF
CPF and UPF overlap, but not completely
For some easy situations, you can convert between them with a “perl” script or equivalentperl script or equivalent
For some hard situations, you can find a correspondence, but it is CPF UPF
Same ideas, completely
different syntax: >80%very tricky
In some cases one language does not even have any way to
syntax: >80% of needs
not even have any way to represent something in the other language; this is “impossible” without syntax additions
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without syntax additions
What Atrenta DoesSpyGlass®
Thousands of designs
1Team®
Dozens of designs
WithAtrenta
Enter @ architecture Debug & close@ RTL
Early Design Closure Late Design Closure
Design Closure:Unambiguous andUnambiguous and
error-free completion of design Enter @ RTL
Without Atrenta
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Debug & close@ implementation
Two Steps to Freedom From Implementation Woes
Enter your design at the architectural level
Build the overall chip connectivityEstablish feasibility for the plan
Validate & close at RTLVerify power, area, timing, clocks testclocks, testHandoff to implementation knowing that the design is ready
Free yourself from long, expensive and costly back-end iteration loops
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Atrenta’s Support for Power Formats
SGDC Pwr
Atrenta SGDC added power intent in 2004 SGDC-Pwr
SpyGlass uses SGDC for power verificationAlso useful for power estimation/reduction Same ideas,
completely
Attempts to standardize power formatsCadence “Common” CPF prod’n use 2007A ll “U ifi d” UPF d’ 2008
completely different
syntax: >80% of needs
Accellera “Unified” UPF prod’n use 2008Atrenta supports CPF & UPF formats now
Need to resolve for RTL signoff
CPF UPF
E.G.Simulation
E.G.Multi cornerNeed to resolve for RTL signoff
Needs increase for advanced technology nodesUsers need solutions to support both
Simulation semantics
Multi-corner STA setup
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ppformats now
Atrenta Power Optimization & Verification
SupportsSpec’s
Spec Sheetor C/C++
Power planning & tradeoffsArchitecture-level to post-layoutAuto-write CPF from spec tablesSpec s
V1
V2
PD2PD1
? RTL
Auto write CPF from spec tablesPower domain planningAccurate RTL power estimation
Power design & optimization
C/C++
VCD
Synth
RTL …
Power design & optimizationIsolate & remove power hogsIntelligent power reductionIntegrated debug environment
VCDFSDBSAIF
UPFCPFSGDC
SDC
P & R
Synth
Libraries
g gClock & DFT aware optimizationIncludes sequential formal methods
Power verificationNetlists
UPFCPF
P & RHDL/CPF Lint & syntax checksCorrectness at all design stepsFind other reduction tool errors
ConstraintsTiming& DFT
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GDSII Atrenta ensures end optimized design == design intent
& DFT
Case Study: Low Power Verification on a Wireless Chip
SynthesisRTL Netlist Place & R t
FinalN tli tSynthesisRTL
w LS & ISO
Netlist Route Netlist
AtrentaSpyGlass
CPF ’InternalInternalPower
y
Messy
CPF
UPF2CPF CPF
ToolkitPower Intent
UPF
Messy ManualProcess
AtrentaSpyGlass
Translator CPF
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System House ASIC Vendor
SpyGlass
Conclusion
Customers want power intent verification for today’s designs and existing tool flowsy g g
Some intent can be easily written in either format, some not so easily, and some does not have any correspondence
Atrenta can help manage this problem and provide a solution for existing design flows and tool environments
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What’s Next in Power?
Kiran VittalJuly 26, 2009
Flow for Defining an Optimal Power ArchitecturePlan for power management from the earliest stages of chip assembly
Capture design, domains and scenariosRefine power estimates as design
Tech data(.lib, Tcl or
CSV)Refine power estimates as design progressesPerform what–if analysis and trade-offs
Map to the implemented chip RTL
UPF/CPFRTL orIP-XACT
Generate CPF/UPF to drive level-shifter/isolation logic insertion through synthesis and rail generation/hookup in physical design
PowerController
Assertions
[%-FOREACH row IN design.tt_table('design.Connections.Interface')%][% SET srcvolt = row.src_instance.voltage;
dstvolt = row.dst_instance.voltage%][%IF srcvolt != dstvolt%]
delete_connection –instance row.src_instance –interface row.src_interface –instance row.dst_instance –interface row.dst_interface
Instrument design with power controllers
Control voltage rail switching, clock scaling, retention/bias logic control
add_connection –instance row.src_instance –interface row.src_interface –instance row.dst_instance –interface row.dst_interface-glue [%lookup_lvs(srcvolt,dstvolt)%][%END%][%END%]
a b c +
G1aG1
cb
Partition the design netlist into a form suitable for physical partitioning
ECO with
d e
+G1e
d
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Generate assertions to verify the instrumented design
RTL orIP-XACT
rip-up
Atrenta Related DAC User Track Presentations
Towards Front-End Design Productivity 6.3s Assessing Design Feasibility Early with Atrenta’s 1Team®-Implement SOCSpeaker: Thierry T. Sejourne - STMicroelectronics, Grenoble, France
Front-End Power Planning and Analysis 9.3s New SOC Integration Strategies for Multi-Million Gate, Multi-Power/Voltage Domain Designs Speaker: Sarveswara Tammali - Texas Instruments, Bangalore, India
Front-End Power Planning and Analysis 9.5 ALPES: Architectural-Level Power Planning and Estimation
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Speaker: Francis Maquin - STMicroelectronics, Crolles, France
