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Author :Tim Oliver, Bertil Schmidt, Darran Nathan, Ralf Clemens, and Douglas Maskell1....

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Author :Tim Oliver, Bertil Schmidt, Darran Nathan, Ralf Clemens, and Douglas Maskell1. Publisher/Conf :2005 11th International Conference on Parallel and Distributed Systems. Speaker : De Yu Chen. Data : 2010.5.19 1
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Page 1: Author :Tim Oliver, Bertil Schmidt, Darran Nathan, Ralf Clemens, and Douglas Maskell1. Publisher/Conf :2005 11th International Conference on Parallel and.

Author :Tim Oliver, Bertil Schmidt, Darran Nathan, Ralf Clemens, and Douglas Maskell1.Publisher/Conf :2005 11th International Conference on Parallel and Distributed Systems.Speaker : De Yu Chen. Data : 2010.5.19

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Page 2: Author :Tim Oliver, Bertil Schmidt, Darran Nathan, Ralf Clemens, and Douglas Maskell1. Publisher/Conf :2005 11th International Conference on Parallel and.

Introduction. Progressive Sequence Alignment. Pairwise Sequence Distance Computation. Mapping onto an FPGA platform. Performance Evaluation.

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Page 3: Author :Tim Oliver, Bertil Schmidt, Darran Nathan, Ralf Clemens, and Douglas Maskell1. Publisher/Conf :2005 11th International Conference on Parallel and.

Due to the rapid growth of biological sequence databasesbiologists have to compute Multiple Sequence Alignments (MSAs) in a far shorter time. In this paper we present a new approach to MSA on reconfigurable hardware platforms to gain high performance at low cost. To derive an efficient mapping onto this type of architecture, fine-grained parallel processing elements (PEs) have been designed.

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Page 4: Author :Tim Oliver, Bertil Schmidt, Darran Nathan, Ralf Clemens, and Douglas Maskell1. Publisher/Conf :2005 11th International Conference on Parallel and.

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Page 5: Author :Tim Oliver, Bertil Schmidt, Darran Nathan, Ralf Clemens, and Douglas Maskell1. Publisher/Conf :2005 11th International Conference on Parallel and.

Progressive alignment is a widely used heuristic [3]. Examples include ClustalW [13], PRALINE [5], and PILEUP. Typically, progressive alignment methods consist of three steps:

Step 1:A distance value between each pair of sequences is computed using pairwise sequencen alignment. The obtained valued from the alignments are stored in a so-called distance matrix.

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Page 6: Author :Tim Oliver, Bertil Schmidt, Darran Nathan, Ralf Clemens, and Douglas Maskell1. Publisher/Conf :2005 11th International Conference on Parallel and.

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Page 7: Author :Tim Oliver, Bertil Schmidt, Darran Nathan, Ralf Clemens, and Douglas Maskell1. Publisher/Conf :2005 11th International Conference on Parallel and.

Step 2: This step uses the distance matrix obtained from the first step and forms a guided-tree using the neighbor-joining method [11]. The leaves of the tree contain the various sequences.

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Page 8: Author :Tim Oliver, Bertil Schmidt, Darran Nathan, Ralf Clemens, and Douglas Maskell1. Publisher/Conf :2005 11th International Conference on Parallel and.

Step 3:Progressive Alignment: First closely related sequences or group of sequences are aligned and at the end most divergent sequences are aligned to get the final MSA.

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Page 9: Author :Tim Oliver, Bertil Schmidt, Darran Nathan, Ralf Clemens, and Douglas Maskell1. Publisher/Conf :2005 11th International Conference on Parallel and.

Profiling of the three stages of ClustalW for different numbers of

globin sequences (see Table 1) reveals that more than 90% of the overall runtime is spent on the first stage (distance matrix computation). Hence, we have decided to parallelize only this stage on an FPGA.

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Page 10: Author :Tim Oliver, Bertil Schmidt, Darran Nathan, Ralf Clemens, and Douglas Maskell1. Publisher/Conf :2005 11th International Conference on Parallel and.

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Page 11: Author :Tim Oliver, Bertil Schmidt, Darran Nathan, Ralf Clemens, and Douglas Maskell1. Publisher/Conf :2005 11th International Conference on Parallel and.

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Page 12: Author :Tim Oliver, Bertil Schmidt, Darran Nathan, Ralf Clemens, and Douglas Maskell1. Publisher/Conf :2005 11th International Conference on Parallel and.

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Page 13: Author :Tim Oliver, Bertil Schmidt, Darran Nathan, Ralf Clemens, and Douglas Maskell1. Publisher/Conf :2005 11th International Conference on Parallel and.

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Page 14: Author :Tim Oliver, Bertil Schmidt, Darran Nathan, Ralf Clemens, and Douglas Maskell1. Publisher/Conf :2005 11th International Conference on Parallel and.

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Page 15: Author :Tim Oliver, Bertil Schmidt, Darran Nathan, Ralf Clemens, and Douglas Maskell1. Publisher/Conf :2005 11th International Conference on Parallel and.

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Page 16: Author :Tim Oliver, Bertil Schmidt, Darran Nathan, Ralf Clemens, and Douglas Maskell1. Publisher/Conf :2005 11th International Conference on Parallel and.

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Page 17: Author :Tim Oliver, Bertil Schmidt, Darran Nathan, Ralf Clemens, and Douglas Maskell1. Publisher/Conf :2005 11th International Conference on Parallel and.

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Page 18: Author :Tim Oliver, Bertil Schmidt, Darran Nathan, Ralf Clemens, and Douglas Maskell1. Publisher/Conf :2005 11th International Conference on Parallel and.

The PCI based ADP-WRC-II board from Alpha-Data with a Xilinx XC2V6000 FPGA has been used in the tests. This FPGA accommodates 92 PEs and is clocked at 34MHz. The ClustalW application is benchmarked on an Intel Pentium4 3GHz processor with 1GB RAM. The results for this are shown in Table 2.

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