AUTOMATED ATTENDANCE USING RFID

PROJECT REPORT

Submitted by

RAKESH.D (070107618037)

SANGEETHKUMAR.G (070107618038)

SHIVABHARATH.A (070107618046)

SUBRAMANI.V (080407618065)

In partial fulfillment for the award of the degree

of

BACHELOR OF ENGINEERING

IN

ELECTRONICS AND COMMUNICATION ENGINEERING

VIDYAA VIKAS COLLEGE OF ENGINEERING AND TECHNOLOGY

ANNA UNIVERSITY OF TECHNOLOGY 641047

OCTOBER 2010

II

ANNA UNIVERSITY OF TECHNOLOGY 641047

BONAFIDE CERTIFICATE

Certified that this project report “AUTOMATED ATTENDANCE USING RFID” is the bonafide work of RAKESH.D ,SANGEETHKUMAR.G, SHIVABHARATH.A, SUBRAMANI.V, Who carried out the project work under my supervision.

SIGNATURE SIGNATURE SUPERVISOR HEAD OF THE DEPARTMENT

Mrs.V.SANGEETHA, M.E. Mr.N.SHANMUGASUNDARAM, M.E

DEPT OF ECE DEPT OF ECE

VIDYAA VIKAS COLLEGE OF VIDYAA VIKAS COLLEGE OF

ENGINEERING &TECHNOLOGY ENGINEERING &TECHNOLOGY

TIRUCHENGODE-637214 TIRUCHENGODE-637214

III

ACKNOWLEDGEMENT

We extend our sincere thanks to our management trustees

DR.S.GUNASEKARAN, DR.T.O.SINGARAVEL, DR.M.MUTHUSAMY,

DR.S.RAMALINGAM, and our respected principal DR.S.SUNDARAM for

providing all facilities for the successful completion of this project.

We express our heartfelt thanks to our head of the department

MR.N.SHANMUGASUNDARAM, M.E., for his valuable guidance and

encouragement throughout the project period and also making various

arrangements required for our project.

We wish to express our gratitude and thanks to our guide

MRS.V.SANGEETHA, M.E., for her valuable contribution in bringing out this

project successfully.

Our sincere thanks to all of our staff members, librarian of

electronics and communication engineering department for their extended help

and co-operation to do this project.

IV

TABLE OF CONTENTS

CHAPTER NO TITLE PAGE NO

ABSTRACT VI

LIST OF TABLES VII

LIST OF FIGURES VIII

LIST OF ABBREVIATIONS IX

1. INTRODUCTION 1

1.1 objectives 1

2. SYSTEM ANALYSIS 2

2.1 Existing System 2

2.1.1Drawbacks 2

2.2 Proposed system 2

3. SYSTEM SPECIFICATIONS 3

3.1 Hardware requirements 3

3.2 Software requirements 3

4. PROJECT DESCRIPTION 4

4.1 Block Diagram 4

4.1.1 Components of system 5

5. MICROCONTROLLER 11

5.1 Introduction 11

5.2 Features of ATMEGA8515 11

5.3 Pin configuration ATMEGA8515 13

5.4 Architecture of ATMEGA8535 16

5.5 Architectural overview 18

V

5.6 Serial Communication 20

5.6.1 Introduction of RS-232 20

5.6.2 Bit streams 21

5.6.3 RS-232 Physical Properties 24

5.6.4 USART 24

5. SOFTWARE DESCRIPTION

5.1 AVR studio

5.2 line by line debugging

5.3 work space window

5.4 memory window

5.5 debugging strategies

27

27

27

28

29

30

6. CONCLUSION AND FUTUREWORKS 31

6.1 Conclusion 31

6.2 Future works 31

7. REFERENCES 32

VI

ABSTRACT

‘AUTOMATIC ATTENDANCE SYSTEM ’ is designed to collect

and manage student’s attendance records from RFID devices installed in

a class rooms. Based on the verification of student identification at the

entrances, the system could generate sophisticated student attendance

data for analysis purposes.

Class room automation is based on personalized profiles. Profiles

can be edited on the run time without making any changes in the

hardware. The database software is smart enough to mark the attendance

if and only if the card holder spent a minimum time required for

attendance in classroom. Embedded module will keep on checking whether

any person entering or leaving.

The RFID system consists of an RFID tag, a reader, and a user-

interface display. When the tag is energized by the RF field, it transmits

back the contents of its memory by modulating the incoming RF field.

The reader detects and demodulates the signal and identifies the tag.

Entering will be considered if persons from IR SLOT 1 to IRSLOT 2, leaving

is considered from IR SLOT 2 to IRSLOT 1.

VII

LIST OF FIGURES

FIG NO TITLE PAGENO

4.1 Basic block diagram 4

4.2 Pin diagram of RFID Reader 6

4.3 IR Sensor 8

4.4 Diagram of LCD Display 8

5.1 Pin configuration 13

5.2 Architecture of ATMEGA8515 16

5.3 Architecture Overview 18

5.4 USART Block Diagram 25

VIII

LIST OF TABLES

TABLE NO. TITLE PAGE

4.1 Frequency chart of RFID 7

4.2 Pin configuration of LCD Display 9

5.1 RS-232C Interface Signals. 21

IX

LIST OF ABBREVIATIONS

1. RF - Radio Frequency

2. ID - Identification

3. RFID - Radio Frequency Identification

4. UART - Universal Asynchronous Receiver/Transmitter

5. IDE - Integrated Development Environment

6. EEPROM - Electrically Erasable Programmable Read-Only Memory

7. IR SENSOR - Infrared Sensor

8. LCD - Liquid Crystal Display

CHAPTER 1

INTRODUCTION

The two major problems faced by organizations are time consuming manual

attendance and wastage of electrical power. Our project is going to solve these problems by

using RFID technology. The project is designed to store up to 50 card IDs but it is easily

scalable up to 65000 card IDs but for that it requires external memory. Radio Frequency

Identification (RFID) is an automatic identification method, relying on storing and remotely

retrieving data using devices called RFID tags or transponders. So the RFID is a wireless

identification.

Normally the RFID system comprises of two main parts: RFID Reader and

RFID Tag. RFID Reader is an integrated or passive network which is used to interrogate

information from RFID tag. The RFID Reader may consist of antenna, filters, modulator,

demodulator, coupler and a micro processor.

1.1 OBJECTIVE

The aim of the project is to design a system that have a small coverage area

and can be use for authentication or identification purposes. “AUTOMATED

ATTENDANCE USING RFID” is to maintain the attendance at real-time that can be

monitored on PC. The objectives of this project is to develop a portable RFID Based

Attendance System that is able to:

1. Store students ID and name.

2. Display the students entry stored in EEPROM on LCD display.

3. Uniquely identify the students data.

4. Track and display absentees data.

1

2

CHAPTER 2

SYSTEM ANALYSIS

2.1 EXISTING SYSTEM

A barcode reader is an electronic device for reading printed barcodes. It

consists of a light source, a lens and a light sensor translating optical impulses into electrical

ones. The hand-held laser scanner has to be close to the bar code in order to do its job. It

reads only a bar code up to 2 inches away.

In this project, the Barcode scanner is interfaced with the micro controller and

when the barcode card is brought to the sight of the scanner, it reads the data on the barcode

card and displays on the LCD. If the data of the card is matched with the data in the program

memory then it compares and adds attendance credit to his record. If the data is not matched

it displays unauthorized.

2.1.1 DRAWBACKS

i. Require line of sight to be read

ii. Can only be read individually

iii. Cannot be read if damaged or dirty

iv. Can only identify the type of item

v. Cannot be updated

vi. Most barcode scanners require a human to operate (labour intensive)

2.2 PROPOSED SYSTEM

Embedded module will keep on checking whether any person entering or

leaving. Entering will be considered if persons from IR SLOT 1 to IRSLOT 2, leaving is

considered from IR SLOT 2 to IRSLOT 1.If any person enters ID is getting from RF Tag, if it

is valid ID then the person will come inside. System will acquire the data from tag and check

with EEPROM.Then the person details displayed in LCD and also display the no of person’s

presence and absence.

3

CHAPTER 3

SYSTEM SPECIFICATION

3.1HARDWARE REQUIREMENTS

The electronic hardware parts can be further divided into three parts which is

input, control system and output. The RFID reader and tag are the devices used as the input.

Other than that, IR slots are act as input. The control system was developed using

ATMEGA 8515 microcontroller. Meanwhile, the 2x16 LCD display and buzzer are chosen as

output of the electronic hardware parts.

A Passive Infrared sensor is also used in the hardware part. It is usually

infrared radiation that is invisible to the human eye but it can identified human, passes in

front of an infrared source

3.2 SOFTWARE REQUIREMENTS

The microcontroller needs to be programmed first before it can be used in the

electronic hardware. The C programming language is chosen to program the ATMEGA 8515

microcontroller under AVR STUDIO 4. Correct and functional code ensures the

microcontroller to work properly and accordingly. The layout of the printed circuit board is

designed by using manual routing of the connections of each electronic component involved

in developing the system.

AVR Studio 4 provides a complete set of features including debugger

supporting run control including source and instruction-level stepping and breakpoints;

registers, memory and I/O views; and target configuration and management as well as full

programming support for standalone programmers.

4

CHAPTER 4

PROJECT DESCRIPTION

4.1BLOCK DIAGRAM

RS232

FIG 4.1 BASIC BLOCK DIAGRAM

MICROCONTROLLER EMBEDDED MODULE

IOPORT

IO PORT

USART

EEPROM

SRAM

FLASH

MEMORY

POWER SUPPLY

MAX232

RFID READER

LCD DISPLAY UNIT

IR SLOT 2

IR SLOT 1

5

4.1.1 COMPONENTS OF SYSTEM

The figure below shows the basic block diagram of the AUTOMATED

ATTENDANCE USING RFID. It contains the following blocks:

1. RFID reader

2. RFID tags

3. Infrared sensors

4. LCD display

5. Microcontroller

6. Power supply unit RFID READER

A reader (now more typically referred to as an RFID interrogator) is basically

a radio frequency (RF) transmitter and receiver, controlled by a microprocessor or digital

signal processor. The reader, using an attached antenna, captures data from tags, then passes

the data to the controller for processing. The reader decodes the data encoded in the tags

integrated circuit (silicon chip) and the data is passed to the microcontroller for processing.

FEATURES OF RFID READER

a. Low cost solution for reading passive RFID transponder tags.

b. Industrial grade casing for better outlook and protection.

c. Integrated RFID reader, antenna, LED, power cable and data cable.

d. Every reader has been tested before is being shipped.

e. 9600 baud RS232 serial interface (output only) to PC.

f. Fully operation with 5VDC power supply.

g. Buzzer as sound indication of activity.

h. Bi-colour LED for visual indication of activity.

i. Standard RS232 serial cable (female) ready to plug to desktop PC or Laptop.

j. 2m reading range.

k. 0.1s response time.

l. Operating frequency: 125KHz

6

FIGURE 4.2 PIN DIAGRAM OF RFID READER RFID TAGS

Tags also sometimes are called “transponders”. RFID tags can come in many

forms and sizes. Some can be as small as a grain of rice. Data is stored in the IC and

transmitted through. The antenna to a reader.

The two commonly used RFID Transponders are Active (that do contain an

internal battery power source that powers the tags chip) and Passive (that do not have an

internal power source, but are externally powered typical from the reader) RFID

Transponders.

WORKING OF RFID

Information is sent to and read from RFID tags by a reader using radio waves.

In passive systems, which are the most common, an RFID reader transmits an energy field

that “wakes up” the tag and provides the power for the tag to respond to the reader. Data

collected from tags is then passed through communication interfaces (cable or wireless) to

ATMEGA 8515 in the same manner that data scanned from bar code labels is captured and

passed to computer systems for interpretation, storage, and action.

7

FREQUENCIES OF RFID

RFID deployments tend to use unlicensed frequencies for their cost benefits.

There are four commonly used frequencies:

Frequency Band

Description Operating Range

Benefits Drawbacks

125KHz to 134 KHz

Low Frequency

< .5M or 1.5ft.

Works well Around water and metal products.

Short read range and slower read rates

13.56 MHz

High Frequency

< 1M or 3ft.

Low cost of tags

Higher read rate than LF

860 MHz to 930MHz

Ultrahigh Frequency (UHF)

3m or 9ft. EPC standard Built around This frequency

Does not work well around items of high water or metal content

2.4GHz Microwave 1m or3 ft. Most Expensive

Fastest read Rates

TABLE 4.1 FREQUENCY CHART OF RFID

INFRARED SENSOR

Infrared radiation exists in the electromagnetic spectrum at a wavelength that is

longer than visible light. It cannot be seen but it can be detected. Objects that generate heat

also generate infrared radiation and those objects include animals and the human body whose

radiation is strongest at a wavelength of 9.4um.

The pyroelectric sensor is made of a crystalline material that generates a

surface electric charge when exposed to heat in the form of infrared radiation. When the

amount of radiation striking the crystal changes, the amount of charge also changes and can

then be measured with a sensitive FET device built into the sensor. The sensor elements are

sensitive to radiation over a wide range so a filter window is added to the TO5 package to

limit detectable radiation to the 8 to 14mm range which is most sensitive to human body

radiation.

8

FIGURE 4.3 IR SENSORS

An IR emitting body moving across the front of a sensor will expose first one,

then both and then the other sensor element. The output signal waveform from an analog

sensor shows that for motion in one direction, first a positive, then zero and then a negative

transition results. Motion in the other direction will produce first a negative, then zero and

then a positive transition.

LCD DISPLAY

The display support 2X16 characters, which means, the LCD can support 2

lines on the display and each line can display up to 16 characters which is relevant as the only

essential output to be displayed is the student’s name and ID. Besides LCD Display, the

output is displayed on LCD. The diagram of LCD display is shown in Figure 4.4 and the

detailed connections of the LCD is shown in table 4.2

FIGURE 4.4 DIAGRAM OF LCD DISPLAY

9

Table 4.2 Pin connections of LCD Display. EEPROM

EEPROM stands for Electrically Erasable Programmable Read-Only Memory

and is a type of non-volatile memory used in computers and other electronic devices

to store small amounts of data that must be saved when power is removed. In

ATMEGA 8515, the data EEPROM and Flash program memory is readable and writable

during normal operation (over the full VDD range). This memory is not directly mapped in

the register file space. Instead, it is indirectly addressed through the Special Function

Registers.

10

There are six SFRs used to read and write this memory:

1. EECON1

2. EECON2

3. EEDATA

4. EEDATH

5. EEADR

6. EEADRH

When interfacing to the data memory block, EEDATA holds the 8-bit data for

read/write and EEADR holds the address of the EEPROM location being accessed.

These devices have 128 or 256 bytes of data EEPROM (depending on the device), with an

address range from 00h to FFh.

On devices with 128 bytes, addresses from 80h to FFh are unimplemented and

will wraparound to the beginning of data EEPROM memory. When writing to

unimplemented locations, the on-chip charge pump will be turned off. When interfacing the

program memory block, the EEDATA and EEDATH registers form a two-byte word that

holds the 14-bit data for read/write and the EEADR and EEADRH registers form a two-byte

word that holds the 13-bit address of the program memory location being accessed.

These devices have 4 or 8K words of 17 programs Flash, with an address

0000h to 1FFFh for the ATMEGA 8515. Addresses above the range of the respective device

will wraparound to the beginning of program memory.

11

CHAPTER 5

MICROCONTROLLER

5.1 INTRODUCTION

The new ATMega8515 Controller is the ideal solution for use as a standard

controller in many applications. The small compact size combined with easy program updates

and modifications make it ideal for use in machinery and control systems, such as alarms,

card readers, real-time monitoring applications and much more. This board is ideal as the

brains of your robot or at the centre of your home-monitoring system. Save time and money,

by simply building your ancillary boards and monitoring circuits around this inexpensive and

easy to use controller.

5.2 FEATURES OF ATMEGA 8515

1. High-performance, Low-power AVR® 8-bit Microcontroller

2. RISC Architecture

a. 130 Powerful Instructions – Most Single Clock Cycle Execution

b. 32 x 8 General Purpose Working Registers

c. Fully Static Operation

d. Up to 16 MIPS Throughput at 16 MHz

e. On-chip 2-cycle Multiplier

3. Non-volatile Program and Data Memories

a. 8K Bytes of In-System Self-programmable Flash

b. Endurance: 10,000 Write/Erase Cycles

c. Optional Boot Code Section with Independent Lock bits

d. In-System Programming by On-chip Boot Program

e. True Read-While-Write Operation

f. 512 Bytes EEPROM

g. Endurance: 100,000 Write/Erase Cycles

h. 512 Bytes Internal SRAM

i. Up to 64K Bytes Optional External Memory Space

j. Programming Lock for Software Security

12

4. Peripheral Features

a. – One 8-bit Timer/Counter with Separate Prescaler and Compare Mode

b. One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and

Capture Mode

c. Three PWM Channels

d. Programmable Serial USART

e. Master/Slave SPI Serial Interface

f. Programmable Watchdog Timer with Separate On-chip Oscillator

g. On-chip Analog Comparator

5. Special Microcontroller Features

a. Power-on Reset and Programmable Brown-out Detection

b. Internal Calibrated RC Oscillator

c. External and Internal Interrupt Sources

d. Three Sleep Modes: Idle, Power-down and Standby

6. I/O and Packages

a. 35 Programmable I/O Lines

b. 40-pin PDIP, 44-lead TQFP, 44-lead PLCC, and 44-pad QFN/MLF

7. Operating Voltages

a. 2.7 - 5.5V for ATmega8515L

b. 4.5 - 5.5V for ATmega8515

8. Speed Grades

a. 0 - 8 MHz for ATmega8515L

b. 0 - 16 MHz for ATmega8515

13

5.3 PIN CONFIGURATION OF ATMEGA 8515

FIGURE 5.1 PIN CONFIGURATION PIN DESCRIPTION VCC Digital supply voltage. GND Ground.

14

Port A (PA7...PA0) Port A is an 8-bit bi-directional I/O port with internal pull-up

resistors (selected for each bit). The Port A output buffers have

symmetrical drive characteristics with both high sink and

source capability. When pins PA0 to PA7 are used as inputs

and are externally pulled low, they will source current if the

internal pull-up resistors are activated. The PortA pins are tri-

stated when a reset condition becomes active, even if the clock

is not running.

Port A also serves the functions of various special features of

the ATmega8515

Port B (PB7...PB0) Port B is an 8-bit bi-directional I/O port with internal pull-up

resistors (selected for each bit). The Port B output buffers have

symmetrical drive characteristics with both high sink and source

capability. As inputs, Port B pins that are externally pulled low

will source current if the pull-up resistors are activated. The

Port B pins are tri-stated when a reset condition becomes active,

even if the clock is not running.

Port B also serves the functions of various special features of

the ATmega8515.

Port C (PC7..PC0) Port C is an 8-bit bi-directional I/O port with internal pull-up

resistors (selected for each bit). The Port C output buffers have

symmetrical drive characteristics with both high sink and

source capability. As inputs, Port C pins that are externally

pulled low will source current if the pull-up resistors are

activated.

The Port C pins are tri-stated when a reset condition becomes

active, even if the clock is not running.

15

Port D (PD7...PD0) Port D is an 8-bit bi-directional I/O port with internal pull-up

resistors (selected for each bit). The Port D output buffers have

symmetrical drive characteristics with both high sink and

source capability. As inputs, Port D pins that are externally

pulled low will source current if the pull-up resistors are

activated. The Port D pins are tri-stated when a reset condition

becomes active, even if the clock is not running.

Port D also serves the functions of various special features of

the ATmega8515

Port E(PE2...PE0) Port E is a 3-bit bi-directional I/O port with internal pull-up

resistors (selected for each bit). The Port E output buffers have

symmetrical drive characteristics with both high sink and

source capability. As inputs, Port E pins that are externally

pulled low will source current if the pull-up resistors are

activated. The Port E pins are tri-stated when a reset condition

becomes active, even if the clock is not running.

Port E also serves the functions of various special features of

the ATmega8515.

RESET Reset input. A low level on this pin for longer than the

minimum pulse length will generate a reset, even if the clock is

not running. Shorter pulses are not guaranteed to generate a

reset.

XTAL1 Input to the inverting Oscillator amplifier and input to the

internal clock operating circuit.

XTAL2 Output from the inverting Oscillator amplifier.

16

5.4 ARCHITECTURE OF ATMEGA8515

BLOCK DIAGRAM

FIGURE 5.2 ARCHITECTURE OF ATMEGA8515

The ATmega8515 is a low-power CMOS 8-bit microcontroller based on the

AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle,

the ATmega8515 achieves throughputs approaching 1 MIPS per MHz allowing the system

designer to optimize power consumption versus processing speed.

17

The AVR core combines a rich instruction set with 32 general purpose

working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit

(ALU), allowing two independent registers to be accessed in one single instruction executed

in one clock cycle. The resulting architecture is more code efficient while achieving

throughputs up to ten times faster than conventional CISC microcontrollers.

The ATmega8515 provides the following features: 8K bytes of In-System

Programmable Flash with Read-While-Write capabilities, 512 bytes EEPROM, 512 bytes

SRAM, an External memory interface, 35 general purpose I/O lines, 32 general purpose

working registers, two flexible Timer/Counters with compare modes, Internal and External

interrupts, a Serial Programmable USART, a programmable Watchdog Timer with internal

Oscillator, a SPI serial port, and three software selectable power saving modes.

The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI

port, and Interrupt system to continue functioning. The Power-down mode saves the Register

contents but freezes the Oscillator, disabling all other chip functions until the next interrupt or

hardware reset. In Standby mode, the crystal/resonator Oscillator is running while the rest of

the device is sleeping. This allows very fast start-up combined with low-power consumption.

The device is manufactured using Atmel’s high density non-volatile memory technology.

The On-chip ISP Flash allows the Program memory to be reprogrammed In-

System through an SPI serial interface, by a conventional non-volatile memory programmer,

or by an On-chip Boot program running on the AVR core. The boot program can use any

interface to download the application program in the Application Flash memory. Software in

the Boot Flash section will continue to run while the Application Flash section is updated,

providing true Read-While-Write operation.

By combining an 8-bit RISC CPU with In-System Self-programmable Flash

on a monolithic chip, the Atmel ATmega8515 is a powerful microcontroller that provides a

highly flexible and cost effective solution to many embedded control applications. The

ATmega8515 is supported with a full suite of program and system development tools

including: C Compilers, Macro assemblers, Program debugger/simulators, In-circuit

Emulators, and Evaluation kits.

18

5.5 ARCHITECTURE OVERVIEW Block Diagram of the AVR Architecture

FIGURE 5.3 ARCHITECTURE OVERVIEW

In order to maximize performance and parallelism, the AVR uses Harvard

architecture with separate memories and buses for program and data. Instructions in the

Program memory are executed with a single level pipelining. While one instruction is being

executed, the next instruction is pre-fetched from the Program memory. This concept enables

instructions to be executed in every clock cycle. The Program memory is In-System re

programmable Flash memory.

19

The fast-access Register File contains 32 x 8-bit general purpose working

registers with a single clock cycle access time. This allows single-cycle Arithmetic Logic

Unit (ALU) operation. In a typical ALU operation, two operands are output from the Register

File, the operation is executed, and the result is stored back in the Register File – in one clock

cycle.

Six of the 32 registers can be used as three 16-bit indirect address register

pointers for Data Space addressing – enabling efficient address calculations. One of these

address pointers can also be used as an address pointer for look up tables in Flash Program

memory. These added function registers are the 16-bit X-, Y-, and Z-register, described later

in this section.

The ALU supports arithmetic and logic operations between registers or

between a constant and a register. Single register operations can also be executed in the ALU.

After an arithmetic operation, the Status Register is updated to reflect information about the

result of the operation.

Program flow is provided by conditional and unconditional jump and call

instructions, able to directly address the whole address space. Most AVR instructions have a

single 16-bit word format. Every Program memory address contains a 16- or 32-bit

instruction.

Program Flash memory space is divided in two sections, the Boot Program

section and the Application Program section. Both sections have dedicated Lock bits for write

and read/write protection. The SPM instruction that writes into the Application Flash memory

section must reside in the Boot Program section.

During interrupts and subroutine calls, the return address Program Counter

(PC) is stored on the Stack. The Stack is effectively allocated in the general data SRAM, and

consequently the Stack size is only limited by the total SRAM size and the usage of the

SRAM. All user programs must initialize the SP in the reset routine (before subroutines or

interrupts are executed). The Stack Pointer SP is read/write accessible in the I/O space. The

data SRAM can easily be accessed through the five different addressing modes supported in

the AVR architecture.

20

The memory spaces in the AVR architecture are all linear and regular memory

maps. A flexible interrupt module has its Control Registers in the I/O space with an

additional Global Interrupt Enable bit in the Status Register. All interrupts have a separate

interrupt vector in the Interrupt Vector table. The interrupts have priority in accordance with

their Interrupt Vector position. The lower the Interrupt Vector address, the higher the priority.

The I/O memory space contains 64 addresses for CPU peripheral functions as

Control Registers, SPI, and other I/O functions. The I/O Memory can be accessed directly, or

as the Data Space locations following those of the Register File.\

5.6 Serial Communication

Serial communication is often used either to control or to receive data from an

embedded microprocessor. Serial communication is a form of I/O in which the bits of a byte

begin transferred appear one after the other in a timed sequence on a single wire.

5.6.1 Introduction of RS-232

RS-232 is a straightforward, universal, and commonly implemented serial interface.

Despite its limited 15 m transmission distance, its low cost and easy wiring features make

RS-232 the first choice for many applications. RS-232 establishes two-way (full-duplex)

communications, with signals represented by voltage levels measured with respect to a

system common ground (power/logic ground).

Serial communication requires that you specify the following four parameters:

• The baud rate of the transmission

• The number of data bits encoding a character

• The number of data bits encoding a character

• The sense of the optional parity bit

• The number of stop bits

21

Pin Description

Pin Description Pin Description

1 Protective Ground 10 (Reserved for Data Set Testing)

19 Secondary Request to Send

2 Transmitted Data 11 Unassigned 20 Data Terminal Ready 3 Received Data

12 Sec. Rec'd. Line Sig.

Detector

21 Signal Quality Detector

4 Request to Send 13 Sec. Clear to Send 22 Ring Indicator 5 Clear to Send 14 Secondary Transmitted

Data 23 Data Signal Rate Selector (DTE/DCE Source)

6 Data Set Ready 15 Transmission Signal Element Timing

24 Transmit Signal Element (DCE Source) Timing (DTE Source)

7 Signal Ground (Common Return)

16 Secondary Received Data

25 Unassigned

8 Received Line Signal 17 Receiver Signal Element Timing Detector (DCE Source)

9 (Reserved for data set

testing)

18 Unassigned

TABLE5.1 RS-232C Interface Signals.

5.6.2 BIT STREAMS

The RS232 standard describes a communication method where information is

sent bit by bit on a physical channel. The information must be broken up in data words. The

length of a data word is variable. On PC's a length between 5 and 8 bits can be selected. This

length is the net information length of each word. For proper transfer additional bits are

added for synchronization and error checking purposes. It is important, that the transmitter

and receiver use the same number of bits. Otherwise, the data word may be misinterpreted, or

not recognized at all.

22

With synchronous communication, a clock or trigger signal must be present

which indicates the beginning of each transfer. The absence of a clock signal makes an

asynchronous communication channel cheaper to operate. Less lines are necessary in the

cable. A disadvantage is, that the receiver can start at the wrong moment receiving the

information. Resynchronization is then needed which costs time. All data received in the

resynchronization period is lost. Another disadvantage is that extra bits are needed in the data

stream to indicate the start and end of useful information. These extra bits take up bandwidth.

Data bits are sent with a predefined frequency, the baud rate. Both the

transmitter and receiver must be programmed to use the same bit frequency. After the first bit

is received, the receiver calculates at which moments the other data bits will be received. It

will check the line voltage levels at those moments.

With RS232, the line voltage level can have two states. The on state is also

known as mark, the off state as space. No other line states are possible. When the line is idle,

it is kept in the mark state.

START BIT

RS232 defines an asynchronous type of communication. This means, that

sending of a data word can start on each moment. If starting at each moment is possible, this

can pose some problems for the receiver to know which is the first bit to receive. To

overcome this problem, each data word is started with an attention bit. This attention bit, also

known as the start bit, is always identified by the space line level. Because the line is in mark

state when idle, the start bit is easily recognized by the receiver.

DATA BITS

Directly following the start bit, the data bits are sent. A bit value 1 causes the

line to go in mark state, the bit value 0is represented by a space. The least significant bit is

always the first bit sent.

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PARITY BIT

For error detecting purposes, it is possible to add an extra bit to the data word

automatically. The transmitter calculates the value of the bit depending on the information

sent. The receiver performs the same calculation and checks if the actual parity bit value

corresponds to the calculated value.

STOP BITS

Suppose that the receiver has missed the start bit because of noise on the

transmission line. It started on the first following data bit with a space value. This causes

garbled date to reach the receiver. A mechanism must be present to resynchronize the

communication. To do this, framing is introduced.

The period of time lying between the start and stop bits is a constant defined

by the baud rate and number of data and parity bits. The start bit has always space value, the

stop bit always mark value. If the receiver detects a value other than mark when the stop bit

should be present on the line, it knows that there is a synchronization failure. This causes a

framing error condition in the receiving UART. The device then tries to resynchronize on

new incoming bits.

For desynchronizing, the receiver scans the incoming data for valid start and

stop bit pairs. This works, as long as there is enough variation in the bit patterns of the data

words.

The stop bit identifying the end of a data frame can have different lengths.

Actually, it is not a real bit but a minimum period of time the line must be idle (mark state) at

the end of each word. On PC's this period can have three lengths: the time equal

to 1, 1.5 or 2 bits. 1.5 bits is only used with data words of 5 bits length and 2 only for longer

words. A stop bit length of 1 bit is possible for all data word sizes.

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5.6.3 RS-232 PHYSICAL PROPERTIES

The RS232 standard describes a communication method capable of communicating in

different environments. This has had its impact on the maximum allowable voltages etc. on

the pins. In the original definition, the technical possibilities of that time were taken into

account. The maximum baud rate defined for example is 20 kbps. With current devices like

the 16550A UART, maximum speeds of 1.5 Mbps are allowed.

5.6.4 USART

USART stands for Universal Synchronous Asynchronous Receiver Transmitter. It is

sometimes called the Serial Communications Interface or SCI

FEATURES

The Universal Synchronous and Asynchronous serial Receiver and Transmitter

is a highly flexible serial communication device.

The main features are:

• Full Duplex Operation (Independent Serial Receive and Transmit Registers)

• Asynchronous or Synchronous Operation

• Master or Slave Clocked Synchronous Operation

• High Resolution Baud Rate Generator

• Supports Serial Frames with 5, 6, 7, 8, or 9 Data Bits and 1 or 2 Stop Bits

• Odd or Even Parity Generation and Parity Check Supported by Hardware

• Data Over Run Detection

• Framing Error Detection

• Noise Filtering Includes False Start Bit Detection and Digital Low Pass Filter

• Three Separate Interrupts on TX Complete, TX Data Register Empty and RX

Complete

• Multi-processor Communication Mode

• Double Speed Asynchronous Communication Mode

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USART BLOCK DIAGRAM

FIGURE 5.4 USART BLOCK DIAGRAM

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The dashed boxes in the block diagram separate the three main parts of the

USART (listed from the top): Clock Generator, Transmitter and Receiver. Control registers

are shared by all units. The clock generation logic consists of synchronization logic for

external clock input used by synchronous slave operation, and the baud rate generator.

The XCK (Transfer Clock) pin is only used by Synchronous Transfer mode.

The Transmitter consists of a single write buffer, a serial Shift Register, Parity Generator and

control logic for handling different serial frame formats. The write buffer allows a continuous

transfer of data without any delay between frames.

The Receiver is the most complex part of the USART module due to its clock

and data recovery units. The recovery units are used for asynchronous data reception. In

addition to the recovery units, the Receiver includes a Parity Checker, control logic, a Shift

Register and a two level receive buffer (UDR). The Receiver supports the same frame

formats as the Transmitter, and can detect frame error, data overrun and parity errors.

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CHAPTER – 6

SOFTWARE DESCRIPTION

AVRSTUDIO 4 AND ATMEGA8515

Atmel offers both 8-bit and 32-bit AVR flash microcontrollers. AVR combines

the most code-efficient architecture for c and assembly programming with the ability to tune

system parameters throughout the entire life cycle of your key products. No other

microcontrollers deliver more computing performance at lower power consumption.

Combined with industry leading development tools and design support, you get to market

faster. And once there, you can easily and cost-effectively refine and improve your product

offering.

6.1 AVR STUDIO

AVR studio 4 is an integrated development environment (IDE). just like any other

IDE, AVR studio 4 is project based. a project is like an environment for a particular program

that is being written. it keeps track of what files are open, compilation instructions, as well as

the current graphical user interface (GUI) selections.

6.2 LINE-BY-LINE DEBUGGING

Line-By-Line debugging is the best way to take control of the simulation. it allows

the programmer to verify data in registers and memory. there are several ways to get into

line-by-line debugging mode. the first would be to start the simulation in line-by-line debug

mode by clicking on the debug icon, or through the menu debug->start debugging.

When the program is in run mode, hitting the pause key will halt the simulation and

put it into line-by-line mode. Also, if a break point was set in the code, the simulation will

automatically pause at the break point and put the simulation into line-by-line mode.

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When running in line-by-line mode, several new buttons will be activated. These allow

you to navigate through the program.

a. Step into (f11) – steps into the code. Normal operation will run program line-

by-line, but will step into routine calls such as the rcall command.

b. Step over (f10) – steps over routine calls. Normal operation will run program

line-by-line, but will treat routine calls as a single instruction and not jump to the

routine instructions.

c. Step out (shift+f11) – steps out of routine calls. This will temporarily put the

simulation into run mode for the remainder of the routine and will pause at the

next instruction after the routine call.

d. run to cursor (ctrl+f10) – runs simulation until cursor is reached. the cursor is

the blinking line indicating where to type. Place the cursor by putting the mouse

over the instruction we want to stop at and hit the run to cursor icon.

After experimenting around with these four commands, we will be able to navigate through

the code with ease.

6.3WORKSPACE WINDOW

The workspace window holds valuable information about the project and the

simulation. There are three areas of the workspace windows signified by tabs at the bottom;

project, I/O, and info.

The project window contains all the information related to the project such as files

and file structuring. From here, files can be created, destroyed, rearranged, or organized. You

can also use this window to select which file appears in the editor window.

The I/O window contains all the registers associated with the simulated chip. By

default, this window should automatically be displayed when simulation is run in line-by-line

mode. I/O window in workspace shows an example of what the I/O window looks like during

the lab 1 simulation.

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By expanding this window, additional information is available such as bits and

address of the registers. it is in this window where you can simulate input on the ports. The

node labelled I/O atmega128 contains all the special registers associated with the chip.

By expanding the I/O atmega8515 node, you have access to the ports and

can simulate input or interrupts through them.

The info window displays information about the current chip that is being

simulated. This information contains names and addresses of registers and external pins. it is

a good point of reference when programming for the chip.

6.4 MEMORY WINDOWS

In actuality, all of the registers are actually parts of memory within the

atmega8515. In addition to the register memory, the atmega8515 has several other memory

banks, including the program memory, data memory, and EEPROM memory. of course, no

good simulator is complete without being able to view and/or modify this memory, and AVR

studio 4 is no exception.

To view the memory window, follow the menu command view->memory

window or hit alt+4. The window will pop up on top and can sometimes get in the way. a

good way to organize it is to drag the window down next to the message window at the

bottom and it will slide in right next to it. Expanding the window will also show additional

information.

The main area of the memory window contains three sets of information;

the address of the line in the blue, the data of the memory in hexadecimal format, and the

ASCII equivalent of that data. The pull down menu on the top left allows you to select the

various memory banks available for the atmega8515. To edit the memory, just place the

cursor in the hexadecimal data area and type in the new data.

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6.5 DEBUGGING STRATEGIES

Debugging code can be the most time consuming process in programming.

here are some tips and strategies that can help with this process:

A. Comment, comment, comment. Unless it is absolutely blatantly obvious of what the

code is doing, comment every line of code. Even if the code is obvious, at least

comment what the group of instruction is doing, for example, “initializing stack

pointer”.

B. Pick a format and stick with it. The format is how you lay out your code. a single

programming format will make reading the code a lot easier.

C. Before writing any actual code, write it out in pseudo-code and convince yourself that

it works.

D. Break the code down into small routines and function calls. Small sections of code are

much easier to debug than one huge section of code.

E. Wait loops should be commented out during debugging. The simulator is much

slower than the actual chip and extensive wait loops take up a lot of time.

F. Use breakpoints to halt the simulation at the area known to be buggy. Proper use of

breakpoints can save a lot of time and frustration.

G. Carefully monitor the i/o window and memory windows throughout the simulation.

These windows will indicate any problem.

H. Make sure the AVR instruction is actually supported by the atmega85c35.

I. The atmega85c35 has certain memory ranges; so make sure that when manipulating

data

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CHAPTER 7

CONCLUSION AND FUTURE WORK

7.1 CONCLUSION

The objective of this project that is “AUTOMATED ATTENDANCE USING RFID” was

to design a system based on RFID technology that will not only change the hectic manual

attendance procedure but also automate user’s office. The final design of the project

accomplished the idea of multinode environment which is responsible for automatic

attendance and office automation according to the personalized profile of the RFID card

holder. The design also deals with the issues (reliable data transfer) of multinode

environment. This project facilitates the users in numerous ways like time saving in

attendance procedure, security, employees’ attendance management and many more.

7.2 FUTURE WORKS

With the coming availability of low cost, short range radios along with advances in

wireless networking, it is expected that wireless ad hoc sensor networks will become

commonly deployed. This project can be improvised by using external memory because the

project design has a capability of handling 65000 card IDs which is large enough for any

organization but the limitation lies in the microcontroller storage capacity. This limitation can

be overcome by the use of NVRAM with the reader node which will not only make the design

scalable but also flexible. NVRAM not only provide us extra memory but also enable us to

add cards IDs on the run time

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CHAPTER 8

REFERENCE

INTERNET

1. Moxa Success Story – Attendance Recording System

http://www.moxa.com/solutions/success_stories_Attendance_Recording_System.html

(Accessed on 5th September, 2007)

2. Atmel Corporation, www.atmel.com/products/8051/ (Accessed on 4th

October,2007)

3. Francisco Silva, Victor Filipe and Antnio Pereira. Automatic control of students

attendance in classrooms using RFID. The Third International Conference on Systems

and Networks Communications. Sliema, Malta. 2008.

4. Wikipedia, RFID Radio-frequency identification. URL

http://en.wikipedia.org/wiki/Rfid.

BOOKS

1. Mohammad Ali Mazidi, “The 8051 Microcontroller and Embedded Systems

UsingAssembly and C”, Second Edition, p 28