Automated Design Strategy for High Performance Mixed ...€¦ · IL-PLL DMDLL DPLL MDLL IL-PLL...

Nov. 6. 2015.

Automated Design Strategyfor High PerformanceMixed Signal Circuits

Akira Matsuzawa

Tokyo Institute of Technology

1Contents

• Background and basic strategy for automated design of mixed signal IPs

• Scalable 12bit SAR ADC for versatile uses

• Layout-driven circuit design and automated layout with regularity

• Fully synthesizable PLL IPs like digital logic gates

• Summary

Nov. 6. 2015. ASICON A. Matsuzawa

2

Background and basic strategy for

automated design of mixed signal IPs


3Analog front-end and M/S circuits

Nov. 6. 2015.

Sensor VGA Filter ADC

1) Sensor systems

PLL

ASICON A. Matsuzawa

Chopper(option)

2) Receiver

LNA VGA Filter ADC

Mixer

DACFilterVGAPA

3) TransmitterMixer

Amp.

ADC

DAC

PLL

Analog front-end can be composed with a few types of mixed signal circuits; only ADC, DAC, PLL, Amplifiers (VGA, Filter) .

M/S: Mixed Signal

4Background and Motivation• Issues

It becomes more difficult to obtain good M/S IPs– Insufficient design resources (Designers, Tools)– Insufficient performance– Expensive– Longer development time

• Proposed solutions– Reduce # of M/S IPs A few IPs for versatile uses– Scalable IPs: performance, power, design rule– Reduce the parasitic effect due to layout– Automated layout with regularity centric– Fully synthesizable IPs like digital logic gates


M/S: Mixed Signal

5Selection of the circuits

• Low voltage operation– Addressable with technology scaling

• Small occupied area– Reducible with technology scaling

• Low power– Scalable with performance

• Regularity in layout pattern• Error can be compensated with digital method


Select the circuits for high performance automated design

6

Scalable 12bit SAR ADC

for versatile uses


7

Nov. 6. 2015.

Scalable ADC

BWSNRSNR log100

)log(10140)( BWdBSNR

sd fP

1

10

100

0.1 1 10 100BW [MHz]

SDCT SDSC VCOISSCC 2008-2013VLSI Symp. 2008-2012

Pow

er d

issi

patio

n (m

W)

BWKPd 1 K1: 0.2 -- 3 (mW/MHz)

Matsuzawa, A. “Digitally-Assisted Analog and RF CMOS Circuit Design for Software-Defined Radio,” Chapter 7, Springer 2011.

SNR should be increased by the reduction of BWPd should be minimized and reduced by the reduction of BW.

50

60

70

80

90

0.1 1 10 100

SDCT SDSC VCO

135dB

143dB

150dB

BW (MHz)

SNR

(dB)

SNR0

ASICON A. Matsuzawa

ADCs for wireless

Many ADCs to cover the almost all wireless communications.

8SAR ADC： ADC for versatile use

12

14

18

12

14 Comp.

Nov. 6. 2015.

SAR ADC is the most energy efficient ADC.It can be used for versatile applications.Conversion errors can be suppressed digitally.

Logic Comp CDAC

12bit, 65nmCMOS, 0.03mm2

S. Lee, A. Matsuzawa, SSDM 2013

Parasitic CAL.Mismatch CAL.

ASICON A. Matsuzawa

9

0.5

0.6

0.7

0.8

0.91

2

3

50 60 70 80 90 100 200

MOM capacitor

MIM capacitor

Design rule (nm)

Den

sity

(fF/

um2 )

Use of MOM capacitor

MOM capacitor


MOM capacitor uses the capacitance between the lateral interconnection.The capacitor density can be increased by technology scaling.Smaller occupied area (same C) can be expected by technology scaling.Furthermore, parasitic capacitance can be controlled.

10

Output

VDDCLK

Vin+For CAL

Vin-

M1 M2

CL CL

ID ID

Dynamic amplifier Latch

Dynamic comparator

N1a N1b

N2a N2b

N3a

N3b

N2

N1

N3a

N3b

VDD

GND

M. Miyahara, Y. Asada, D. Paik, and A. Matsuzawa, "A Low-Noise Self-Calibrating Dynamic Comparator for High-Speed ADCs," A-SSCC, Nov. 2008.

Yusuke Asada, Kei Yoshihara, Tatsuya Urano, Masaya Miyahara, and Akira Matsuzawa, "A 6bit, 7mW, 250fJ, 700MS/s Subranging ADC," A-SSCC, 5-3, pp. 141-144, Taiwan, Taipei, Nov. 2009.


Dynamic comparator doesn't consume any static power.Large noise was an issue, however can be improved by our proposedcircuit using CMOS inter-stage amplifier.

11Intermitted operation by self-clocking

Nov. 6. 2015.

Sampling

Power off

Conversion period

Conversion

End flag

Power on

2ns

12ns: 1.2V18ns: 1.0V

dsd EfP

ASICON A. Matsuzawa

Successive comparison is started after the sampling period and ended at 12 conversions. Pd is proportional to the sampling frequency. The leakage current can be blocked by using power gating.

12Scalable power dissipation

Nov. 6. 2015.

50MSps: 2mW5MSps: 200uW500KSps: 20uW50KSps: 2uW5kSps: 0.2uW

S. Lee, A. Matsuzawa, et al., SSDM 2013

ASICON A. Matsuzawa

Pd is completely proportional to the sampling frequency.Therefore an ultra-low power is possible at low speed operation.Further low power is possible by using low voltage operation.

Suitable for the versatile uses; wireless and sensor

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

0 10 20 30 40 50 60 70 80

Pow

er d

issi

patio

n [m

W]

Sampling frequency [MHz]

1.2V1.0V0.8V

13Performance comparison

Nov. 6. 2015.

[3] W. Liu, P. Huang, Y. Chiu, ISSCC, pp. 380-381, Feb. 2010.[4] T. Morie, et al., ISSCC, pp.272-273, Feb. 2013.

・ Highest conversion rate：70MSps・ Lowest voltage：0.8V・ Lowest Pd：2.2mW at 50MSps・ Smallest FoM：28fJ・ Smallest area：0.03mm2 12bit SAR ADCs

[3] [4]

Resolution　(bit) 12 12

VDD (V) 0.8 1 1.2 1.2 1.2

fsample (MHz) 30 50 70 45 50

Pd (mW) 0.8 2.2 4.6 3 4.2

SNDR (dB) 62 64 65 67 71

FoM (fJ) Nyq/DC 81/28 62/33 100/45 36/31 36/29

Technology (nm) 130 90

Occupied area(mm2) 0.06 0.1

This work

12

65

0.03

S. Lee, A. Matsuzawa, et al., SSDM 2013.

ASICON A. Matsuzawa

14Performance scalable ADC

Nov. 6. 2015.

50

60

70

80

90

0.1 1 10 100

SNR

[dB

]

BW [MHz]

SDCT SDSC VCO

135dB

143dB

150dB

ISSCC 2008-2013VLSI Symp. 2008-2012

SAR ADC w/ OVS

Interleaving

Over sampling

1V, 50MSps Operation

1

10

100

0.1 1 10 100BW [MHz]

SDCT SDSC VCOISSCC 2008-2013VLSI Symp. 2008-2012

This ADC

Over sampling OptimizedP

ower

dis

sipa

tion

(mW

)

S. Lee, A. Matsuzawa, et al., SSDM 2013

ASICON A. Matsuzawa

SNR can be increased up to 78 dB by reducing BW.Smallest Pd among ADCs for wireless communications.

84 dB will be attained by dither and DEM method.SNR0 is 140 dB and it can be increased.

15


Layout-driven circuit design

and automated layout with regularity

16Conventional idea for analog IP design

Place the componentsRoute wires between them


17

MSB

Top

Plat

e

Parasitic cap. (3.5fF)

Issue of conventional idea for analog design

23C

VrefGND

VX

B7

23CC

B8 B11

2C Layout of CDAC

CDAC


Parasitic capacitance (3.5 fF)Between top prate and bottom platesCauses large conversion error of 50 LSB(12 bit).

A conventional idea of Place the components and Route themcauses parasitic components essentially and it results in performancedegradation.

18

Nov. 6. 2015.

Layout driven design with regularity

ASICON A. Matsuzawa

Avoid wires between componentsWire itself is the componentRespect the regularity and Pitch should be aligned

Furthermore, if layout has a regularity,Layout programming becomes easier

19Ideal layout design

Nov. 6. 2015.

SAR ADC

ASICON A. Matsuzawa

Pitch is aligned.It minimizes parasitic component , wire length, delay and capacitance.Low power, high speed, small area, and high robustness can be realized.

20Synthesized layout

Nov. 6. 2015.

RDAC circuit

RDAC layout composed by the programming in skill language

Automated optimizationAutomated layout with SKILL language

ASICON A. Matsuzawa

We can synthesize analog layout by programming

Digital circuits

Analog circuits

21


Design flow for mixed signal IP synthesis

Specification Process info（ＰＤＫ）

Automated layout programmed in Skill language

CKT Schematics GDS Symbol

Automated design for circuit and layout

Add digital CAL and TEST circuits +

Optimization of parameters

22

Nov. 6. 2015.

Circuit schematic and layout

PMOS PMOSNMOSNMOS

ASICON A. Matsuzawa

Logic gates should have regularity and launch the automated layout.

23

Nov. 6. 2015.

Align the layout pitch

ASICON A. Matsuzawa

Logic gates, DFFs, switches, and resistors are aligned

2412 bit R-DAC with automated design


(a)(b)

Simulated DNL and INL (a) without LPE, and (b) with LPE.

Small 12b R-DAC can be composed by programming in Skill

65nm CMOS

25LC VCO with MOM capacitor bank


0 128 256 384 5123.2833.2843.2853.2863.2873.2883.2893.29

3.291

Fine Tune Code Df[8:0]

Freq

uenc

y (G

Hz)

Dc[1:0]=00Dc[1:0]=01Dc[1:0]=10Dc[1:0]=11

1k 10k 100k 1M 10M-140

-120

-100

-80

-60

-40-20

foffset (Hz)

Phas

e no

ise

(dB

c/H

z)65nm CMOSLC VCO

MOM capacitancePhase noiseFine tuning

18bit LC [email protected]

-121 dBc at 1MHz

18bit LC VCO without varactors has been developedwith MOM capacitors using by programed layout method

Z. Xu, A. Matsuzawa, SSDM 2014.

26


Fully synthesizable PLL IPs

like digital logic gates

27Small, low jitter, and low power PLL for SoC

Nov. 6. 2015.

This work [1] [2] [5]IL-PLL DMDLL DPLL MDLL IL-PLL

Freq. [GHz] 1.2(0.5-1.6)1.5

(0.8-1.8)1.5

(0.8-1.8) 1.6 0.216

Ref. [MHz] 300(40-300) 375 375 50 27

Power [mW] 0.97 0.89 1.35 12 6.9Area [mm2] 0.022 0.25 0.25 0.058 0.03

Integ. Jitter [ps] 0.7 0.4 3.2 0.68 2.4Jitter RMS/PP

[ps]1.81/19.410M hits

0.92/9.25M hits

4.2/335M hits

0.93/11.130M hits N.A.

FOM [dB] -243 -248.46 -228.59 -233.76 -225

CMOS Tech. 65nm 130nm 130nm 130nm 55nm

IL VCO Comparison

Tj=1.8ps, 1.0 mW, 0.02mm2 Automated circuit and layout design is possible.

W. Deng, K. Okada, A. Matsuzawa,ISSCC 2013

ASICON A. Matsuzawa

Small, low jitter, and low power PLL for SoC by using inject locking.

28Injection-locked Ring Oscillator

Injection

Delay Cell

Delay Cell

Delay Cell

DAC DAC DAC

Vout

VInj

Differential ring VCO with injection locking

W. Deng. ISSCC 2013

April 21, 2015 UMC Matsuzawa

29Effect of the injection locking

Free Run

Locked

Offset Frequency [Hz]

Phas

e N

oise

[dB

c/H

z]

10k 100k 1M 10M

-120

-80

-40

0

Ref.: 300MHz (40MHz-300MHz) Freq.: 1.2GHz (0.5-1.6GHz)Integrated jitter: 0.7ps (10kHz-40MHz) Pdc: 0.97mW (1.2GHz)

1.08GHz 1.32GHz

1.199GHz 1.201GHz

-40dBc/Hz

Phase noise is reduced so muchby the injection locking


30Automated design

Verilog netlist(gate-level)

Verilog RTL

Verilog netlist(gate-level)

DCO DAC

Logic

Logic

Logic Synt. Tool

GDSII

P&R Tool

Netlist


Automated design is possible like digital circuits with HDL.

31Results

70m

DCO DCO

Hierarchical P&R with synthesized DCOs

130 m

60m

110 m

Fully synthesized

Integrating Jitter: 1.7psPDC: 780W

FOM: -236.5 dB

Integrating Jitter: 2.32psPDC: 640W

FOM: -234.6 dB

DCO DCO

W. Deng, K. Okada, A. Matsuzawa,ISSCC 2014.

W. Deng, K. Okada, A. Matsuzawa,ISSCC 2013


Low jitter, low power, and small area PLL can be realizedwith full automated design

32Performance ComparisonLow FoM and Small area Synthesizable PLL has been developed.


33Proposed M/S IP design and business

Nov. 6. 2015.

Users IPCompany

Engineer

Input the specification

Circuit schematicLayout GDSSimulation results

On the Web

RDAC：CompletedCDAC：CompletedSAR ADC：Almost completedOP Amp・Filter： will be developed PLL： under developing

Status

ASICON A. Matsuzawa

Circuits designProgram

Circuits should be synthesized automatically.Users can obtain M/S IPs immediately with less money.No limitation for # of design requests

34Summary

April 21, 2015

• IssuesIt becomes more difficult to obtain good mixed signal IPs

• Proposed solutions– A few mixed signal IPs for versatile uses

Ex: Scalable 12b SAR ADC for versatile use– Regularity driven analog layout

• Avoid wires between components by using wires as a component• Respect the regularity and pitch should be aligned

– Developed the synthesizable mixed signal IPs programmed in Skill language

– Developed synthesizable full automated PLL using injection locking, like digital logic design

– It may create a new IP business model?UMC Matsuzawa

35


Backup slides

36Coarse Tuning using DAC

DACn

Coarse tuning is made by current control

37Proposed I-linear DAC

• A feedback for forming a current mirror.

D0

D1

D2

D3

1

1

Iout

×1

×2

×4

×8

38Tuning Capacitors

0.4 pS

Time [pS]

4.8 pS

0 10 20 30 0 10 20 30Time[ps]

0 10 20 30Time[ps]

V in[

V]

VDD

V in[

V]

VDD

4.8ps0.4ps

Vin

DM=1DM=0DF=0DF=1

Vin

(0.066ps×6)

(Proposed)

39High precision Time to Digital Converter

Nov. 6. 2015.

0 32 64 96 128 160 192 224 256

-1

0

1

DNL and INL in 8-bit with 0.84ps/LSB

DN

L [L

SB]

0 32 64 96 128 160 192 224 256

-2

0

2

Code

INL

[LSB

]

Resolution of conventional inverter based TDC is 10 ps at most.

0.8ps, 10bit, 100Msps, 4mW, 0.02mm2 Z. Xu, A. Matsuzawa, CICC 2013.

ASICON A. Matsuzawa

Charge pump + SAR ADC realizes sub-ps (0.8 ps) TDC

Low phase noise fractional PLLOn-chip jitter measurementSub-mm laser radar

0.8ps, 10bit, 100Msps, 4mW, 0.02mm2

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