Automated FPGA Layout

Ian Kuon

Work done in conjunction with Aaron Egier, Ketan Padalia, Ryan Fung, Mark Bourgeault

Supervised by Jonathan Rose

Challenge

Making ASICs is hard That’s why we use FPGAs!

Making FPGAs is even harder

>50 person-years for a new FPGA

NetlistGenerator

Placer &Router

FinalAssembly

ArchitectureDescription

# Logic block parameterssubblocks_per_clb 1 # 1 BLE per logic clustersubblock_lut_size 4 # 4-input LUTs

# Logic block inputs and outputsinpin class: 0 bottominpin class: 0 leftinpin class: 0 topinpin class: 0 rightoutpin class: 1 bottom # Logic block outputinpin class: 2 global left # Clock input

# Connection block flexibilitiesFc_type fractional # Specified as fractional number of tracksFc_input 0.5625 # Flexibility of input connection blockFc_output 1 # Flexibility of output connection blockFc_pad 1 # Flexibility of I/O pads

# Switch typesswitch 0 buffered: no ...switch 1 buffered: yes ...

# Length 4 routing tracks, half bufferedsegment frequency: 0.5 length: 4 wire_switch: 0 ...segment frequency: 0.5 length: 4 wire_switch: 1 ...

The GILES CAD Flow

Summary Chip made in 0.18

um process 358,374 transistors

Significant time savings 34 person-weeks

vs. > 50 person-years

Future Directions Further automate FPGA design

Transistor sizing

LUTQ

QSET

CLR

D

Q

QSET

CLR

D