Automatic Test Pattern Generation · PDF fileSimple Illustration of ATPG • Consider the...

Automatic Test

Pattern Generation

Testing of VLSI Design

Usha Mehta

Acknowledge

• This presentation has been summarized from

various books, papers, websites and presentations

on VLSI Design and its various topics all over the

world. I couldn’t itemwise mention from where

these large pull of hints and work come. However,

I’d like to thank all professors and scientists who

created such a good work on this emerging field.

Without those efforts in this very emerging

technology, these notes and slides can’t be

finished.

01-04-2015 Dr Usha Mehta 2

Simple Illustration of ATPG

• Consider the fault d/1 in the defective circuit

• Need to distinguish the output of the defective

circuit from the defect-free circuit

• Need: set d=0 in the defect-free circuit

• Need: propagate effect of fault to output

• Vector: abc=001 (output = 0/1)



• Instead of using two circuits (fault-free and

the faulty)

• We will solve the ATPG problem on one

single circuit

• To do so, every signal value must be able to

capture fault-free and faulty values

simultaneously

• 5-Value Algebra: 0, 1, X, D, D-bar

– D: 1/0 fault free/faulty

– D-bar: 0/1


Notations….

• For fault to be detected, the corresponding output of the circuit

should be different in case of circuit is faulty and faultfree.


Boolean Algebra on 5-Valued Logic


Basic ATPG Algorithm

Path Sensitization Method

• Initialize all inputs with X

• Activate the fault s-a-v by justifying

the line to value v’

• Propagate the fault effect ot PO


Fault Excitation

• Fault excitation – the signal value at the fault site

must be different from the value of the stuck-at

fault (thus fault site must contain a D or a D’)

• Propagation: The fault effect must be propagated to

a primary output (a D or a D’ must appear at the

output)

• Some simple observations

– There must be at least a D or a D on some

circuit nets)

– Ds must form a chain to some output


Justify


Propagate


Controlling and Inversion Value

• Controlling value for AND and NAND

is 0 while for OR and NOR, it is 1

• Inversion value for NOT, NOR and

NAND is 1 while for ND and OR, it is 0


One example…..


Contd.


Contd.


Contd.


Algorithm for Combinational ATPG



contd.



contd.



contd.


Decision Procedure

• For ATPG Algorithm, the decisions are

to be taken for

– To select the fault for consideration from

the given list of faults

– For the fault under consideration, to

select the path during propagation and

justification


Selection of fault

Selection of path for Justification and Propagation

• So you have list of faults

– I hope you have generated it by your own

EDA tools for fault list generation and

reduction using fault equivalence….

• Which fault to choose from list?

– Randomly?

– With some selection criteria?


Easy/Hard heuristic

• If many choices to meet an objective, and

satisfaction of any one of the choices will

satisfy the objective

• choose the easiest one first

• If all conditions must be satisfied to meet

the desired objective,

• choose the hardest one first


Which fault to pick next

• Target to generate tests for easy faults first

– Hard faults may get detected with no extra effort

• Target to generate tests for hard faults first

– Easy faults will be detected any way, why waste time

• Anytime a fault is detected, there is a chance that the test vector detects a lot more faults.


Which fault is easy/hard?

• The fault is easy or hard based on • difficulty involved in setting the corresponding

– inputs to specific values (controlling the inputs)

– Checking the outputs for correctness (observing the

output)

Easy/hard can be determined

–Distance from PIs and POs

–Testability measures


Testability Measures

• Analysis of difficulty of testing internal

circuit parts –redesign or add special

test hardware

• Guidance for algorithms computing

test patterns – avoid using hard-to-

control lines

• Estimation of fault coverage

• Estimation of test vector length


Sandia Controllability and Observability Analysis

Program (SCOAP)

• Involves Circuit Topological analysis,

but no test vectors and no search

algorithm

• Static analysis

• Linear computational complexity

– Otherwise, is pointless – might as well

use automatic test-pattern generation

and calculate: Exact fault coverage and

Exact test vectors


• Combinational measures:

– CC0 – Difficulty of setting circuit line to logic 0

– CC1 – Difficulty of setting circuit line to logic 1

– CO – Difficulty of observing a circuit line

• Sequential measures – analogous:

– SC0

– SC1

– SO


• Controllabilities – 1 (easiest) to infinity (hardest)

• Observabilities – 0 (easiest) to infinity (hardest)

• Combinational measures:

– Roughly proportional to # circuit lines that must

be set to control or observe given line

• Sequential measures:

– Roughly proportional to # times a flip-flop must

be clocked to control or observe given line


Controllability


Observability


Develop your own ATPG

• Algorithms …..

• Run by computing machines….

• What can be inputs to algorithm?……

• And outputs…….

– Netlist

– Fault list

– Test set


Future Scope

• This tool can be further developed with higher fanout branches and fan in for gates capabilities.

• It can further accommodate the XOR, XNOR types of gates also.

• When there is a contradiction for reconvergent fan out, it chooses the second option based on nearby controllability value. With this if still the problem is not solved, such faults can be referred to advanced ATPGs.

• For that link to those tools can be applied. Or fault coverage loss because of such case can be calculated. Based on list of test vectors generated, test compaction can be applied.


Thanks!


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