AVR Microcontroller with Core Independent...

ATmega48PB/88PB/168PB AVR Microcontroller with Core Independent Peripherals

and PicoPower technology

Introduction

ATmega48PB/88PB/168PB is a low-power CMOS 8-bit microcontroller based on the AVR® enhancedRISC architecture. By executing powerful instructions in a single clock cycle, the ATmega48PB/88PB/168PB achieves throughputs approaching 1MIPS/MHz, allowing the system designer to optimize powerconsumption versus processing speed.

Features

• Advanced RISC architecture– 131 instructions – most single clock cycle execution– 32 x 8 general purpose working registers– Fully static operation– Up to 20MIPS throughput at 20MHz– On-chip 2-cycle Multiplier

• High endurance non-volatile memory segments– 4/8/16KBytes of in-system self-programmable Flash program memory– 256/512/512Bytes EEPROM– 512/1K/1KBytes internal SRAM– Write/Erase cycles: 10,000 Flash/100,000 EEPROM– Data retention: 20 years at 85°C/100 years at 25°C– Optional boot code section with independent lock bits

• In-system programming by on-chip boot program

• True Read-While-Write (RWW) operation– Programming lock for software security

• QTouch® library support– Capacitive touch buttons, sliders and wheels– QTouch and QMatrix® acquisition– Up to 64 sense channels

• Peripheral Features– Two 8-bit Timer/Counters (TC) with separate prescaler and compare mode– 16-bit Timer/Counter with separate prescaler, compare mode, and capture mode– Real Time Counter (RTC) with separate oscillator– Six Pulse Width Modulation (PWM) channels– 8-channel 10-bit Analog-to-Digital converter (ADC) with temperature measurement– Programmable serial USART with start-of-frame detection

© 2017 Microchip Technology Inc. Datasheet Complete DS40001909A-page 1

– Master/Slave Serial Interface (SPI)– Byte-oriented Two-Wire serial Interface (TWI), Philips I2C compatible– Programmable Watchdog Timer (WDT) with separate on-chip oscillator– On-chip Analog Comparator (AC)– Interrupt and Wake-up on pin change

• 256-channel capacitive touch and proximity sensing• Special microcontroller features

– Power-On Reset (POR) and programmable brown-out detection (BOD)– Internal calibrated oscillator– External and internal interrupt sources– Six Sleep Modes: Idle, ADC Noise Reduction, Power-Save, Power-Down, Standby, and Extended

Standby– Unique device ID

• I/O– 27 programmable I/O pins

• Packages– 32-pin TQFP, VFQFN

• Operating voltage– 1.8V – 5.5V

• Temperature range– -40°C to 105°C

• Speed grades– 0 - 4MHz at 1.8-5.5V– 0 - 10MHz at 2.7-5.5.V– 0 - 20MHz at 4.5-5.5V

• Power consumption at 1MHz, 1.8V, 25°C– Active mode: 0.35mA– Power-down mode: 0.23μA– Power-save mode:

Table of Contents

Introduction......................................................................................................................1

Features.......................................................................................................................... 1

1. Description.................................................................................................................9

2. Configuration Summary...........................................................................................10

3. Ordering Information................................................................................................113.1. ATmega48PB..............................................................................................................................113.2. ATmega88PB..............................................................................................................................113.3. ATmega168PB .......................................................................................................................... 12

4. Block Diagram......................................................................................................... 13

5. Pin Configurations................................................................................................... 145.1. Pin Descriptions......................................................................................................................... 15

6. I/O Multiplexing........................................................................................................18

7. Comparison Between Processors........................................................................... 19

8. Resources............................................................................................................... 20

9. Data Retention.........................................................................................................21

10. About Code Examples.............................................................................................22

11. Capacitive Touch Sensing....................................................................................... 2311.1. QTouch Library...........................................................................................................................23

12. AVR CPU Core........................................................................................................ 2412.1. Overview.................................................................................................................................... 2412.2. ALU – Arithmetic Logic Unit....................................................................................................... 2512.3. Status Register...........................................................................................................................2512.4. General Purpose Register File...................................................................................................2712.5. Stack Pointer..............................................................................................................................2812.6. Instruction Execution Timing...................................................................................................... 2912.7. Reset and Interrupt Handling..................................................................................................... 30

13. AVR Memories.........................................................................................................3213.1. Overview.................................................................................................................................... 3213.2. In-System Reprogrammable Flash Program Memory................................................................3213.3. SRAM Data Memory.................................................................................................................. 3313.4. EEPROM Data Memory............................................................................................................. 3513.5. I/O Memory.................................................................................................................................3613.6. Register Description...................................................................................................................36


14. System Clock and Clock Options............................................................................ 4314.1. Clock Systems and Their Distribution........................................................................................ 4314.2. Clock Sources............................................................................................................................ 4414.3. Low Power Crystal Oscillator..................................................................................................... 4614.4. Low Frequency Crystal Oscillator...............................................................................................4714.5. Calibrated Internal RC Oscillator................................................................................................4914.6. 128kHz Internal Oscillator.......................................................................................................... 5014.7. External Clock............................................................................................................................ 5014.8. Clock Output Buffer.................................................................................................................... 5114.9. Timer/Counter Oscillator.............................................................................................................5114.10. System Clock Prescaler.............................................................................................................5214.11. Register Description...................................................................................................................52

15. PM - Power Management and Sleep Modes...........................................................5515.1. Sleep Modes.............................................................................................................................. 5515.2. BOD Disable...............................................................................................................................5515.3. Idle Mode....................................................................................................................................5615.4. ADC Noise Reduction Mode...................................................................................................... 5615.5. Power-Down Mode.....................................................................................................................5715.6. Power-Save Mode......................................................................................................................5715.7. Standby Mode............................................................................................................................ 5715.8. Extended Standby Mode............................................................................................................5815.9. Power Reduction Register..........................................................................................................5815.10. Minimizing Power Consumption.................................................................................................5815.11. Register Description...................................................................................................................59

16. SCRST - System Control and Reset....................................................................... 6416.1. Resetting the AVR...................................................................................................................... 6416.2. Reset Sources............................................................................................................................6416.3. Power-on Reset..........................................................................................................................6416.4. External Reset............................................................................................................................6516.5. Brown-out Detection...................................................................................................................6616.6. Watchdog System Reset............................................................................................................6616.7. Internal Voltage Reference.........................................................................................................6716.8. Watchdog Timer......................................................................................................................... 6716.9. Register Description...................................................................................................................69

17. Interrupts................................................................................................................. 7317.1. Interrupt Vectors in ATmega48PB.............................................................................................. 7317.2. Interrupt Vectors in ATmega88PB.............................................................................................. 7517.3. Interrupt Vectors in ATmega168PB............................................................................................ 8017.4. Register Description...................................................................................................................85

18. EXINT - External Interrupts..................................................................................... 8718.1. Pin Change Interrupt Timing.......................................................................................................8718.2. Register Description...................................................................................................................88

19. I/O-Ports.................................................................................................................. 94

ATmega48PB/88PB/168PB


19.1. Overview.................................................................................................................................... 9419.2. Ports as General Digital I/O........................................................................................................9519.3. Alternate Port Functions.............................................................................................................9819.4. Register Description..................................................................................................................111

20. TC0 - 8-bit Timer/Counter0 with PWM...................................................................11920.1. Features................................................................................................................................... 11920.2. Overview...................................................................................................................................11920.3. Timer/Counter Clock Sources.................................................................................................. 12120.4. Counter Unit............................................................................................................................. 12120.5. Output Compare Unit............................................................................................................... 12220.6. Compare Match Output Unit.....................................................................................................12420.7. Modes of Operation..................................................................................................................12520.8. Timer/Counter Timing Diagrams.............................................................................................. 12920.9. Register Description.................................................................................................................131

21. TC1 - 16-bit Timer/Counter1 with PWM.................................................................14021.1. Features................................................................................................................................... 14021.2. Overview.................................................................................................................................. 14021.3. Accessing 16-bit Timer/Counter Registers...............................................................................14121.4. Timer/Counter Clock Sources.................................................................................................. 14421.5. Counter Unit............................................................................................................................. 14421.6. Input Capture Unit.................................................................................................................... 14521.7. Output Compare Units..............................................................................................................14721.8. Compare Match Output Unit.....................................................................................................14921.9. Modes of Operation..................................................................................................................15021.10. Timer/Counter Timing Diagrams.............................................................................................. 15821.11. Register Description.................................................................................................................160

22. Timer/Counter 0, 1 Prescalers...............................................................................16922.1. Internal Clock Source...............................................................................................................16922.2. Prescaler Reset........................................................................................................................16922.3. External Clock Source..............................................................................................................16922.4. Register Description.................................................................................................................170

23. TC2 - 8-bit Timer/Counter2 with PWM and Asynchronous Operation...................17223.1. Features................................................................................................................................... 17223.2. Overview.................................................................................................................................. 17223.3. Timer/Counter Clock Sources.................................................................................................. 17423.4. Counter Unit............................................................................................................................. 17423.5. Output Compare Unit............................................................................................................... 17523.6. Compare Match Output Unit.....................................................................................................17723.7. Modes of Operation..................................................................................................................17823.8. Timer/Counter Timing Diagrams.............................................................................................. 18223.9. Asynchronous Operation of Timer/Counter2............................................................................18323.10. Timer/Counter Prescaler.......................................................................................................... 18523.11. Register Description.................................................................................................................185

24. SPI – Serial Peripheral Interface........................................................................... 195



24.1. Features................................................................................................................................... 19524.2. Overview.................................................................................................................................. 19524.3. SS Pin Functionality................................................................................................................. 19924.4. Data Modes..............................................................................................................................19924.5. Register Description.................................................................................................................200

25. USART - Universal Synchronous Asynchronous Receiver Transceiver................20425.1. Features................................................................................................................................... 20425.2. Overview.................................................................................................................................. 20425.3. Clock Generation......................................................................................................................20425.4. Frame Formats.........................................................................................................................20725.5. USART Initialization................................................................................................................. 20825.6. Data Transmission – The USART Transmitter......................................................................... 20925.7. Data Reception – The USART Receiver.................................................................................. 21125.8. Asynchronous Data Reception.................................................................................................21425.9. Multi-Processor Communication Mode.................................................................................... 21825.10. Examples of Baud Rate Setting............................................................................................... 21925.11. Register Description.................................................................................................................222

26. USARTSPI - USART in SPI Mode.........................................................................23026.1. Features................................................................................................................................... 23026.2. Overview.................................................................................................................................. 23026.3. Clock Generation......................................................................................................................23026.4. SPI Data Modes and Timing.....................................................................................................23126.5. Frame Formats.........................................................................................................................23126.6. Data Transfer............................................................................................................................23326.7. AVR USART MSPIM vs. AVR SPI............................................................................................23426.8. Register Description.................................................................................................................235

27. TWI - 2-wire Serial Interface..................................................................................23627.1. Features................................................................................................................................... 23627.2. Two-Wire Serial Interface Bus Definition..................................................................................23627.3. Data Transfer and Frame Format.............................................................................................23727.4. Multi-master Bus Systems, Arbitration, and Synchronization...................................................24027.5. Overview of the TWI Module....................................................................................................24227.6. Using the TWI...........................................................................................................................24427.7. Transmission Modes................................................................................................................ 24727.8. Multi-master Systems and Arbitration...................................................................................... 26427.9. Register Description.................................................................................................................266

28. AC - Analog Comparator....................................................................................... 27128.1. Overview.................................................................................................................................. 27128.2. Analog Comparator Multiplexed Input......................................................................................27128.3. Register Description.................................................................................................................272

29. ADC - Analog to Digital Converter.........................................................................27629.1. Features................................................................................................................................... 27629.2. Overview.................................................................................................................................. 27629.3. Starting a Conversion...............................................................................................................278



29.4. Prescaling and Conversion Timing...........................................................................................27929.5. Changing Channel or Reference Selection..............................................................................28129.6. ADC Noise Canceler................................................................................................................ 28329.7. ADC Conversion Result........................................................................................................... 28629.8. Temperature Measurement...................................................................................................... 28729.9. Register Description.................................................................................................................287

30. DBG - debugWIRE On-chip Debug System.......................................................... 29430.1. Features................................................................................................................................... 29430.2. Overview.................................................................................................................................. 29430.3. Physical Interface.....................................................................................................................29430.4. Software Break Points..............................................................................................................29530.5. Limitations of debugWIRE........................................................................................................29530.6. Register Description.................................................................................................................295

31. Self-Programming the Flash..................................................................................29731.1. Overview.................................................................................................................................. 29731.2. Addressing the Flash During Self-Programming......................................................................29831.3. Register Description.................................................................................................................303

32. BTLDR - Boot Loader Support – Read-While-Write Self-Programming................ 30632.1. Features................................................................................................................................... 30632.2. Overview.................................................................................................................................. 30632.3. Application and Boot Loader Flash Sections............................................................................30632.4. Read-While-Write and No Read-While-Write Flash Sections...................................................30732.5. Boot Loader Lock Bits.............................................................................................................. 30932.6. Entering the Boot Loader Program...........................................................................................31032.7. Addressing the Flash During Self-Programming...................................................................... 31132.8. Self-Programming the Flash.....................................................................................................31232.9. Register Description.................................................................................................................321

33. MEMPROG- Memory Programming......................................................................32333.1. Program And Data Memory Lock Bits......................................................................................32333.2. Fuse Bits.................................................................................................................................. 32433.3. Signature Bytes........................................................................................................................32733.4. Calibration Byte........................................................................................................................32733.5. Page Size.................................................................................................................................32733.6. Parallel Programming Parameters, Pin Mapping, and Commands..........................................32833.7. Parallel Programming...............................................................................................................33033.8. Serial Downloading.................................................................................................................. 337

34. Electrical Characteristics....................................................................................... 34234.1. Absolute Maximum Ratings......................................................................................................34234.2. DC Characteristics................................................................................................................... 34234.3. Speed Grades.......................................................................................................................... 34634.4. Clock Characteristics................................................................................................................34634.5. System and Reset Characteristics........................................................................................... 34734.6. SPI Timing Characteristics....................................................................................................... 34834.7. Two-wire Serial Interface Characteristics.................................................................................349



34.8. ADC Characteristics.................................................................................................................35134.9. Parallel Programming Characteristics......................................................................................352

35. Typical Characteristics...........................................................................................35535.1. ATmega48PB/88PB Typical Characteristics............................................................................ 35535.2. ATmega168PB Typical Characteristics.................................................................................... 372

36. Register Summary.................................................................................................395

37. Instruction Set Summary....................................................................................... 398

38. Packaging Information...........................................................................................40238.1. 32-pin 32A................................................................................................................................40238.2. 32-pin 32MS1...........................................................................................................................403

39. Errata.....................................................................................................................40439.1. Errata ATmega48PB................................................................................................................ 40439.2. Errata ATmega88PB................................................................................................................ 40539.3. Errata ATmega168PB.............................................................................................................. 407

40. Datasheet Revision History................................................................................... 41040.1. Rev. DS40001909A – 05/2017.................................................................................................41040.2. Rev. 42176G – 03/2016........................................................................................................... 41040.3. Rev. 42176F – 02/2016............................................................................................................ 41040.4. Rev. 42176E – 10/2015............................................................................................................41040.5. Rev. 42176D – 04/2015............................................................................................................41140.6. Rev. 42176C – 03/2015............................................................................................................41140.7. Rev. 42176B – 11/2014............................................................................................................ 41140.8. Rev. 42176A - 11/2014.............................................................................................................412

The Microchip Web Site.............................................................................................. 413

Customer Change Notification Service........................................................................413

Customer Support....................................................................................................... 413

Microchip Devices Code Protection Feature............................................................... 413

Legal Notice.................................................................................................................414

Trademarks................................................................................................................. 414

Quality Management System Certified by DNV...........................................................415

Worldwide Sales and Service......................................................................................416



1. DescriptionThe AVR core combines a rich instruction set with 32 general purpose working registers. All the 32registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers tobe accessed in one single instruction executed in one clock cycle. The resulting architecture is more codeefficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.

The ATmega48PB/88PB/168PB provides the following features: 4/8/16Kbytes of In-SystemProgrammable Flash with Read-While-Write capabilities, 256/512/512 bytes EEPROM, 512/1K/1KbytesSRAM, 27 general purpose I/O lines, 32 general purpose working registers, three flexible Timer/Counterswith compare modes, internal and external interrupts, a serial programmable USART, a byte-oriented 2-wire Serial Interface (I²C), an SPI serial port, a 6-channel 10-bit ADC (8 channels in TQFP and VFQFNpackages), a programmable Watchdog Timer with internal Oscillator, and six software selectable powersaving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, USART, 2-wireSerial Interface, SPI port, and interrupt system to continue functioning. The Power-down mode saves theregister contents but freezes the Oscillator, disabling all other chip functions until the next interrupt orhardware reset. In Power-save mode, the asynchronous timer continues to run, allowing the user tomaintain a timer base while the rest of the device is sleeping. The ADC Noise Reduction mode stops theCPU and all I/O modules except asynchronous timer and ADC, to minimize switching noise during ADCconversions. In Standby mode, the crystal/resonator Oscillator is running while the rest of the device issleeping. This allows very fast start-up combined with low power consumption.

It offers the QTouch® library for embedding capacitive touch buttons, sliders and wheels functionality intoAVR microcontrollers. The patented charge-transfer signal acquisition offers robust sensing and includesfully debounced reporting of touch keys and includes Adjacent Key Suppression® (AKS®) technology forunambiguous detection of key events. The easy-to-use QTouch Composer allows programers to explore,develop and debug the their touch applications.

The device is manufactured using high density non-volatile memory technology. The On-chip ISP Flashallows the program memory to be reprogrammed In-System through an SPI serial interface, by aconventional nonvolatile memory programmer, or by an On-chip Boot program running on the AVR core.The Boot program can use any interface to download the application program in the Application Flashmemory. Software in the Boot Flash section will continue to run while the Application Flash section isupdated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-SystemSelf-Programmable Flash on a monolithic chip, the ATmega48PB/88PB/168PB is a powerfulmicrocontroller that provides a highly flexible and cost effective solution to many embedded controlapplications.

The ATmega48PB/88PB/168PB is supported with a full suite of program and system development toolsincluding: C Compilers, Macro Assemblers, Program Debugger/Simulators, and Evaluation kits.



2. Configuration SummaryTable 2-1. Configuration Summary

ATmega48PB ATmega88PB ATmega168PB

Pin count 32 32 32

Flash (KB) 4 8 16

SRAM (Bytes) 512 1024 1024

EEPROM (Bytes) 256 512 512

Max I/O pins 27

SPI 1

TWI (I2C) 1

USART 1

ADC 10-bit 15ksps

ADC channels 8

AC 1

8-bit Timer/Counters 2

16-bit Timer/Counters 1

PWM channels 6

Operating voltage 1.8V - 5.5V

Max operating frequency 20MHz

Temperature range -40°C to +105°C



3. Ordering Information

3.1 ATmega48PB

Speed [MHz](3) Power Supply [V] Ordering Code(2) Package(1) Operational Range

20 1.8 - 5.5 ATmega48PB-AUATmega48PB-AUR(4)ATmega48PB-MUATmega48PB-MUR(4)

32A32A32MS132MS1

Industrial(-40°C to +85°C)

ATmega48PB-ANATmega48PB-ANR(4)ATmega48PB-MNATmega48PB-MNR(4)

32A32A32MS132MS1


Note: 1. This device can also be supplied in wafer form. Contact your local sales office for detailed ordering

information and minimum quantities.2. Pb-free packaging complies to the European Directive for Restriction of Hazardous Substances

(RoHS directive). Also Halide free and fully Green.3. See ”Speed Grades” on page 304.4. Tape & Reel.

Package Type

32A 32-lead, Thin (1.0mm) Plastic Quad Flat Package (TQFP)

32MS1 32-pad, 5.0x5.0x0.9mm body, Lead Pitch 0.50mm, Very-thin Fine pitch, Quad Flat No LeadPackage (VFQFN)

3.2 ATmega88PB

Speed[MHz](3)

Power Supply[V]

Ordering Code(2) Package(1) Operational Range


32A32A32MS132MS



32A32A32MS132MS1


Note: 1. This device can also be supplied in wafer form. Contact your local sales office for detailed ordering

information and minimum quantities.



2. Pb-free packaging complies to the European Directive for Restriction of Hazardous Substances(RoHS directive).Also Halide free and fully Green.

3. See ”Speed Grades” on page 304.4. Tape & Reel.

Package Type



3.3 ATmega168PB

Speed [MHz] Power Supply [V] Ordering Code(2) Package(1) Operational Range


32A32A32MS132MS1



32A32A32MS132MS1


Note: 1. This device can also be supplied in wafer form. Contact your local Atmel sales office for detailed

ordering information and minimum quantities.2. Pb-free packaging complies to the European Directive for Restriction of Hazardous Substances

(RoHS directive).Also Halide free and fully Green.3. Tape & Reel.

Package Type





4. Block DiagramFigure 4-1. Block Diagram

CPU

USART

ADCADC[7:0]AREF

RxDTxDXCK

I/OPORTS

DATABUS

GPIOR[2:0]

SRAM

OCD

EXTINT

FLASHNVMprogramming

debugWire

IN/OUT

DATABUS

TC 0(8-bit)

SPI

ACAIN0AIN1ACOADCMUX

EEPROM

EEPROMIF

TC 1(16-bit)

OC1A/BT1

ICP1

TC 2(8-bit async) TWI

SDASCL

InternalReference

Watchdog Timer

Power management

and clock control

VCC

GND

Clock generation8MHz

Calib RC

128kHz int osc

32.768kHz XOSC

External clock

Power SupervisionPOR/BOD &

RESET

XTAL2 / TOSC2

RESET

XTAL1 /TOSC1

16MHz LP XOSC

INT[1:0]PCINT[23:16], PCINT[14:0]

OC0AOC0BT0

MISOMOSISCKSS

OC2AOC2B

PB[7:0]PC[6:0]PD[7:0]PE[3:0]

SPIPROG

PARPROG



5. Pin ConfigurationsFigure 5-1. 32 TQFP Pinout ATmega48PB/88PB/168PB

1

2

3

4

32 31 30 29 28 27 26

5

6

7

8

24

23

22

21

20

19

18

1725

9 10 11 12 13 14 15 16

PD0

(RX

D/P

CIN

T16)

PD1

(TX

D/P

CIN

T17)

PD2

(INT0

/PCI

NT1

8)

PC6

(RES

ET/P

CIN

T14)

PC2

(AD

C2/P

CIN

T10)

PC3

(AD

C3/P

CIN

T11)

PC4

(AD

C4/S

DA

/PCI

NT1

2)

PC5

(AD

C5/S

CL/P

CIN

T13)

PC0 (ADC0/PCINT8)

PC1 (ADC1/PCINT9)

GND

PE2 (ADC6)

AVCC

PB5 (SCK/PCINT5)

AREF

PE3 (ADC7)

(PCINT20/XCK/T0) PD4

GND

VCC

(ACO) PE0

PE1

(PCINT6/XTAL1/TOSC1) PB6


(PCI

NT2

3/A

IN1)

PD

7

(PCI

NT1

/OC1

A) P

B1

(PCI

NT2

/SS/

OC1

B) P

B2

(PCI

NT4

/MIS

O) P

B4

(PCINT19/OC2B/INT1) PD3(P

CIN

T21/

OC0

B/T1

) PD

5

(PCI

NT2

2/O

C0A

/AIN

0) P

D6

(PCI

NT0

/CLK

O/IC

P1) P

B0

(PCI

NT3

/MO

SI/O

C2A

) PB3



Figure 5-2. 32 VQFN Pinout ATmega48PB/88PB/168PB

1

2

3

4

32 31 30 29 28 27 26

5

6

7

8

24

23

22

21

20

19

18

1725

9 10 11 12 13 14 15 16

NOTE:Bottom pad should be soldered to ground

(PCI

NT2

1/O

C0B/

T1) P

D5

(PCI

NT2

2/O

C0A

/AIN

0) P

D6

(PCI

NT2

3/A

IN1)

PD

7

(PCI

NT0

/CLK

O/IC

P1) P

B0

(PCI

NT1

/OC1

A) P

B1

(PCI

NT2

/SS/

OC1

B) P

B2

(PCI

NT3

/MO

SI/O

C2A

) PB3

(PCI

NT4

/MIS

O) P

B4

(PCINT19/OC2B/INT1) PD3

(PCINT20/XCK/T0) PD4

GND

VCC

(ACO) PE0

PE1



PD0

(RX

D/P

CIN

T16)

PD1

(TX

D/P

CIN

T17)

PD2

(INT0

/PCI

NT1

8)

PC6

(RES

ET/P

CIN

T14)

PC2

(AD

C2/P

CIN

T10)

PC3

(AD

C3/P

CIN

T11)

PC4

(AD

C4/S

DA

/PCI

NT1

2)

PC5

(AD

C5/S

CL/P

CIN

T13)

PC0 (ADC0/PCINT8)

PC1 (ADC1/PCINT9)

GND

PE2 (ADC6)

AVCC

PB5 (SCK/PCINT5)

AREF

PE3 (ADC7)

5.1 Pin Descriptions

5.1.1 VCCDigital supply voltage.

5.1.2 GNDGround.



5.1.3 Port B (PB[7:0]) XTAL1/XTAL2/TOSC1/TOSC2Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each pin). The Port Boutput buffers have symmetrical drive characteristics with both high sink and source capability. As inputs,Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The PortB pins are tri-stated during a reset condition even if the clock is not running.

Depending on the clock selection fuse settings, PB6 can be used as input to the inverting Oscillatoramplifier and input to the internal clock operating circuit.

Depending on the clock selection fuse settings, PB7 can be used as output from the inverting Oscillatoramplifier.

If the Internal Calibrated RC Oscillator is used as chip clock source, PB[7:6] is used as TOSC[2:1] inputfor the Asynchronous Timer/Counter2 if the AS2 bit in ASSR is set.

Related LinksSystem Clock and Clock OptionsAlternate Port Functions

5.1.4 Port C (PC[5:0])Port C is a 7-bit bi-directional I/O port with internal pull-up resistors (selected for each pin). The PC[5:0]output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs,Port C pins that are externally pulled low will source current if the pull-up resistors are activated. The PortC pins are tri-stated during a reset condition even if the clock is not running.

5.1.5 PC6/RESETIf the RSTDISBL Fuse is programmed, PC6 is used as an I/O pin. Note that the electrical characteristicsof PC6 differ from those of the other pins of Port C.

If the RSTDISBL Fuse is unprogrammed, PC6 is used as a Reset input. A low level on this pin for longerthan the minimum pulse length will generate a Reset, even if the clock is not running. Shorter pulses arenot guaranteed to generate a Reset.

The various special features of Port C are elaborated in the Alternate Functions of Port C section.

5.1.6 Port D (PD[7:0])Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each pin). The Port Doutput buffers have symmetrical drive characteristics with both high sink and source capability. As inputs,Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The PortD pins are tri-stated during a reset condition even if the clock is not running.

Related LinksAlternate Port Functions

5.1.7 Port E (PE[3:0])Port E is an 4-bit bi-directional I/O port with internal pull-up resistors (selected for each pin). The Port Eoutput buffers have symmetrical drive characteristics with both high sink and source capability. As inputs,Port E pins that are externally pulled low will source current if the pull-up resistors are activated. The PortE pins are tri-stated during a reset condition even if the clock is not running.

Related LinksAlternate Port Functions



5.1.8 AVCCAVCC is the supply voltage pin for the A/D Converter, PC[3:0], and PE[3:2]. It should be externallyconnected to VCC, even if the ADC is not used. If the ADC is used, it should be connected to VCC througha low-pass filter. Note that PC[6:4] use digital supply voltage, VCC.

5.1.9 AREFAREF is the analog reference pin for the A/D Converter.

5.1.10 ADC[7:6] (TQFP and VFQFN Package Only)In the TQFP and VFQFN package, ADC[7:6] serve as analog inputs to the A/D converter. These pins arepowered from the analog supply and serve as 10-bit ADC channels.



6. I/O MultiplexingEach pin is by default controlled by the PORT as a general purpose I/O and alternatively it can beassigned to one of the peripheral functions.

The following table describes the peripheral signals multiplexed to the PORT I/O pins.

Table 6-1. PORT Function Multiplexing

No PAD EXTINT PCINT ADC/AC OSC T/C # 0 T/C # 1 USART I2C SPI

1 PD[3] INT1 PCINT19 OC2B

2 PD[4] PCINT20 T0 XCK

3 PE[0] ACO

4 VCC

5 GND

6 PE[1]

7 PB[6] PCINT6 XTAL1/TOSC1

8 PB[7] PCINT7 XTAL2/TOSC2

9 PD[5] PCINT21 OC0B T1

10 PD[6] PCINT22 AIN0 OC0A

11 PD[7] PCINT23 AIN1

12 PB[0] PCINT0 CLKO ICP1

13 PB[1] PCINT1 OC1A

14 PB[2] PCINT2 OC1B SS

15 PB[3] PCINT3 OC2A MOSI

16 PB[4] PCINT4 MISO

17 PB[5] PCINT5 SCK

18 AVCC

19 PE[2] ADC6

20 AREF

21 GND

22 PE[3] ADC7

23 PC[0] PCINT8 ADC0




27 PC[4] PCINT12 ADC4 SDA

28 PC[5] PCINT13 ADC5 SCL

29 PC[6]/RESET PCINT14

30 PD[0] PCINT16 RXD

31 PD[1] PCINT17 TXD

32 PD[2] INT0 PCINT18



7. Comparison Between ProcessorsThe ATmega48PB/88PB/168PB differ only in memory sizes, boot loader support, and interrupt vectorsizes. The table below summarizes the different memory and interrupt vector sizes for the devices.

Table 7-1. Memory Size Summary

Device Flash EEPROM RAM Interrupt Vector Size

ATmega48PB 4KBytes 256Bytes 512Bytes 1 instruction word/vector

ATmega88PB 8KBytes 512Bytes 1KBytes 1 instruction word/vector

ATmega168PB 16KBytes 512Bytes 1KBytes 2 instruction words/vector

ATmega88PB/168PB support a real Read-While-Write Self-Programming Mechanism (SPM). The SPMinstruction can only execute from the separate Boot Loader Section. In ATmega48PB there is no Read-While-Write support and no separate Boot Loader Section. The SPM instruction can execute from theentire Flash.



8. ResourcesA comprehensive set of development tools, application notes and datasheets are available for downloadon http://www.microchip.com/design-centers/8-bit/microchip-avr-mcus.



http://www.microchip.com/design-centers/8-bit/microchip-avr-mcus

9. Data RetentionReliability Qualification results show that the projected data retention failure rate is much less than 1 PPMover 20 years at 85°C or 100 years at 25°C.



10. About Code ExamplesThis documentation contains simple code examples that briefly show how to use various parts of thedevice. These code examples assume that the part specific header file is included before compilation. Beaware that not all C compiler vendors include bit definitions in the header files and interrupt handling in Cis compiler dependent. Confirm with the C compiler documentation for more details.

For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructionsmust be replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS”combined with “SBRS”, “SBRC”, “SBR”, and “CBR”.

Related LinksData TransferUSART MSPIM Initialization



11. Capacitive Touch Sensing

11.1 QTouch LibraryThe QTouch® Library provides a simple to use solution to realize touch sensitive interfaces on most AVR®

microcontrollers. The QTouch Library includes support for the Touch and QMatrix® acquisition methods.

Touch sensing can be added to any application by linking the appropriate QTouch Library for the AVRMicrocontroller. This is done by using a simple set of APIs to define the touch channels and sensors, andthen calling the touch sensing API’s to retrieve the channel information and determine the touch sensorstates.

The QTouch Library is FREE and down-loadable from QTouch Library . For implementation details andother information, refer to the QTouch Library User Guide - also available for download from the website.



http://www.microchip.com/developmenttools/productdetails.aspx?partno=atmel+qtouch+libraryhttp://ww1.microchip.com/downloads/en/DeviceDoc/doc8207.pdf

12. AVR CPU Core

12.1 OverviewThis section discusses the AVR core architecture in general. The main function of the CPU core is toensure correct program execution. The CPU must therefore be able to access memories, performcalculations, control peripherals, and handle interrupts.

Figure 12-1. Block Diagram of the AVR Architecture

Register file

Flash program memory

Program counter

Instruction register

Instruction decode

Data memory

ALUStatus register

R0R1R2R3R4R5R6R7R8R9

R10R11R12R13R14R15R16R17R18R19R20R21R22R23R24R25

R26 (XL)R27 (XH)R28 (YL)R29 (YH)R30 (ZL)R31 (ZH)

Stack pointer

In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with separatememories and buses for program and data. Instructions in the program memory are executed with asingle level pipelining. While one instruction is being executed, the next instruction is pre-fetched from theprogram memory. This concept enables instructions to be executed in every clock cycle. The programmemory is In-System Reprogrammable Flash memory.

The fast-access Register File contains 32 x 8-bit general purpose working registers with a single clockcycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALUoperation, two operands are output from the Register File, the operation is executed, and the result isstored back in the Register File – in one clock cycle.

Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Spaceaddressing – enabling efficient address calculations. One of the these address pointers can also be usedas an address pointer for look up tables in Flash program memory. These added function registers arethe 16-bit X-, Y-, and Z-register, described later in this section.



The ALU supports arithmetic and logic operations between registers or between a constant and aregister. Single register operations can also be executed in the ALU. After an arithmetic operation, theStatus Register is updated to reflect information about the result of the operation.

Program flow is provided by conditional and unconditional jump and call instructions, able to directlyaddress the whole address space. Most AVR instructions have a single 16-bit word format. Everyprogram memory address contains a 16- or 32-bit instruction.

Program Flash memory space is divided in two sections, the Boot Program section and the ApplicationProgram section. Both sections have dedicated Lock bits for write and read/write protection. The SPMinstruction that writes into the Application Flash memory section must reside in the Boot Program section.

During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the Stack.The Stack is effectively allocated in the general data SRAM, and consequently the Stack size is onlylimited by the total SRAM size and the usage of the SRAM. All user programs must initialize the SP in theReset routine (before subroutines or interrupts are executed). The Stack Pointer (SP) is read/writeaccessible in the I/O space. The data SRAM can easily be accessed through the five different addressingmodes supported in the AVR architecture.

The memory spaces in the AVR architecture are all linear and regular memory maps.

A flexible interrupt module has its control registers in the I/O space with an additional Global InterruptEnable bit in the Status Register. All interrupts have a separate Interrupt Vector in the Interrupt Vectortable. The interrupts have priority in accordance with their Interrupt Vector position. The lower theInterrupt Vector address, the higher the priority.

The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers, SPI,and other I/O functions. The I/O Memory can be accessed directly, or as the Data Space locationsfollowing those of the Register File, 0x20 - 0x5F. In addition, this device has Extended I/O space from0x60 - 0xFF in SRAM where only the ST/STS/STD and LD/LDS/LDD instructions can be used.

12.2 ALU – Arithmetic Logic UnitThe high-performance AVR ALU operates in direct connection with all the 32 general purpose workingregisters. Within a single clock cycle, arithmetic operations between general purpose registers orbetween a register and an immediate are executed. The ALU operations are divided into three maincategories – arithmetic, logical, and bit-functions. Some implementations of the architecture also providea powerful multiplier supporting both signed/unsigned multiplication and fractional format. See InstructionSet section for a detailed description.

12.3 Status RegisterThe Status Register contains information about the result of the most recently executed arithmeticinstruction. This information can be used for altering program flow in order to perform conditionaloperations. The Status Register is updated after all ALU operations, as specified in the Instruction SetReference. This will in many cases remove the need for using the dedicated compare instructions,resulting in faster and more compact code.

The Status Register is not automatically stored when entering an interrupt routine and restored whenreturning from an interrupt. This must be handled by software.

12.3.1 Status Register



When addressing I/O Registers as data space using LD and ST instructions, the provided offset must beused. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in anI/O address offset within 0x00 - 0x3F.

Name: SREGOffset: 0x5FReset: 0x00Property:

When addressing as I/O Register: address offset is 0x3F

Bit 7 6 5 4 3 2 1 0 I T H S V N Z C

Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0

Bit 7 – I: Global Interrupt EnableThe Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual interruptenable control is then performed in separate control registers. If the Global Interrupt Enable Register iscleared, none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enablesubsequent interrupts. The I-bit can also be set and cleared by the application with the SEI and CLIinstructions, as described in the instruction set reference.

Bit 6 – T: Copy StorageThe Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or destination forthe operated bit. A bit from a register in the Register File can be copied into T by the BST instruction, anda bit in T can be copied into a bit in a register in the Register File by the BLD instruction.

Bit 5 – H: Half Carry FlagThe Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry Flag is useful inBCD arithmetic. See the Instruction Set Description for detailed information.

Bit 4 – S: Sign Flag, S = N ㊉ V

The S-bit is always an exclusive or between the Negative Flag N and the Two’s Complement OverflowFlag V. See the Instruction Set Description for detailed information.

Bit 3 – V: Two’s Complement Overflow FlagThe Two’s Complement Overflow Flag V supports two’s complement arithmetic. See the Instruction SetDescription for detailed information.

Bit 2 – N: Negative FlagThe Negative Flag N indicates a negative result in an arithmetic or logic operation. See the Instruction SetDescription for detailed information.

Bit 1 – Z: Zero FlagThe Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the Instruction SetDescription for detailed information.



Bit 0 – C: Carry FlagThe Carry Flag C indicates a carry in an arithmetic or logic operation. See the Instruction Set Descriptionfor detailed information.

12.4 General Purpose Register FileThe Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve therequired performance and flexibility, the following input/output schemes are supported by the RegisterFile:

• One 8-bit output operand and one 8-bit result input• Two 8-bit output operands and one 8-bit result input• Two 8-bit output operands and one 16-bit result input• One 16-bit output operand and one 16-bit result input

The figure shows the structure of the 32 general purpose working registers in the CPU.

Figure 12-2. AVR CPU General Purpose Working Registers

7 0 Addr.

R0 0x00

R1 0x01

R2 0x02

…

R13 0x0D

General R14 0x0E

Purpose R15 0x0F

Working R16 0x10

Registers R17 0x11

…

R26 0x1A X-register Low Byte

R27 0x1B X-register High Byte

R28 0x1C Y-register Low Byte

R29 0x1D Y-register High Byte

R30 0x1E Z-register Low Byte

R31 0x1F Z-register High Byte

Most of the instructions operating on the Register File have direct access to all registers, and most ofthem are single cycle instructions. As shown in the figure, each register is also assigned a data memoryaddress, mapping them directly into the first 32 locations of the user Data Space. Although not beingphysically implemented as SRAM locations, this memory organization provides great flexibility in accessof the registers, as the X-, Y-, and Z-pointer registers can be set to index any register in the file.

12.4.1 The X-register, Y-register, and Z-registerThe registers R26...R31 have some added functions to their general purpose usage. These registers are16-bit address pointers for indirect addressing of the data space. The three indirect address registers X,Y, and Z are defined as described in the figure.

Figure 12-3. The X-, Y-, and Z-registers15 XH XL 0

X-register 7 0 7 0

R27 R26

15 YH YL 0

Y-register 7 0 7 0

R29 R28

15 ZH ZL 0

Z-register 7 0 7 0

R31 R30

In the different addressing modes these address registers have functions as fixed displacement,automatic increment, and automatic decrement (see the instruction set reference for details).



12.5 Stack PointerThe Stack is mainly used for storing temporary data, for storing local variables and for storing returnaddresses after interrupts and subroutine calls. The Stack is implemented as growing from higher tolower memory locations. The Stack Pointer Register always points to the top of the Stack.

The Stack Pointer points to the data SRAM Stack area where the Subroutine and Interrupt Stacks arelocated. A Stack PUSH command will decrease the Stack Pointer. The Stack in the data SRAM must bedefined by the program before any subroutine calls are executed or interrupts are enabled. Initial StackPointer value equals the last address of the internal SRAM and the Stack Pointer must be set to pointabove start of the SRAM. See the table for Stack Pointer details.

Table 12-1. Stack Pointer Instructions

Instruction Stack pointer Description

PUSH Decremented by 1 Data is pushed onto the stack

ICALL

RCALL

Decremented by 2 Return address is pushed onto the stack with a subroutine call orinterrupt

POP Incremented by 1 Data is popped from the stack

RET

RETI

Incremented by 2 Return address is popped from the stack with return from subroutine orreturn from interrupt

The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of bits actuallyused is implementation dependent. Note that the data space in some implementations of the AVRarchitecture is so small that only SPL is needed. In this case, the SPH Register will not be present.

12.5.1 Stack Pointer Register Low and High byte


Reset value of SPL is RAMEND.

Name: SPL and SPHOffset: 0x5D [ID-000004d0]Reset: 0xXXProperty:

When addressing as I/O Register: address offset is 0x3D



Bit 15 14 13 12 11 10 9 8 SP[15:8]


Bit 7 6 5 4 3 2 1 0 SP[7:0]

Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 x

Bits 15:0 – SP[15:0]: Stack Pointer Address

12.6 Instruction Execution TimingThis section describes the general access timing concepts for instruction execution. The AVR CPU isdriven by the CPU clock clkCPU, directly generated from the selected clock source for the chip. No internalclock division is used. The Figure below shows the parallel instruction fetches and instruction executionsenabled by the Harvard architecture and the fast-access Register File concept. This is the basicpipelining concept to obtain up to 1 MIPS per MHz with the corresponding unique results for functions percost, functions per clocks, and functions per power-unit.

Figure 12-4. The Parallel Instruction Fetches and Instruction Executions

clk

1st Instruction Fetch1st Instruction Execute

2nd Instruction Fetch2nd Instruction Execute

3rd Instruction Fetch3rd Instruction Execute

4th Instruction Fetch

T1 T2 T3 T4

CPU

The following figure shows the internal timing concept for the Register File. In a single clock cycle an ALUoperation using two register operands is executed, and the result is stored back to the destinationregister.

Figure 12-5. Single Cycle ALU Operation

Total Execution Time

Register Operands Fetch

ALU Operation Execute

Result Write Back

T1 T2 T3 T4

clkCPU



12.7 Reset and Interrupt HandlingThe AVR provides several different interrupt sources. These interrupts and the separate Reset Vectoreach have a separate program vector in the program memory space. All interrupts are assignedindividual enable bits which must be written logic one together with the Global Interrupt Enable bit in theStatus Register in order to enable the interrupt. Depending on the Program Counter value, interrupts maybe automatically disabled when Boot Lock bits BLB02 or BLB12 are programmed. This feature improvessoftware security. See the section on MEMPROG- Memory Programming for details.

The lowest addresses in the program memory space are by default defined as the Reset and InterruptVectors. The complete list of vectors is shown in Interrupts. The lower the address the higher is thepriority level. RESET has the highest priority, and next is INT0 – the External Interrupt Request 0. TheInterrupt Vectors can be moved to the start of the Boot Flash section by setting the IVSEL bit in the MCUControl Register (MCUCR). Refer to Interrupts for more information. The Reset Vector can also be movedto the start of the Boot Flash section by programming the BOOTRST Fuse, see BTLDR - Boot LoaderSupport – Read-While-Write Self-Programming.

When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled. Theuser software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can theninterrupt the current interrupt routine. The I-bit is automatically set when a Return from Interruptinstruction – RETI – is executed.

There are basically two types of interrupts. The first type is triggered by an event that sets the InterruptFlag. For these interrupts, the Program Counter is vectored to the actual Interrupt Vector in order toexecute the interrupt handling routine, and hardware clears the corresponding Interrupt Flag. InterruptFlags can also be cleared by writing a logic one to the flag bit position(s) to be cleared. If an interruptcondition occurs while the corresponding interrupt enable bit is cleared, the Interrupt Flag will be set andremembered until the interrupt is enabled, or the flag is cleared by software. Similarly, if one or moreinterrupt conditions occur while the Global Interrupt Enable bit is cleared, the corresponding InterruptFlag(s) will be set and remembered until the Global Interrupt Enable bit is set, and will then be executedby order of priority.

The second type of interrupts will trigger as long as the interrupt condition is present. These interrupts donot necessarily have Interrupt Flags. If the interrupt condition disappears before the interrupt is enabled,the interrupt will not be triggered. When the AVR exits from an interrupt, it will always return to the mainprogram and execute one more instruction before any pending interrupt is served.

The Status Register is not automatically stored when entering an interrupt routine, nor restored whenreturning from an interrupt routine. This must be handled by software.

When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled. Nointerrupt will be executed after the CLI instruction, even if it occurs simultaneously with the CLIinstruction. The following example shows how this can be used to avoid interrupts during the timedEEPROM write sequence.

Assembly Code Example

in r16, SREG ; store SREG valuecli ; disable interrupts during timed sequencesbi EECR, EEMPE ; start EEPROM writesbi EECR, EEPEout SREG, r16 ; restore SREG value (I-bit)

C Code Example

char cSREG;cSREG = SREG; /* store SREG value */



/* disable interrupts during timed sequence */_CLI();EECR |= (1

13. AVR Memories

13.1 OverviewThis section describes the different memory types in the device. The AVR architecture has two mainmemory spaces, the Data Memory and the Program Memory space. In addition, the device features anEEPROM Memory for data storage. All memory spaces are linear and regular.

13.2 In-System Reprogrammable Flash Program MemoryThe device contains 4/8/16Kbytes On-chip In-System Reprogrammable Flash memory for programstorage. Since all AVR instructions are 16 or 32 bits wide, the Flash is organized as 2/4/8K x 16. Forsoftware security, the Flash Program memory space is divided into two sections, Boot Loader Section andApplication Program Section in ATmega88PB and ATmega168PB.

The Flash memory has an endurance of at least 10,000 write/erase cycles. The device Program Counter(PC) is 11/12/13 bits wide, thus addressing the 2/4/8K program memory locations.

Constant tables can be allocated within the entire program memory address space (see the LPM – LoadProgram Memory instruction description).

Timing diagrams for instruction fetch and execution are presented in Instruction Execution Timing.

Figure 13-1. Program Memory Map ATmega48PB

0x0000

0x7FF

Program Memory

Application Flash Section



Figure 13-2. Program Memory Map ATmega88PB and ATmega168PB

0x0000

0x0FFF/0x1FFF

Program Memory

Application Flash Section

Boot Flash Section

Related LinksMemory ProgrammingInstruction Execution TimingBoot Loader Support – Read-While-Write Self-ProgrammingSelf-Programming the Flash

13.3 SRAM Data MemoryThe following figure shows how the device SRAM Memory is organized.

The device is a complex microcontroller with more peripheral units than can be supported within the 64locations reserved in the Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60- 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.

The lower 768/1280/1280 data memory locations address both the Register File, the I/O memory,Extended I/O memory, and the internal data SRAM. The first 32 locations address the Register File, thenext 64 location the standard I/O memory, then 160 locations of Extended I/O memory, and the next512/1024/1024 locations address the internal data SRAM.

The five different addressing modes for the data memory cover:1. Direct

– The direct addressing reaches the entire data space.2. Indirect with Displacement

– The Indirect with Displacement mode reaches 63 address locations from the base addressgiven by the Y- or Z-register.

3. Indirect



– In the Register File, registers R26 to R31 feature the indirect addressing pointer registers.4. Indirect with Pre-decrement

– The address registers X, Y, and Z are decremented.5. Indirect with Post-increment

– The address registers X, Y, and Z are incremented.

The 32 general purpose working registers, 64 I/O Registers, 160 Extended I/O Registers, and the512/1024/1024 bytes of internal data SRAM in the device are all accessible through all these addressingmodes.

Figure 13-3. Data Memory Map

Related LinksGeneral Purpose Register File

13.3.1 Data Memory Access TimesThe internal data SRAM access is performed in two clkCPU cycles as described in the following Figure.

Figure 13-4. On-chip Data SRAM Access Cycles

clk

WR

RD

Data

Data

Address Address valid

T1 T2 T3

Compute Address

Rea

dW

rite

CPU

Memory Access Instruction Next Instruction



13.4 EEPROM Data MemoryThe device contains 256/512/512 bytes of data EEPROM memory. It is organized as a separate dataspace, in which single bytes can be read and written. The EEPROM has an endurance of at least100,000 write/erase cycles. The access between the EEPROM and the CPU is described in the following,specifying the EEPROM Address Registers, the EEPROM Data Register, and the EEPROM ControlRegister.

See the related links for a detailed description on EEPROM Programming in SPI or Parallel Programmingmode.

Related LinksMemory Programming

13.4.1 EEPROM Read/Write AccessThe EEPROM Access Registers are accessible in the I/O space.

The write access time for the EEPROM is given in Table 13-2. A self-timing function, however, lets theuser software detect when the next byte can be written. If the user code contains instructions that writethe EEPROM, some precautions must be taken. In heavily filtered power supplies, VCC is likely to rise orfall slowly on power-up/down. This causes the device for some period of time to run at a voltage lowerthan specified as minimum for the clock frequency used. Please refer to Preventing EEPROM Corruptionfor details on how to avoid problems in these situations.

In order to prevent unintentional EEPROM writes, a specific write procedure must be followed. Refer tothe description of the EEPROM Control Register for details on this.

When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction isexecuted. When the EEPROM is written, the CPU is halted for two clock cycles before the next instructionis executed.


13.4.2 Preventing EEPROM CorruptionDuring periods of low VCC, the EEPROM data can be corrupted because the supply voltage is too low forthe CPU and the EEPROM to operate properly. These issues are the same as for board level systemsusing EEPROM, and the same design solutions should be applied.

An EEPROM data corruption can be caused by two situations when the voltage is too low. First, a regularwrite sequence to the EEPROM requires a minimum voltage to operate correctly. Secondly, the CPU itselfcan execute instructions incorrectly, if the supply voltage is too low.

EEPROM data corruption can easily be avoided by following this design recommendation:

Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This can be doneby enabling the internal Brown-out Detector (BOD). If the detection level of the internal BOD does notmatch the needed detection level, an external low VCC reset Protection circuit can be used. If a resetoccurs while a write operation is in progress, the write operation will be completed provided that thepower supply voltage is sufficient.




13.5 I/O MemoryThe I/O space definition of the device is shown in the Register Summary.

All device I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed by theLD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32 general purpose workingregisters and the I/O space. I/O Registers within the address range 0x00-0x1F are directly bit-accessibleusing the SBI and CBI instructions. In these registers, the value of single bits can be checked by usingthe SBIS and SBIC instructions.

When using the I/O specific commands IN and OUT, the I/O addresses 0x00-0x3F must be used. Whenaddressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to theseaddresses. The device is a complex microcontroller with more peripheral units than can be supportedwithin the 64 location reserved in Opcode for the IN and OUT instructions. For the Extended I/O spacefrom 0x60..0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.

For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/Omemory addresses should never be written.

Some of the Status Flags are cleared by writing a '1' to them; this is described in the flag descriptions.Note that, unlike most other AVRs, the CBI and SBI instructions will only operate on the specified bit, andcan therefore be used on registers containing such Status Flags. The CBI and SBI instructions work withregisters 0x00-0x1F only.

The I/O and Peripherals Control Registers are explained in later sections.

Related LinksRegister SummaryInstruction Set SummaryMemory Programming

13.5.1 General Purpose I/O RegistersThe device contains three General Purpose I/O Registers, General Purpose I/O Register 0/1/2 (GPIOR0/1/2). These registers can be used for storing any information, and they are particularly useful for storingglobal variables and Status Flags. General Purpose I/O Registers within the address range 0x00 - 0x1Fare directly bit-accessible using the SBI, CBI, SBIS, and SBIC instructions.

Related LinksRegister SummaryInstruction Set SummaryMemory Programming

13.6 Register Description

13.6.1 Accessing 16-bit RegistersThe AVR data bus is 8 bits wide, and so accessing 16-bit registers requires atomic operations. Theseregisters must be byte-accessed using two read or write operations. 16-bit registers are connected to the8-bit bus and a temporary register using a 16-bit bus.

For a write operation, the low byte of the 16-bit register must be written before the high byte. The low byteis then written into the temporary register. When the high byte of the 16-bit register is written, thetemporary register is copied into the low byte of the 16-bit register in the same clock cycle.



For a read operation, the low byte of the 16-bit register must be read before the high byte. When the lowbyte register is read by the CPU, the high byte of the 16-bit register is copied into the temporary registerin the same clock cycle as the low byte is read. When the high byte is read, it is then read from thetemporary register.

This ensures that the low and high bytes of 16-bit registers are always accessed simultaneously whenreading or writing the register.

Interrupts can corrupt the timed sequence if an interrupt is triggered and accesses the same 16-bitregister during an atomic 16-bit read/write operation. To prevent this, interrupts can be disabled whenwriting or reading 16-bit registers.

The temporary registers can also be read and written directly from user software.

13.6.2 EEPROM Address Register Low and High Byte

The EEARL and EEARH register pair represents the 16-bit value, EEAR. The low byte [7:0] (suffix L) isaccessible at the original offset. The high byte [15:8] (suffix H) can be accessed at offset + 0x01. Formore details on reading and writing 16-bit registers, refer to Accessing 16-bit Registers.


Name: EEARL and EEARHOffset: 0x41 [ID-000004d0]Reset: 0xXXProperty:

When addressing as I/O Register: address offset is 0x21

Bit 15 14 13 12 11 10 9 8 EEAR[9:8]

Access R/W R/W Reset x x

Bit 7 6 5 4 3 2 1 0 EEAR[7:0]

Access R/W R/W R/W R/W R/W R/W R/W R/W Reset x x x x x x x x

Bits 9:0 – EEAR[9:0]: EEPROM AddressThe EEPROM Address Registers – EEARH and EEARL specify the EEPROM address in the 1024 BytesEEPROM space. The EEPROM data bytes are addressed linearly between 0 and 1023. The initial valueof EEAR is undefined. A proper value must be written before the EEPROM may be accessed.

13.6.3 EEPROM Data Register




Name: EEDROffset: 0x40 [ID-000004d0]Reset: 0x00Property:

When addressing as I/O Register: address offset is 0x20

Bit 7 6 5 4 3 2 1 0 EEDR[7:0]


Bits 7:0 – EEDR[7:0]: EEPROM DataFor the EEPROM write operation, the EEDR Register contains the data to be written to the EEPROM inthe address given by the EEAR Register. For the EEPROM read operation, the EEDR contains the dataread out from the EEPROM at the address given by EEAR.

13.6.4 EEPROM Control Register

Name: EECROffset: 0x3F [ID-000004d0]Reset: 0x00Property:

When addressing as I/O Register: address offset is 0x1F

Bit 7 6 5 4 3 2 1 0 EEPM[1:0] EERIE EEMPE EEPE EERE

Access R/W R/W R/W R/W R/W R/W Reset x x 0 0 x 0

Bits 5:4 – EEPM[1:0]: EEPROM Programming Mode BitsThe EEPROM Programming mode bit setting defines which programming action that will be triggeredwhen writing EEPE. It is possible to program data in one atomic operation (erase the old value andprogram the new value) or to split the Erase and Write operations into two different operations. TheProgramming times for the different modes are shown in the table below. While EEPE is set, any write toEEPMn will be ignored. During reset, the EEPMn bits will be reset to 0b00 unless the EEPROM is busyprogramming.

Table 13-1. EEPROM Mode Bits

EEPM[1:0] Programming Time Operation

00 3.4ms Erase and Write in one operation (Atomic Operation)

01 1.8ms Erase Only

10 1.8ms Write Only

11 - Reserved for future use

Bit 3 – EERIE: EEPROM Ready Interrupt EnableWriting EERIE to one enables the EEPROM Ready Interrupt if the I bit in SREG is set. Writing EERIE tozero disables the interrupt. The EEPROM Ready interrupt generates a constant interrupt when EEPE iscleared. The interrupt will not be generated during EEPROM write or SPM.



Bit 2 – EEMPE: EEPROM Master Write EnableThe EEMPE bit determines whether writing EEPE to '1' causes the EEPROM to be written.When EEMPE is '1', setting EEPE within four clock cycles will write data to the EEPROM at the selectedaddress.

If EEMPE is zero, setting EEPE will have no effect. When EEMPE has been written to '1' by software,hardware c

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