Kondalarao PolisettiSenior Design Engineer , Xilinx

MIPI CSI-2SM for Multi-camera, Long Range Use Cases and Implementation Methods Using FPGAs

©2017MIPIAlliance,Inc.

Agenda• MIPI CSI-2 Introduction & Features• Camera Market & Projections• Multi-camera & Long Distance Use Case(s)• System Requirements• Value of FPGA for MIPI CSI-2• Q & A

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Xilinx

©2017MIPIAlliance,Inc.

mipi.org• MIPIAlliance: Developingtheworld’smostcomprehensiveset

ofinterfacespecificationsformobileandmobile-influencedproducts.

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Source:mipi.orgXilinx

©2017MIPIAlliance,Inc.

MIPICSI-2FeaturesNote:MIPICSI-2SM 1.1,MIPID-PHYSM 1.1consideredinthispresentation.

• Multi-lanesupport(1.5Gbps/Lane)• Multipledatatypes(RAW,RGB,YUV)• Interleaving(VC,Datatype)

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Xilinx

©2017MIPIAlliance,Inc.

MIPICSI-2Features

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Xilinx

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MIPICSI-2Features

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Xilinx

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CameraProjections

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• Cameramarketbyapplication

Source:grandviewresearch.comXilinx

©2017MIPIAlliance,Inc.

Automotive-ADASProjections

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Source:IHSXilinx

©2017MIPIAlliance,Inc.

VideoSurveillanceProjections

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Source:IHSXilinx

©2017MIPIAlliance,Inc.

Multi-cameraSystems

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CSI-2Rx VideoProcessing

Visualization

Multiplechannels,multipleinstances

Singlechannel,singleinstanceHowmanycam’scanbesupported?Systemlevelaspectsinsuchdesigns

Howmanycam’scanbesupported?Systemlevelaspectsinsuchdesignsü Bandwidth

ü Protocolsupportü MuxChipsupport

ü Bandwidthü Protocolsupportü MuxChipsupportü IOSupport

CSI-2Rx VideoProcessing

VisualizationCSI-2Rx

CSI-2RxVideo

ProcessingVisualization

MuxChip

CSI-2RxMuxChip

CSI-2Rx VideoProcessing

Visualization

MuxChip

Type-1 Type-2Xilinx

©2017MIPIAlliance,Inc.

Systemaspects-Type1

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VC=0,RAW8

VC=1,RAW8

VC=2,RAW8

VC=3,RAW8

MIPICSI-2MuxChip

MIPISingleChannel

VC=0,RAW10

VC=1,RAW10

VC=2,RAW10

VC=3,RAW10

VC=0,RAW12

VC=1,RAW12

VC=2,RAW12

VC=3,RAW12

üTotalbandwidthavailableüInterleavingassupportedMIPICSI-2SpecificationüMaximuminputchannelssupportedbymuxchip

CSI-2Rx VideoProcessing

Visualization

MuxChip

Howmanycam’scanbesupported?Systemlevelaspectsinsuchdesigns

Xilinx

©2017MIPIAlliance,Inc.

Systemaspects-Type2

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üTotalbandwidthavailableüInterleavingassupportedMIPICSI-2SpecificationüMaximuminputchannelssupportedbymuxchipüMaximumCSI-2Instancesthatcanbeimplementedonthechip

VC=0,RAW8

VC=1,RAW8

VC=2,RAW8

VC=3,RAW8

MIPICSI-2MuxChip

VC=0,RAW10

VC=1,RAW10

VC=2,RAW10

VC=3,RAW10

VC=0,RAW12

VC=1,RAW12

VC=2,RAW12

VC=3,RAW12

VC=0,RAW8

VC=1,RAW8

VC=2,RAW8

VC=3,RAW8

MIPICSI-2MuxChip

VC=0,RAW10

VC=1,RAW10

VC=2,RAW10

VC=3,RAW10

VC=0,RAW12

VC=1,RAW12

VC=2,RAW12

VC=3,RAW12

MIPICSI-2RxInstances

CSI-2RxVideo

ProcessingVisualization

MuxChip

CSI-2RxMuxChip

Howmanycam’scanbesupported?Systemlevelaspectsinsuchdesigns

ü Protocolsupportü MuxChipsupportü IOSupport

Xilinx

©2017MIPIAlliance,Inc.

SystemRequirements-Type1

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• 1920x1080@30fps,RAW8->Requires~0.74Gbps

Bandwidth Interleaving MuxChip

6/0.74=8

1.5Gbps,4L=6

4*1=4

VC=4DT=1(RAW8)

Letssay‘4’

BasedonChip

min(8,4,4)=4

Xilinx

©2017MIPIAlliance,Inc.

SystemRequirements-Type2

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• 1920x1080@30fps,RAW8->Requires~0.74Gbps

Bandwidth Interleaving MuxChip

6/0.74=8

1.5Gbps,4L=6

4*1=4

VC=4DT=1(RAW8)

Letssay‘4’

BasedonChip

IOSupport

BasedonFPGAIO

AutoGrade US+supports8

InstanceswithNativeIO’s

min(8,4,4)=4CSI-2Instances=8MaxCam’s=4*8=32

Xilinx

©2017MIPIAlliance,Inc. 15

Source:mipi.org

SurroundView

TrafficSignPark

Assistance

LaneDeparture

SurroundView

Multi-camera&LongDistanceUseCase(s)

Xilinx

©2017MIPIAlliance,Inc. 16

LongDistanceUsingBridgeIC’s

CSI-2Rx VideoProcessing

Visualization

MuxChip

BridgeIC

ConvertsMIPID-PHYSMtoLVDS

ConvertsLVDStoMIPID-PHYSM

MIPIInterfacesmaybeconvertedto/fromthesehighspeedtransportsinbridgechipswhenlengthexceedMIPISpecificationlengths

Supportedcablelength,data rateetc.,determined

byBridgeIC

BridgeIC

Xilinx

©2017MIPIAlliance,Inc. 17

Xilinx

ValueofFPGAforMIPICSI-2• Mostflexible&scalableplatformformaximumreuseandbest

TTMü ImplementEnd-to-Endsystemswithease

• LatestFPGAscanspeakMIPID-PHYü SingleChip(PHY+Controller),reducesBOM.MoreD-PHYinterfacesperchip(>16)ü Flexibleinterfaces:Lanes(1,2,3,4),Datarates,VCfilteringetc..

• LatestFPGAsbuiltonacommonreal-timeprocessor andprogrammablelogic equippedplatformenablesunlimitedpossibilitiesfornextgenerationADASapplicationsü InnovativeARM®+FPGAarchitecturefordifferentiation,analytics&control

©2017MIPIAlliance,Inc.

Q&A

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Xilinx