This document contains information on a new product. Specifications and information herein are subject to change without notice.
This B4420 QorIQ Qonverge chip is a Freescale heterogeneous multicore SoC based on StarCore, Power Architecture®, CoreNet, MAPLE, and DPAA technologies. The chip targets the emerging broadband wireless metro cell deployments and builds upon the proven success of Freescale’s existing multicore DSPs and CPUs. It is designed to bolster the rapidly changing and expanding wireless base station markets, such as LTE (FDD and TDD), LTE-Advanced, TD-SCDMA, and WCDMA.
This chip can be used for combined control, data path, and application layer processing in base stations and in general-purpose embedded computing systems. Its high level of integration offers performance benefits compared to multiple discrete devices, while also simplifying board design.This chip includes these functions and features:
• Two fully-programmable StarCore SC3900 FVP core subsystems—each core runs up to 1.2 GHz, with an architecture highly optimized for wireless base station applications
• Two dual-thread e6500 Power Architecture processors organized in one cluster—each core runs up to 1.6 GHz
• DDR3/3L controller for high-speed, industry-standard memory interfaces running up to 1866 MT/s
• MAPLE-B3 hardware acceleration—for forward error correction schemes including Turbo or Viterbi decoding, Turbo encoding and rate matching, MIMO MMSE equalization scheme, matrix operations, CRC insertion and check, DFT/iDFT and FFT/iFFT calculations, PUSCH/PDSCH acceleration, and UMTS chip rate acceleration
• CoreNet fabric supports coherency using MESI protocol between the e6500 cores, SC3900 FVP cores, memories and external interfaces. CoreNet fabric interconnect runs at up to 667 MHz and supports coherent and non-coherent out of order transactions with prioritization and bandwidth allocation amongst CoreNet endpoints.
• Data Path Acceleration Architecture, which includes:– Frame Manager (FMan), which supports in-line packet
parsing and general classification to enable policing and QoS-based packet distribution
– Queue Manager (QMan) and Buffer Manager (BMan), which allow offloading of queue management, task management, load distribution, flow ordering, buffer management, and allocation tasks from the cores
– Security engine (SEC 5.3)—crypto-acceleration for protocols such as IPsec, SSL and 802.16
• Large internal cache memory with snooping and stashing capabilities for bandwidth saving and high utilization of processor elements. The 4864 KB internal memory space includes the following:– 32 KB L1 ICache per e6500/SC3900 core– 32 KB L1 DCache per e6500/SC3900 core– 2048 KB unified L2 cache for SC3900 FVP cluster– 2048 KB unified L2 cache for e6500 cluster– 512 KB shared L3 CoreNet platform cache (CPC)
• Eight 10 Gbps SerDes lanes serving:– Four lanes common public radio interface (CPRI V4.2)
controller for glueless antenna connection running at up to 9.8 GT/s
– Three 1 GT/s/2.5 GT/s Ethernet controllers for network communications
– Four lanes PCI Express controller running at up to 5 GT/s
– Two lanes 2.5 GT/s/3.125 GT/s/5 GT/s Debug (Aurora)• One OCeaN DMA• Various system peripherals• 90 32-bit timers
1. MDIC[0] is grounded through a 237 precision 1% resistor and MDIC[1] is connected to GnVDD through a 237 precision 1% resistor. For either full or half driver strength calibration of DDR IOs, use the same MDIC resistor value of 237 . Memory controller register setting can be used to determine automatic calibration is done to full or half-drive strength. These pins are used for automatic calibration of the DDR3/DDR3L IOs.
2. This pin is an open drain signal.3. Recommend that a weak pull-up resistor (2-10 K) be placed on this pin to OVDD.4. Recommend that a pull-up resistor (1 k) be placed on this pin to DVDD when the I2C interface is used.5. Recommend that a weak pull-up resistor (2-10 K) be placed on this pin to OVDD, when used as IRQ_OUT_B pin.6. This is an active low signal. When not used, connect it to OVDD by a pull up resistor of 2–10K.7. QVDD is an internal IO quiet power domain. Externally it should be connected to OVDD supply.8. Pin has a weak (~20 k) internal pull-up P-FET, which is always enabled.9. This output is actively driven during reset rather than being tristated during reset.10.This pin requires a 698 (1% accuracy) pull-up to XVDD.11.This pin requires a 200 (1% accuracy) pull-up to SVDD.12.Recommend that a weak pull-down resistor (10 K) be placed on this pin to GND.13.See Section 2.2, “Power sequencing,” and Section 5, “Security fuse processor,” for additional details on this signal.14.These pins are connected to the same global power and ground (VDD and GND) nets internally and may be connected as
a differential pair to be used by the voltage regulators with remote sense function.15.Do not connect. These pins should be left floating.16.The QVDD supply to these pins is not an actual supply pin, but a functional pin requires the QVDD supply connectivity, via
pull-up resistor of 10 K. 17.The GND supply to these pins is not an actual supply pin, but a functional pin requires the GND supply connectivity. Pin must
be connected with a pull-down resistor of 10 k.18.The Thermal Monitoring Unit (TMU) is defeatured on this device. TH_VDD should be connected to an OVDD supply.19.This pin is a reset configuration pin. It has a weak (~20 k) internal pull-up P-FET that is enabled only when the processor
is in its reset state. This pull-up is designed such that it can be overpowered by an external 4.7 k resistor. However, when the signal is intended to be high after reset, and when there is a device on the net that might pull down the value of the net at reset, a pull-up or active driver is needed.
20.CFG_DRAM_TYPE configuration pin selects the DRAM type: “0” - DDR3 (IO is 1.5V), “1” - DDR3L (IO is 1.35 V). 21.CFG_XVDD_SEL configuration pin selects the XVDD Voltage: “0” - XVDD is 1.5V, “1” - XVDD is 1.35 V22.CFG_IFC_TE configuration pin selects the IFC External Transceiver Enable Pin Polarity: “0” - Default value of IFC’s
CSPR0[TE] is logic 1, “1” - Default value of IFC’s CSPR0[TE] is logic 0.23.CFG_RSP_DIS configuration pin allows the chip to enter debug mode immediately after reset. The board should be
configurable (by some FPGA/dip-switch) to drive the CFG_RSP_DIS pin during PORESET sequence to logic 0 or logic 1, with default level of logic 1, with the timing as defined for all other CFG pins. After POR completion, the pin is used as IFC_AVD function.
24.Pin must NOT be pulled down during power-on reset. This pin may be pulled up, driven high, or if there are any externally connected devices, left in tristate. If this pin is connected to a device that pulls down during reset, external pull-up is required to drive this pin to a safe state during reset.
25.Pin must be pulled down during power-on reset, by pull down resistor of 2 K.26.The GND supply to these pins is not an actual supply pin, but a functional pin requires the GND supply connectivity. Pin must
be connected with a pull down resistor of 10 k.27.The SGND supply to these pins is not an actual supply pin, but a functional pin requires the SGND supply connectivity. 28.The OVDD supply to these pins is not an actual supply pin, but a functional pin requires the OVDD supply connectivity. 29.Functionally, this pin is an output or an input, but structurally it is an I/O because it either samples configuration input during
reset, is a muxed pin, or it has other manufacturing test functions. Therefore, this pin is described as an I/O for boundary scan.Recommend that a weak pull-up resistor (4.7-k) be placed on this pin to the respective power supply.
30.Recommend that a weak pull-up resistor (2-10 k) be placed on this pin to the respective power supply.31.Recommend that a weak pull-up resistor (1 k) be placed on this pin to the respective power supply.32.Must be pulled down externally (for any active CPRI lane that is not connected to an SFP).33.When configured as DUART (using RCW[UART_EXT] bits), pins are internally pulled down. When the pins are configured
as CP_LOSi, they should be pulled down externally for any active CPRI lane that is not connected to an SFP.34.When the thermal diode is not used, its pins (anode, cathode) should be connected to GND.
Table 1. Pinout list by bus (continued)
Signal name Signal descriptionPackage
pin number
Pin typePower supply
Notes
B4420 QorIQ Qonverge Data Sheet, Rev. 0
Pin assignments
Freescale Semiconductor48
WARNING
See Section 3.5, “Connection recommendations for unused pins,” for additional details on properly connecting these pins for specific applications.
1.3 Pinout list by package pin numberThis table provides the pinout list for the chip sorted by package pin number.
PLL supply voltage (SerDes) • SerDes1 PLL1 • SerDes2 PLL1
AVDD_SRDS1_PLL1AVDD_SRDS2_PLL1
–0.3 to 1.45/1.6 V —
Fuse programming override supply POVDD –0.3 to 1.99 V —
Thermal monitor unit supply TH_VDD –0.3 to 1.90 V 5
UART, I2C, CPRI LOS and GPIO I/O voltage DVDD –0.3 to 1.9 V/2.6 V —
IFC, SPI, (e)SDHC, MPIC, Trust, power management, clocking, debug, JTAG, CPRI SYNC/RCLK, 1588, Ethernet MI, USB ULPI, DMA, GPIO, system control I/O voltage
OVDD –0.3 to 1.9 V —
SYSCLK, PORESET_B I/O voltage QVDD –0.3 to 1.9 V —
DDR DRAM I/O voltage • DDR1 G1VDD
–0.3 to 1.45/1.6 V 2
Core power supply for SerDes receivers SVDD –0.3 to 1.1 V —
Pad power supply for SerDes transmitters XVDD –0.3 to 1.45/1.6 V —
Electrical characteristics
B4420 QorIQ Qonverge Data Sheet, Rev. 0
Freescale Semiconductor 65
2.1.2 Recommended operating conditions
This table provides the recommended operating conditions for this chip.
NOTE
The values shown are the recommended operating conditions. Proper device operation outside these conditions is not guaranteed.
Input voltage DDR DRAM signals MVIN –0.3 to (G1VDD + 0.3) V 2
DDR DRAM reference M1VREF –0.3 to (G1VDD/2 + 0.3) V —
UART, I2C, Ethernet MI1, CPRI LOS and GPIO signals
QVIN –0.3 to (DVDD + 0.3) V 3
SYSCLK and PORESET_B signals QVIN –0.3 to (QVDD + 0.3) V 4
IFC, SPI, (e)SDHC, MPIC, Trust, power management, clocking, debug, JTAG, CPRI SYNC/RCLK, 1588, USB ULPI, DMA, GPIO, system signals
OVIN –0.3 to (OVDD + 0.3) V 3
SerDes signals SVIN –0.4 to (SVDD + 0.3) V —
Storage junction temperature range Tstg –55 to 150 C —
Note:
1. Functional operating conditions are given in Table 4. Absolute maximum ratings are stress ratings only; functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause permanent damage to the device.
2. Caution: MVIN must not exceed G1VDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences.
3. Caution: OVIN must not exceed OVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences.
4. Caution: QVIN must not exceed QVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences.
5. The Thermal Monitoring Unit (TMU) supply is defeatured on this device. TH_VDD should be connected to an OVDD supply.
Table 4. Recommended operating conditions
Characteristic SymbolRecommended
ValueUnit Notes
Core and platform supply voltage At initial start-up VDD 1.05 V 30 mV V 4, 5, 6
During normal operation VID ± 30 mV V 1, 4, 5
PLL supply voltage (core, platform, DDR) AVDD_CGAnAVDD_CGBnAVDD_PLATAVDD_DDR1
1.8 V ± 90 mV V —
PLL supply voltage (SerDes, filtered from XnVDD) AVDD_SDRSn_PLLn 1.5 V ± 75 mV1.35 V ± 67 mV
V —
Fuse programming override supply POVDD 1.8 V ± 90 mV V 2
Operating temperature range Normal operation TA,TJ
TA = 0 (min) toTJ = 105 (max)
°C —
Extended Temperature TA,TJ
TA = -40 (min) toTJ = 105 (max)
°C —
Secure boot fuse programming TA,TJ
TA = 0 (min) toTJ = 70 (max)
°C 2
Note:
1. The Voltage ID (VID) operating range is between 0.95 V and 1.05 V. Regulator selection should be based on a Vout range of at least 0.9 V to 1.1 V, with resolution of 12.5 mV or better. See Section 3.2.1, “Voltage ID (VID) controllable supply” for more details.
2. POVDD must be supplied 1.8 V and the chip must operate in the specified fuse programming temperature range only –0 –70°C during secure boot fuse programming. For all other operating conditions, POVDD must be tied to GND, subject to the power sequencing constraints shown in Section 2.2, “Power sequencing.”
3. Ethernet MII management interface 2 pins function as open drain I/Os. The interface conforms to 1.2 V nominal voltage levels.4. See Section 3.2.2, “Core supply voltage filtering,” for additional information.
5. Supply voltage specified at the voltage sense pin. Voltage input pins should be regulated to provide specified voltage at the sense pin.
6. Operation at 1.05 V is allowable for up to 1 second at initial power on.
7. Add a bypass cap of 0.1uF on this power ball pin.
This figure shows the undershoot and overshoot voltages at the interfaces of the chip.
Figure 7. Overshoot/Undershoot voltage for DVDD/QVDD/OVDD/G1VDD
See Table 4 for actual recommended core voltage. Voltage to the processor interface I/Os are provided through separate sets of supply pins and must be provided at the voltages shown in Table 4. The input voltage threshold scales with respect to the associated I/O supply voltage. DVDD, QVDD, and OVDD-based receivers are simple CMOS I/O circuits and satisfy appropriate LVCMOS type specifications. The DDR SDRAM interface uses differential receivers referenced by the externally supplied M1VREF signal (nominally set to G1VDD/2) as is appropriate for the SSTL_1.35/SSTL_1.5 electrical signaling standard. The DDR DQS receivers cannot be operated in single-ended fashion. The complement signal must be properly driven and cannot be grounded.
2.1.3 Output driver characteristics
This chip provides information on the characteristics of the output driver strengths. These values are preliminary estimates.
Table 5. Output drive capability
Driver type Output impedance () Supply voltage Notes
DDR3 signal 18 (full-strength mode)27 (half-strength mode)
G1VDD= 1.5 V 1
GNDGND – 0.3 V
GND – 0.7 VNot to exceed 10%
[Nominal]D/Q/O/G1VDD + 20%
D/Q/O/G1VDD
D/Q/O/G1VDD + 5%
of tCLOCK
tCLOCK refers to the clock period associated with the respective interface:
VIH
VIL
Note:
For I2C and JTAG, tCLOCK refers to SYSCLK.
For DDR G1VDD, tCLOCK refers to Dn_DDRCLK.
For SerDes XVDD, tCLOCK refers to SD_REF_CLK.
For SPI OVDD, tCLOCK refers to SPI_CLK.
Electrical characteristics
B4420 QorIQ Qonverge Data Sheet, Rev. 0
Freescale Semiconductor 69
2.2 Power sequencing The chip requires that its power rails be applied in a specific sequence in order to ensure proper device operation. For power up, these requirements are as follows:
1. There are no restrictions on the order of Power supplies bringing up. During power up, drive POVDD = GND.
— PORESET_B input must be driven asserted and held during this step.
2. Negate PORESET_B input as long as the required assertion/hold time has been met per Table 13.
3. For secure boot fuse programming, use the following steps:
a) After negation of PORESET_B, drive POVDD = 1.8 V after a required minimum delay per Table 6.
b) After fuse programming is completed, it is required to return POVDD = GND before the system is power cycled (PORESET_B assertion) or powered down (VDD ramp down) per the required timing specified in Table 6. See Section 5, “Security fuse processor,” for additional details.
WARNING
No activity other than that required for secure boot fuse programming is permitted while POVDD is driven to any voltage above GND, including the reading of the fuse block. The reading of the fuse block may only occur while POVDD = GND.
From a system standpoint, if any of the I/O power supplies ramp prior to the VDD supply, the I/Os associated with that I/O supply may drive a logic one or zero during power-up, and extra current may be drawn by the device.
WARNING
Only 300,000 POR cycles are permitted per lifetime of a device. Note that this value is based on design estimates and is preliminary.
All supplies must be at their stable values within 75 ms.
DDR3L signal 18 (full-strength mode)27 (half-strength mode)
G1VDD = 1.35 V 1
IFC, eSPI, eSDHC, MPIC, Trust, power management, clocking, debug, JTAG, CPRI SYNC/RCLK, 1588, USB ULPI, DMA, GPIO, system control, Reset
1. The drive strength of the DDR3 or DDR3L interface in half-strength mode is at Tj = 105 C and at G1VDD (min).
Table 5. Output drive capability (continued)
Driver type Output impedance () Supply voltage Notes
B4420 QorIQ Qonverge Data Sheet, Rev. 0
Electrical characteristics
Freescale Semiconductor70
This figure provides the POVDD timing diagram.
Figure 8. POVDD timing diagram
This table provides information on the power-down and power-up sequence parameters for POVDD.
NOTE
While VDD is ramping, current may be supplied from VDD through the chip to G1VDD. Nevertheless, G1VDD from an external supply should follow the sequencing described above.
2.3 Power-down requirementsThe power-down cycle must complete such that power supply values are below 0.4 V before a new power-up cycle can be started.
If performing secure boot fuse programming per Section 2.2, “Power sequencing,” it is required that POVDD = GND before the system is power cycled (PORESET_B assertion) or powered down (VDD ramp down) per the required timing specified in Table 6.
Table 6. POVDD timing5
Driver type Min Max Unit Notes
tPOVDD_DELAY 100 — SYSCLKs 1
tPOVDD_PROG 0 — s 2
tPOVDD_VDD 0 — s 3
tPOVDD_RST 0 — s 4
Note:
1. Delay required from the deassertion of PORESET_B to driving POVDD ramp up. Delay measured from PORESET_B deassertion at 90% OVDD to 10% POVDD ramp up.
2. Delay required from fuse programming finished to POVDD ramp down start. Fuse programming must complete while POVDD is stable at 1.8 V. No activity other than that required for secure boot fuse programming is permitted while POVDD is driven to any voltage above GND, including the reading of the fuse block. The reading of the fuse block may only occur while POVDD = GND. After fuse programming is completed, it is required to return POVDD = GND.
3. Delay required from POVDD ramp down complete to VDD ramp down start. POVDD must be grounded to minimum 10% POVDD before VDD is at 90% VDD.
4. Delay required from POVDD ramp down complete to PORESET_B assertion. POVDD must be grounded to minimum 10% POVDD before PORESET_B assertion reaches 90% OVDD.
5. Only two secure boot fuse programming events are permitted per lifetime of a device.
tPOVDD_PROG
tPOVDD_DELAY
POVDD
VDD
tPOVDD_RST
Fuse programming
90% OVDD
10% POVDD10% POVDD
90% VDDtPOVDD_VDD
NOTE: POVDD must be stable at 1.8 V prior to initiating fuse programming.
90% OVDD
PORESET_B
Electrical characteristics
B4420 QorIQ Qonverge Data Sheet, Rev. 0
Freescale Semiconductor 71
2.4 Power characteristicsBecause it depends strongly on application type, the power characteristics for the average power and instantaneous peak current numbers are supplied by the device’s detailed power calculator.
2.5 Power-on ramp rateThis section describes the AC electrical specifications for the power-on ramp rate requirements. Controlling the maximum power-on ramp rate is required to avoid excess in-rush current.
This table provides the power supply ramp rate specifications.
2.6 Input clocks
2.6.1 System clock (SYSCLK) timing specifications
This section provides the system clock DC and AC timing specifications.
2.6.1.1 System clock DC timing specifications
This table provides the system clock (SYSCLK) DC specifications.
Table 7. Power supply ramp rate
Parameter Min Max Unit Notes
Required ramp rate for all voltage supplies (including OVDD/DVDD/ G1VDD/QVDD/SVDD/XVDD, core VDD supply, M1VREF and all AVDD supplies.)
— 25 V/ms 1, 2
Required ramp rate for POVDD — 25 V/ms 1, 2
Note:
1. Ramp rate is specified as a linear ramp from 10 to 90%. If nonlinear (for example, exponential), the maximum rate of change from 200 to 500 mV is the most critical as this range might falsely trigger the ESD circuitry. If needed to slow down the rate, usage of larger capacitors is recommended.
2. Over full recommended operating temperature range (see Table 4)
Table 8. SYSCLK DC electrical characteristics
At recommended operating conditions with QVDD = 1.8 V, see Table 4.
Parameter Symbol Min Typical Max Unit Notes
Input high voltage VIH 1.25 — — V 1
Input low voltage VIL — — 0.6 V 1
Input capacitance CIN — 7 12 pF —
Input current (OVIN= 0 V or OVIN = QVDD)
IIN — — 50 A 2
Note:
1. The min VILand max VIH values are based on the respective min and max QVIN values found in Table 4.
2. The symbol OVIN, in this case, represents the OVIN symbol referenced in Section 2.1.2, “Recommended operating conditions.”
B4420 QorIQ Qonverge Data Sheet, Rev. 0
Electrical characteristics
Freescale Semiconductor72
2.6.1.2 System clock AC timing specifications
This table provides the system clock (SYSCLK) AC timing specifications.
2.6.2 Spread-spectrum sources
Spread-spectrum clock sources are an increasingly popular way to control electromagnetic interference emissions (EMI) by spreading the emitted noise to a wider spectrum and reducing the peak noise magnitude in order to meet industry and government requirements. These clock sources intentionally add long-term jitter to diffuse the EMI spectral content. The jitter specification given in this table considers short-term (cycle-to-cycle) jitter only. The clock generator’s cycle-to-cycle output jitter should meet the chip’s input cycle-to-cycle jitter requirement. Frequency modulation and spread are separate concerns; the chip is compatible with spread spectrum sources if the recommendations listed in this table are observed.
CAUTION
The processor’s minimum and maximum SYSCLK and core/platform/DDR frequencies must not be exceeded regardless of the type of clock source. Therefore, systems in which the processor is operated at its maximum rated core/platform/DDR frequency should avoid violating the stated limits by using down-spreading only.
Table 9. SYSCLK AC timing specifications
At recommended operating conditions with OVDD = 1.8 V, see Table 4.
Parameter/Condition Symbol Min Typ Max Unit Notes
SYSCLK frequency fSYSCLK 66.667 — 133.333 MHz 1, 2
AC Input Swing Limits at 1.8 V QVDD VAC 0.35 x QVDD — 0.65 x QVDD V —
Notes:1. Caution: The relevant clock ratio settings must be chosen such that the resulting SYSCLK frequency do not exceed their
respective maximum or minimum operating frequencies.2. Measured at the rising edge and/or the falling edge at QVDD/2. 3. Slew rate is measured from 10% ~ 90% of VIL to VIH.4. Phase noise is calculated as FFT of TIE jitter.
At recommended operating conditions with OVDD = 1.8 V, see Table 4.
Parameter Min Max Unit Notes
Frequency modulation — 60 kHz —
Frequency spread — 1.0 % 1, 2
Notes: 1. SYSCLK frequencies that result from frequency spreading and the resulting core frequency must meet the minimum and
maximum specifications given in Table 9.2. Maximum spread spectrum frequency may not result in exceeding any maximum operating frequency of the device.
Electrical characteristics
B4420 QorIQ Qonverge Data Sheet, Rev. 0
Freescale Semiconductor 73
2.6.3 Real-time clock timing
The real-time clock timing (RTC) input is sampled by the platform clock. The output of the sampling latch is then used as an input to the counters of the MPIC and the time base unit of the core; there is no need for jitter specification. The minimum period of the RTC signal should be greater than or equal to 16 the period of the platform clock with a 50% duty cycle. There is no minimum RTC frequency; RTC may be grounded if not needed.
2.6.4 DDR clock timing
2.6.4.1 DDR D1_DDRCLK clock DC timing specifications
This table provides the system clock (MCLK) DC specifications.
2.6.4.2 DDR D1_DDRCLK clock AC timing specifications
This table provides the system clock (D1_DDRCLK) AC timing specifications.
Table 11. D1_DDRCLK3 DC electrical characteristics
At recommended operating conditions with OVDD = 1.8v, see Table 4.
Parameter Symbol Min Typical Max Unit Notes
Input high voltage VIH 1.25 — — V 1
Input low voltage VIL — — 0.6 V 1
Input capacitance CIN — 7 12 pF —
Input current (OVIN= 0 V or OVIN = OVDD)
IIN — — 50 A 2
Note:
1. The min VILand max VIH values are based on the respective min and max OVIN values found in Table 4.
2. The symbol OVIN, in this case, represents the OVIN symbol referenced in Section 2.1.2, “Recommended operating conditions.”
3. D1_DDRCLK must toggle in order to get out of PORESET, even if the DDR1 interface is not required. AVDD_DDR1 voltage must be supplied.
Table 12. D1_DDRCLK AC timing specifications
At recommended operating conditions with OVDD = 1.8V, see Table 4.
Parameter/Condition Symbol Min Typ Max Unit Notes
D1_DDRCLK frequency fMCLK 66.667 — 133.333 MHz 1, 2
D1_DDRCLK cycle time tMCLK 7.5 — 15 ns 1, 2
D1_DDRCLK duty cycle tKHK/tMCLK 40 50 60 % 2
D1_DDRCLK slew rate — 1 — 4 V/ns 3
B4420 QorIQ Qonverge Data Sheet, Rev. 0
Electrical characteristics
Freescale Semiconductor74
2.6.5 Other input clocks
A description of the overall clocking of this device is available in the chip reference manual in the form of a clock subsystem block diagram. For information about the input clock requirements of functional modules sourced external of the chip, such as SerDes, I2C, eSDHC, IFC, USB, and 1588, see the specific interface section.
2.7 RESET initializationThis table describes the AC electrical specifications for the RESET initialization timing.
D1_DDRCLK peak period jitter — — — 150 ps —
D1_DDRCLK jitter phase noise at –56 dBc
— — — 500 KHz 4
AC Input Swing Limits at 1.8 V OVDD VAC 0.35 x OVDD — 0.65 x OVDD V —
Notes:1. Caution: The relevant clock ratio settings must be chosen such that the resulting D1_DDRCLK frequency do not exceed
their respective maximum or minimum operating frequencies.2. Measured at the rising edge and/or the falling edge at OVDD/2. 3. Slew rate is measured from 10% ~ 90% of VIL to VIH.4. Phase noise is calculated as FFT of TIE jitter.
Required input assertion time of HRESET_B 32 — SYSCLKs 1, 2
Maximum rise/fall time of HRESET_B — 1 SYSCLK 4
PLL input setup time with stable SYSCLK before HRESET_B negation 100 — s —
Input setup time for POR configs with respect to negation of PORESET_B
4 — SYSCLKs 1
Input hold time for all POR configs with respect to negation of PORESET_B
2 — SYSCLKs 1
Maximum valid-to-high impedance time for actively driven POR configs with respect to negation of PORESET_B
— 5 SYSCLKs 1
Notes:
1. SYSCLK is the primary clock input for the chip.
2. The device asserts HRESET_B as an output when PORESET_B is asserted to initiate the power-on reset process. The device releases HRESET_B sometime after PORESET_B is deasserted. The exact sequencing of HRESET_B deassertion is documented in the “Power-On Reset Sequence” section of the chip reference manual.
3. PORESET_B must be driven asserted before the core and platform power supplies are powered up.
4. The system/board must be designed to ensure the input requirement to the device is achieved. Proper device operation is guaranteed for inputs meeting this requirement by design, simulation, characterization, or functional testing.
Table 12. D1_DDRCLK AC timing specifications (continued)
At recommended operating conditions with OVDD = 1.8V, see Table 4.
Parameter/Condition Symbol Min Typ Max Unit Notes
Electrical characteristics
B4420 QorIQ Qonverge Data Sheet, Rev. 0
Freescale Semiconductor 75
This table provides the PLL lock times.
2.8 DDR3 and DDR3L SDRAM controllerThis section describes the DC and AC electrical specifications for the DDR3 and DDR3L SDRAM controller interface. Note that the required G1VDD(typ) voltage is 1.5 V when interfacing to DDR3 SDRAM and the G1VDD(typ) voltage is 1.35 V when interfacing to DDR3L SDRAM.
NOTE
When operating at DDR data rates of 1866 MT/s, only one dual-ranked module per memory controller is supported.
2.8.1 DDR3 and DDR3L SDRAM interface DC electrical characteristics
This table provides the recommended operating conditions for the DDR SDRAM controller when interfacing to DDR3 SDRAM.
For recommended operating conditions, see Table 4.
Parameter Symbol Min Max Unit Note
I/O reference voltage M1VREF 0.49 G1VDD 0.51 G1VDD V 2, 3, 4
Input high voltage VIH M1VREF + 0.100 G1VDD V 5
Input low voltage VIL GND M1VREF – 0.100 V 5
I/O leakage current IOZ –100 100 A 6
Notes:
1. G1VDD is expected to be within 50 mV of the DRAM’s voltage supply at all times. The DRAM’s and memory controller’s voltage supply may or may not be from the same source.
2. M1VREF is expected to be equal to 0.5 G1VDD and to track G1VDD DC variations as measured at the receiver. Peak-to-peak noise on M1VREF may not exceed the M1VREF DC level by more than ±1% of the DC value (that is, ±15 mV).
3. VTT is not applied directly to the device. It is the supply to which far end signal termination is made, and it is expected to be equal to M1VREF with a min value of M1VREF – 0.04 and a max value of M1VREF + 0.04. VTT should track variations in the DC level of M1VREF.
4. The voltage regulator for M1VREF must meet the specifications stated in Table 18.
5. Input capacitance load for DQ, DQS, and DQS_B are available in the IBIS models.6. Output leakage is measured with all outputs disabled, 0 V VOUT G1VDD.
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This table provides the recommended operating conditions for the DDR SDRAM controller when interfacing to DDR3L SDRAM.
This table provides the DDR controller interface capacitance for DDR3 and DDR3L.
This table provides the current draw characteristics for M1VREF.
For recommended operating conditions, see Table 4.
Parameter Symbol Min Max Unit Note
I/O reference voltage M1VREF 0.49 G1VDD 0.51 G1VDD V 2, 3, 4
Input high voltage VIH M1VREF + 0.090 G1VDD V 5
Input low voltage VIL GND M1VREF – 0.090 V 5
I/O leakage current IOZ –100 100 A 6
Output high current (VOUT = 0.641V) IOH — –23.3 mA 7, 8
Output low current (VOUT =0.641 V) IOL 23.3 — mA 7, 8
Notes:
1. G1VDD is expected to be within 50 mV of the DRAM’s voltage supply at all times. The DRAM’s and memory controller’s voltage supply may or may not be from the same source.
2. M1VREF is expected to be equal to 0.5 G1VDD and to track G1VDD DC variations as measured at the receiver. Peak-to-peak noise on M1VREF may not exceed the M1VREF DC level by more than ±1% of the DC value (that is, ±13.5mV).
3. VTT is not applied directly to the device. It is the supply to which far end signal termination is made, and it is expected to be equal to M1VREF with a min value of M1VREF – 0.04 and a max value of M1VREF + 0.04. VTT should track variations in the DC level of M1VREF.
4. The voltage regulator for M1VREF must meet the specifications stated in Table 18.
5. Input capacitance load for DQ, DQS, and DQS_B are available in the IBIS models.6. Output leakage is measured with all outputs disabled, 0 V VOUT G1VDD.
7. See the IBIS model for the complete output IV curve characteristics.
8. IOH and IOL are measured at G1VDD = 1.283 V.
Table 17. DDR3 and DDR3L SDRAM capacitance
For recommended operating conditions, see Table 4.
For recommended operating conditions, see Table 4.
Parameter Symbol Min Max Unit Notes
Current draw for DDR3 SDRAM for M1VREF IM1VREF — 500 A —
Current draw for DDR3L SDRAM for M1VREF IM1VREF — 500 A —
Electrical characteristics
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2.8.2 DDR3 and DDR3L SDRAM interface AC timing specifications
This section provides the AC timing specifications for the DDR SDRAM controller interface. The DDR controller supports DDR3 and DDR3L memories. Note that the required G1VDD(typ) voltage is 1.5 V when interfacing to DDR3 SDRAM and the required G1VDD(typ) voltage is 1.35 V when interfacing to DDR3L SDRAM.
2.8.2.1 DDR3 and DDR3L SDRAM interface input AC timing specifications
This table provides the input AC timing specifications for the DDR controller when interfacing to DDR3 SDRAM.
Table 19. DDR3 and DDR3L SDRAM interface input AC timing specifications
For recommended operating conditions, see Table 4.
Parameter Symbol Min Max Unit Notes
Controller Skew for MDQS—MDQ/MECC tCISKEW ps 1
1600 MT/s data rate –112 112
1333 MT/s data rate –125 125
1200 MT/s data rate –142 142
1066 MT/s data rate –170 170
Tolerated Skew for MDQS—MDQ/MECC tDISKEW ps 2
1600 MT/s data rate –200 200
1333 MT/s data rate –250 250
1200 MT/s data rate –275 275
1066 MT/s data rate –300 300
Note:
1. tCISKEW represents the total amount of skew consumed by the controller between MDQS[n] and any corresponding bit that is captured with MDQS[n]. This must be subtracted from the total timing budget.
2. The amount of skew that can be tolerated from MDQS to a corresponding MDQ signal is called tDISKEW.This can be determined by the following equation: tDISKEW = ±(T 4 – abs(tCISKEW)), where T is the clock period and abs(tCISKEW) is the absolute value of tCISKEW.
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This figure shows the DDR3 and DDR3L SDRAM interface input timing diagram.
Figure 9. DDR3 and DDR3L SDRAM interface input timing diagram
2.8.2.2 DDR3 and DDR3L SDRAM interface output AC timing specifications
This table contains the output AC timing targets for the DDR3 SDRAM interface.
Table 20. DDR3 and DDR3L SDRAM interface output AC timing specifications
For recommended operating conditions, see Table 4
Parameter Symbol1 Min Max Unit Notes
MCK[n] cycle time tMCK 1.072 1.876 ns 2
ADDR/CMD output setup with respect to MCK tDDKHAS ns 3
1600 MT/s data rate 0.495 —
1333 MT/s data rate 0.606 —
1200 MT/s data rate 0.675 —
1066 MT/s data rate 0.744 —
ADDR/CMD output hold with respect to MCK tDDKHAX ns 3
For the ADDR/CMD setup and hold specifications in Table 20, it is assumed that the clock control register is set to adjust the memory clocks by ½ applied cycle.
This figure shows the DDR3 and DDR3L SDRAM interface output timing for the MCK to MDQS skew measurement (tDDKHMH).
1333 MT/s data rate 0.500 —
1200 MT/s data rate 0.550 —
1066 MT/s data rate 0.600 —
MDQS preamble tDDKHMP 0.9 x tMCK — ns —
MDQS postamble tDDKHME 0.4 x tMCK 0.6 x tMCK ns —
Note:
1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. Output hold time can be read as DDR timing (DD) from the rising or falling edge of the reference clock (KH or KL) until the output went invalid (AX or DX). For example, tDDKHAS symbolizes DDR timing (DD) for the time tMCK memory clock reference (K) goes from the high (H) state until outputs (A) are setup (S) or output valid time.
2. All MCK/MCK_B and MDQS/MDQS_B referenced measurements are made from the crossing of the two signals.3. ADDR/CMD includes all DDR SDRAM output signals except MCK/MCK_B, MCS_B, and MDQ/MECC/MDM/MDQS.
4. Note that tDDKHMH follows the symbol conventions described in note 1. For example, tDDKHMH describes the DDR timing (DD) from the rising edge of the MCK[n] clock (KH) until the MDQS signal is valid (MH). tDDKHMH can be modified through control of the MDQS override bits (called WR_DATA_DELAY) in the TIMING_CFG_2 register. This is typically set to the same delay as in DDR_SDRAM_CLK_CNTL[CLK_ADJUST]. The timing parameters listed in the table assume that these two parameters have been set to the same adjustment value. See the chip reference manual for a description and explanation of the timing modifications enabled by use of these bits.
5. Available eye for data (MDQ), ECC (MECC), and data mask (MDM) outputs at the pin of the processor. Memory controller
will center the strobe (MDQS) in the available data eye at the DRAM (end point) during the initialization.
6. For data rates of 1200 MT/s and higher, it is required to program the start value of the DQS adjust for write leveling.
Table 20. DDR3 and DDR3L SDRAM interface output AC timing specifications (continued)
For recommended operating conditions, see Table 4
Parameter Symbol1 Min Max Unit Notes
MDQS
MCK[n]
MCK[n]tMCK
MDQS
tDDKHMH(max)
tDDKHMH(min)
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Figure 10. tDDKHMH timing diagram
This figure shows the DDR3 and DDR3L SDRAM output timing diagram.
Figure 11. DDR3 and DDR3L output timing diagram
ADDR/CMD
tDDKHAS, tDDKHCS
tDDKLDS
tDDKHDS
MDQ[x]
MDQS[n]
MCK_B
MCKtMCK
tDDKLDX
tDDKHDX
D1D0
tDDKHAX, tDDKHCX
Write A0 NOOP
tDDKHME
tDDKHMH
tDDKHMP
VTR
VCP
GND
G1VDD
VOX or VIX
G1VDD/2
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2.9 DC electrical characteristics
2.9.1 DC characteristics for 1.8 V IO cells
This table provides the DC electrical characteristics for the IFC, SPI, MPIC, Trust, power management, clocking, debug, JTAG, CPRI SYNC/RCLK, 1588, eSDHC, USB ULPI, DMA, Timers, UART and GPIO interface operating at VDDIO = OVDD/QVDD/DVDD= 1.8 V.
2.9.2 DC characteristics for 2.5 V IO cells
This table provides the DC electrical characteristics for the UART, Ethernet MI1, and GPIO interface operating at DVDD = 2.5 V.
Table 21. DC electrical characteristics (1.8 V)
For recommended operating conditions, see Table 4.
Parameter Symbol Min Typ Max Unit Notes
High-level output voltage VOH — — V —
IOH = 1 mA VDDIOMIN – 0.15
IOH = 2 mA VDDIOMIN x 0.8
IOH = -100uA VDDIOMIN – 0.2 3
Low-level output voltage VOL — — V —
IOL = 1 mA 0.15
IOL = 2 mA 0.2 x VDDIOMAX
IOL = 2 mA 0.3 3
Input current (VIN = 0 V or VIN = OVDD/QVDD/DVDD) IIN — — ±50 A 2
High-level DC input voltage VIH 0.7 x VDDIOMAX — — V 1
Low-level DC input voltage VIL — — 0.3 x VDDIOMIN V 1
Note:
1. The min VILand max VIH values are based on the respective min and max OVIN/QVIN values found in Table 4.
2. The symbol VIN, in this case, represents the OVIN/QVIN symbol referenced in Section 2.1.2, “Recommended operating conditions.”
3. eSDHC protocol open-drain mode for MMC cards only.
Table 22. DC electrical characteristics (2.5 V)
For recommended operating conditions, see Table 4.
Parameter Symbol Min Typ Max Unit Notes
High-level output voltage VOH — — V —
IOH = 1 mA VDDIOMIN – 0.15
IOH = 2 mA VDDIOMIN x 0.8
Low-level output voltage VOL — — V —
IOL = 1 mA 0.15
IOL = 2 mA 0.2 x VDDIOMAX
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2.10 eSPI interfaceThis section describes the AC electrical specifications for the eSPI interface.
2.10.1 eSPI AC timing specifications
This table provides the eSPI input and output AC timing specifications.
Input current (VIN = 0 V or VIN = OVDD/QVDD/DVDD) IIN — — ±50 A 2
High-level DC input voltage VIH 0.7 x VDDIOMAX — — V 1
Low-level DC input voltage VIL — — 0.3 x VDDIOMIN V 1
Note:
1. The min VILand max VIH values are based on the respective min and max QVIN values found in Table 4.
2. The symbol VIN, in this case, represents the QVIN symbol referenced in Section 2.1.2, “Recommended operating conditions.”
Table 23. eSPI AC timing specifications1
Characteristic Symbol 2 Min Max Unit Note
SPI_MOSI output—Master data (internal clock) hold time
tNIKHOX n1 + (tPLATFORM_CLK/2 * SPMODE[HO_ADJ])
— ns 2, 3, 4
SPI_MOSI output—Master data (internal clock) delay
tNIKHOV — n2 + (tPLATFORM_CLK/2 * SPMODE[HO_ADJ])
ns 2, 3, 4
SPI_CS outputs—Master data (internal clock) hold time
tNIKHOX2 0 — ns 2
SPI_CS outputs—Master data (internal clock) delay
tNIKHOV2 — 8.5 ns 2, 5
SPI inputs—Master data (internal clock) input setup time
tNIIVKH 5 — ns —
SPI inputs—Master data (internal clock) input hold time
tNIIXKH 0 — ns —
Clock-high/low time tNIKCKH/tNIKCKL
4 — ns —
Table 22. DC electrical characteristics (2.5 V) (continued)
For recommended operating conditions, see Table 4.
Parameter Symbol Min Typ Max Unit Notes
Electrical characteristics
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This figure provides the AC test load for the eSPI.
Figure 12. eSPI AC test load
This figure provides the eSPI clock output timing diagram.
Figure 13. eSPI clock output timing diagram
CLKOUT period SPI_CLK 12 — ns —
Notes:
1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tNIKHOV symbolizes the NMSI outputs internal timing (NI) for the time tSPI memory clock reference (K) goes from the high state (H) until outputs (O) are valid (V).
2. Output specifications are measured from the 50% level of the rising edge of SPI_CLK to the 50% level of the signal. Timings are measured at the pin.
3. See the chip reference manual for details about the SPMODE register.
4. The optimal n1 and n2 values are –1.0 and 1.0, respectively, based on the AC timing specifications for the majority of the SPI flash devices on the market.
5. The SPI_CS signal is asserted/negated long enough before/after the actual data transmit that there is no problem with SPI_CS timing constraints.
Table 23. eSPI AC timing specifications1 (continued)
Characteristic Symbol 2 Min Max Unit Note
Output Z0 = 50 OVDD/2RL = 50
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This figure represents the AC timing from Table 23 in master mode (internal clock). Note that although the specifications generally reference the rising edge of the clock, these AC timing diagrams also apply when the falling edge is the active edge. Also, note that the clock edge is selectable on eSPI.
Figure 14. eSPI AC timing in master mode (internal clock) diagram
2.11 DUART interfaceThis section describes the AC electrical specifications for the DUART interface.
2.11.1 UART AC electrical specifications
This table provides the AC timing parameters for the UART interface.
This section provides the AC and DC electrical characteristics for the Ethernet controller and the Ethernet management interface.
Table 24. UART AC timing specifications
Parameter Value Unit Notes
Minimum baud rate fPLAT/(2 × 1,048,576) baud 1, 3
Maximum baud rate fPLAT/(2 × 16) baud 1, 2
Notes:
1. fPLAT refers to the internal platform clock. 2. The actual attainable baud rate is limited by the latency of interrupt processing.3. The middle of a start bit is detected as the eighth sampled 0 after the 1-to-0 transition of the start bit. Subsequent bit values
are sampled each 16th sample.
SPI_CLK (output)
tNIIXKH
tNIKHOV
Input signals:SPI_MISO
Output signals:SPI_MOSI
tNIIVKH
tNIKHOX
Output signals:SPI_CS[0:3]
tNIKHOV2 tNIKHOX2
Electrical characteristics
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2.12.1 SGMII electrical specifications
See Section 2.23.6, “SGMII interface.”
2.12.2 Ethernet management interface (EMI)
This section discusses the electrical characteristics for the EMI1 interface.
EMI1 is the PHY management interface controlled by the MDIO controller associated with Frame Manager GMAC1-3.
Table 22, “DC electrical characteristics (2.5 V),” provides the Ethernet Management interface EMI1 DC electrical characteristics.
2.12.2.1 Ethernet management interface 1 AC electrical specifications
This table provides the Ethernet management interface 1 AC electrical characteristics.
Table 25. Ethernet management interface 1 AC timing specifications 6
Parameter/Condition Symbol1 Min Typ Max Unit Notes
1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs and t(first
two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMDKHDX symbolizes management data timing (MD) for the time tMDC from clock reference (K) high (H) until data outputs (D) are invalid (X) or data hold time.Also, tMDDVKH symbolizes management data timing (MD) with respect to the time data input signals (D) reach the valid state(V) relative to the tMDC
clock reference (K) going to the high (H) state or setup time.2. This parameter is dependent on the Ethernet clock frequency. MDIO_CFG [MDIO_CLK_DIV] field determines the clock
frequency of the MgmtClk Clock MDIO_MDC.In Rev2 the default value of MDIO_CFG [MDIO_CLK_DIV] is 0 means no clock is available. Recommended to configure this field in PBL.
3. This parameter is dependent on the Ethernet clock frequency. The delay is equal to Y x Ethernet clock periods ±4 ns. For example, with an Ethernet clock of 333 MHz, the min/max delay is (5 x 1/333M) = 15 ns ± 4 ns.Default values for Rev 1: silicon:MDIO_CFG[MDIO_HOLD] = 3’b010 which selects 5 tenet_clk cyclesDefault values for Rev 2 silicon:MDIO_CFG[MDIO_HOLD] = 3’b010 which selects 5 tenet_clk cyclesMDIO_CFG[NEG] = 1MDIO_CFG[EHOLD] = 0For Rev 1 silicon: Y = MDIO_CFG[MDIO_HOLD]For Rev 2 silicon:If MDIO_CFG[EHOLD] = 0 then Y = MDIO_CFG[MDIO_HOLD] If MDIO_CFG[EHOLD] = 1 then Y = 8 x MDIO_CFG[MDIO_HOLD] +14. tMDKHDX transition:
For Rev 1 silicon: tMDKHDX is MDC positive edge to MDIO transitionFor Rev 2 silicon:If MDIO_CFG[NEG] = 0 then tMDKHDX is MDC positive edge to MDIO transitionIf MDIO_CFG[NEG] = 1 then tMDKHDX is MDC negative edge to MDIO transition5. tenet_clk is the Ethernet clock period derived from Frame Manger clock, FM clock. tenet_clk=1/2 × FM_clock.6. For recommended operating conditions, see Table 4.
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This figure shows the Ethernet management interface timing diagram.
Notes:1.TRX_CLK is the maximum clock period of Ethernet receiving clock selected by TMR_CTRL[CKSEL]. See the chip reference
manual for a description of TMR_CTRL registers.2. It needs to be at least two times the clock period of the clock selected by TMR_CTRL[CKSEL]. See the chip reference manual
for a description of the TMR_CTRL registers.3. The maximum value of tT1588CLK is not only defined by the value of TRX_CLK, but also defined by the recovered clock. For
example, for 10/100/1000 Mbps modes, the maximum value of tT1588CLK are 2800, 280, and 56 ns, respectively.
Table 26. IEEE 1588 AC timing specifications (continued)
For recommended operating conditions, see Table 4.
Parameter/Condition Symbol Min Typ Max Unit Notes
TSEC_1588_CLK_OUT
TSEC_1588_PULSE_OUTTSEC_1588_ALARM_OUT
tT1588OV
tT1588CLKOUT
tT1588CLKOUTH
Note: The output delay is counted starting at the rising edge if tT1588CLKOUT is non-inverting. Otherwise, itis counted starting at the falling edge.
TSEC_1588_TRIG_IN
tT1588TRIGH
tT1588CLK
tT1588CLKH
TSEC_1588_CLK
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2.13.1 USB AC electrical specifications
This table describes the general timing parameters of the USB interface of the device.
The following two figures provide the USB AC test load and signals, respectively.
Figure 18. USB AC test load
Table 27. USB general timing parameters (ULPI mode only) 1,6
For recommended operating conditions, see Table 4.
Parameter Symbol1 Min Max Unit Notes
USB clock cycle time tUSCK 15 — ns 2, 3, 4, 5
Input setup to USB clock—all inputs tUSIVKH 4 — ns 2, 3, 4, 5
Input hold to USB clock—all inputs tUSIXKH 1 — ns 2, 3, 4, 5
USB clock to output valid—all outputs tUSKHOV — 7 ns 2, 3, 4, 5
Output hold from USB clock—all outputs tUSKHOX 2 — ns 2, 3, 4, 5
Note:
1. The symbols for timing specifications follow the pattern of t(First two letters of functional block)(signal)(state) (reference)(state) for inputs and t(First two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tUSIXKH symbolizes USB timing (US) for the input (I) to go invalid (X) with respect to the time the USB clock reference (K) goes high (H). Also, tUSKHOX symbolizes USB timing (US) for the USB clock reference (K) to go high (H) with respect to the output (O) going invalid (X) or output hold time.
2. All timings are in reference to the USB clock.3. All signals are measured from OVDD/2 of the rising edge of the USB clock to OVDD/2 of the signal.
4. Input timings are measured at the pin.
5. For active/float timing measurements, the high impedance or off state is defined to be when the total current delivered through the component pin is less than or equal to that of the leakage current specification.
6. When switching the data pins from outputs to inputs using the USBn_DIR pin, the output timings are violated on that cycle because the output buffers are tristated asynchronously. This should not be a problem, because the PHY should not be functionally looking at these signals on that cycle as per the ULPI specifications.
Output Z0 = 50 OVDD/2RL = 50
Electrical characteristics
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Freescale Semiconductor 89
Figure 19. USB signals
2.14 Integrated flash controllerThis section describes the AC electrical specifications for the integrated flash controller.
2.14.1 Integrated flash controller AC timing specifications
This section describes the AC timing specifications for the integrated flash controller.
All output signal timings are relative to the falling edge of any IFC_CLK. The external circuit must use the rising edge of the IFC_CLKs to latch the data.
All input timings are relative to the rising edge of IFC_CLKs.
This table describes the timing specifications of the integrated flash controller interface.
IFC_CLK[n] skew to IFC_CLK[m] tIBKSKEW — ± 75 ps 2
Input setup tIBIVKH 4 — ns —
Input hold tIBIXKH 1 — ns —
Output signals:
tUSKHOV
USB_CLK
Input signals
tUSIXKHtUSIVKH
tUSKHOX
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This figure shows the AC timing diagram.
Figure 20. Integrated flash controller signals
Output delay tIBKLOV — 1.5 ns —
Output hold tIBKLOX –2 — ns 4
IFC_CLK to output high impedance for AD tIBKLOZ — 2 ns 3
Note:
1. All signals are measured from OVDD/2 of rising/falling edge of IFC_CLK to OVDD/2 of the signal in question.
2. Skew is measured between different IFC_CLK signals at OVDD/2.3. For purposes of active/float timing measurements, the high impedance or off state is defined to be when the total current
delivered through the component pin is less than or equal to the leakage current specification.4. Here the negative sign means that the output transit happens earlier than the falling edge of IFC_CLK.
Figure 20 applies to all the controllers that IFC supports.
• For input signals, the AC timing data is used directly for all controllers.
• For output signals, each type of controller provides its own unique method to control the signal timing. The final signal delay value for output signals is the programmed delay plus the AC timing delay.
This figure shows how the AC timing diagram applies to GPCM. The same principle also applies to other controllers of IFC.
1 taco, trad, teahc, teadc, tacse, tcs, tch, twp are programmable. See the chip reference manual.2 For output signals, each type of controller provides its own unique method to control the signal timing. The final signal delay
value for output signals is the programmed delay plus the AC timing delay.
Figure 21. GPCM output timing diagram
2.14.2 Test condition
This figure provides the AC test load for the integrated flash controller.
Figure 22. Integrated flash controller AC test load
2.15 Enhanced secure digital host controller (eSDHC)This section describes the AC electrical specifications for the eSDHC interface. For the DC electrical specifications, see Table 21.
trad + tIBKHOV
IFC_CLK
AD
BCTL
CE_B
OE_B
address
taco + tIBKLOV
WE_B
tacse + tIBKLOV
address
tcs+ tIBKLOV
read data write data
tch + tIBKLOV
twp + tIBKLOV
writeread
AVDteadc + tIBKLOV
teahc + tIBKLOV
Output Z0 = 50 OVDD/2RL = 50
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2.15.1 eSDHC AC timing specifications
This table provides the eSDHC AC timing specifications as defined in Figure 23.
This figure provides the eSDHC clock input timing diagram.
Figure 23. eSDHC clock input timing diagram
Table 29. eSDHC AC timing specifications
For recommended operating conditions, see Table 4.
1. The symbols used for timing specifications herein follow the pattern of t(first three letters of functional block)(signal)(state) (reference)(state) for inputs and t(first three letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tFHSKHOV symbolizes eSDHC high-speed mode device timing (SHS) clock reference (K) going to the high (H) state, with respect to the output (O) reaching the invalid state (X) or output hold time. Note that in general, the clock reference symbol is based on five letters representing the clock of a particular functional. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
2. In full-speed mode, the clock frequency value can be 0–20 MHz for an MMC card. In high-speed mode, the clock frequency value can be 0–52 MHz for an MMC card.
3. To satisfy setup timing, one-way board-routing delay between Host and Card, on SDHC_CLK, SDHC_CMD, and SDHC_DATx should not exceed 1 ns.
1. MPIC inputs and outputs are asynchronous to any visible clock. MPIC outputs must be synchronized before use by any external synchronous logic. MPIC inputs are required to be valid for at least tPIWID ns to ensure proper operation when working in edge triggered mode
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2.17.1 JTAG AC timing specifications
This table provides the JTAG AC timing specifications as defined in Figure 25 through Figure 28.
This figure provides the AC test load for TDO and the boundary-scan outputs of the device.
Figure 25. AC test load for the JTAG interface
Table 31. JTAG AC timing specifications
For recommended operating conditions, see Table 4
Parameter Symbol1 Min Max Unit Notes
JTAG external clock frequency of operation fJTG 0 20 MHz —
JTAG external clock cycle time tJTG 50 — ns —
JTAG external clock pulse width measured at 1.4 V tJTKHKL 25 — ns —
JTAG external clock rise and fall times tJTGR/tJTGF 0 2 ns —
TRST_B assert time tTRST 50 — ns 2
Input setup times tJTDVKH 4 — ns —
Input hold time for TDI/TMS tJTDXKH1 13 — ns —
Input hold time for boundary-scan data tJTDXKH2 15 — ns —
Output valid times
TCK to TDO output valid time tJTKLDV1 — 13 ns 4
TCK to boundary-scan data out times tJTKLDV2 — 34
Output hold times tJTKLDX 0 — ns 3
Note:
1. The symbols used for timing specifications follow the pattern t(first two letters of functional block)(signal)(state)(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tJTDVKH symbolizes JTAG device timing (JT) with respect to the time data input signals (D) reaching the valid state (V) relative to the tJTG clock reference (K) going to the high (H) state or setup time. Also, tJTDXKH symbolizes JTAG timing (JT) with respect to the time data input signals (D) reaching the invalid state (X) relative to the tJTG clock reference (K) going to the high (H) state. Note that in general, the clock reference symbol representation is based on three letters representing the clock of a particular functional. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
2. TRST_B is an asynchronous level sensitive signal. The setup time is for test purposes only.
3. All outputs are measured from the midpoint voltage of the falling edge of tTCLK to the midpoint of the signal in question. The output timings are measured at the pins. All output timings assume a purely resistive 50-load. Time-of-flight delays must be added for trace lengths, vias, and connectors in the system.
4. Due to value of tJTKLDV1, after Update-IR or Update-DR transitions for EXTEST* or CLAMP instructions, a transition
through the optional Run-Test-Idle state is recommended to allow for board level propagation and setup times of observationpoints.
Output Z0 = 50 OVDD/2RL = 50
Electrical characteristics
B4420 QorIQ Qonverge Data Sheet, Rev. 0
Freescale Semiconductor 95
This figure provides the JTAG clock input timing diagram.
Figure 26. JTAG clock input timing diagram
This figure provides the TRST_B timing diagram.
Figure 27. TRST_B timing diagram
This figure provides the TDI/TMS/TDO and boundary-scan data timing diagram.
Figure 28. TDI/TMS/TDO and boundary-scan timing diagram
JTAG
tJTKHKL tJTGR
external clock VMVMVM
tJTG tJTGF
VM = Midpoint voltage (OVDD/2)
TRST_B
VM = Midpoint Voltage (OVDD/2)
VM VM
tTRST
VM = midpoint voltage (OVDD/2)
VM VM
tJTDVKHtJTDXKH2
TDO and boundarydata outputs
JTAGexternal clock
boundarydata inputs
Output data valid
tJTKLDX
Inputdata valid
TDI/TMS and
tJTKLDV2
tJTKLDV1
tJTDXKH1
B4420 QorIQ Qonverge Data Sheet, Rev. 0
Electrical characteristics
Freescale Semiconductor96
2.18 I2C interfaceThis section describes the DC and AC electrical characteristics for the I2C interface.
2.18.1 I2C DC electrical characteristics
This table provides the DC electrical characteristics for the I2C interfaces operating at 2.5 V.
This table provides the DC electrical characteristics for the I2C interfaces operating at 1.8 V.
Table 32. I2C DC electrical characteristics (DVDD = 2.5 V)
For recommended operating conditions, see Table 4.
Parameter Symbol Min Max Unit Notes
Input high voltage VIH 1.7 — V 1
Input low voltage VIL — 0.7 V 1
Output low voltage (DVDD = min, IOL = 3 mA) VOL 0 0.4 V 2
Pulse width of spikes which must be suppressed by the input filter tI2KHKL 0 50 ns 3
Input current each I/O pin (input voltage is between 0.1 DVDD and 0.9 DVDD(max)
IIN — ±50 A 4
Capacitance for each I/O pin CI — 10 pF —
Notes:
1. The min VILand max VIH values are based on the respective min and max QVIN values found in Table 4.
2. Output voltage (open drain or open collector) condition = 2 mA sink current.
3. See the chip reference manual for information about the digital filter used.4. I/O pins obstruct the SDA and SCL lines if DVDD is switched off.
Table 33. I2C DC electrical characteristics (DVDD = 1.8 V)
For recommended operating conditions, see Table 4.
Parameter Symbol Min Max Unit Notes
Input high voltage VIH 1.25 — V 1
Input low voltage VIL — 0.6 V 1
Output low voltage (DVDD = min, IOL = 1 mA) VOL 0 0.36 V 2
Pulse width of spikes which must be suppressed by the input filter tI2KHKL 0 50 ns 3
Input current each I/O pin (input voltage is between 0.1 DVDD and 0.9 DVDD(max)
IIN — ±50 A 4
Capacitance for each I/O pin CI — 10 pF —
Notes:
1. The min VILand max VIH values are based on the respective min and max QVIN values found in Table 4.
2. Output voltage (open drain or open collector) condition = 2 mA sink current.
3. See the chip reference manual for information about the digital filter used.4. I/O pins obstruct the SDA and SCL lines if DVDD is switched off.
Electrical characteristics
B4420 QorIQ Qonverge Data Sheet, Rev. 0
Freescale Semiconductor 97
2.18.2 I2C AC timing specifications
This table provides the AC timing parameters for the I2C interfaces.
Table 34. I2C AC timing specifications
For recommended operating conditions, see Table 4.
Parameter Symbol1 Min Max Unit Notes
SCL clock frequency fI2C 0 400 kHz 2
Low period of the SCL clock tI2CL 1.3 — s —
High period of the SCL clock tI2CH 0.6 — s —
Setup time for a repeated START condition tI2SVKH 0.6 — s —
Hold time (repeated) START condition (after this period, the first clock pulse is generated)
tI2SXKL 0.6 — s —
Data setup time tI2DVKH 100 — ns —
Data input hold time:CBUS compatible masters
I2C bus devices
tI2DXKL—0
——
s 3
Data output delay time tI2OVKL — 0.9 s 4
Setup time for STOP condition tI2PVKH 0.6 — s —
Bus free time between a STOP and START condition tI2KHDX 1.3 — s —
Noise margin at the LOW level for each connected device (including hysteresis)
VNL 0.1 DVDD — V —
Noise margin at the HIGH level for each connected device (including hysteresis)
VNH 0.2 DVDD — V —
Capacitive load for each bus line Cb — 400 pF —
Notes:
1. The symbols used for timing specifications herein follow the pattern t(first two letters of functional block)(signal)(state)(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tI2DVKH symbolizes I2C timing (I2) with respect to the time data input signals (D) reaching the valid state (V) relative to the tI2C clock reference (K) going to the high (H) state or setup time. Also, tI2SXKL symbolizes I2C timing (I2) for the time that the data with respect to the START condition (S) went invalid (X) relative to the tI2C clock reference (K) going to the low (L) state or hold time. Also, tI2PVKH symbolizes I2C timing (I2) for the time that the data with respect to the STOP condition (P) reaches the valid state (V) relative to the tI2C clock reference (K) going to the high (H) state or setup time.
2. The requirements for I2C frequency calculation must be followed. See Determining the I2C Frequency Divider Ratio for SCL (AN2919).
3. As a transmitter, the chip provides a delay time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge the undefined region of the falling edge of SCL to avoid unintended generation of a START or STOP condition. When the chip acts as the I2C bus master while transmitting, it drives both SCL and SDA. As long as the load on SCL and SDA are balanced, the chip does not generate an unintended START or STOP condition. Therefore, the 300 ns SDA output delay time is not a concern. If, under some rare condition, the 300 ns SDA output delay time is required for the chip as transmitter, see Determining the I2C Frequency Divider Ratio for SCL (AN2919).
4. The maximum tI2OVKL has to be met only if the device does not stretch the LOW period (tI2CL) of the SCL signal.
B4420 QorIQ Qonverge Data Sheet, Rev. 0
Electrical characteristics
Freescale Semiconductor98
This figure provides the AC test load for the I2C.
Figure 29. I2C AC test load
This figure shows the AC timing diagram for the I2C bus.
Figure 30. I2C Bus AC timing diagram
2.19 GPIO interfaceThis section describes the AC electrical characteristics for the GPIO interface.
2.19.1 GPIO AC timing specifications
This table provides the GPIO input and output AC timing specifications.
This figure provides the AC test load for the GPIO.
Figure 31. GPIO AC test load
Table 35. GPIO Input AC timing specifications
For recommended operating conditions, see Table 4.
Parameter Symbol Min Unit Notes
GPIO inputs—minimum pulse width tPIWID 20 ns 1
Notes:
1. GPIO inputs and outputs are asynchronous to any visible clock. GPIO outputs should be synchronized before use by any external synchronous logic. GPIO inputs are required to be valid for at least tPIWID to ensure proper operation.
Output Z0 = 50 ODVDD/2RL = 50
SrS
SDA
SCL
tI2SXKL
tI2CL
tI2CHtI2DXKL,tI2OVKL
tI2DVKH
tI2SXKL
tI2SVKH
tI2KHKL
tI2PVKH
P S
tI2KHDX
Output Z0 = 50 (D/O)VDD/2RL = 50
Electrical characteristics
B4420 QorIQ Qonverge Data Sheet, Rev. 0
Freescale Semiconductor 99
2.20 Timers interfaceThis section describes the AC electrical characteristics for the Timers interface.
2.20.1 Timers AC timing specifications
This table provides the Timers input AC timing specifications.
This figure provides the AC test load for the timers.
2.21 Asynchronous signal timingThis table provides AS specifications for the asynchronous signal timing specifications.
The following interfaces use the specified asynchronous signals:
• Debug port—Signals EVT_B[9–0]
• DMA signals
• Interrupt outputs—Signals IRQn, CKSTP_OUT_B
2.22 CPRI interface signalsThis section describes the DC and AC electrical characteristics for the CPRI interface signals.
Table 36. GPIO input AC timing specifications
For recommended operating conditions, see Table 4.
1. The maximum allowed frequency of timer outputs is 1/(timers clock source/2). Configure the timer modules appropriately.2. Timer inputs and outputs are asynchronous to any visible clock. Timer outputs should be synchronized before use by any
external synchronous logic. Timer inputs are required to be valid for at least tTIWID ns to ensure proper operation.
Table 37. Signal timing
Characteristics Symbol Type Min
Input tIN Asynchronous One SYSCLK cycle
Output tOUT Asynchronous Application-dependent
Note: Input value relevant for DMA, EVT_B[9–0] only.
Output Z0 = 50 OVDD/2RL = 50
B4420 QorIQ Qonverge Data Sheet, Rev. 0
Electrical characteristics
Freescale Semiconductor100
2.22.1 CPRI signals DC electrical characteristics
This table provides the DC electrical characteristics for the CPRI LOS interfaces operating at 2.5 V.
2.22.2 CPRI signals AC specifications
This table provides the CPRI signals timing specifications.
2.23 High-speed serial interfaces (HSSI)The chip features a serializer/deserializer (SerDes) interface to be used for high-speed serial interconnect applications. The SerDes interface can be used for PCI Express, SGMII, CPRI, Aurora, and 2.5x SGMII data transfers.
This section describes the common portion of SerDes DC electrical specifications: the DC requirement for SerDes reference clocks. The SerDes data lane’s transmitter (Tx) and receiver (Rx) reference circuits are also shown.
2.23.1 Signal terms definition
The SerDes utilizes differential signaling to transfer data across the serial link. This section defines the terms that are used in the description and specification of differential signals.
For recommended operating conditions, see Table 4.
Parameter Symbol Min Max Unit Notes
Input high voltage VIH 1.7 — V 1
Input low voltage VIL — 0.7 V 1
Output high voltage (OVDD/DVDD = min, IOH = –2 mA)
VOH 2.0 — V —
Output low voltage (OVDD/DVDD = min, IOL = 2 mA) VOL 0 0.4 V —
Input current for each I/O pin (input voltage is between 0.1 OVDD/DVDD and 0.9 OVDD/DVDD(max)
II –40 40 A —
Notes:
1. The min VILand max VIH values are based on the respective min and max DVIN values found in Table 4.
Table 39. CPRI signals timing specifications
For recommended operating conditions, see Table 4.
Parameter/condition Symbol Min Typ Max Unit Notes
CP_SYNC period tCP-SYNCCLK — 10 — ms 1, 3
CP_RCLK frequency tCP-RCLK — — — MHz 2
CP_RCLK jitter — — — — — 4
Notes:1.TCP-SYNCCLK is the required sync period for both input or output sync. 2. The recovery output clock frequency. See Table 41 for details on using CP_RCLK as RefClk for RE to SLAVE
configuration.3. CP_SYNC and CPRI SerDes reference clock are generated from a common source with the following ratio:
tCP_SYNCCLK = 1228800 * tREFCLK4. CP-RCLK jitter or other definition required for the JCPLL input requirements.
Electrical characteristics
B4420 QorIQ Qonverge Data Sheet, Rev. 0
Freescale Semiconductor 101
This figure shows how the signals are defined. For illustration purposes only, one SerDes lane is used in the description. This figure shows the waveform for either a transmitter output (SD_TXn and SD_TXn_B) or a receiver input (SD_RXn and SD_RXn_B). Each signal swings between A volts and B volts where A > B.
Figure 32. Differential voltage definitions for transmitter or receiver
Using this waveform, the definitions are as shown in the following list. To simplify the illustration, the definitions assume that the SerDes transmitter and receiver operate in a fully symmetrical differential signaling environment:
Single-Ended Swing The transmitter output signals and the receiver input signals SD_TXn, SD_TXn_B, SD_RXn, and SD_RXn_B each have a peak-to-peak swing of A – B volts. This is also referred as each signal wire’s single-ended swing.
The differential output voltage (or swing) of the transmitter, VOD, is defined as the difference of the two complimentary output voltages: VSD_TXn – VSD_TXn_B. The VOD value can be either positive or negative.
Differential Input Voltage, VID (or Differential Input Swing)
The differential input voltage (or swing) of the receiver, VID, is defined as the difference of the two complimentary input voltages: VSD_RXn – VSD_RXn_B. The VID value can be either positive or negative.
Differential Peak Voltage, VDIFFp
The peak value of the differential transmitter output signal or the differential receiver input signal is defined as the differential peak voltage, VDIFFp = |A – B| volts.
Differential Peak-to-Peak, VDIFFp-p
Since the differential output signal of the transmitter and the differential input signal of the receiver each range from A – B to –(A – B) volts, the peak-to-peak value of the differential transmitter output signal or the differential receiver input signal is defined as differential peak-to-peak voltage, VDIFFp-p = 2 VDIFFp = 2 |(A – B)| volts, which is twice the differential swing in amplitude, or twice of the differential peak. For example, the output differential peak-to-peak voltage can also be calculated as VTX-DIFFp-p = 2 |VOD|.
Differential Waveform
The differential waveform is constructed by subtracting the inverting signal (SD_TXn_B, for example) from the non-inverting signal (SD_TXn_B, for example) within a differential pair. There is only one signal trace curve in a differential waveform. The voltage represented in the differential waveform is not referenced to ground. See Figure 37 as an example for differential waveform.
The common mode voltage is equal to half of the sum of the voltages between each conductor of a balanced interchange circuit and ground. In this example, for SerDes output, Vcm_out = (VSD_TXn + VSD_TXn_B) 2 = (A + B) 2, which is the arithmetic mean of the two complimentary output voltages within a differential pair. In a system, the common mode voltage may often differ from one component’s output to the other’s input. It may be different between the receiver input and driver output circuits within the same component. It is also referred to as the DC offset on some occasions.
To illustrate these definitions using real values, consider the example of a current mode logic (CML) transmitter that has a common mode voltage of 2.25 V and outputs, TD and TD_B. If these outputs have a swing from 2.0 V to 2.5 V, the peak-to-peak voltage swing of each signal (TD or TD_B) is 500 mV p-p, which is referred to as the single-ended swing for each signal. Because the differential signaling environment is fully symmetrical in this example, the transmitter output’s differential swing (VOD) has the same amplitude as each signal’s single-ended swing. The differential output signal ranges between 500 mV and –500 mV. In other words, VOD is 500 mV in one phase and –500 mV in the other phase. The peak differential voltage (VDIFFp) is 500 mV. The peak-to-peak differential voltage (VDIFFp-p) is 1000 mV p-p.
2.23.2 SerDes reference clocks
The SerDes reference clock inputs are applied to an internal PLL whose output creates the clock used by the corresponding SerDes lanes. The SerDes reference clocks inputs are SD1_REF1_CLK and SD1_REF1_CLK_B for SerDes 1, SD2_REF1_CLK and SD2_REF1_CLK_B for SerDes 2.
SerDes 1–2 may be used for various combinations of the following IP blocks based on the RCW Configuration field SRDS_PRTCLn:
SD2_REF1_CLK/SD2_REF1_CLK_B are designed to work with spread spectrum clock for PCI Express protocol only with the spreading specification defined in Table 40. When using spread spectrum clocking for PCI Express, both ends of the link partners should use the same reference clock. For best results, a source without significant unintended modulation must be used.
The spread spectrum clocking cannot be used if the same SerDes reference clock is shared with other non-spread spectrum supported protocols. For example, if the spread spectrum clocking is desired on a SerDes reference clock for PCI Express and the same reference clock is used for any other protocol such as SGMII or AURORA due to the SerDes lane usage mapping option, spread spectrum clocking cannot be used at all.
This figure shows a receiver reference diagram of the SerDes reference clocks.
Figure 33. Receiver of SerDes reference clocks
The characteristics of the clock signals are as follows:
• The SerDes receivers core power supply voltage requirements (SVDD) are as specified in Section 2.1.2, “Recommended operating conditions.”
• The SerDes reference clock receiver reference circuit structure is as follows:
— The SDn_REF1_CLK and SDn_REF1_CLK_B are internally AC-coupled differential inputs as shown in Figure 33. Each differential clock input (SDn_REF1_CLK or SDn_REF1_CLK_B) has on-chip 50- termination to SGND followed by on-chip AC-coupling.
— The external reference clock driver must be able to drive this termination.
— The SerDes reference clock input can be either differential or single-ended. See the differential mode and single-ended mode descriptions below for detailed requirements.
• The maximum average current requirement also determines the common mode voltage range.
— When the SerDes reference clock differential inputs are DC coupled externally with the clock driver chip, the maximum average current allowed for each input pin is 8 mA. In this case, the exact common mode input voltage is not critical as long as it is within the range allowed by the maximum average current of 8 mA because the input is AC-coupled on-chip.
— This current limitation sets the maximum common mode input voltage to be less than 0.4 V (0.4 V 50 = 8 mA) while the minimum common mode input level is 0.1 V above SGND. For example, a clock with a 50/50 duty cycle can be produced by a clock driver with output driven by its current source from 0 mA to 16 mA (0–0.8 V), such that each phase of the differential input has a single-ended swing from 0 V to 800 mV with the common mode voltage at 400 mV.
— If the device driving the SDn_REF1_CLK and SDn_REF1_CLK_B inputs cannot drive 50 to SGND DC or the drive strength of the clock driver chip exceeds the maximum input current limitations, it must be AC-coupled off-chip.
• The input amplitude requirement is described in detail in the following sections.
InputAmp
50
50
SDn_REF1_CLK
SDn_REF1_CLK_B
B4420 QorIQ Qonverge Data Sheet, Rev. 0
Electrical characteristics
Freescale Semiconductor104
2.23.2.3 DC-level requirement for SerDes reference clocks
The DC level requirement for the SerDes reference clock inputs is different depending on the signaling mode used to connect the clock driver chip and SerDes reference clock inputs, as described below:
• Differential Mode
— The input amplitude of the differential clock must be between 400 mV and 1600 mV differential peak-to-peak (or between 200 mV and 800 mV differential peak). In other words, each signal wire of the differential pair must have a single-ended swing of less than 800 mV and greater than 200 mV. This requirement is the same for both external DC-coupled or AC-coupled connection.
— For an external DC-coupled connection, as described in Section 2.23.2.2, “SerDes reference clock receiver characteristics,” the maximum average current requirements sets the requirement for average voltage (common mode voltage) as between 100 mV and 400 mV. Figure 34 shows the SerDes reference clock input requirement for DC-coupled connection scheme.
Figure 34. Differential reference clock input DC requirements (external DC-coupled)
— For an external AC-coupled connection, there is no common mode voltage requirement for the clock driver. Because the external AC-coupling capacitor blocks the DC level, the clock driver and the SerDes reference clock receiver operate in different common mode voltages. The SerDes reference clock receiver in this connection scheme has its common mode voltage set to SGND. Each signal wire of the differential inputs is allowed to swing below and above the common mode voltage (SGND). Figure 35 shows the SerDes reference clock input requirement for AC-coupled connection scheme.
Figure 35. Differential reference clock input DC requirements (external AC-coupled)
• Single-Ended Mode
— The reference clock can also be single-ended. The SDn_REF1_CLK input amplitude (single-ended swing) must be between 400 mV and 800 mV peak-to-peak (from VMIN to VMAX) with SDn_REF1_CLK_B either left unconnected or tied to ground.
— The SDn_REF1_CLK input average voltage must be between 200 and 400 mV. Figure 36 shows the SerDes reference clock input requirement for single-ended signaling mode.
— To meet the input amplitude requirement, the reference clock inputs may need to be DC- or AC-coupled externally. For the best noise performance, the reference of the clock could be DC- or AC-coupled into the unused phase (SDn_REF1_CLK_B) through the same source impedance as the clock input (SDn_REF1_CLK) in use.
Figure 36. Single-ended reference clock input DC requirements
2.23.2.4 AC requirements for SerDes reference clocks
This table lists the AC requirements for SerDes reference clocks for protocols running at data rates up to 8 Gb/s.
This includes PCI Express (2.5, 5 GT/s), SGMII (1.25Gbps), 2.5x SGMII (3.125Gbps), Aurora (2.5, 3.125, 5 Gbps), CPRI (1.2288, 2.4576, 3.072, 4.9152, 6.144 Gbps). SerDes reference clocks to be guaranteed by the customer’s application design.
For recommended operating conditions, see Table 4.
Parameter Symbol Min Typ Max Unit Notes
SDn_REF1_CLK/SDn_REF1_CLK_B frequency range tCLK_REF — 100/122.88/125/156.25
— MHz 1
SDn_REF1_CLK/SDn_REF1_CLK_B clock frequency toleranceFor PEX Gen 1, 2
tCLK_TOL –300 — 300 ppm 7, 10
SDn_REF1_CLK/SDn_REF1_CLK_B clock frequency toleranceFor SGMII, 2.5x SGMII, Aurora, CPRI
tCLK_TOL –100 — 100 ppm 8, 10
SDn_REF1_CLK/SDn_REF1_CLK_B reference clock duty cycle (measured at 1.6 V)
tCLK_DUTY 40 50 60 % —
SDn_REF1_CLK/SDn_REF1_CLK_B max deterministic peak-to-peak jitter at 10-6 BER
tCLK_DJ — — 42 ps —
SDn_REF1_CLK/SDn_REF1_CLK_B total reference clock jitter at 10-6 BER (peak-to-peak jitter at refClk input)
tCLK_TJ — — 86 ps 2
SDn_REF1_CLK/SDn_REF1_CLK_B Allowed cut-off frequency of REC-slave synchronization mechanism
tCLK_TC — — 300 Hz 9
SDn_REF1_CLK/SDn_REF1_CLK_B df/f0 contribution of jitter between REC master to REC slave to the frequency accuracy budget
tCLK_TF –0.002 — 0.002 ppm 9
SDn_REF1_CLK
SDn_REF1_CLK_B
400 mV < SDn_REF1_CLK input amplitude < 800 mV
0 V
B4420 QorIQ Qonverge Data Sheet, Rev. 0
Electrical characteristics
Freescale Semiconductor106
This table lists the AC requirements for SerDes reference clocks for protocols running at data rates greater than 8 Gb/s. This includes CPRI (9.8304 Gbps). SerDes reference clocks to be guaranteed by the customer’s application design.
Rising edge rate (SDn_REF1_CLK) to falling edge rate (SDn_REF1_CLK_B) matching
Rise-Fall Matching
— — 20 % 5, 6
Notes:1. Caution: Only 100, 122.88, 125 and 156.25 have been tested. In-between values do not work correctly with the rest of the
system.
2. Limits from PCI Express CEM Rev 2.03. Measured from –200 mV to +200 mV on the differential waveform (derived from SDn_REF1_CLK minus
SDn_REF1_CLK_B). The signal must be monotonic through the measurement region for rise and fall time. The 400 mV measurement window is centered on the differential zero crossing. See Figure 37.
4. Measurement taken from differential waveform.VCM is the common mode voltage
5. Measurement taken from single-ended waveform
6. Matching applies to rising edge for SDn_REF1_CLK and falling edge rate for SDn_REF1_CLK_B. It is measured using a 200 mV window centered on the median cross point where SDn_REF1_CLK rising meets SDn_REF1_CLK_B falling. The median cross point is used to calculate the voltage thresholds that the oscilloscope uses for the edge rate calculations. The rise edge rate of SDn_REF1_CLK must be compared to the fall edge rate of SDn_REF1_CLK_B, the maximum allowed difference should not exceed 20% of the slowest edge rate. See Figure 38.
7. For PCI Express (2.5, 5 GT/s)
8. For SGMII, 2.5x SGMII, Aurora, CPRI.9. This spec is applied to CPRI protocol clocks only. The TCLK_TC is to comply with R-17 requirement in the protocol. TCLK_TF,
to comply to R-18 requirement.10. When two or more protocols share the same PLL on a SerDes module, the tightest SDn_REFn_CLK/ SDn_REFn_CLK_B
Rising edge rate (SDn_REF1_CLK) to falling edge rate (SDn_REF1_CLK_B) matching
Rise-Fall Matching
— — 20 % 5, 6
Notes:1. Caution: Only 122.88 have been tested. In-between values do not work correctly with the rest of the system.3. Measured from –200 mV to +200 mV on the differential waveform (derived from SDn_REF1_CLK minus SDn_REF1_CLK_B).
The signal must be monotonic through the measurement region for rise and fall time. The 400 mV measurement window is centered on the differential zero crossing. See Figure 37.
4. Measurement taken from differential waveform5. Measurement taken from single-ended waveform
6. Matching applies to rising edge for SDn_REF1_CLK and falling edge rate for SDn_REF1_CLK_B. It is measured using a 200 mV window centered on the median cross point where SDn_REF1_CLK rising meets SDn_REF1_CLK_B falling. The median cross point is used to calculate the voltage thresholds that the oscilloscope uses for the edge rate calculations. The rise edge rate of SDn_REF1_CLK must be compared to the fall edge rate of SDn_REF1_CLK_B, the maximum allowed difference should not exceed 20% of the slowest edge rate. See Figure 38.
7. When two or more protocols share the same PLL on a SerDes module, the tightest SDn_REFn_CLK/ SDn_REFn_CLK_B clock frequency tolerance must be followed.
8. This spec is applied to CPRI protocol clocks only. The TCLK_TC is to comply with R-17 requirement in the protocol. TCLK_TF, to comply to R-18 requirement.
For recommended operating conditions, see Table 4.
Parameter Symbol Min Typ Max Unit Notes
VIH = +200 mV
VIL = –200 mV
0.0 V
SDn_REFn_CLK – SDn_REFn_CLK_B
Fall edge rateRise edge rate
B4420 QorIQ Qonverge Data Sheet, Rev. 0
Electrical characteristics
Freescale Semiconductor108
Figure 37. Differential measurement points for rise and fall time
Figure 38. Single-ended measurement points for rise and fall time matching
2.23.3 SerDes transmitter and receiver reference circuits
This figure shows the reference circuits for SerDes data lane’s transmitter and receiver.
Figure 39. SerDes transmitter and receiver reference circuits
The DC and AC specification of SerDes data lanes are defined in each interface protocol section below based on the application usage
• Section 2.23.4, “PCI Express interface”
• Section 2.23.5, “Aurora interface”
• Section 2.23.6, “SGMII interface”
• Section 2.23.7, “CPRI interface”
Note that external AC-coupling capacitor is required for the above serial transmission protocols with the capacitor value defined in the specification of each protocol section.
SDn_REF1_CLK_B SDn_REF1_CLK_B
SDn_REF1_CLKSDn_REF1_CLK
VCROSS MEDIAN VCROSS MEDIAN
VCROSS MEDIAN + 100 mV
VCROSS MEDIAN – 100 mV
TFALL TRISE
50 ReceiverTransmitter
SDn_TXn_B
SDn_TXn SDn_RXn
SDn_RXn_B
100
50
Electrical characteristics
B4420 QorIQ Qonverge Data Sheet, Rev. 0
Freescale Semiconductor 109
This figure shows the single-frequency sinusoidal jitter limits for 2.5 GBaud and 3.125 GBaud rates.
This section describes the clocking dependencies as well as the DC and AC electrical specifications for the PCI Express bus.
2.23.4.1 Clocking dependencies
The ports on the two ends of a link must transmit data at a rate that is within 600 parts per million (ppm) of each other at all times. This is specified to allow bit rate clock sources with a ± 300 ppm tolerance.
2.23.4.2 PCI Express clocking requirements for SDn_REF1_CLK/SDn_REF1_CLK_B
SerDes 2 (SD2_REF1_CLK and SD2_REF1_CLK_B) may be used for various SerDes PCI Express configurations based on the RCW Configuration field SRDS_PRTCL_S2. PCI Express is supported on SerDes 2 only.
For more information on these specifications, see Section 2.23.2, “SerDes reference clocks.”
2.23.4.3 PCI Express DC physical layer specifications
This section contains the DC specifications for the physical layer of PCI Express on this chip.
2.23.4.3.1 PCI Express DC physical layer transmitter specifications
This section discusses the PCI Express DC physical layer transmitter specifications for 2.5 GT/s and 5 GT/s.
5 UI p-p
0.05 UI p-p
Sinusoidal
Jitter
Amplitude
35.2kHz 3MHz 20 MHzFrequency
20dB/dec
Electrical characteristics
B4420 QorIQ Qonverge Data Sheet, Rev. 0
Freescale Semiconductor 111
This table defines the PCI Express 2.0 (2.5 GT/s) DC specifications for the differential output at all transmitters. The parameters are specified at the component pins.
This table defines the PCI Express 2.0 (5 GT/s) DC specifications for the differential output at all transmitters. The parameters are specified at the component pins.
2.23.4.3.2 PCI Express DC physical layer receiver specifications
This section discusses the PCI Express DC physical layer receiver specifications for 2.5 GT/s and 5 GT/s.
Table 43. PCI Express 2.0 (2.5 GT/s) differential transmitter output DC specifications (XVDD = 1.35 V or 1.5 V)
For recommended operating conditions, see Table 4.
VTX-DE-RATIO 3.0 3.5 4.0 dB Ratio of the VTX-DIFFp-p of the second and following bits after a transition divided by the VTX-DIFFp-p of the first bit after a transition.
DC differential transmitter impedance
ZTX-DIFF-DC 80 100 120 Transmitter DC differential mode low impedance
Transmitter DC impedance ZTX-DC 40 50 60 Required transmitter D+ as well as D– DC Impedance during all states
Table 44. PCI Express 2.0 (5 GT/s) differential transmitter output DC specifications (XVDD = 1.35 V or 1.5 V)
For recommended operating conditions, see Table 4.
VTX-DE-RATIO-3.5dB 3.0 3.5 4.0 dB Ratio of the VTX-DIFFp-p of the second and following bits after a transition divided by the VTX-DIFFp-p of the first bit after a transition.
De-emphasized differential output voltage (ratio)
VTX-DE-RATIO-6.0dB 5.5 6.0 6.5 dB Ratio of the VTX-DIFFp-p of the second and following bits after a transition divided by the VTX-DIFFp-p of the first bit after a transition.
DC differential transmitter impedance
ZTX-DIFF-DC 80 100 120 Transmitter DC differential mode low impedance
Transmitter DC Impedance ZTX-DC 40 50 60 Required transmitter D+ as well as D– DC impedance during all states
B4420 QorIQ Qonverge Data Sheet, Rev. 0
Electrical characteristics
Freescale Semiconductor112
This table defines the DC specifications for the PCI Express 2.0 (2.5 GT/s) differential input at all receivers. The parameters are specified at the component pins.
For recommended operating conditions, see Table 4.
Parameter Symbol Min Typ Max Units Notes
Differential input peak-to-peak voltage VRX-DIFFp-p 120 1000 1200 mV VRX-DIFFp-p = 2 |VRX-D+ – VRX-D-| See Note 1.
DC differential input impedance ZRX-DIFF-DC 80 100 120 Receiver DC differential mode impedance.See Note 2
DC single input impedance ZRX-DC 40 50 60 Required receiver D+ as well as D– DC Impedance (50 ±20% tolerance).See Notes 1 and 2.
Powered down DC input impedance ZRX-HIGH-IMP-DC 50 — — k Required receiver D+ as well as D– DC Impedance when the receiver terminations do not have power.See Note 3.
Electrical idle detect threshold VRX-IDLE-DET-DIF
Fp-p
65 — 175 mV VRX-IDLE-DET-DIFFp-p =2 |VRX-D+ – VRX-D–| Measured at the package pins of the receiver
Notes:1. Measured at the package pins with a test load of 50 to GND on each pin.
2. Impedance during all LTSSM states. When transitioning from a fundamental reset to detect (the initial state of the LTSSM) there is a 5 ms transition time before receiver termination values must be met on all unconfigured lanes of a port.
3. The receiver DC common mode impedance that exists when no power is present or fundamental reset is asserted. This helps ensure that the receiver detect circuit does not falsely assume a receiver is powered on when it is not. This term must be measured at 300 mV above the receiver ground.
Electrical characteristics
B4420 QorIQ Qonverge Data Sheet, Rev. 0
Freescale Semiconductor 113
This table defines the DC specifications for the PCI Express 2.0 (5 GT/s) differential input at all receivers. The parameters are specified at the component pins.
2.23.4.4 PCI Express AC physical layer specifications
This section contains the AC specifications for the physical layer of PCI Express on this device.
2.23.4.4.1 PCI Express AC physical layer transmitter specifications
This section discusses the PCI Express AC physical layer transmitter specifications for 2.5 GT/s and 5 GT/s.
For recommended operating conditions, see Table 4.
Parameter Symbol Min Typ Max Units Notes
Differential input peak-to-peak voltage VRX-DIFFp-p 120 1000 1200 mV VRX-DIFFp-p = 2 |VRX-D+ – VRX-D–| See Note 1.
DC differential input impedance ZRX-DIFF-DC 80 100 120 Receiver DC differential mode impedance. See Note 2
DC input impedance ZRX-DC 40 50 60 Required receiver D+ as well as D– DC Impedance (50 ±20% tolerance). See Notes 1 and 2.
Powered down DC input impedance ZRX-HIGH-IMP-DC 50 — — k Required receiver D+ as well as D– DC Impedance when the receiver terminations do not have power. See Note 3.
Electrical idle detect threshold VRX-IDLE-DET-DIF
Fp-p
65 — 175 mV VRX-IDLE-DET-DIFFp-p = 2 |VRX-D+ – VRX-D–| Measured at the package pins of the receiver
Notes:1. Measured at the package pins with a test load of 50 to GND on each pin.
2. Impedance during all LTSSM states. When transitioning from a fundamental reset to detect (the initial state of the LTSSM) there is a 5 ms transition time before receiver termination values must be met on all unconfigured lanes of a port.
3. The receiver DC common mode impedance that exists when no power is present or fundamental reset is asserted. This helps ensure that the receiver detect circuit does not falsely assume a receiver is powered on when it is not. This term must be measured at 300 mV above the receiver ground.
B4420 QorIQ Qonverge Data Sheet, Rev. 0
Electrical characteristics
Freescale Semiconductor114
This table defines the PCI Express 2.0 (2.5 GT/s) AC specifications for the differential output at all transmitters. The parameters are specified at the component pins. The AC timing specifications do not include RefClk jitter.
This table defines the PCI Express 2.0 (5 GT/s) AC specifications for the differential output at all transmitters. The parameters are specified at the component pins. The AC timing specifications do not include RefClk jitter.
For recommended operating conditions, see Table 4.
Parameter Symbol Min Typ Max Units Notes
Unit interval UI 399.88 400 400.12 ps Each UI is 400 ps ± 300 ppm. UI does not account for spread-spectrum clock dictated variations.
Minimum transmitter eye width
TTX-EYE 0.75 — — UI The maximum transmitter jitter can be derived as TTX-MAX-JITTER = 1 – TTX-EYE = 0.25 UI. Does not include spread-spectrum or RefCLK jitter. Includes device random jitter at 10-12. See Notes 1 and 2.
Maximum time between the jitter median and maximum deviation from the median
TTX-EYE-MEDIAN-
to-
MAX-JITTER
— — 0.125 UI Jitter is defined as the measurement variation of the crossing points (VTX-DIFFp-p = 0 V) in relation to a recovered transmitter UI. A recovered transmitter UI is calculated over 3500 consecutive unit intervals of sample data. Jitter is measured using all edges of the 250 consecutive UI in the center of the 3500 UI used for calculating the transmitter UI.See Notes 1 and 2.
AC coupling capacitor CTX 75 — 200 nF All transmitters must be AC coupled. The AC coupling is required either within the media or within the transmitting component itself. See Note 3.
Notes:1. Specified at the measurement point into a timing and voltage test load as shown in Figure 43 and measured over any 250
consecutive transmitter UIs.
2. A TTX-EYE = 0.75 UI provides for a total sum of deterministic and random jitter budget of TTX-JITTER-MAX = 0.25 UI for the transmitter collected over any 250 consecutive transmitter UIs. The TTX-EYE-MEDIAN-to-MAX-JITTER median is less than half of the total transmitter jitter budget collected over any 250 consecutive transmitter UIs. It must be noted that the median is not the same as the mean. The jitter median describes the point in time where the number of jitter points on either side is approximately equal as opposed to the averaged time value.
3. The chip’s SerDes transmitter does not have CTX built-in. An external AC coupling capacitor is required.
For recommended operating conditions, see Table 4.
Parameter Symbol Min Typ Max Units Notes
Unit Interval UI 199.94 200.00 200.06 ps Each UI is 200 ps ± 300 ppm. UI does not account for spread-spectrum clock dictated variations.
Minimum transmitter eye width TTX-EYE 0.75 — — UI The maximum transmitter jitter can be derived as: TTX-MAX-JITTER = 1 – TTX-EYE = 0.25 UI.See Note 1.
Electrical characteristics
B4420 QorIQ Qonverge Data Sheet, Rev. 0
Freescale Semiconductor 115
2.23.4.4.2 PCI Express AC physical layer receiver specifications.
This section discusses the PCI Express AC physical layer receiver specifications for 2.5 GT/s and 5 GT/s.
This table defines the AC specifications for the PCI Express 2.0 (2.5 GT/s) differential input at all receivers. The parameters are specified at the component pins. The AC timing specifications do not include RefClk jitter.
AC coupling capacitor CTX 75 — 200 nF All transmitters must be AC coupled. The AC coupling is required either within the media or within the transmitting component itself.See Note 2.
Notes:1. Specified at the measurement point into a timing and voltage test load as shown in Figure 43 and measured over any 250
consecutive transmitter UIs.
2. The chip’s SerDes transmitter does not have CTX built-in. An external AC coupling capacitor is required.
For recommended operating conditions, see Table 4.
Parameter Symbol Min Typ Max Units Notes
Unit Interval UI 399.88 400.00 400.12 ps Each UI is 400 ps ± 300 ppm. UI does not account for spread spectrum clock dictated variations.
Minimum receiver eye width TRX-EYE 0.4 — — UI The maximum interconnect media and transmitter jitter that can be tolerated by the receiver can be derived as TRX-MAX-JITTER = 1 – TRX-EYE= 0.6 UI.See Notes 1 and 2.
For recommended operating conditions, see Table 4.
Parameter Symbol Min Typ Max Units Notes
B4420 QorIQ Qonverge Data Sheet, Rev. 0
Electrical characteristics
Freescale Semiconductor116
This table defines the AC specifications for the PCI Express 2.0 (5 GT/s) differential input at all receivers. The parameters are specified at the component pins. The AC timing specifications do not include RefClk jitter. If spread spectrum clocking is desired, the common clock must be used.
Maximum time between the jitter median and maximum deviation from the median.
TRX-EYE-MEDIAN-
to-MAX-JITTER
— — 0.3 UI Jitter is defined as the measurement variation of the crossing points (VRX-DIFFp-p = 0 V) in relation to a recovered transmitter UI. A recovered transmitter UI is calculated over 3500 consecutive unit intervals of sample data. Jitter is measured using all edges of the 250 consecutive UI in the center of the 3500 UI used for calculating the transmitter UI. See Notes 1, 2 and 3.
Notes:1. Specified at the measurement point and measured over any 250 consecutive UIs. The test load in Figure 43 must be used as
the receiver device when taking measurements. If the clocks to the receiver and transmitter are not derived from the same reference clock, the transmitter UI recovered from 3500 consecutive UI must be used as a reference for the eye diagram.
2. A TRX-EYE = 0.40 UI provides for a total sum of 0.60 UI deterministic and random jitter budget for the transmitter and interconnect collected any 250 consecutive UIs. The TRX-EYE-MEDIAN-to-MAX-JITTER specification ensures a jitter distribution in which the median and the maximum deviation from the median is less than half of the total. UI jitter budget collected over any 250 consecutive transmitter UIs. It must be noted that the median is not the same as the mean. The jitter median describes the point in time where the number of jitter points on either side is approximately equal as opposed to the averaged time value. If the clocks to the receiver and transmitter are not derived from the same reference clock, the transmitter UI recovered from 3500 consecutive UI must be used as the reference for the eye diagram.
3. It is recommended that the recovered transmitter UI is calculated using all edges in the 3500 consecutive UI interval with a fit algorithm using a minimization merit function. Least squares and median deviation fits have worked well with experimental and simulated data.
For recommended operating conditions, see Table 4.
Parameter Symbol Min Typ Max Units Notes
Electrical characteristics
B4420 QorIQ Qonverge Data Sheet, Rev. 0
Freescale Semiconductor 117
Figure 42. Swept sinusoidal jitter mask
2.23.4.5 Test and measurement load
The AC timing and voltage parameters must be verified at the measurement point. The package pins of the device must be connected to the test/measurement load within 0.2 inches of that load, as shown in the following figure.
NOTE
The allowance of the measurement point to be within 0.2 inches of the package pins is meant to acknowledge that package/board routing may benefit from D+ and D– not being exactly matched in length at the package pin boundary. If the vendor does not explicitly state where the measurement point is located, the measurement point is assumed to be the D+ and D– package pins.
Figure 43. Test/Measurement load
2.23.5 Aurora interface
This section describes the Aurora clocking requirements and its DC and AC electrical characteristics.
1.0 UI
0.1 UI
~ 3.0 ps RMS
0.01 MHz 0.1 MHz 1.0 MHz 10 MHz
100 MHz
1000 MHz
Sj
Rj
Rj (
ps R
MS
)S
j (U
I PP
)
0.03 MHz
Sj sweep range
100 MHz
20 dB decade
Transmittersilicon
+ package
C = CTX
C = CTX
R = 50 R = 50
D+ package pin
D– package pin
B4420 QorIQ Qonverge Data Sheet, Rev. 0
Electrical characteristics
Freescale Semiconductor118
2.23.5.1 Aurora clocking requirements for SDn _REF1 _CLK and SDn _REF1 _CLK_B
SerDes 1 and SerDes 2 (SD[1:2]_REF1_CLK and SD[1:2]_REF1_CLK_B) may be used for SerDes Aurora configurations based on the RCW Configuration field SRDS_PRTCL_Sn.
For more information on these specifications, see Section 2.23.2, “SerDes reference clocks.”
2.23.5.2 Aurora DC electrical characteristics
This section describes the DC electrical characteristics for the Aurora interface.
2.23.5.2.1 Aurora transmitter DC electrical characteristics
This table defines the Aurora transmitter DC electrical characteristics.
2.23.5.2.2 Aurora receiver DC electrical characteristics
This table defines the Aurora receiver DC electrical characteristics for the Aurora interface.
2.23.5.3 Aurora AC timing specifications
This section describes the AC timing specifications for Aurora.
Table 51. Aurora transmitter DC electrical characteristics (XVDD = 1.35 V or 1.5 V)
For recommended operating conditions, see Table 4.
Parameter Symbol Min Typical Max Unit
Differential output voltage VDIFFPP 800 1000 1600 mV p-p
DC Differential transmitter impedance ZTX-DIFF-DC 80 100 120
Table 52. Aurora receiver DC electrical characteristics (SVDD = 1.0 V )
For recommended operating conditions, see Table 4.
Parameter Symbol Min Typical Max Unit Notes
Differential input voltage VIN 200 — 1600 mV p-p 1
DC Differential receiver impedance ZRX-DIFF-DC 80 100 120 2
Note:
1. Measured at receiver.
2. DC Differential receiver impedance
Electrical characteristics
B4420 QorIQ Qonverge Data Sheet, Rev. 0
Freescale Semiconductor 119
2.23.5.3.1 Aurora transmitter AC timing specifications
This table defines the Aurora transmitter AC timing specifications. RefClk jitter is not included.
2.23.5.3.2 Aurora receiver AC timing specifications
This table defines the Aurora receiver AC timing specifications. RefClk jitter is not included.
2.23.6 SGMII interface
Each SGMII port features a 4-wire AC-coupled serial link from the SerDes interface of the chip, as shown in Figure 44, where CTX is the external (on board) AC-coupled capacitor. Each SerDes transmitter differential pair features100-output impedance. Each input of the SerDes receiver differential pair features 50- on-die termination to XGND. The reference circuit of the SerDes transmitter and receiver is shown in Figure 39.
Table 53. Aurora transmitter AC timing specifications
For recommended operating conditions, see Table 4.
2. Total jitter is composed of three components: deterministic jitter, random jitter, and single frequency sinusoidal jitter. The sinusoidal jitter may have any amplitude and frequency in the unshaded region of Figure 43. The sinusoidal jitter component is included to ensure margin for low frequency jitter, wander, noise, crosstalk and other variable system effects.
B4420 QorIQ Qonverge Data Sheet, Rev. 0
Electrical characteristics
Freescale Semiconductor120
2.23.6.1 SGMII clocking requirements for SDn_REF1_CLK and SDn_REF1_CLK_B
When operating in SGMII mode, a SerDes reference clock is required on SD[1:2]_REF1_CLK and SD[1:2]_REF1_CLK_B pins. SerDes 1–2 may be used for SerDes SGMII configurations based on the RCW Configuration field SRDS_PRTCL_Sn.
For more information on these specifications, see Section 2.23.2, “SerDes reference clocks.”
2.23.6.2 SGMII DC electrical characteristics
This section discusses the electrical characteristics for the SGMII interface.
2.23.6.2.1 SGMII and SGMII 2.5x transmit DC specifications
This table describes the SGMII SerDes transmitter AC-coupled DC electrical characteristics. Transmitter DC characteristics are measured at the transmitter outputs (SDn_TXn and SDn_TXn_B) as shown in Figure 45.
Table 55. SGMII DC transmitter electrical characteristics (XVDD = 1.35 V or 1.5 V)
For recommended operating conditions, see Table 4.
Parameter Symbol Min Typ Max Unit Notes
Output high voltage VOH — — 1.5 x |VOD|-max mV 1
Output low voltage VOL |VOD|-min/2 — — mV 1
Electrical characteristics
B4420 QorIQ Qonverge Data Sheet, Rev. 0
Freescale Semiconductor 121
Output differential voltage2, 3
(XVDD-Typ at 1.35 V and 1.5 V)|VOD| 320 500.0 725.0 mV Amp Setting:
Notes:1. This does not align to DC-coupled SGMII. 2. |VOD| = |VSD_TXn– VSD_TXn_B|. |VOD| is also referred to as output differential peak voltage. VTX-DIFFp-p = 2 × |VOD|.3. The |VOD| value shown in the Typ column is based on the condition of XVDD-Typ = 1.35 V or 1.5 V, no common mode offset
variation. SerDes transmitter is terminated with 100- differential load between SDn _TXn and SDn_TXn_B.
Table 55. SGMII DC transmitter electrical characteristics (XVDD = 1.35 V or 1.5 V) (continued)
For recommended operating conditions, see Table 4.
Parameter Symbol Min Typ Max Unit Notes
B4420 QorIQ Qonverge Data Sheet, Rev. 0
Electrical characteristics
Freescale Semiconductor122
This figure shows an example of a 4-wire AC-coupled SGMII serial link connection.
Figure 44. 4-wire AC-coupled SGMII serial link connection example
This figure shows the SGMII transmitter DC measurement circuit.
Figure 45. SGMII transmitter DC measurement circuit
SGMIISerDes Interface
50
50 Transmitter
SDn_TXn SDn_RXn
SDn_TXn_B SDn_RXn_B
Receiver
CTX
CTX
50
50
SDn_RXn
SDn_RXn_B
Receiver Transmitter
SDn_TXn
SDn_TXn_B
CTX
CTX
100
100
50
Transmitter
SDn_TXn
SDn_TXn_B50
VOD
SGMIISerDes Interface
100
Electrical characteristics
B4420 QorIQ Qonverge Data Sheet, Rev. 0
Freescale Semiconductor 123
This table defines the SGMII 2.5x transmitter DC electrical characteristics for 3.125 GBaud.
2.23.6.2.2 SGMII and SGMII 2.5x DC receiver electrical characteristics
This table lists the SGMII DC receiver electrical characteristics. Source synchronous clocking is not supported. Clock is recovered from the data.
This table defines the SGMII 2.5x receiver DC electrical characteristics for 3.125 GBaud.
2.23.6.3 SGMII AC timing specifications
This section discusses the AC timing specifications for the SGMII interface.
Table 56. SGMII 2.5x transmitter DC electrical characteristics (XVDD = 1.35 V or 1.5 V)
For recommended operating conditions, see Table 4.
2. VRX_DIFFp-p is also referred to as peak-to-peak input differential voltage.3. The concept of this parameter is equivalent to the electrical idle detect threshold parameter in PCI Express. See
Section 2.23.4.3.2, “PCI Express DC physical layer receiver specifications,” and Section 2.23.4.4.2, “PCI Express AC physical layer receiver specifications.,” for further explanation.
4. Default lost threshold sel = ‘001.’
Table 58. SGMII 2.5x receiver DC timing specifications (SVDD = 1.0 V )
For recommended operating conditions, see Table 4.
Parameter Symbol Min Typical Max Unit Notes
Input differential voltage VRX_DIFFp-p 200 — 1200 mV —
2.23.6.3.1 SGMII and SGMII 2.5x transmit AC timing specifications
This table provides the SGMII and SGMII 2.5x transmit AC timing specifications. A source synchronous clock is not supported. The AC timing specifications do not include RefClk jitter.
2.23.6.3.2 SGMII AC measurement details
Transmitter and receiver AC characteristics are measured at the transmitter outputs (SDn_TXn and SDn_TXn_B) or at the receiver inputs (SDn_RXn and SDn_RXn_B) respectively.
Figure 46. SGMII AC test/measurement load
2.23.6.3.3 SGMII and SGMII 2.5x receiver AC timing specifications
This table provides the SGMII and SGMII 2.5x receiver AC timing specifications. The AC timing specifications do not include RefClk jitter. Source synchronous clocking is not supported. Clock is recovered from the data.
Table 59. SGMII transmit AC timing specifications
For recommended operating conditions, see Table 4.
Combined deterministic and random jitter tolerance JDR — — 0.55 UI p-p 1
Total jitter tolerance JT — — 0.65 UI p-p 1, 2
Transmittersilicon
+ package
C = CTX
C = CTX
R = 50 R = 50
D+ package pin
D– package pin
Electrical characteristics
B4420 QorIQ Qonverge Data Sheet, Rev. 0
Freescale Semiconductor 125
The sinusoidal jitter in the total jitter tolerance may have any amplitude and frequency in the unshaded region of Figure 40.
2.23.7 CPRI interface
This section describes the CPRI clocking requirements and its DC and AC electrical characteristics.
2.23.7.1 CPRI clocking requirements for SD1_REF1_CLK and SD1_REF1_CLK_B
Only SerDes 1 (SD1_REF1_CLK and SD1_REF1_CLK_B) may be used for SerDes CPRI configurations based on the RCW Configuration field SRDS_PRTCL_S1.
For more information on these specifications, see Section 2.23.2, “SerDes reference clocks.”
2.23.7.2 CPRI LV
This section describes the CPRI LV XAUI based interface, designed to work at 1.2288, 2.4576 and 3.072 GB/s.
2.23.7.2.1 Transmitter specifications
This table defines the DC specifications for the differential output at all transmitters (TXs). The parameters are specified at the component pins.
The following table defines the AC specifications for the differential output at all transmitters (TXs). The parameters are specified at the component pins.
2. Total jitter is composed of three components: deterministic jitter, random jitter, and single frequency sinusoidal jitter. The sinusoidal jitter may have any amplitude and frequency in the unshaded region of Figure 40. The sinusoidal jitter component is included to ensure margin for low frequency jitter, wander, noise, crosstalk and other variable system effects.
Table 61. Transmitter DC specifications (XVDD = 1.35 V or 1.5 V)
Characteristic Symbol Min Nom Max Unit
Output voltage VO –0.40 — 2.30 Volts
Differential output voltage VDIFFPP 800 — 1600 mV p-p
Differential resistance T_Rd 80 100 120
Table 62. Transmitter AC specifications
Characteristic Symbol Min Nom Max Unit
Deterministic jitter JD — — 0.17 UI p-p
Total jitter JT — — 0.35 UI p-p
Table 60. SGMII receive AC timing specifications (continued)
For recommended operating conditions, see Table 4.
Parameter Symbol Min Typ Max Unit Notes
B4420 QorIQ Qonverge Data Sheet, Rev. 0
Electrical characteristics
Freescale Semiconductor126
2.23.7.2.2 Receiver specifications
This table defines the DC specifications for the differential input at all receivers (RXs). The parameters are specified at the component pins.
This table defines the AC specifications for the differential input at all receivers (RXs). The parameters are specified at the component pins.
2.23.7.3 CPRI LV-II/LV-III
This section describes the CPRI LV-II CEI-6G-LR based (1.2288, 2.4576, 3.072, 4.9152 and 6.144 Gb/s) and CPRI LV-III IEEE 802.3 [22], clause 72.7 based (9.8304 Gb/s)
Unit interval: 1.2288 GBaud
UI 1/1228.8-100ppm 1/1228.8 1/1228.8+100ppm us
Unit interval: 2.4576 GBaud
UI 1/2457.6-100ppm 1/2457.6 1/2457.6+100ppm us
Unit interval: 3.072 GBaud
UI 1/3072.0-100ppm 1/3072.0 1/3072.0+100ppm us
Note:
The AC specifications do not include Refclk jitter.
Table 63. Receiver DC specifications (SVDD = 1.0 V)
Combined deterministic and random jitter tolerance
JDR — — 0.55 UI p-p Measured at receiver
Total jitter tolerance JT — — 0.65 UI p-p Measured at receiver
Bit error ratio BER — — 10-12 — —
Unit interval: 1.2288 GBaud UI 1/1228.8-100ppm 1/1228.8 1/1228.8+100ppm ps —
Unit interval: 2.4576 GBaud UI 1/2457.6-100ppm 1/2457.6 1/2457.6+100ppm ps —
Unit interval: 3.072 GBaud UI 1/3072.0-100ppm 1/3072.0 1/3072.0+100ppm ps —
Note:
1. Total random jitter is composed of deterministic jitter, random jitter and single frequency sinusoidal jitter. The sinusoidal jitter’s amplitude and frequency is defined in agreement with XAUI specification IEEE 802.3-2005 [1], clause 47.
2. The AC specifications do not include Refclk jitter. The sinusoidal jitter in the total jitter tolerance may have any amplitude and frequency in the unshaded region of Figure 43.
Table 62. Transmitter AC specifications (continued)
Electrical characteristics
B4420 QorIQ Qonverge Data Sheet, Rev. 0
Freescale Semiconductor 127
2.23.7.3.1 CPRI LV-II and LV-III transmitter specifications
This table provides the CPRI-LV-II and LV-III transmitter DC specifications.
This table provides the CPRI-LV-II/LV-III transmitter AC specifications.
Table 65. CPRI LV-II and LV-III transmitter DC specifications (XVDD = 1.35 V or 1.5 V)
Parameter Symbols Min Nom Max Units Condition
Output differential voltage (into floating load Rload=100 )
Unit interval: 1.2288 GBaud UI 1/1228.8-100ppm 1/1228.8 1/1228.8+100ppm us
Unit interval: 2.4576 GBaud UI 1/2457.6-100ppm 1/2457.6 1/2457.6+100ppm us
Unit interval: 3.072 GBaud UI 1/3072.0-100ppm 1/3072.0 1/3072.0+100ppm us
Unit interval: 4.9152 GBaud UI 1/4915.2-100ppm 1/4915.2.0 1/4915.2+100ppm us
Unit interval: 9.8304 GBaud UI 1/9830.4-100ppm 1/9.8304 1/9830.4+100ppm us
Note:
1. The Refclk jitter measured using Golden PLL is to be less than 0.05UI. The Golden PLL should have at maximum a bandwidth of baud rate over 1667, with a maximum of 20dB/dec rolloff, until at least baud rate over 16.67, with no peaking around the corner frequency.
B4420 QorIQ Qonverge Data Sheet, Rev. 0
Electrical characteristics
Freescale Semiconductor128
This table provides the CPRI-LV-II/LV-III transmitter AC specifications for 6.144 GBaud.
2.23.7.3.2 CPRI LV-II and LV-III receiver specifications
This table provides the CPRI LV-II and the CPRI LV-III receiver DC timing specifications.
Table 67. CPRI LV-II/LV-III transmitter AC specifications (6.144 GBaud)
Unit interval: 6.144 GBaud UI 1/6144.0-100ppm 1/61440 1/6144.0+100ppm us
Note:
1. The Refclk jitter measured using Golden PLL is to be less than 0.05UI. The Golden PLL should have at maximum a bandwidth of baud rate over 1667, with a maximum of 20dB/dec rolloff, until at least baud rate over 16.67, with no peaking around the corner frequency.
Table 68. CPRI-LV-II receiver DC specifications (SVDD = 1.0 V)
Parameter Symbols Min Nom Max Units
Input differential voltage R_Vdiff N/A — 1200 mV
Differential Resistance R_Rdin 80 — 120
Note:
1. It is assumed that for the R_diff Min spec, the eye can be closed at the receiver after passing the signal through a CEI/CPRI Level II LR-compliant channel.
Sinusoidal jitter, maximum R_SJ-max — — 5.000 UI p-p
Sinusoidal jitter, high frequency R_SJ-hf — — 0.050 UI p-p
Total jitter does not include sinusoidal jitter R_Tj — — 0.950 UI p-p
Unit Interval: 1.2288 GBaud UI 1/1228.8-100ppm 1/1228.8 1/1228.8+100ppm us
Unit Interval: 2.4576 GBaud UI 1/2457.6-100ppm 1/2457.6 1/2457.6+100ppm us
Unit Interval: 3.072 GBaud UI 1/3072.0-100ppm 1/3072.0 1/3072.0+100ppm us
Electrical characteristics
B4420 QorIQ Qonverge Data Sheet, Rev. 0
Freescale Semiconductor 129
This table provides the CPRI LV-II receiver AC specifications for 6.144 GBaud.
This table provides the LV-III RX parameters guided by 10GBase-KR electrical interface (IEEE 802.3 [22], clause 72.7.2).
Unit Interval: 4.9152 GBaud UI 1/4915.2-100ppm 1/4915.2.0 1/4915.2+100ppm us
Note:
1. The AC specifications do not include Refclk jitter. The sinusoidal jitter in the total jitter tolerance may have any amplitude and frequency in the unshaded region of Figure 43.
2. The ISI jitter (R_CBHPJ) and amplitude have to be correlated for example by a PCB trace.
3. The intended application is as a point-to-point interface of approximately 100cm and up to two connectors. The maximum allowed total loss (channel + interconnect+ other loss) is 20.6dB @ 6.144 Gb/s.
Table 70. CPRI LV-II receiver AC specifications (6.144 GBaud)
Sinusoidal jitter, maximum R_SJ-max — — 5.000 UI p-p
Sinusoidal jitter, high frequency R_SJ-hf — — 0.125 UI p-p
Total jitter does not include sinusoidal jitter R_Tj — — 0.6 UI p-p
Unit Interval: 6.144 GBaud UI 1/6144.0-100ppm 1/61440 1/6144.0+100ppm us
Note:
1. The AC specifications do not include Refclk jitter. The sinusoidal jitter in the total jitter tolerance may have any amplitude and frequency in the unshaded region of Figure 43.
2. The ISI jitter (R_CBHPJ) and amplitude have to be correlated for example by a PCB trace.
3. The intended application is as a point-to-point interface of approximately 60cm and up to two connectors. The maximum allowed total loss (channel + interconnect+ other loss) is 12.2dB @ 6.144 Gb/s.
4. R_Tj total jitter is measured at receiver inputs without post-equalizer.
Table 71. CPRI LV-III receiver AC specifications
Symbols Parameter Min Nom Max Units
Gaussian Jitter R_GJ — — 0.130 UI p-p
Sinusoidal Jitter, maximum R_SJ-max — — 0.115 UI p-p
Table 69. CPRI LV-II receiver AC specifications (continued)
Parameter Symbols Min Nom Max Units
B4420 QorIQ Qonverge Data Sheet, Rev. 0
Hardware design considerations
Freescale Semiconductor130
3 Hardware design considerations
3.1 System clockingThis section describes the PLL configuration of the chip.
3.1.1 PLL characteristics
Characteristics of the chip’s PLLs include the following:
• There are a total of 11 PLLs on the chip.
• There are two selectable e6500 core cluster PLLs which generate a core clock from the externally supplied SYSCLK input. The e6500 core complex can select from CGA1 PLL or CGA2 PLL. The frequency ratio between e6500 core cluster PLLs and SYSCLK is selected using the configuration bits as described in the applicable chip reference manual.
• There are two selectable SC3900 core clusters PLLs which generate a core clock from the externally supplied SYSCLK input. The SC3900 core clusters can select from CGB1 PLL or CGB2 PLL. The frequency ratio between SC3900 core clusters PLLs and SYSCLK is selected using the configuration bits as described in the applicable chip reference manual.
• The platform PLL generates the platform clock from the externally supplied SYSCLK input. The frequency ratio between the platform and SYSCLK is selected using the platform PLL ratio configuration bits as described in the applicable chip reference manual.
• The DDR PLLs generate the DDR clock, from the externally supplied D1_DDRCLK input (asynchronous mode). The frequency ratio is selected using the Memory Controller Complex PLL multiplier/ratio configuration bits as described in the applicable chip reference manual.
• Each of the two SerDes blocks has 1 PLLs which generate a core clock from their respective externally supplied SDn_REF1_CLK/SDn_REF1_CLK_B inputs. The frequency ratio is selected using the SerDes PLL ratio configuration bits as described in Section 3.1.5, “SerDes PLL ratio.”
Unit Interval: 9.8304 GBaud UI 1/9.8304-100ppm 1/9.8304 1/9.8304+100ppm us
Note:
1. The R_Tj is per Interference Tolerance Test IEEE Std 802.3ap-2007 specified in Annex 69A.
2. The AC specifications do not include Refclk jitter.
3. The maximum channel insertion loss is achieved by manual tuning TX equalization.
Table 71. CPRI LV-III receiver AC specifications (continued)
Hardware design considerations
B4420 QorIQ Qonverge Data Sheet, Rev. 0
Freescale Semiconductor 131
3.1.2 Clock ranges
This table provides the clocking specifications for the e6500 core, SC3900 core, Maple ETVPE, Maple/CPRI, Maple ULB, platform, and DDR memory.
NOTE
Hardware accelerators cannot run at core/3 and core/4 speeds if the core speed is configured to less than 1 GHz. When the core speed is configured to less than 1 GHz, core/4 speed is not feasible for DFS. Cluster PLL maximum output frequency is 1800 MHz if SYSCLK is lower than 100 MHz.
3.1.3 Platform to SYSCLK PLL ratio
The allowed platform clock to SYSCLK ratio is from 3:1 to 12:1.
3.1.4 PPC core cluster to SYSCLK PLL ratio
The allowed e6500 core cluster or SC3900 cluster PLL clock to SYSCLK ratio are from 6:1 to 27:1.
3.1.5 SerDes PLL ratio
The allowed platform clock to SYSCLK ratio are from 3:1 to 12:1.
Table 72. Clocking specifications
Characteristic Frequency
UnitNotes
Min Max —
e6500 core frequency 250 1600 MHz 1,2,3
SC3900 core frequency 250 1200 MHz 1,2,3
Maple ETVPE frequency 250 1000 MHz —
Maple/CPRI frequency 250 600 MHz —
Maple ULB frequency 250 800 MHz —
Platform clock frequency 400 667 MHz 1, 5
DDR memory bus clock frequency 1067 1600 MHz —
FM frequency 450 667 MHz 4
Notes:
1. Caution: The platform clock to SYSCLK ratio and any core to SYSCLK ratio settings must be chosen such that the resulting cores frequency, and platform clock frequency do not exceed their respective maximum or minimum operating frequencies.
2.The core can run at core complex PLL/1, PLL/2 or PLL/4 with a minimum PLL frequency of 1000.0 MHz. This results in a minimum allowable core frequency of 250 MHz for PLL/4.
3. The e6500 and SC3900 clusters frequency must be at least the (Platform frequency)/2 and higher.
4. FM minimum frequency is 450 MHz when only SGMII at 1 Gbps ports are required (for example, no usage of SGMII2.5). Otherwise, FM minimum frequency is 625 MHz.
5. 5G SRIO port operation is not supported for platform frequencies below 528 MHz.
B4420 QorIQ Qonverge Data Sheet, Rev. 0
Hardware design considerations
Freescale Semiconductor132
The clock ratio between each of the three SerDes PLLs and their respective externally supplied SDn_REF1_CLK/SDn_REF1_CLK_B inputs is determined by a set of RCW Configuration fields—SRDS_PRTCL_S1, SRDS_PLL_REF_CLK_SEL_S1 — as shown in this table.
Table 73. Valid SerDes RCW encoding and reference clocks
SerDes protocol (given lane)Valid reference clock frequency
1. A spread-spectrum reference clock is permitted for PCI Express. However, if any other high-speed interfaces such as debug is used concurrently on the same SerDes bank, spread-spectrum clocking is not permitted.
Hardware design considerations
B4420 QorIQ Qonverge Data Sheet, Rev. 0
Freescale Semiconductor 133
3.1.5.1 D1_DDRCLK and DDR1 memory frequency options
This table shows the expected frequency options for Dn_DDRCLK and DDRn memory frequencies.
3.2 Power supply design
3.2.1 Voltage ID (VID) controllable supply
To guarantee performance and power specifications, a specific method of selecting the optimum voltage-level must be implemented when the chip is used. As part of the chip's boot process, software must read the VID efuse values stored in the Fuse Status register (DCFG_CCSR_FUSESR) and then configure the external voltage regulator based on this information. This method requires an adjustable point of load voltage regulator (POL).
NOTE
During the power-on reset process, the fuse values are read and stored in the DCFG_CCSR_FUSESR. It is expected that the chip's boot code reads the DCFG_CCSR_FUSESR register very early in the boot sequence and updates the regulator accordingly.
Table 74. D1_DDRCLK and DDR1 data rate options
DDR1 data rate: D1_DDRCLK
D1_DDRCLK (MHz)
66.667 100.000 125.000 133.333
DDR1 data rate (MT/s)1
8:1 1067
9:1
10:1 1333
11:1
12:1 1600
13:1 1300
14:1
15:1
16:1 1067 1600
17:1
18:1 1200
19:1
20:1 1333
Notes:
1. DDR data rate values are shown rounded to the nearest whole number (decimal place accuracy removed)
B4420 QorIQ Qonverge Data Sheet, Rev. 0
Hardware design considerations
Freescale Semiconductor134
The default voltage regulator setting that is safe for the system to boot is the recommended operating VDD at initial start-up of 1.05 V. It is highly recommended to select a regulator with a Vout range of at least 0.9 V to 1.1 V, with a resolution of 12.5 mV or better, when implementing a VID solution.
For additional information on VID, see the chip reference manual.
3.2.1.1 Options for system design
There are several widely-accepted options available to the system designer for obtaining the benefits of a VID solution. The most common option is to use the VID solution to drive a system's controllable voltage-regulators through a sideband interface such as a simple parallel bus or PMBus interface. PMBus is similar to I2C but with extensions to improve robustness and address shortcomings of I2C; the PMBus specification can be found at www.pmbus.org. The simple parallel bus is supported by the chip through GPIO pins and the PMBus interface is supported by an I2C interface. Other VID solutions may be to access an FPGA/ASIC or separate power management chip through the IFC, SPI, or other chip-specific interface, where the other device then manages the voltage regulator. The method chosen for implementing the chip-specific voltage in the system is decided by the user.
3.2.1.1.1 Example 1: Regulators supporting parallel bus configuration
In this example, a user builds a VID solution using controllable regulators with a parallel bus. In this implementation, the user chooses to utilize any subset of the available GPIO pins on the chip except those noted below.
NOTE
GPIO pins that are muxed on an interface used by the application for loading RCW information are not available for VID use.
It is recommended that all GPIO pins used for VID are located in the same 32-bit GPIO IP block so that all bits can be accessed with a single read or write.
The general procedure for setting the core voltage regulator to the desired operating voltage is as follows:
1. The GPIO pins are released to high-impedance at POR. Because GPIO pins default to being inputs, they do not begin automatically driving after POR, and only work as outputs under software control.
2. The board is responsible for a default voltage regulator setting that is "safe" for the system to boot. To achieve this, the user puts pull-up and/or pull-down resistors on the GPIO pins as needed for that specific system. For the case where the regulator's interface operates at a different voltage than OVDD, the chip's GPIO module can be operated in an open drain configuration.
3. There is no direct connection between the Fuse Status Register (FUSESR) and the chip's pins. As part of the chip's boot process, software must read the efuse values stored in the FUSESR and then configure the voltage regulator based on this information. The software determines the proper value for the parallel interface and writes it to the GPIO block data (GPDAT) register. It then changes the GPIO direction (GPDIR) register from input to output to drive the new value on the device pins, thus overriding the board configuration default value. Note that some regulators may require a series of writes so that the voltage is slowly stepped from its old to its new value.
4. When the voltage has stabilized, software adjusts the operating frequencies as desired.
Upon completion of configuration, some regulators may have a write-protect pin to prevent undesired data changes after configuration is complete. A single GPIO pin on the chip could be allocated for this task if desired.
3.2.1.1.2 Example 2: Regulators supporting PMBus configuration
In this example, a user builds a VID solution using controllable regulators with a PMBus interface. For the case where the regulator's interface operates at a different voltage than DVDD, the chip's I2C module can be operated in an open-drain configuration.
In this implementation, the user chooses to utilize any I2C interface available on the chip. These regulators have a means for setting a safe, default, operating value either through strapping pins or through a default, non-volatile store.
Hardware design considerations
B4420 QorIQ Qonverge Data Sheet, Rev. 0
Freescale Semiconductor 135
NOTE
If I2C1 controller is selected, it is important that its calling address is different than the 7-bit value of 0x50h used by the pre-boot loader (PBL) for RCW and pre-boot initialization.
The general procedure for setting the core voltage regulator to the desired operating voltage is as follows:
1. The board is responsible for configuring a safe default value for the controllable regulator either through dedicated pins or its non-volatile store.
2. As part of the chip's boot process, software must read the efuse values stored in the FUSESR register and then configure the voltage regulator based on this information. The software decides on a new configuration and sends this value across the I2C interface connected to the regulator's PMBus interface. Note that some regulators may require a series of writes so that the voltage is slowly stepped from its old to its new value.
3. When the voltage has stabilized, software adjusts the operating frequencies as desired.
Upon completion of configuration, some regulators may have a write-protect pin to prevent undesired data changes after configuration is complete. A single GPIO pin on the chip could be allocated for this task, if desired.
3.2.1.1.3 Example 3: Regulators supporting FPGA/ASIC or separate power management device configuration
In this example, a user builds a VID solution using controllable regulators that are managed by a FPGA/ASIC or a separate power-management device. In this implementation, the user chooses to utilize the IFC, eSPI or any other available chip interface to connect to the power-management device.
The general procedure for setting the core voltage regulator to the desired operating voltage is as follows:
1. The board is responsible for configuring a safe default value for the controllable regulator either through dedicated pins or its non-volatile store.
2. As part of the chip's boot process, software must read the efuse values stored in the FUSESR and then configure the voltage regulator based on this information. The software decides on a new configuration and sends this value across the IFC, eSPI, or any other interface that is used to connect to the FPGA/ASIC or separate power-management device that manages the regulator. Note that some regulators may require a series of writes so that the voltage is slowly stepped from its old to its new value.
3. When the voltage has stabilized, software adjusts the operating frequencies as desired.
Upon completion of configuration, some regulators may have a write-protect pin to prevent undesired data changes after configuration is complete. A single GPIO pin on the chip could be allocated for this task, if desired.
3.2.2 Core supply voltage filtering
The VDD supply is normally derived from a high current capacity or switching power supply which can regulate its output voltage very accurately despite changes in current demand from the chip within the regulator’s relatively low bandwidth. Several bulk decoupling capacitors must be distributed around the PCB to supply transient current demand above the bandwidth of the voltage regulator.
These bulk capacitors should have a low ESR (equivalent series resistance) rating to ensure the quick response time necessary. They should also be connected to the power and ground planes through two vias to minimize inductance. However, customers should work directly with their power regulator vendor for best values and types of bulk capacitors.
As a guideline for customers and their power regulator vendors, Freescale recommends that these bulk capacitors be chosen to maintain the power supply voltage within ± 30 mV.
These bulk decoupling capacitors ideally supply a stable voltage for current transients into the megahertz range. Above that, see Section 3.3, “Decoupling recommendations for further decoupling recommendations.
B4420 QorIQ Qonverge Data Sheet, Rev. 0
Hardware design considerations
Freescale Semiconductor136
3.2.3 PLL power supply filtering
Each of the PLLs described in Section 3.1, “System clocking,” is provided with power through independent power supply pins (AVDD_PLAT, AVDD_CGAn, AVDD_CGBn and AVDD_DDR1 and AVDD_SRDSn_PLL1). AVDD_PLAT, AVDD_CGAn, AVDD_CGBn and AVDD_DDR1 voltages must be derived directly from a 1.8 V voltage source through a low frequency filter scheme. AVDD_SRDSn_PLL1 voltage must be derived directly from the XVDD voltage source through a low frequency filter scheme. The recommended solution for PLL filtering is to provide independent filter circuits per PLL power supply, as illustrated in Figure 47, one for each of the AVDD pins. By providing independent filters to each PLL, the opportunity to cause noise injection from one PLL to the other is reduced. This circuit is intended to filter noise in the PLL’s resonant frequency range from a 500 kHz to 10 MHz range.
Each circuit should be placed as close as possible to the specific AVDD pin being supplied to minimize noise coupled from nearby circuits. It should be possible to route directly from the capacitors to the AVDD pin, which is on the periphery of the footprint, without the inductance of vias.
This figure shows the PLL power supply filter circuit.
Where:
R = 5 ± 5%
C1 = 10 F ± 10%, 0603, X5R, with ESL 0.5 nH
C2 = 1.0 F ± 10%, 0402, X5R, with ESL 0.5 nH
NOTE
A higher capacitance value for C2 may be used to improve the filter as long as the other C2 parameters do not change (0402 body, X5R, ESL 0.5 nH).
Voltage for AVDD is defined at the input of the PLL supply filter and not the pin of AVDD.
Figure 47. PLL power supply filter circuit
The AVDD_SRDSn_PLL1 signals provides power for the analog portions of the SerDes PLL. To ensure stability of the internal clock, the power supplied to the PLL is filtered using a circuit similar to the one shown in following Figure 48. For maximum effectiveness, the filter circuit is placed as closely as possible to the AVDD_SRDSn_PLL1 balls to ensure it filters out as much noise as possible. The ground connection should be near the AVDD_SRDSn_PLL1 balls. The 0.003-µF capacitors closest to the balls, followed by a 4.7-µF and 47-µF capacitor, and finally the 0.33 resistor to the board supply plane. The capacitors are connected from AVDD_SRDSn_PLL1 to the ground plane. Use ceramic chip capacitors with the highest possible self-resonant frequency. All traces should be kept short, wide, and direct.
Figure 48. SerDes PLL power supply filter circuit
Note the following:
• AVDD_SRDSn_PLL1 should be a filtered version of XVDD.
AVDD_PLAT, AVDD_CGAn, AVDD_CGBn, AVDD_DDR1
C1 C2
GNDLow-ESL surface-mount capacitors
R1.8 V source
4.7 µF 0.003 µF
0.33
47 µF
AGND_SRDSn_PLL1
XVDD AVDD_SRDSn_PLL1
Hardware design considerations
B4420 QorIQ Qonverge Data Sheet, Rev. 0
Freescale Semiconductor 137
• Signals on the SerDes interface are fed from the XVDD power plane.
• Voltage for AVDD_SRDSn_PLL1 is defined at the PLL supply filter and not the pin of AVDD_SRDSn_PLL1.
• A 47-µF 0805 XR5 or XR7, 4.7-µF, and 0.003-µF or smaller capacitor are recommended. The size and material type are important. A 0.33-± 1% resistor is recommended.
• There needs to be dedicated analog ground, AGND_SRDSn_PLL1 for each AVDD_SRDSn_PLL1 pin up to the physical local of the filters themselves.
3.2.4 SVDD power supply filtering
SVDD should be supplied by a dedicated linear regulator. Systems may design to allow flexibility to address system noise dependencies.
NOTE
For initial system bring-up, the linear regulator option is highly recommended.
An example solution for SVDD filtering, where SVDD is sourced from linear regulator, is illustrated in Figure 49. The component values in this example filter are system dependent and are still under characterization, component values may need adjustment based on the system or environment noise.
Where:
C1 = 0.003F ± 10%, X5R, with ESL 0.5 nH
C2 and C3 = 2.2 F ± 10%, X5R, with ESL 0.5 nH
F1 to F4 are 0603 sized Ferrite SMD, like the Murata part BLM18PG121SH1. Its maximum DC resistance is 0.05, or 0.0125 for the parallel resultant, and each has about a 120+-25% of AC impedance at 100 MHz, which will be quarter valued for the parallel resultant, with individual maximum DC current carrying capacity of 2Amps. Bulk and decoupling capacitors are added, as needed, per power supply design.
Figure 49. SVDD power supply filter circuit
Note the following:
• See Section 2.5, “Power-on ramp rate for maximum SVDD power-up ramp rate.
• There must be enough output capacitance or a soft start feature to ensure that the ramp rate requirement is met.
3.2.5 XVDD power supply filtering
XVDD must be supplied by a linear regulator or sourced by a filtered G1VDD. Systems may design in both options to allow flexibility to address system noise dependencies.
NOTE
For initial system bring-up, the linear regulator option is highly recommended.
An example solution for XVDD filtering, where XVDD is sourced from a linear regulator, is illustrated in Figure 50. The component values in this example filter are system dependent and are still under characterization, component values may need adjustment based on the system or environment noise.
Where:
C1 = 0.003F ± 10%, X5R, with ESL 0.5 nH
SVDD Liner regulator output
C1 C2
GND
C3
Bulk anddecouplingcapacitors
F1
F2
B4420 QorIQ Qonverge Data Sheet, Rev. 0
Hardware design considerations
Freescale Semiconductor138
C2 and C3 = 2.2 F ± 10%, X5R, with ESL 0.5 nH
F1 to F4 are 0603 sized Ferrite SMD, like the Murata part BLM18PG121SH1. Its maximum DC resistance is 0.05, or 0.0125 for the parallel resultant, and each has about a 120+-25% of AC impedance at 100 MHz, which will be quarter valued for the parallel resultant, with individual maximum DC current carrying capacity of 2Amps.Bulk and decoupling capacitors are added, as needed, per power supply design.
Figure 50. XVDD power supply filter circuit
Note the following:
• See Section 2.5, “Power-on ramp rate for maximum XVDD power-up ramp rate.
• There must be enough output capacitance or a soft start feature to ensure the ramp rate requirement is met.
3.2.6 Remote power-supply sense recommendations
There is a practice of connecting the remote sense signal of an on-board power supply to one of power supply pins of an IC device. The advantage of this connection is the ability to compensate for the slow components of the IR droop caused by the resistive supply current path from the on-board power supply to the C5 pins layer on-package (for flip-chip packages).
However, not every C5 pin is selected to be the remote sense pin. It may be a reserved pin that requires a connection to be a supply or ground pin, and therefore must remain connected to the corresponding supply. Alternatively, the C5 pin may be supplying the critical power-consuming area of the IC die whose usage as non-supply pin may cause shortage in the supply current during high-current peaks.
It is recommended that these pins be used as the board supply remote sense output, because they do not degrade the power and ground supply quality:
• VDD/VSS sense pair: K9/J9 or AE12/AD11
Connect to either sense pair and leave the other pair unconnected.
3.3 Decoupling recommendationsDue to large address and data buses, and high operating frequencies, the device can generate transient power surges and high frequency noise in its power supply, especially while driving large capacitive loads. This noise must be prevented from reaching other components in the chip system, and the chip itself requires a clean, tightly regulated source of power. Therefore, it is recommended that the system designer place decoupling capacitors at each VDD, OVDD, QVDD, DVDD and G1VDD pin of the device. These decoupling capacitors should receive their power from separate VDD, OVDD, QVDD, DVDD and G1VDD and GND power planes in the PCB, utilizing short traces to minimize inductance. Capacitors may be placed directly under the device using a standard escape pattern. Others may surround the part.
These capacitors should have a value of 0.1 µF. Only ceramic SMT (surface mount technology) capacitors should be used to minimize lead inductance, preferably 0402 or 0603 sizes.
As presented in Section 3.2.2, “Core supply voltage filtering,” it is recommended that there be several bulk storage capacitors distributed around the PCB, feeding the VDD and other planes (For example, OVDD, QVDD, DVDD and G1VDD), to enable quick recharging of the smaller chip capacitors.
XVDDLinear regulator output
C1 C2
GND
F1
F2C3
Bulk anddecouplingcapacitors
Hardware design considerations
B4420 QorIQ Qonverge Data Sheet, Rev. 0
Freescale Semiconductor 139
3.4 SerDes block power supply decouplingrecommendations
The SerDes block requires a clean, tightly regulated source of power (SVDD and XVDD) to ensure low jitter on transmit and reliable recovery of data in the receiver. An appropriate decoupling scheme is outlined below.
NOTE
Only SMT capacitors should be used to minimize inductance. Connections from all capacitors to power and ground should be done with multiple vias to further reduce inductance.
1. The board should have at least 1 0.1-µF SMT ceramic chip capacitor placed as close as possible to each supply ball of the device. Where the board has blind vias, these capacitors should be placed directly below the chip supply and ground connections. Where the board does not have blind vias, these capacitors should be placed in a ring around the device as close to the supply and ground connections as possible.
2. Between the device and any SerDes voltage regulator there should be a lower bulk capacitor, for example, a 10-µF, low ESR SMT tantalum or ceramic chip capacitor and a higher bulk capacitor, for example, a 100-µF–300-µF low ESR SMT tantalum or ceramic chip capacitor.
3.5 Connection recommendations for unused pinsTo ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal level. All unused active low inputs and open-drain I/O should be tied to VDD, QVDD, DVDD, OVDD and G1VDD as required. All unused active high inputs should be connected to GND. All NC (no connect) signals must remain unconnected. Power and ground connections must be made to all external VDD, QVDD, DVDD, OVDD, G1VDD and GND pins of the chip.
Unused LVCMOS pins recommendations:
• For unused input only and bidirectional pins, connect with a pull-down resistor of 10 k.
• Unused output only pins can be left floating.
Unused DDR pins recommendations:
• When the following conditions are met, clocks, address, control, mask, cmd, data, strobes, MAPAR_OUT pin, and MAPAR_ERR_B pins can be left floating:
— the output buffer is tristated,
— the receiver is in sleep mode,
— and termination is off.
• When the conditions above are not met, connect the clocks, address, control, mask, cmd, data, positive strobes, MAPAR_OUT pin, and MAPAR_ERR_B pins to GND via a 1 kresistor. Negative strobes should be pulled-up to GnVDD via a 1 kresistor.
3.5.1 Legacy JTAG configuration signals
Correct operation of the JTAG interface requires configuration of a group of system control pins as demonstrated in Figure 52. Care must be taken to ensure that these pins are maintained at a valid deasserted state under normal operating conditions as most have asynchronous behavior and spurious assertion gives unpredictable results.
Boundary-scan testing is enabled through the JTAG interface signals. The TRST_B signal is optional in the IEEE Std 1149.1 specification, but it is provided on all processors built on Power Architecture technology. The device requires TRST_B to be asserted during power-on reset flow to ensure that the JTAG boundary logic does not interfere with normal chip operation. While the TAP controller can be forced to the reset state using only the TCK and TMS signals, generally systems assert TRST_B during the power-on reset flow. Simply tying TRST_B to PORESET_B is not practical because the JTAG interface is also used for accessing the common on-chip processor (COP), which implements the debug interface to the chip.
B4420 QorIQ Qonverge Data Sheet, Rev. 0
Hardware design considerations
Freescale Semiconductor140
The COP function of these processors allow a remote computer system (typically, a PC with dedicated hardware and debugging software) to access and control the internal operations of the processor. The COP interface connects primarily through the JTAG port of the processor, with some additional status monitoring signals. The COP port requires the ability to independently assert PORESET_B or TRST_B in order to fully control the processor. If the target system has independent reset sources, such as voltage monitors, watchdog timers, power supply failures, or push-button switches, then the COP reset signals must be merged into these signals with logic.
The arrangement shown in Figure 52 allows the COP port to independently assert PORESET_B or TRST_B, while ensuring that the target can drive PORESET_B as well.
The COP interface has a standard header, shown in Figure 51, for connection to the target system, and is based on the 0.025" square-post, 0.100" centered header assembly (often called a Berg header). The connector typically has pin 14 removed as a connector key.
The COP header adds many benefits such as breakpoints, watchpoints, register and memory examination/modification, and other standard debugger features. An inexpensive option can be to leave the COP header unpopulated until needed.
There is no standardized way to number the COP header; so emulator vendors have issued many different pin numbering schemes. Some COP headers are numbered top-to-bottom then left-to-right, while others use left-to-right then top-to-bottom. Still others number the pins counter-clockwise from pin 1 (as with an IC). Regardless of the numbering scheme, the signal placement recommended in Figure 51 is common to all known emulators.
3.5.1.1 Termination of unused signals
If the JTAG interface and COP header are not used, Freescale recommends the following connections:
• TRST_B should be tied to PORESET_B through a 0 k isolation resistor so that it is asserted when the system reset signal (PORESET_B) is asserted, ensuring that the JTAG scan chain is initialized during the power-on reset flow. Freescale recommends that the COP header be designed into the system as shown in Figure 52. If this is not possible, the isolation resistor will allow future access to TRST_B in case a JTAG interface may need to be wired onto the system in future debug situations.
• No pull-up/pull-down is required for TDI, TMS or TDO.
Figure 51. Legacy COP Connector Physical Pinout
3
13
9
5
1
6
10
15
11
7
16
12
8
4
KEYNo pin
1 2COP_TDO
COP_TDI
NC
NC
COP_TRST_B
COP_VDD_SENSE
COP_CHKSTP_IN_B
NC
NC
GND
COP_TCK
COP_TMS
COP_SRESET_B
COP_HRESET_B
COP_CHKSTP_OUT_B
Hardware design considerations
B4420 QorIQ Qonverge Data Sheet, Rev. 0
Freescale Semiconductor 141
Figure 52. Legacy JTAG interface connection
PORESET_B
From targetboard sources
COP_HRESET13
COP_SRESET
HRESET_B
NC
11
COP_VDD_SENSE26
15
10
10 k
COP_CHKSTP_IN_B8
COP_TMS
COP_TDO
COP_TDI
COP_TCK
TMS
TDO
TDI
9
1
3
4COP_TRST
7
16
2
10
12
(if any)
CO
P H
ead
er
14 3
Notes:
10 k
TRST_B110 k
10 k
10 k
CKSTP_OUT_BCOP_CHKSTP_OUT_B
3
13
9
5
1
6
10
15
11
7
16
12
8
4
KEYNo pin
COP ConnectorPhysical Pinout
1 2
NC
HRESET_B6
2. Populate this with a 10 resistor for short-circuit/current-limiting protection.
NC
OVDD
10 kPORESET_B1
in order to fully control the processor as shown here.
1. The COP port and target board should be able to independently assert POREST_B and TRST_B to the processor
signal integrity.
TCK
4
5
5.This switch is included as a precaution for BSDL testing. The switch should be closed to position A during BSDL testing
to position B.
10 k
6. Asserting HRESET_B causes a hard reset on the chip.
3. The KEY location (pin 14) is not physically present on the COP header.4. Although pin 12 is defined as a No-Connect, some debug tools may use pin 12 as an additional GND pin for improved
to avoid accidentally asserting the TRST_B line. If BSDL testing is not being performed, this switch should be closed
AB
5
System logic
7. This gate is an open-drain gate.
1 k7
B4420 QorIQ Qonverge Data Sheet, Rev. 0
Hardware design considerations
Freescale Semiconductor142
3.5.2 Aurora configuration signals
Correct operation of the Aurora interface requires configuration of a group of system control pins as demonstrated in Figure 54. Care must be taken to ensure that these pins are maintained at a valid deasserted state under normal operating conditions as most have asynchronous behavior and spurious assertion gives unpredictable results.
Freescale recommends the Aurora 34 or 70 pin duplex connectors be designed into the system as shown in the following figures.
If the Aurora interface is not used, Freescale recommends the legacy COP header be designed into the system as described in Section 3.5.1.1, “Termination of unused signals.”
1. The Aurora port and target board should be able to independently assert PORESET_B and TRST_B to the processor
TCK
3 10 k
_B4
AB
34 Vendor I/O 5 (Aurora_HRESET_B)
18 Vendor I/O 2 (Aurora_Event_Out_B)
16Vendor I/O 1 (Aurora_Event_In_B)
14Vendor I/O 0 (Aurora_HALT_B)
5,11,17
EVT[4]
EVT[1]
EVT[0]
1TX0_P
3TX0_N
SD1_TX3_P
SD1_TX3_N
7TX1_P
9TX1_N
SD1_TX2_P
SD1_TX2_N
13RX0_P
15RX0_N
SD1_RX3_P
SD1_RX3_N
19RX1_P
21RX1_N
SD1_RX2_P
SD1_RX2_N
0.01 uF0.01 uF
0.01 uF0.01 uF
20,25 NC
REF_CLK_B
SD1_REF1_CLKSD1_REF1_CLK_B
2628
3
13
9
5
1
6
10
15
11
7
16
12
8
4
1 2
17 18
2019
21 22
14
25
31
27
23
28
32
33
29
34
30
26
24
32,3327,31
10 k
HRESET_B
1 k
5
CLK_NCLK_P
REF_CLKREF_CLK1REF_CLK1_B
100 nF
100 nF
66
AURORA_TRST_B
in order to fully control the processor as shown here.2. Populate this with a 1 k resistor for short-circuit/current-limiting protection.3. This switch is included as a precaution for BSDL testing. Close the switch to position A during BSDL testing to avoid
accidentally asserting the TRST_B line. If BSDL testing is not being performed, close this switch to position B.4. Asserting HRESET_B causes a hard reset on the device. 5. This is an open-drain output gate.6. REF_CLK/REF_CLK_B and REF_CLK1/REF_CLK1_B are buffered clocks from the same common source.
2. Populate this with a 1 k resistor for short-circuit/current-limiting protection.
OVDD
10 k
in order to fully control the processor as shown here.1. The Aurora port and target board should be able to independently assert PORESET_B and TRST_B to the processor
3
3.This switch is included as a precaution for BSDL testing. Close the switch to position A during BSDL testing to avoid
10 k
accidentally asserting the TRST_B line. If BSDL testing is not being performed, close this switch to position B.
4. Asserting HRESET_B causes a hard reset on the device. 5. This is an open-drain gate.6. REF_CLK/REF_CLK_B and REF_CLK1/REF_CLK1_B are buffered clocks from the same common source.
HRESET_B4 1 k
PORESET_B1
TRST_B1
TMS
TDO
TCK
TDI
SD2_REF1_CLK_B
SD2_REF1_CLK
EVT[4]EVT[1]EVT[0]
SD2_TX3
SD2_TX3_BSD2_TX2
SD2_TX2_BSD2_RX3
SD2_RX3_B
SD2_RX2
SD2_RX2_B
B4420 QorIQ Qonverge Data Sheet, Rev. 0
Hardware design considerations
Freescale Semiconductor146
3.5.3 Guidelines for high-speed interface termination
3.5.3.1 SerDes interface entirely unused
If the high-speed SerDes interface is not used at all, the unused pin should be terminated as described in this section.
Note that both SVDD and XVDD must remain powered.
The following pins must be left unconnected:
• SD1_TX[5:2]
• SD1_TX[5:2]_B
• SD2_TX[3:0]
• SD2_TX[3:0]_B
The following pins must be connected to SGND:
• SDn_REF1_CLK
• SDn_REF1_CLK_B
• SD1_RX[5:2]
• SD1_RX[5:2]_B
• SD2_RX[3:0]
• SD2_RX[3:0]_B
The following pins must be left unconnected:
• SDn_IMP_CAL_RX
• SDn_IMP_CAL_TX
In the RCW configuration fields SRDS_PLL_PD_S2 must be set to power down mode in any case, SRDS_PLL_PD_S1 will be set to power down if the SerDes is completely not used.
3.5.3.2 SerDes interface partly unused
If only part of the high speed SerDes interface pins are used, the remaining high-speed serial I/O pins should be terminated as described in this section.
The following unused pins must be left unconnected:
• SDn_TX[n]
• SDn_TX[n]_B
The following unused pins must be connected to SGND:
• SDn_RX[n]
• SDn_RX[n]_B
In the RCW configuration field SRDS_PLL_PD_Sn, the respective bits for each unused module must be set to power down PLL1 of the corresponding SerDes module.
After POR, if an entire SerDes module is unused, it can be powered down by clearing the SDEN fields of its corresponding PLL1 reset control registers (SRDSn_PLL1RSQCTL).
Unused lanes can be powered down by clearing the RRST and TRST fields and setting the RX_PD and TX_PD fields in the corresponding lane’s general control register (SRDSn_LxGCR0).
Hardware design considerations
B4420 QorIQ Qonverge Data Sheet, Rev. 0
Freescale Semiconductor 147
3.6 ThermalThis table shows the thermal characteristics for the chip.
3.7 Thermal management informationThis section provides thermal management information for the flip-chip, plastic-ball, grid array (FC-PBGA) package for air-cooled applications. Proper thermal control design is primarily dependent on the system-level design—the heat sink, airflow, and thermal interface material. The recommended attachment method to the heat sink is illustrated in Figure 57. The heat sink
1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance.
2. Per JEDEC JESD51–3 and JESD51–6 with the board (JESD51–9) horizontal.3. Thermal resistance between the die and the printed-circuit board per JEDEC JESD51–8. Board temperature is measured on
the top surface of the board near the package.4. Junction-to-case-top at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate temperature is
used for the case temperature. Reported value includes the thermal resistance of the interface layer.5. Junction-to-lid-top thermal resistance is determined using the MIL-STD 883 Method 1012.1. However, instead of the cold
plate, the lid-top temperature is used here for the reference case temperature. Reported value does not include the thermal resistance of the interface layer between the package and the cold plate.
6. See Section 3.7, “Thermal management information,” for additional details.
B4420 QorIQ Qonverge Data Sheet, Rev. 0
Hardware design considerations
Freescale Semiconductor148
should be attached to the printed-circuit board with the spring force centered over the die. This spring force should not exceed 31 lbs (137 Newton).
The system board designer can choose between several types of heat sinks to place on the device. There are several commercially-available thermal interfaces to choose from in the industry. Ultimately, the final selection of an appropriate heat sink depends on many factors, such as thermal performance at a given air velocity, spatial volume, mass, attachment method, assembly, and cost.
3.7.1 Internal package conduction resistance
For the package, the intrinsic internal conduction thermal resistance paths are as follows:
• The die junction-to-case thermal resistance
• The die junction-to-lid-top thermal resistance
• The die junction-to-board thermal resistance
This figure depicts the primary heat transfer path for a package with an attached heat sink mounted to a printed-circuit board.
Figure 58. Package with heat sink mounted to a printed-circuit board
Adhesive or
Heat sink FC-PBGA package (with lid)
Heat sink clip
Printed-circuit board
thermal interface materialDie
Die lid
Lid adhesive
External resistance
External Resistance
Internal resistance
Radiation Convection
Radiation Convection
Heat sink
Printed-circuit board
Thermal interface material
Package/Solder ballsDie junctionDie/Package
(Note the internal versus external package resistance)
Junction to lid top
Junction to case top
Package information
B4420 QorIQ Qonverge Data Sheet, Rev. 0
Freescale Semiconductor 149
The heat sink removes most of the heat from the device. Heat generated on the active side of the chip is conducted through the silicon and through the heat sink attach material (or thermal interface material), and finally to the heat sink. The junction-to-case thermal resistance is low enough that the heat sink attach material and heat sink thermal resistance are the dominant terms.
3.7.2 Thermal interface materials
A thermal interface material is required at the package-to-heat sink interface to minimize the thermal contact resistance. The performance of thermal interface materials improves with increasing contact pressure; this performance characteristic chart is generally provided by the thermal interface vendor. The recommended method of mounting heat sinks on the package is by means of a spring clip attachment to the printed-circuit board (see Figure 57).
The system board designer can choose among several types of commercially-available thermal interface materials.
3.8 Temperature diodeThe chip has temperature diodes that can be used to monitor its temperature using external temperature monitoring devices (such as Analog Devices, ADT7461A™). These on-chip temperature diodes have pins that may be connected to test points, or left as a no connect when they are not used.
The following are specifications of the chip temperature diodes:
• Operating range: 10–230A
• Non-ideality factor over entire temperature range: n = 1.006 ± 0.003
4 Package information
4.1 Package parameters for the FC-PBGAThe package parameters are as provided in the following list. The package type is 33 mm 33 mm, 1020 flip-chip, plastic-ball, grid array (FC-PBGA). The device part is designed to be RoHS and Pb-free compliant.
Package outline 33 mm 33 mm
Interconnects 1020
Ball Pitch 1.0 mm
Ball Diameter (typical) 0.60 mm
Solder Balls 96.5% Sn, 3% Ag, 0.5% Cu
Module height (typical) 2.63 mm to 2.93 mm (maximum)
B4420 QorIQ Qonverge Data Sheet, Rev. 0
Package information
Freescale Semiconductor150
4.2 Mechanical dimensions of the B4420 FC-PBGAThis figure shows the mechanical dimensions and bottom surface nomenclature of the chip.
Figure 59. Mechanical dimensions of the FC-PBGA with full lid
NOTES:
1. All dimensions are in millimeters.2. Dimensions and tolerances per ASME Y14.5M-1994.
3. All dimensions are symmetric across the package center lines unless dimensioned otherwise.
4. Maximum solder ball diameter measured parallel to datum A.5. Datum A, the seating plane, is determined by the spherical crowns of the solder balls.
6. Parallelism measurement excludes any effect of mark on top surface of package.
Security fuse processor
B4420 QorIQ Qonverge Data Sheet, Rev. 0
Freescale Semiconductor 151
5 Security fuse processorThis chip implements the trust architecture, supporting capabilities such as secure boot. Use of the trust architecture features is dependent on programming fuses in the Security Fuse Processor (SFP). The details of the trust architecture and SFP can be found in the chip reference manual.
To program SFP fuses, the user is required to supply 1.8 V to the POVDD pin per Section 2.2, “Power sequencing.” POVDD should only be powered for the duration of the fuse programming cycle, with a per device limit of two fuse programming cycles. All other times POVDD should be connected to GND. The sequencing requirements for raising and lowering POVDD are shown in Figure 8. To ensure device reliability, fuse programming must be performed within the recommended fuse programming temperature range per Table 4.
NOTE
Users not implementing the QorIQ platform’s trust architecture features should connect POVDD to GND.
6 Ordering informationContact your local Freescale sales office or regional marketing team for order information.
6.1 Part numbering nomenclatureThis table provides the Freescale QorIQ Qonverge platform part numbering nomenclature.
Note:
1. One XVDD = 1.35V option is available for part ‘X’ extended temperature range.
Table 76. Part numbering nomenclature
B 4 4 2 0 N S1 E 7 Q U M A
Platform
Numberof Power
corethreads
Number of DSP cores
Deriv-ative
Qualstatus
Temperature
range and power levels
Encryp-tion
Packagetype
CPUspeed
DDR speed
DSPspeed
Dierevision
B =Base-bandPB =ProtoBase-band
4 =Macro
4 = 4 core threads
2 = 2 cores 0 = First product
P =Prototype
N =Indust tier
S =Standard temperature (0 to 105) and standard powerX =Extended temperature (–40 to 105) and standard power
E =SEC presentN =No SEC
7 =FC-PBGAC4/C5Pb-free
Q =1600 MHz
Q =1600 MHz
M =1200 MHz
A =Rev 1.0B =Rev 2.0C =Rev 2.1D =Rev 2.2
B4420 QorIQ Qonverge Data Sheet, Rev. 0
Revision history
Freescale Semiconductor152
6.1.1 Part marking
Parts are marked as in the example shown in this figure.
Figure 60. Part marking for FC-PBGA chip
7 Revision historyThis table summarizes changes to this document.
Table 77. Revision history
Rev.Number
Date Description
0 08/2015 • Initial public release
Notes:
MMMMM is the mask number.
ATWLYYWW is the test traceability code.
FC-PBGA
B4420XXX7XXMX
B4420XXX7XXMX represents the orderable part number.
CCCCC is the assembly country code.
MMMMM
YWWLAZ
YWWLAZ is the assembly traceability code.
ATWLYYWW
CCCCC
Document Number: B4420Rev. 0
08/2015
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Freescale reserves the right to make changes without further notice to any products
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