BACKGROUND DIGITAL ERROR CORRECTION TECHNIQUE FOR PIPELINEDANALOG-DIGITAL CONVERTERS
Sameer R. Sonkusale and Jan Van der Spiegel
Department of Electrical EngineeringUniversity of Pennsylvania
200 S. 33rd St. Philadelphia, PA 19104, USA
K. Nagaraj
Texas Instruments15 Independence Blvd.
Warren, NJ 07059, USA
ABSTRACT
This paper describes a technique for digital error correctionin pipelined analog-digital converters. It makes use of aslow, high resolution ADC in conjunction with an LMS al-gorithm to perform error correction in the background duringnormal conversion. The algorithm will be shown to correctfor errors due to capacitor ratio mismatch, finite amplifiergain and charge injection within the same framework.
1. INTRODUCTION
Pipelined ADCs have been shown to work at very highspeeds but their resolution is limited by component mis-matches, op-amp gain error, offsets, charge injection errorsand component non-linearities. Self calibration and back-ground calibration techniques have been developed to cor-rect for these non-idealities[1],[2],[3],[4]. One method forbackground calibration is to employ an extra pipeline stagethat is used to substitute the stage being calibrated [4]. Thedisadvantage of this technique is that it results in fixed pat-tern noise due to periodic substitution of stages. Anotherproposed background calibration scheme inplemented fortime-interleaved ADC requires the addition of a calibrationsignal to the input [5]. Such techniques result in a reductionof the useful dynamic range of the converter. A backgrounderror correction technique using a skip-and-fill algorithmhas also been proposed in [3]. But it needs to bandlimit thesignal below the nyquist rate. Moreover, none of the errorcorrection techniques mentioned above correct for all thesystematic non-idealities in a pipelined ADC within a singleframework.This paper describes a true background error correction tech-nique for a one-bit per stage pipelined ADC using a slow,high-resolution ADC (SHADC) in conjunction with an LMSalgorithm [6]. The idea can also be extended to a multi-bitper stage pipelined converter.
2. ONE-BIT PER STAGE PIPELINE A/DCONVERTER
A simplified block diagram of an ideal N-stage, 1-bit perstage, A/D converter is shown in figure 1. The most signifi-
cant bits are resolved by the stages earlier in the pipeline. Amost conventional switched capacitor implementation of apipeline stage is shown in figure 2 [7]. A single ended circuitis shown for simplicity.
� ! " #is the positive reference volt-
age and� ! " $
is a negative reference voltage.� ! " #&%'� ! " $
defines the resolvable range of the A/D converter. Each
stage consists of two nominally equal capacitors E 1 and E 2,an operational amplifier, and a comparator. During the sam-pling phase F 1, the comparator produces a digital output GIH :
GIH&J K 1 if� H $ML N OQPR� S T
0 if� H $ML N OQUR� S T L
1O
where,� S T
is the threshold voltage defined midway between� ! " #and� ! " $
.During the multiply-by-2 and subtract phase, the above cir-
cuit generates a residue voltage V W X Y Z [ \ given by:
Vout ] i ^M_ K ` a 1 b C1C2 c Vin ] i ^db C1
C2a e DiVrefp e D̄iVrefn c f bhgi _kj 0
1 lQm 1m 2l j 0 ] 2 ^
where, the parameter n is an op-amp gain error coeffecient(ideally unity) and o 0 is the finite op-amp gain. Differentialcharge injection has been included in the above expressionas an additive error term p . Ideally, we expect the residuevoltage to be:
V W X Y Z [ \rq 2 V s tdZ [ \&uwvIs V x y z {Iu ¯vIs V x y z t|Z 3 \This output residue voltage is then passed to the next stage[d} 1, and the same operation continues.
3. PROPOSED DIGITAL ERROR CORRECTIONSCHEME
Thebasic idea of the proposed digital error correction schemeis to correct for the residue errors in a non-ideal pipeline stageusing a suitable set of parameters which are determined bycomparing it’s residue output with the ideal estimate gener-ated using a slow high-resolution ADC(SHADC) [6]. Everystage needing error correction has an associatedset of param-eters. For practical values of the capacitor ratio mismatchand other non-idealities in the present technologies, errorcorrection is usually required only for the first few stagesin the pipeline. Error correction proposed in this paper in-volves two steps. The first step is the parameter estimationstep shown in the figure 3. In this figure, the pipelined
F(.)
Vin
DMSB
ADC-FE ADC-BE
Earlier stagesin the pipeline
Stage needingerror correction
Later stagesin the pipeline
D
D
DDi
out
est
FE
Dideal
stage i
CorrectionAlgorithm SHADC
Vout
Slow high-resolution ADC
Figure 3: Basic idea of the calibration algorithm
ADC of figure 1 is represented as a combination of an ADCFront-End(ADC-FE), the stage needing error correction andan ADC Back-End(ADC-BE). ADC-FE and ADC-BE areused to represent the stages in the pipeline, before and after
the stage needing error correction(calibration). The slow,high-resolution ADC (SHADC) is connected in parallel tothe stage under correction. The digital output of the ADC-BE, v~W X Y is processed digitally by a function � , given by:
v~y � Y&qR�~Z v~W X Y \&qR�&v~W X YM}w� Z 4 \If the values of the parameters, � and � are chosen appro-priately, v~y � Y can be made as close to the ideal value ofvIs � y � � as possible. v~y � Y can now be used instead of v~W X Yfor the final computation of the digital output. Once the pa-rameters for the present stage are estimated, we can start theparameter estimation for the next stage needing calibration.Parameter estimation starts with the least significant stageneeding error correction till the most significant stage.Once the parameters � , � for all the stages needing calibra-tion are known, the second step is to compute the final digitaloutput of the ADC. This is discussed in section 5. Anotherissue is to implement the correction algorithm to determinethe parameter set Z �Q� ��\ . We use a Least-Mean-Squaresapproach to estimate these parameters. The algorithm issummarized below:
1. Initialize the parameter set Z �Q� ��\ .2. Compute Error �rqRvIs � y � � uwv~y � Y and � 23. Modify � and � as:
��t y ��qR�&W � ��u���� � 2� � q��&W � ��} ´��� v~W X Y� t y ��q��dW � ��u���� � 2� � q��dW � ��} ´��� Z 5 \The ´� is the update step size for the LMS algorithm. Theabove algorithm gives a unique desired solution for the pa-rameter set Z �Q� ��\ . For ease of implementation and to getrid of multipliers, a modified sign implementation of thegradient descent algorithm can be used.
��t y �hqR�&W � �Q} ´��� � ��Z � \r� [ � ��Z v~W X Y \� t y ��q��dW � ��} ´��� � ��Z � \ Z 6 \where, � � ��Z � \�q 0 if ��q 0, otherwise � � ��Z � \�q 1 if � ispositive and � � ��Z � \rq�u 1 if � is negative [8], [9].
4. CORRECTION OF NON-IDEALITIES
It can be shown that v~W X Y of the ADC-BE in figure 3 is anexact digital representation of the residue output V W X Y of thestage under calibration, if the following stages constitutingthe ADC-BE are ideal. This is a reasonable assumptionfor the practical values of the non-idealities in the circuit,when we use a few extra stages of pipeline at the end [6].Similarly vIs � y � � will give an accurate digital representa-tion of the ideal residue output ( V s � y � � ) of the same stage(under calibration) for the same input. The parameter esti-mation described in the previous section essentially drivesthe V W X Y to be as close to V s � y � � as possible. Let’s assume
. In this case, we need two parameters perpipeline stage for error correction. Three special cases forequation 7 are outlined below.
1. Capacitor ratio mismatch Æ , ÆÈÇ� 1: In this case,ÉÊ�1 and ¤ � 0. The parameter set ( ªQ« ¬ ) of
function obtained via parameter estimation will be:
ª � 21 ËwÆ « ¬� � � � � ¿ 1
Æ1 ËwÆ Ì 8 Í
The above equation implies that we need just oneparameter per stage for error correction.
2. Finite op-amp gain errorÉ Ç� 1,
É£Î1: In this case,Æ � 1 and ¤ � 0. The parameters for the function
obtained will then be:
ª � 1É « ¬� � � � � 0 Ì 9 ÍIn this case we just one parameter per pipeline stagefor error correction.
3. Finite op-amp gain error and capacitor ratio mis-match: In this case, we have ¤ � 0. The parameterset ( ªQ« ¬ ) of function obtained via parameter esti-mation will be:
ª � 2É Ì 1 ËwÆ�Í «¬� � � � � ¿ 1
Æ1 Ë�Æ|Ì 10 Í
In this case, we need two parametersper pipeline stageto estimate the correct residue.
In the above discussion, we have neglected the input depen-dency of the non-idealities like finite op-amp gain. Usingmore parameters, we can account for the variation of theop-amp gain over the input range. Some of the other not-so-serious non-idealities like comparator offsets and op-ampoffsets can be minimized using established circuit designtechniques.
5. DIGITAL COMPUTATION OF THE OUTPUT
Once the function or equivalently the parameters ( ªQ« ¬ )for the MSB stages needing error correction have been es-timated, it can be stored in an on-chip memory. The com-putation of a digital output for an input voltage involvesrecursive processing of the raw digital output through thefunctions for the MSB stages. One such implementation
is given in [6]. Lets assume that the estimated function inequation 4 for any stage Ï is given by &Ð . Assume that thereare M stages in a pipeline and let B be the required resolution(MÅ
B). Also lets assume that the parameter estimation hasbeen performed only for the first Q stages in the pipeline.The computation of the digital output is summarized below:
1. Start with the last calibrated stage (l = Q).
2. Set the digital estimate ( Ñ � Ò Ã )= digital code from stagel+1 onwards.
3. Get the refined digital estimate Ñ ¢ � Ó� Ò Ã by processingthe previous digital estimate ( Ñ � Ò Ã ) by function &Ðand add the bit Ñ~Ð to the estimate as its MSB. Thus,we have Ñ ¢ � Ó� Ò Ã � Ñ~Ð &Ð Ì Ñ � Ò Ã Í � 2 Ô²Õ Ð Ë�&Ð Ì Ñ � Ò Ã Í .
4. Move to the next most significant stage (l := l -1).Assign Ñ � Ò Ã :
� Ñ ¢ � Ó� Ò Ã .
5. If l = 1 (MSB stage), go to the next step, else, go tostep 3.
6. Discard the least significant M-B bits in Ñ � Ò Ã . Thiswill give a B-bit corrected output code.
Parameter estimation can be run in the background dur-ing normal conversion. Since the parameters change onlyslowly with time, the algorithm can be run only once in fewthousand cycles. This greatly relaxes the speed requirementof the SHADC, giving an opportunity to trade-off speedfor high linearity in its design. The SHADC can be a self-calibrating algorithmic ADC, with a slow, high-gain op-amp[1]. The whole algorithm for calibration and computation ofthe output is done in the digital domain with the use of fewparameters (small memory), few multiplications and addi-tions (few multipliers and adders). These multiplications atfull speed can be easily implemented using shift registerssince the parameters can be expressed in binary with a suffi-ciently high resolution. However, multipliers will be neededto implement the LMS algorithm for parameter estimationusing equation 5. However, if we use the modified LMSalgorithm of equation 6, we get rid of mulitpliers as well.
6. SIMULATION RESULTS
A 10-bit resolution ADC has been simulated in MATLABfor illustration purposes. However the scheme is intendedto be implemented for resolutions greater than 12bits. Thereare 15 stages in the pipeline. Only the first four stages arecalibrated. The quantization error in the computation ofthe parameters for each stage has been neglected. Simu-lation results are presented for the pipelined ADC havingcapacitor ratio mismatch of 2
6% and the op-amp gain
of 300
500. The parameter estimation for the ADC wasstopped when all the stages, needing calibration were cali-brated within 0.5LSB of the expected resolution of the rest of
I-410
the pipeline. A ramp input was given to the ADC. Figure 4shows the uncorrected and the corrected INL profile for theADC and similarly, figure 5 shows the DNL profile for theADC before and after digital error correction(calibration).The results indicate that the worst case INL has been im-proved from Ö 7 × 5 LSB to Ö 0 × 5 LSB. Similarly the DNLprofile indicate an improvement from 14 LSB to Ö 1 LSB.Simulations for the case1 and case2 of section 4 were alsocarried out and the results are summarized in the table below:
Cap. Mismatch 2-6% Nil 2-6%Op-amp gain 80000 200-500 300-500
Figure 4: INL error profile: capacitor ratio mismatch 2-6%,op-amp gain 300-500 a) Before Correction b) After ErrorCorrection
0 200 400 600 800 10000
2
4
6
8
10
12
14
Transition Codes (982/1024)
DN
L in
LS
B
0 200 400 600 800 1000−2
−1
0
1
2
Transition Codes (1024/1024)
DN
L in
LS
B
Figure 5: DNL error profile: capacitor ratio mismatch 2-6%, op-amp gain 300-500 a) Before Correction b) AfterError Correction
7. CONCLUSIONS
A background error correction technique for pipelined ADChas been proposed. It has been shown to correct for system-atic non-idealities like op-amp finite gain error, capacitor
ratio mismatch and charge injection. Different cases fornon-idealities in the pipelined converter have been formu-lated. The idea has been illustrated using a 10-bit converter.
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