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“Enabling Semiconductor Innovation and Growth”
EUV lithography drives Moore’s law well into the next decade
Craig De Young
Vice President IR - Asia IR
March 14, 2018
Public
BAML 2018 APAC TMT ConferenceTaipei, Taiwan
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Public
Slide 2
January 17, 2018
Forward looking statements
This document contains statements relating to certain projections, business trends and other matters that are forward-looking, including statements with respect to expected trends and outlook, including expected trends in the semiconductor market, expected annual operating profit, systems backlog, statements with respect to expected revenue growth in the semiconductor market, including expected forecast growth by market, the expected relative semiconductor content in automotive innovations by 2030, expected growth drivers in lithography demand in 2020, statements with respect to industry shrink roadmaps, EUV insertion plans and customer roadmaps, statements with respect to the expected continuation of scaling and transistor density by 2030, expectations with respect to EUV, including expected benefits, including lithography cost reduction and the expected benefits of High NA, target performance, EUV industrialization, including availability and throughput, shipments and the expectation that the installed base of EUV systems will double in 2018, the expected innovation pipeline in the next 10 years and beyond, the expected increased impact of new scalable memory types in the next 10 years and the expectation that such types will continue driving lithography, statements with respect to shrink being a key driver supporting innovation and providing long-term industry growth, lithography enabling affordable shrink and delivering value to customers, and statements with respect to the expected continuation of Moore's law and that EUV and scaling and shrinking will continue to support and enable Moore’s law and drive long term value for ASML beyond the next decade. You can generally identify these statements by the use of words like "may", "will", "could", "should", "project", "believe", "anticipate", "expect", "plan", "estimate", "forecast", "potential", "intend", "continue", "targets", "commits to secure" and variations of these words or comparable words.
These statements are not historical facts, but rather are based on current expectations, estimates, assumptions and projections about the business and our future financial results and readers should not place undue reliance on them. Forward-looking statements do not guarantee future performance and involve risks and uncertainties. These risks and uncertainties include, without limitation, economic conditions, product demand and semiconductor equipment industry capacity, worldwide demand and manufacturing capacity utilization for semiconductors, including the impact of general economic conditions on consumer confidence and demand for our customers' products, competitive products and pricing, the impact of any manufacturing efficiencies and capacity constraints, performance of our systems, the continuing success of technology advances and the related pace of new product development and customer acceptance of new products including EUV, the number and timing of EUV systems expected to be shipped and recognized in revenue, delays in EUV systems production and development and volume production by customers, including meeting development requirements for volume production, demand for EUV systems being sufficient to result in utilization of EUV facilities in which ASML has made significant investments, our ability to enforce patents and protect intellectual property rights, the outcome of intellectual property litigation, availability of raw materials, critical manufacturing equipment and qualified employees, trade environment, changes in exchange rates, changes in tax rates, available cash and liquidity, our ability to refinance our indebtedness, distributable reserves for dividend payments and share repurchases, results of the new share repurchase plan and other risks indicated in the risk factors included in ASML's Annual Report on Form 20-F and other filings with the US Securities and Exchange Commission. These forward-looking statements are made only as of the date of this document. We do not undertake to update or revise the forward-looking statements, whether as a result of new information, future events or otherwise.
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Slide 3
Semiconductor Scaling has changed how we…
Tra
nsis
tor
density
Mill
ion
s p
er
mm
2
WORK PLAYLIVE
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Insatiable need to transfer, store and analyse datadrives a continuous and growing demand for semiconductors
Smartphones
Autonomous driving
Factory
Automation
Consumer
Electronics
PC, laptop,
tablets
Slide 4
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Slide 5Moore’s Law is underpinning a business model
IC performance improvement at
similar cost
Improved electronic devices and new
applications
Part of the profits are reinvested in R&D,
equipment
Takeaways
>$250+ billion of annual
operating profit is riding on
the industry’s ability to
keep this cycle going
1
24
>$250+ billion of
operating profit
per year
Consumers and businesses upgrade or adopt new products
3
Scaling/Shrinking Supports Moore’s Law
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Slide 6
Top technology companies in our ecosystem (EBIT CY2016, B$)
Source: Bloomberg (GICS 45 classification)
ASML Applied Materials LAM Research KLA-Tencor TEL
13 12 6 72024
4
2
13 12
2 2
2
1 1
2224 2
2513
1
60
11
2
2
25 6 5 2 3
eB
ay
Co
gn
iza
nt
AD
PN
etE
as
e
Ya
ho
o
Can
on
Mu
rata
TE
Co
nn
ec
t
ASML
Peers
Semi
Non-Semi
/ Alphabet®
2013
~250~280
15 2016
~275 ~290
14
Total EBIT, B$
There remains a lot of
income generated
Baid
uN
VID
IA
8
Semi Equipment
Semi Manufacturing
Semi Design
Hardware
Software & Services
ASML operates in a highly profitable value chain
with strong incentives to compete and drive innovation
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Leading edge Logic and Memory processes drive
growth in semiconductor markets
0
50
100
150
200
250
300
350
400
450
2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021
WW
sem
ico
nd
uct
or R
even
ue [B
$]
Legacy
Logic > 20 nm
Logic ≤20 nm
DRAM2D NAND
3D NAND
Source: ASML analysis, Gartner
Revenue growth is coming from those segments where roadmap
innovation continues: advanced logic, DRAM and NAND (non-
volatile memory)
CAGR14%
CAGR-2%
WW Semiconductor revenue [B$]
Lately we’ve seen the following trends in
semiconductor markets:
• Strong transition to 3D-NAND to
continue enabling large capacities at
lower cost
• Slowing DRAM roadmap leading to
lower bit growth resulting in price
increases, triggering capacity
investments
• Increasing focus on new memory
devices (i.e. x-Point)
• Continuing strong drive for logic
shrink with process improvements
coming on an annual cadence
CAGR5%
Slide 7
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Semiconductors drive 80% of automotive innovationsExpected to represent 50% of the cost of goods in 2030 (per Audi)
Source: Berthold Hellenhtal, Audi, “Cross industry collaboration networks accelerate innovations”, ISS Europe, Munich, March 2017
0
10
20
30
40
50
60
70
80
90
100
1991 2015 2020 2030
Relative Semiconductor
content in automotive [%COG]
Slide 8
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Disruptive trends also drive litho demandGrowth drivers: 2017 to 2020+
IoT devices shipments, B units
Emerging connected devices
market (IoT)
0
+65% p.a.
0.1
2015
0.4
2020
0.3
1918
0.2
17
0.2
16
2010 2020
Sensors & Devices
Text
Enterprise
Images & Media
You
are
here
Data volume
& complexity
Internet of Things will connect a growing number of
devices from 12 billion in 2012 to 50 billion in 2020
Chinese government
supports massive
investment into domestic
semi industry
IoT
Source: John Kelly III, IBM, December 2015
China Greenfield
InvestmentsStorage Class Memory Growth and
transition to 3D NAND
NA
ND
CH
INA
Slide 9
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Slide 10
Scaling will continue towards 1 billion transistors per mm2
We are ready to support the Semi industry’s ambition through the extension
of Moore’s LawT
ransis
tor
density
Mill
ion
s p
er
mm
2
Immersion (+ optical proximity correction)
Multi-patterning(+ source-mask optimization, control loops)
EUV(+ pattern fidelity control)
High-NA
EUV
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• New technology transitions: customer perspective
• EUV progress & plans
• EUV infrastructure
• EUV extendibility
Slide 11EUV – A New Technology in Lithography
~8 m~3 m
~4 m
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What is EUV? A litho technology that delivers 3x -> 5x
Resolution Enhancement
193nm 13.5nm
76nm38nm half pitch
26nm13nm half pitch
NA 1.35
Maximum
NA 0.33
Current
Resolution
Minimum pitch
NA
Numerical Aperture
l Wavelength
k1 difficulty, limit = 0.25
k1 = 0.265
strong OPC mask
k1 = 0.32
OPC mask
NA > 0.5
Future
< 16nm< 8nm half pitch
Slide 12
Resolution = k1 NAx
l ArF immersion EUV
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Dilemmas when adopting a game-changing technologyEarly decision making
It worksIt does not
work
We have it ☺
We do not
have it ??
Slide 13
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How customers approach new technology insertions
• Visionary/champion
• R&D enthusiasm
• First results
• Business manager “Shouldn’t we go for this?”
• Manufacturing push back
• Tough criteria, entrance hurdles
• Dynamics: progress vs. milestones
• Product roadmap timing
• Business decision with up/down ticks
• Different risk appetite per customer and per segment
Slide 14
Done
To be addressed
To be considered
EUV Case
Public
Technology transitions: decisions based on early results“You have to move to where the puck will be, not where it is” (Wayne Gretzky)
Time
Performance
Desired performance
at the time of volume
ramp
Decision point
Increasing complexity
introduces additional
risk - lengthening
leadtimes
Slide 15
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Slide 16
General rule of New Technology adoption
Early adoption is
risky
Late adoption is
expensive
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Jan 2018
Slide 17
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EUV “rewards” at 7nm are clear: simpler process,
shorter cycle time enabling faster yield ramp and time to
market
0 1 2 3 4 5 6 7 8 9 10 11 12 13
-33%
-19%
EUV
High
EUV
Low
ArFi
only
Modelled 7nm Cycle Time, weeks 90
60
75
85
80
70
65
0
-13%
10nm
-21%
7nm14/16nm
Typical # Litho Passes
Dr. Gary Patton, Global Foundries
SEMI ISS 2017
Public
Jan 2018
Slide 18
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EUV introduction delivers compelling benefits in layout
flexibility and process simplification
Esin Terzioglu, Qualcomm, International Symposium on EUV, October, 2014 Jeffrey Shearer et al, IBM, AVS, November 2014
2D EUV patterning
• More layout flexibility for designers
• Simpler process integration for engineers
EUV process simplification
• Superior device performance
• Improved device variability
Resulting in more effective shrink + higher yields
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Slide 19
EUV alternatives are very costly and complex
10
Single
exposure
LE4
34
0
10
20
30
40
50
60
LE3
27
CMP
Dry Etch
Metrology
Track
Deposition
Hard mask
Clean
Lithography
# P
roce
ss s
tep
s fo
r 1
pa
tte
rnin
g s
tep
EUV
60
SAQP
+ 3 cuts
Immersion Multiple Patterning
LE3 = 3x Litho-Etch, “Triple patterning”
LE4 = 4x Litho-Etch, “Quad patterning”
SAQP = Spacer Assisted Quad Patterning
Cut = Separate Litho-Etch step
Process Steps
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0.001
0.01
0.1
1
1984 1987 1990 1993 1996 1999 2002 2005 2008 2011 2014 2017
Slide 20
EUV enables continued Litho cost reduction
TBD
Re
lati
ve
Co
st
pe
r P
ixe
l
XT:1400
Resolution 65nm
300mm 145wph
AT:850
Res. 110nm
300mm 102wph
PAS 5500/60
Res. 450nm
200mm 48wph
PAS 2500/10
Res. 900nm,
150mm 66wph
NXE:3400
Res. 13nm
300mm 125wph NXT:1950i
Res 38nm,
300mm 190wph
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So where are we now?
Slide 21
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Slide 22
EUV industrialisation: from technology demonstration to
HVM System20172006
40 nm
15 nm
0.05 WPH
Resolution :
Overlay :
Throughput :
13 nm
1.5 nm
125 WPH
3x
10x
2,500x
Public
Significant progress in EUV industrialisation
1 Demonstrated on test rig, 2 Demonstrated at ASML or Customer, 3 Enables 145W/Hr on NXE:3400B
EUV Source & ThroughputProven Power1 & Wafers/Hour2
125 W/Hr
2017
250W3
201620152014
Source Power
Throughput, W/Hr ✓
✓
2020Target
2011 2012 2013 2014 2015 2016 2017
>2M
1.1M
0.6M
0.3M
Cumulative EUV wafer exposuresNXE:3xxx, Wafers
300W
155W/Hr
EUV AvailabilityUptime %
2016 2017 2018
0%
100%
Uptime
Planned upgrades
Slide 23
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Evolution of EUV Infrastructure readinessSlide 24
Source: Britt Turkot, Intel, International Workshop on EUV Lithography, California, June 2017.
From 2016 EUVL
Symposium
EUV Infrastructure 11/14 10/15 11/15 10/16 02/17
E-beam mask
inspection
AIMS Mask
Inspection
Actinic Blank
Inspection
EUV
Pellicle
EUV Blank
Quality
Blank multi-layer
deposition tool
EUV Resist QC
Actinic Patterned
Mask Inspection
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EUV in Production
2014 2015 2016 2017 2018 2019 2020 2021 2022
>x200>x192>x128
Planar Floating Gate NAND
>x96
Sto
rag
e
Me
mo
ry 14-15
3D NAND
x64
17-1822
x48x32x24
Industry shrink roadmap and EUV insertion plans
HVM
Production1
Research1
Development1
Roadmap2
Today’s status
x number of layers
3 nm5 nm7 nm10 nm16-14 nm20 nmLo
gic
Pe
rfo
rma
nce
Me
mo
ry
Source: 1) Customers - public statements,, IC Knowledge LLC; 2) ASML extrapolations
Sto
rag
e
Cla
ss
Me
mo
ry
next1Z 1Y 1X 20-2228-30
DRAM
1Z”/x81Y”/x8
PC-RAM, ReRAM etc.
1X”/x42X’/x2
Node name
Minimum half pitch
Minimum half pitch
/x number of layers
Slide 25
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NXE:33x0 and NXE:3400
Shipments and Installed Base
42 3
10
3
79
12
30+
’13 ’15’14 ’16 ’20’19’18
22
’17
22
Planned
Shipments
Installed Base
...which is supported by Customer shipments and ordersInstalled Base of EUV systems expected to double in 2018
HVM rampR&D
End Q4 ‘17 order backlog: 28
systems from 6 Customers
Slide 26
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Slide 27
And by recent customer statements on EUV insertion
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What’s next?
Slide 28
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Slide 29
Customer roadmaps extend 10 years
7 nm
5 nm
3 nm
2 nm
1 nm
2007
Tra
nsit
or
De
ns
ity
MT
r/ m
m2
2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 1
10
100
45/40 nm
28/32 nm
28 nm
20 nm14/16 nm
10 nm
HVM Wafer Start Date
1000
2021 2022 2023 2024 2025 2026 2027
Density extrapolated,
timing based on customer
reviews 2017
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1
10
100
1,000
1985 1990 1995 2000 2005 2010 2015 2020 2025
13.5, EUV
193, ArF
248, KrF
365, i-line
436, g-line
>10x
45%
67%
High NA extends EUV with a larger resolution step than
immersion did for ArF
EUV
g-line ArF
i-line
KrF
Immersion
Re
so
luti
on
, n
m
= k
1x W
avele
ng
th / N
A
Wavelength, nm
xx% Increase in NA
Development systems
Timing TBD
NXE:3400
EUV 13.5 nm
13nm, 0.33 NA
NXT:1950i
ArFi 193nm
38nm, 1.35 NA
XT:1400
ArF 193nm
65nm, 0.93 NA
High NA EUV
EUV, 13.5nm
<8nm, >0.5 NA
Slide 31
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Slide 31
High NA EUV extends cost per pixel reduction
0.000
0.001
0.010
0.100
1.000
1984 1987 1990 1993 1996 1999 2002 2005 2008 2011 2014 2017 2020 2023TBD
Re
lati
ve
Co
st
pe
r P
ixe
l
NXE:3400
Res. 13nm
300mm 125wph NXT:1950i
Res 38nm,
300mm 190wph
XT:1400
Resolution 65nm
300mm 145wph
High NA EUV
Res. <8nm
300mm 185wph
AT:850
Res. 110nm
300mm 102wph
PAS 5500/60
Res. 450nm
200mm 48wph
PAS 2500/10
Res. 900nm,
150mm 66wph
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Slide 32
EUV shrink + Holistic Litho (addressing k1) keeps Moore’s
Law affordable
Ensure measurement captures a
maximum of relevant information
Exposure with high order
optimisation
Optical & e-beam Metrology
Computational Lithography
Our innovation pipeline will enable advanced imaging
and imaging process control the next 10 years and
beyond
Slide 33
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Slide 34
EUV Summary
Customers are targeting EUV introduction at 7nm to take advantage
of process complexity, cycle time, IC shrink, yield, & performance
benefits
Key EUV industrialisation & performance milestones have been
achieved in 2017, together with solid progress in EUV mask and
resist infrastructure
EUV introduction enables a return to Litho enabled cost reduction
with the opportunity to extend multiple generations
ASML is investing in a roadmap to enable continued Holistic
Lithography scaling for the coming decade
7nm
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Slide 35
What this means for ASML – As IC units grow and Litho
Intensity grows…….. ASML grows!
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Summary - Our customers and their environment
• Strong incentives for the entire industry to continue IC
performance and cost improvements, now also driving system
innovations
• Our logic customers have roadmaps that extend to 2027 and
are not planning to slow down scaling
• Memory market is growing and performance improvements
continue, enabled by 3D stacking and new scalable memory
types. The latter will have an increasing impact the coming 10
years and continue to drive lithography
Slide 36
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