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Basic Memory Management
Chapter 3C6000 Integration Workshop
Copyright © 2005 Texas Instruments. All rights reserved. Technical Training
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Outline C6416 Memory Architecture C6713 Memory Architecture Section Memory Placement
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'C6416 Internal Memory0000_0000 Level 2
Internal Memory Level 1 Memory
Always cache (not in map) L1P (prog), L1D (data)
Level 2 Memory (L2) RAM (prog or data) Up to 256 KB can be cache C6416
L1P = 16 KBL1D = 16 KBL2 = 1 MB
FFFF_FFFF
L2 RAMProg/DataCPU
EMIFA
EMIFB
ProgramCache
DataCache
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C64x External Memory0000_0000 Level 2
Internal Memory
External (A2)
External (A3)
A000_0000
B000_0000
FFFF_FFFF
External (A0)
External (A1)
8000_0000
9000_0000
External (B2)External (B3)
6800_00006C00_0000
External (B0)External (B1)
6000_00006400_0000
L2 RAMProg/DataCPU
EMIFA
EMIFB
C64x memory details ...
ProgramCache
DataCache
Each EMIF has four ranges Program or Data Named: CE0, CE1, CE2, CE3
Remaining memory is unused
C64x Memory Details0000_0000 Level 2
Internal Memory
External (A2)
External (A3)
A000_0000
B000_0000
FFFF_FFFF
External (A0)
External (A1)
8000_0000
9000_0000
External (B2)External (B3)
6800_00006C00_0000
External (B0)External (B1)
6000_00006400_0000
Devices Internal(L2)
External
C6414C6415C6416
1MB
A: 1GB (64-bit)B: 256MB(16-bit)
DM642 256KB 1GB (64-bit)
C6411 256KB 256MB (32-bit)
Each device is different Some have two EMIF's
EMIFA is 64-bits wide EMIFB is 16-bits wide
'C6416 DSK Block DiagramDaughter-Card
Roomfor
Expansion
SDRAM(16MB)
CE2
CE3
Flash ROM(512KB)
CPLDCE1
CE0
DSK uses both EMIFs (A and B) EMIFA
CE0 for SDRAM CE2 and CE3 pinned-out to daughter card connector
EMIFB CE1 for Flash Memory and CPLD (switches, LED’s, etc.)
L2 RAMProg/Data
(1MB)CPU
EMIFA
EMIFB
ProgramCache
DataCache
CE0
Outline C6416 Memory Architecture C6713 Memory Architecture Section Memory Placement
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'C6713 Internal Memory0000_0000 Level 2
Internal Memory Level 1 Memory
Always cache (not in map) L1P (prog), L1D (data)
Level 2 Memory (L2) 192KB RAM (prog or data) Up to 64KB cache
L2SRAM
prog/dataCPU
ProgramCache
DataCache
C6713L1P = 4 KBL1D = 4 KBL2 =256 KB
FFFF_FFFF
EMIF
What about the External Memory?Technical Training
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'C6713 External Memory0000_0000 Level 2
Internal Memory
FFFF_FFFF
Level 2Prog/DataCPU
ProgramCache
DataCache
External (CE2)
External (CE3)
A000_0000
B000_0000
External (CE0)
External (CE1)
8000_0000
9000_0000
EMIF
Four External ranges Program or Data 128 Mbytes each Named: CE0, CE1, CE2, CE3
Remaining memory is unused
How does this apply to the DSK?Technical Training
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'C6713 DSK Block DiagramDaughter-Card
Roomfor
Expansion
InternalMemoryCPU
ProgramCache
DataCache
EMIF
SDRAM(16MB)
CE2
CE3Flash ROM
(256KB)I/O Port
CE1
CE0
DSK uses all four External Memory regions CE0 for SDRAM CE1 for Flash Memory and I/O Port (switches, LED’s, etc.) CE2 and CE3 pinned-out to daugher card connector
So what does the Memory Map look like?
Outline C6416 Memory Architecture C6713 Memory Architecture Section Memory Placement
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Sections
short m = 10;short x = 2;short b = 5;
main(){ short y = 0;
y = m * x; y = y + b;
printf("y=%d",y);}
Every C program consists of different parts called Sections
All default section names begin with "."
Let’s review thelist of compiler
sections…
Global Vars (.bss) Init Vals (.cinit)
Local Vars(.stack)
Code(.text)
Std C I/O(.cio)
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Compiler's Section NamesSection Name Description Memory
Type.text Code initialized
.switch Tables for switch instructions initialized
.const Global and static string literals initialized
.cinit Initial values for global/static vars initialized
.pinit Initial values for C++ constructors initialized
.bss Global and static variables uninitialized
.far Global and static variables uninitialized
.stack Stack (local variables) uninitialized
.sysmem Memory for malloc fcns (heap) uninitialized
.cio Buffers for stdio functions uninitialized
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Exercise
16MBSDRAM
8000_0000CE0
4MBFLASH
9000_0000CE1
C6000CPU
InternalMemory
Where would you place each
of these sections?
Section Location Why.text.cinit .bss .stack.cio
16MBSDRAM
8000_0000CE0
4MBFLASH
9000_0000CE1
C6000CPU
InternalMemory
Solution
Where would you place each
of these sections?
Section Location Why.text FLASH Must exist after reset.cinit.bss.stack.cio
Initialized Memory
16MBSDRAM
8000_0000CE0
4MBFLASH
9000_0000CE1
C6000CPU
InternalMemory
Solution
Where would you place each
of these sections?
Section Location Why.text FLASH Must exist after reset.cinit FLASH Must exist after reset.bss.stack.cio
Initialized Memory
16MBSDRAM
8000_0000CE0
4MBFLASH
9000_0000CE1
C6000CPU
InternalMemory
Solution
Where would you place each
of these sections?
Section Location Why.text FLASH Must exist after reset.cinit FLASH Must exist after reset.bss Internal Must be in RAM memory.stack.cio
Initialized Memory
16MBSDRAM
8000_0000CE0
4MBFLASH
9000_0000CE1
C6000CPU
InternalMemory
Solution
Where would you place each
of these sections?
Section Location Why.text FLASH Must exist after reset.cinit FLASH Must exist after reset.bss Internal Must be in RAM memory.stack Internal Must be in RAM memory.cio
Initialized Memory
16MBSDRAM
8000_0000CE0
4MBFLASH
9000_0000CE1
C6000CPU
InternalMemory
Solution
Where would you place each
of these sections?
Section Location Why.text FLASH Must exist after reset.cinit FLASH Must exist after reset.bss Internal Must be in RAM memory.stack Internal Must be in RAM memory.cio SDRAM Needs RAM, speed not critical
Initialized Memory
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Placing Sections In Memory
.text
.bss
.cinit
.cio
.stack
How do you define the memory areas(e.g. FLASH, SDRAM) ?
How do you place the sections intothese memory areas ?
8000_0000
9000_0000 4MB FLASH
16MB SDRAM
1MB Internal0000_0000
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Using the Memory Section Manager
MEM Manager allowsyou to create memoryareas & place sections
To Create a NewMemory Area: Right-click on MEM
and select Insert Mem Fill in base/len, etc.
How do you placesections into these
memory areas?
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MEM Manager Properties To Place a Section Into a Memory Area…
1. Right-click on MEM Section Manager
and select Properties2. Select the appropriate
tab (e.g. Compiler)3. Select the memory area
for each section
What about the BIOS Sections?Technical TrainingOrganization
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Placing BIOS Sections
BIOS creates both Data andCode sections
User needs to place these into appropriate memory region
What gets created afteryou make these selections?
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Config Tool Creates CDB File
*cfg_c.c*cfg.s62*cfg.cmd
*cfg.h
*cfg.h62
Config tool generates five different files
Notice, one of them is the linker command file
CMD file is generated from your MEM settings
MEMORY{ EPROM: origin=0, length = 0x20000… }
SECTIONS { .text: > EPROM .cinit:> EPROM .bss: > IDRAM … }
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GUI’s Linker Command File
app.cdb
Linkerappcfg.cmd
myApp.out
Do not modify appcfg.cmd – your changes will beoverwritten during “Build” (or “Rebuild”)
“Build”
.obj fileslibraries
(.lib).map
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Outline C6416 Memory Architecture C6713 Memory Architecture Section Memory Placement
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Go directly to Chapter 4
Optional Topics ’0x Memory Scheme
C6201, C6202, C6203, C6204, C6205 C6701
‘1x Memory Scheme C6211 C6711, C6712, (C6713) (C6411), C6414, C6415, C6416
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ti
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