FCAL collaboration meeting, May 6-7, 2008, Krakow, Poland
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BeamCal Front-End Design:Challenges, solutions
and techniques
Angel Abusleme, Angelo Dragone and Gunther Haller
Stanford Linear Accelerator Center
FCAL collaboration meeting, May 6-7, 2008, Krakow, Poland
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Presentation Outline
BeamCal FE design challenges Solutions Techniques
Stanford Linear Accelerator Center
FCAL collaboration meeting, May 6-7, 2008, Krakow, Poland
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BeamCal FE Design Challenges
Stanford Linear Accelerator Center
FCAL collaboration meeting, May 6-7, 2008, Krakow, Poland
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High occupancy High rate (3.25 MHz) Peaking time limited to time between pulses
(308ns) Large
memoryrequired
Stanford Linear Accelerator Center
FCAL collaboration meeting, May 6-7, 2008, Krakow, Poland
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Large input capacitance
Detector+wiring (CD): ~40pF Implies increased voltage noise component
Stanford Linear Accelerator Center
FCAL collaboration meeting, May 6-7, 2008, Krakow, Poland
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Large input signals Large feedback
capacitance (40pF)
Large charge amplifier output current to provide sufficient slew rate
Ballistic Deficit Nonlinearity
Stanford Linear Accelerator Center
FCAL collaboration meeting, May 6-7, 2008, Krakow, Poland
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Wide range of operation
50x gain between science and calibration Single circuit must cope with two different
sets of specs Challenges in calibration mode
Noise (still 40pF input capacitance) Amplifier linearity is an issue
DOLF
inOLO CAC
QAV
1
Stanford Linear Accelerator Center
FCAL collaboration meeting, May 6-7, 2008, Krakow, Poland
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More BeamCal FE Challenges
Fast feedback requirement Additional output Low latency ADC
Radiation tolerance Using non-standard transistor geometries
No models readily available
Low power dissipation About 2mW per channel
Stanford Linear Accelerator Center
FCAL collaboration meeting, May 6-7, 2008, Krakow, Poland
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Solutions
Stanford Linear Accelerator Center
FCAL collaboration meeting, May 6-7, 2008, Krakow, Poland
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Gated front-end
This addresses high occupancy and limited peaking time Charge amplifier and filter have periodic reset This allows longer integration time, no tail Time-domain noise analysis is required
Stanford Linear Accelerator Center
FCAL collaboration meeting, May 6-7, 2008, Krakow, Poland
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Amplifier topology This addresses slew
rate problem Load branch borrows
current from input device during settling
Still nonlinearity and ballistic deficit are important issues
Both are a consequence of pulse shaping
Stanford Linear Accelerator Center
FCAL collaboration meeting, May 6-7, 2008, Krakow, Poland
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Reconfigurable architecture
But “no shaper” implies “no problem”
Shaper will only be used in calibration
Stanford Linear Accelerator Center
FCAL collaboration meeting, May 6-7, 2008, Krakow, Poland
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Digital memory
This addresses large storage requirement Advantages of digital memory in 0.18um
More versatile solutions against SEE (e.g., parity)
No leakage High density in 0.18-um technology
Stanford Linear Accelerator Center
FCAL collaboration meeting, May 6-7, 2008, Krakow, Poland
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Dual feedback capacitance
This addresses dual range problem New issues: additional noise and amplifier
open-loop gain requirement
Gain and noise problems are mitigated by amplifier precharge…
DOLF
inOLO CAC
QAV
1
Stanford Linear Accelerator Center
FCAL collaboration meeting, May 6-7, 2008, Krakow, Poland
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Amplifier precharge idea Improves linearity and SNR
h
Stanford Linear Accelerator Center
FCAL collaboration meeting, May 6-7, 2008, Krakow, Poland
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Amplifier precharge implementation
Stanford Linear Accelerator Center
FCAL collaboration meeting, May 6-7, 2008, Krakow, Poland
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More solutions Analog fast feedback
Still a low latency ADC is required Radiation tolerance
TSMC 0.18 is inherently tolerant Prototype with standard transistors will help to assess
tolerance Power dissipation
Analog front-end turned off between pulse trains PSRR could become an issue… More on this in next part
Stanford Linear Accelerator Center
FCAL collaboration meeting, May 6-7, 2008, Krakow, Poland
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Techniques
Stanford Linear Accelerator Center
FCAL collaboration meeting, May 6-7, 2008, Krakow, Poland
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Differential circuits
Commonly used in precision, low voltage integrated circuits
Improved output swing, SNR and PSRR, reduced parasitics effects, but requires more power
This technique can help significantly to reduce the transient effects of switching the front-end power supply
Stanford Linear Accelerator Center
FCAL collaboration meeting, May 6-7, 2008, Krakow, Poland
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Differential circuit implementation
Signal is pseudo differential at the charge amplifier, and fully differential at the filter
Stanford Linear Accelerator Center
FCAL collaboration meeting, May 6-7, 2008, Krakow, Poland
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Switched-Capacitor filter A SC filter is a sampled-
data, analog filter Widely used technique for
IC filters since the 80’s Resistors are simulated
using capacitors and switches
Filter time constants are accurately set by capacitor ratios and external clock R
Seq C
TR
Stanford Linear Accelerator Center
FCAL collaboration meeting, May 6-7, 2008, Krakow, Poland
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More on SC filters
Operational transconductance amplifiers (OTA) are used instead of operational amplifiers Ideally a voltage-controlled current source No need for an output buffer, load is a
capacitor Settling time matters; settling transient
doesn’t
Stanford Linear Accelerator Center
FCAL collaboration meeting, May 6-7, 2008, Krakow, Poland
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Noise analysis based on gm/ID MOSFET long channel models are not accurate for current
technologies Higher electric field Moderate and weak inversion operation
SPICE models have hundreds of parameters Great for simulation, bad for design purposes
gm/ID methodology overcomes this limitation SPICE computes curves adequate for design
Stanford Linear Accelerator Center
FCAL collaboration meeting, May 6-7, 2008, Krakow, Poland
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Example of gm/ID curves
Stanford Linear Accelerator Center
FCAL collaboration meeting, May 6-7, 2008, Krakow, Poland
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gm/ID and noise analysis
Noise equations are not functions of gm/ID or any corresponding ratio…
But a simple normalization allows to have transistor noise equations as functions of gm/ID or corresponding ratios
SPICE computes noise curves, which are then available for precise noise calculations
Results are valid for any region of operation Details to be shown in a future publication
Stanford Linear Accelerator Center
FCAL collaboration meeting, May 6-7, 2008, Krakow, Poland
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Example of normalized noise curves
Stanford Linear Accelerator Center
FCAL collaboration meeting, May 6-7, 2008, Krakow, Poland
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Tentative design schedule April 2007: High level design complete July 2007: Charge amplifier designed May 2008: Filter designed August 2008: ADC designed September 2008: Memory designed October 2008: Fast feedback designed November 2008: Bias and supporting circuits January 2009: Circuit layout complete February 2009: Verification complete April 2009: Prototype ready June 2009: Prototype tests complete
Stanford Linear Accelerator Center
FCAL collaboration meeting, May 6-7, 2008, Krakow, Poland
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People Angel Abusleme (PhD student)2
Professor Martin Breidenbach1
Angelo Dragone1
Dietrich Freytag1 Gunther Haller1
Professor Bruce Wooley2
Affiliations1. SLAC2. Department of Electrical Engineering, Stanford University