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BiasingBiasing: Application of dc voltages to establish a fixed level
of current and voltage.
BJT Biasing Circuits:• Fixed Bias Circuit
• Fixed Bias with Emitter Resistor Circuit
• Voltage-Divider Bias Circuit
• Feedback Bias Circuit
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Fixed Bias Circuit
• This is a Common Emitter (CE) configuration.
• Solve the circuit using KVL.• 1st step: Locate capacitors and replace them with an
open circuit• 2nd step: Locate 2 main loops
which areBE loopCE loop
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Fixed Biased Circuit• 1st step: Locate capacitors and replace them with an
open circuit
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Fixed Biased Circuit
• 2nd step: Locate 2 main loops.
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1
2
BE Loop CE Loop
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Fixed Biased Circuit• BE Loop Analysis:
1 From KVL:
IB
0VRIV BEBBCC
B
BECCB R
VVI
Solving for IB
(1)
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Fixed Biased Circuit• CE Loop Analysis: From KVL:
0VRIV CECCCC
B
BECCdcC R
VVI
As we know IC = dcIB2
IC
CECCCC VRIV
Substituting IB from equation (1)
Also note thatVCE = VC - VE
But VE = 0
VCE = VC In addition, since
VBE = VB - VE
Since VE = 0
VBE = VB
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Fixed Biased Circuit
• DISADVANTAGE Unstable – because it is too dependent on β and
produce width change of Q-pointFor improved bias stability , add emitter resistor to
dc bias.
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Example 1: Determine the Followingfor the given Fixed Biased Circuit.(a) IBQ and ICQ (b) VCEQ (c) VBC
Solution:
A08.4710002407.012
RVVIB
BECCBQ
mAII BQdcCQ 35.21008.4750 6
V83.6)k240)(mA35.2(12RIVV CCCCCEQ
V83.6VVV7.0VV
CEC
BEB
V13.683.67.0VVV CBBC
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Example 2: For the given fixed bias circuit, determine IBQ, ICQ, VCEQ, VC, VB and VE.
Solution:
A55.3210002707.016
RVVIB
BECCBQ
mA93.21055.3290II 6BQdcCQ
V09.8)k7.2)(mA93.2(16RIVV CCCCCEQ
V09.8VVV7.0VV
CEC
BEB
0VE
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Example 3: Given the information appearing in the Fig. (a) , determine IC, RC, RB, and VCE.
Solution: IC = 3.2 mA, RC = 1.875k,RB = 282.5 k, VCE = 6 V.Example 4: Given the information appearing in Fig. (b), determine IC, VCC, and RB.Solution:IC = 3.98 mA, VCC = 15.96 V, = 199, RB = 763 k.
Fig. (a)
Fig. (b)
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Load line Analysis with Fixed Bias CircuitDC load line is drawn by using the following equations: VCE = VCC
C
CCC R
VI
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Load line Analysis with Fixed Bias Circuit
Effect of Varying IB on the Q-Point:
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Load line Analysis with Fixed Bias Circuit
Effect of varying VCC on the Q-Point:
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Load line Analysis with Fixed Bias Circuit
Effect of varying RC on the Q-Point:
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Example: Given the load line and the defined Q-point , determine the required values of VCC, RC, and RB for a fixed bias configuration.
Solution:VCE = VCC = 20 V
k2mA1020
IVR
RVI
C
CCC
C
CCC
B
BECCB R
VVI
k772A257.020
IVVR
B
BECCB
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Emitter-Stabilized Bias Circuit
Resistor RE added
• An emitter resistor, RE is added to improve stability
• Solve the circuit using KVL.• 1st step: Locate capacitors
and replace them with an open circuit
• 2nd step: Locate 2 main loops which; BE loop CE loop
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Emitter-Stabilized Bias Circuit
• 1st Step: Locate capacitors and replace them with an open circuit.
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Emitter-Stabilized Bias Circuit
• 2nd Step: Locate two main loops
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1
2
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Emitter-Stabilized Bias Circuit
BE Loop Analysis:
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Using KVL:
EEBEBBCC RIVRIV
Recall that IE = ( + 1)IB
EBBEBBCC RI)1(VRIV EBBBECC R)1(RIVV
EB
BECCB R1R
VVI
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Emitter-Stabilized Bias Circuit CE Loop Analysis:
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From KVL:EECECCCC RIVRIV
Substituting IE IC we get
ECCECCCC RIVRIV
CEECCCC VRRIV
EC
CECCC RR
VVI
ECCE VVV
ECEC VVV
CCCCB RIVV
EBEB VVV
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Example: For the given emitter bias network, determine IB, IC, VCE, VC, VE, VB and VBC.
Solution:
A1.41)k1)(150(k430
7.020R)1(R
VVIEB
BECCB
mA01.2101.4050II 6BC
V97.13)k1k2)(mA01.2(20
RRIVV ECCCCCE
V98.1502.420)k2)(mA01.2(20RIVV CCCCC
V01.297.1398.15VVV CECE V71.201.27.0VVV EBEB
V27.1398.1571.2VVV CBBC
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Load line Analysis for Emitter Stabilized Bias Circuit
The collector-emitter loop equation that defines the load line is:
ECCCCCE RRIVV
Choosing IC = 0 gives
CCCE VV
And choosing VCE = 0 gives
EC
CCC RR
VI
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Example: For the given emitter stabilized bias circuit, determine IBQ, ICQ, VCEQ, VC, VB, VE.
Solution:
A18.29)k5.1)(1100(k510
7.020R1R
VVIEB
BECCBQ
mA92.2A18.29100II BQCQ
V61.8RRIVV ECCCCCEQ
V13RIVV CCCCC
V12.5RIVV BBCCB
V39.461.813VVV CECE
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Voltage Divider Bias• Provides good Q-point stability
with a single polarity supply voltage• Solve the circuit using KVL• 1st step: Locate capacitors and
replace them with an open circuit
• 2nd step: Simplify circuit using Thevenin Theorem
• 3rd step: Locate 2 main loops which; BE loop CE loop
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Voltage Divider Bias
• 1st step: Locate capacitors and replace them with an open circuit
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Voltage Divider Rule
2nd step: Simplify the circuit using Thevenin Theorem
From Thevenin’s Theorem
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2121TH RR
RRR//RR
CC21
2TH V
RRRV
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Voltage Divider Bias
3rd step: Locate 2 main loops.
1
2
BE Loop
1
CE Loop
2
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Voltage Divider BiasBE Loop Analysis:
1
0RIVRIV EEBETHBTH
ERTH
BETHB
EBBETHBTH
R)1(RVVI
0RI)1(VRIV
BE I)1(I
From KVL:
But
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Voltage Divider BiasCE Loop Analysis:
2
From KVL:0RIVRIV EECECCCC
AssumeIC IE
0RIVRIV ECCECCCC
)RR(IVV ECCCCCE
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IC
DC load line with Voltage Divider BiasThe dc load line can be drawn from the following
equation:)RR(IVV ECCCCCE
VCC
EC
CCC RR
VI
VCE
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Example: Determine the dc bias voltage VCE and the current IC for the given voltage divider configuration.
Solution:
K55.3K9.3k39k9.3k39
RRRRR
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21TH
V2k9.3k3922k9.3
RRVRV
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CC2TH
A05.6R1R
VVIETH
BETHB
mA85.0A05.6140II BdcC
V22.12RRIVV ECCCCCE
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DC Bias with Voltage Feedback
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DC Bias with Voltage FeedbackUsing KVL:
BE Loop
EEBEBBCCCC IRVRI'IRV In this circuit, IB is assumedto be very small andI’C IC = IC. The above Equation may therefore beRe-written as
CEBEBBCCCC IRVRIIRV
BEBEBBBCCC IRVRIIRV
BECBBECC RRRIVV
ECB
BECCB RRR
VVI
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DC Bias with Voltage Feedback
CE Loop
EECECCCC RIVR'IV Since I’C IC and IC IE, we have
ECCECCCC RIVRIV
ECCCCCE RRIVV
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Example: Determine the quiescent level of ICQ and VCEQ for the given network.
Solution:
ECB
BECCB RRR
VVI
A91.11k2.1k7.4)90(k250
7.010
mA07.11091.1190II 6BCQ
V69.3)k2.1k7.4)(mA07.1(10RRIVV ECCCCCEQ