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ANALOG BiCMOS

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Introduction

What is BiCMOS?

BiCMOS technologycombines

Bipolarand CMOS transistors ontoa

single integratedcircuit wheretheadvantages ofbothcanbeutilized.

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Advantages ofCMOS overBipolar

Powerdissipation

N

ois

emarg

in

Packingdensity

Theabilityto integratelargecomples

functions withhighyields

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Advantages ofBipolaroverCMOS

Switching speed

Currents drive perunitarea

Noise perfomance

Analogcapability

Input/output speed

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Advantages ofBiCMOS Technology

Improved speedoverCMOS

Lowerpowerdissipationthan Bipolar

Flexible input/outputs

High performanceanalog

Latchup immunity

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Analog BiCMOS Complexity

Higherperformance

analogcircuits Reduceddesignefforts

Fasterdesigncycles

Higherwafercost

Longermanufacturingtime

Lowerprocess yields

Analog BiCMOS processes arecharacterizedbytheir

complexity,mostneeding15masks. Someup to 30 masks.

Advantages of complexity Disadvantages of complexity

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EvolutionofBiCMOS from CMOS

BiCMOS technologies havetendedtoevolvefrom CMOS

processes inordertoobtainthehighest CMOSperformance possible.

Thebipolarprocessing steps havebeenaddedtothecore

CMOS flow torealizethedesireddevicecharacteristics.

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FabricationEquipmentMolecularBeamEpitaxy

(MBE)

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FabricationEquipmentPhotoresist Spinner Bake-out Ovens

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FabricationEquipmentMaskAligner ReactiveIonEtching (RIE)

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FabricationEquipmentChemical VaporDeposition

(CVD)

Plasma Quest Sputter

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FabricationEquipmentPlasma Sputter Perk in-ElmerMBE

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FabricationEquipmentProbe Station ScanningElectron

Microscope (SEM)

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N-well CMOS StructureNMOS device,built ina15umthickP-epitaxiallayerontop ofP+substrate

PMOS transistor,built inan implanted N-wellapproximately5umdeep

P+ substrate is usedtoreducelatchup susceptibilityby providingalowimpedance patchthroughaverticalPNPdevice

Polysilicongates areusedforboththePMOS and NMOS transistors

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Adding NPN BipolarTransistorThe simplest waytoaddan NPNbipolartransistortothe previous CMOSstructure is byusingPMOS N-wellas thecollectorofthe Bipolardevice

and introducinganadditionalmasklevelfortheP-baseregion.

theP-base is approx1umdeep withadopinglevelofabout1e17atoms/cm^3

the N+ source/drain ion implantation step is usedfortheemitterand

collectorcontactofthebipolarstructure

theP+ source/drain ion implantation step is usedtocreateaP+base

contacttominimizethebase series resistance

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Contacts

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Contacts

EFnEc

Ev

EFi

qJs,n

qGs

n-type s/c

qJm

EFm

metal

qJBnqVbi

qJnDepl reg

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Pattern Shift NBL Shadow (1/2)

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Pattern Shift NBL Shadow (2/2)

Stacking faults

Anextra planeofatoms

Thelackofa planeofatoms

Other Causes

Temprature

Pressure

Waferpre-leaning

Growth precursor

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PIsolationvs. CDI

CollectorDiffusedIsolationPIsolation

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Keyfactorindeterminingoverallcircuit performanceand

density

CollectorDiffusedIsolation (CDI) N-wellusedtoformcollectorofNPN transistor

Baseandemitterconsistofsuccessivecounterdopingof

the well.

CDItransistors Saturate prematurely

Limits low-voltageoperation

Complicates devicemodeling

Causes undesired substrate injection

BiCMOS Isolation Consideration

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System-on-a-Chip Technology

personalInternetaccess devices

set-topboxes

thinclients

Applicationsof

BiCMOS Technology