BiCMOS Technology.ppt

8/9/2019 BiCMOS Technology.ppt

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BiCMOS Technology

12-1

BiCMOS Technology


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BiCMOS Technology

12-2

BiCMOS Technology

Combines Bipolar and CMOS transistors in a single integrated circuit

By retaining benefits of bipolar and CMOS, BiCMOS is able to achieve !S" circuits #ith

speed-po#er-density performance previously unattainable #ith either technology individually$


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BiCMOS Technology

12-%

Characteristics of CMOS Technology

!o#er static po#er dissipation&igher noise margins

&igher pac'ing density ( lo#er manufacturing cost per device

&igh yield #ith large integrated comple) functions

&igh input impedance *lo# drive current+

Scaleable threshold voltage

&igh delay sensitivity to load *fan-out limitations+

!o# output drive current *issue #hen driving large capacitive loads+

!o# transconductance, #here transconductance, gmα

in

Bi-directional capability *drain source are interchangeable+

near ideal s#itching device

Advantages of CMOS

over bipolar

Other CMOS Advantages


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BiCMOS Technology

12-

Combine advantages in BiCMOS Technology

3 "t follo#s that BiCMOS technology goes some #ay to#ards combining the virtues

of both CMOS and Bipolar technologies

3 4esign uses CMOS gates along #ith bipolar totem-pole stage #here driving of high

capacitance loads is re0uired

3 5esulting benefits of BiCMOS technology over solely CMOS or solely bipolar 6

3 "mproved speed over purely-CMOS technology3 !o#er po#er dissipation than purely-bipolar technology *simplifying

pac'aging and board re0uirements+3 7le)ible "Os *i$e$, TT!, CMOS or 8C!+ (

BiCMOS technology is #ell suited for "O intensive applications$

8C!, TT! and CMOS input and output levels can easily be generated #ith no

speed or trac'ing conse0uences3 high performance analogue


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BiCMOS Technology

12-9The simplified BiCMOS "nverter

Two bipolar transistors (T3 and T4), one nMOS and one pMOS transistor (both enhancement-

type devices, OFF at in!")

The MOS switches perform the lo#ic f$nction % bipolar transistors drive o$tp$t loads

out

dd

in

T2

T.

T1

T%

C!

Vin = 0 :

T1 is off$ Therefore T% is non-conducting

T2 O: - supplies current to base of T.T. base voltage set to

dd$

T. conducts acts as current source to charge load C! to#ards

dd$

out rises to dd - be *of T.+ :ote 6

be *of T.+ is base-emitter voltage of T.$

*pullup bipolar transistor turns off as the output approaches -

be *of T.++

Vin = Vdd

:

T2 is off$ Therefore T. is non-conducting$

T1 is on and supplies current to the base of T%T% conducts acts as a current sin' to discharge load C

! to#ards ;

out

falls to ;< C8sat *of T%+

:ote 6 C8sat *of T%+ is saturation from T% collector to emitter


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12-=The simplified BiCMOS "nverter

3 T% T. present lo# impedances #hen turned on into saturation load C! #ill be

charged or discharged rapidly

3 Output logic levels #ill be good #ill be close to rail voltages since C8sat is 0uite

small B8 ≈ ;$=$ Therefore, inverter has high noise margins

3 "nverter has high input impedance, i$e$, MOS gate input3 "nverter has lo# output impedance3 "nverter has high drive capability but occupies a relatively small area3 &o#ever, this is not a good arrangement to implement since no discharge path

e)ists for current from the base of either bipolar transistor #hen it is being turned

off, i$e$,

3 #hen in>dd, T2 is off and no

conducting path to the base of T. e)ists

3 #hen in>;, T1 is off and

no conducting path to the base of T% e)ists$

This #ill slo# do#n the action of the circuit out

dd

in

T2

T.

T1

T%

C!


8/17BiCMOS Technology

12-?The conventional BiCMOS "nverter

Two additional enhancement-type nMOS devices have been added (T& and T')

These transistors provide dischar#e paths for transistor base c$rrents d$rin# t$rn-off

itho$t T&, the o$tp$t low volta#e cannot fall below the base to emitter volta#e *+

of T3

out

dd

in

T2

T.

T1

T%

C!

Vin = 0 :

T1 is off$ Therefore T% is non-conducting

T2 O: - supplies current to base of T.T. base voltage set to

dd$

T is turned on clamps base of T% to /:4$ T% is turned off$T. conducts acts as current source to charge load C

!

to#ards dd

$

out

rises to dd

- be *of T.+

· Vin = Vdd

:

T2 is off

T1 is on and supplies current to the base of T%

T9 is turned on and clamps the base of T. to /:4$ T. is turned off$T% conducts acts as a current sin' to discharge load C

! to#ards ;

out

falls to ;< C8sat *of T%+

T9

T



12-@The conventional BiCMOS "nverter

gain, this BiCMOS gate does not s#ing rail to rail$ &ence some finite po#er is dissipated

#hen driving another CMOS or BiCMOS gate$ The lea'age component of po#er dissipation

can be reduced by varying the BiCMOS device parameters

out

dd

in

T2

T.

T1

T%

C!

T9

T



12-1;More advanced BiCMOS structures

arious types of BiCMOS gates have been devised to overcome the shortcomings of the

conventional BiCMOS gate

BiCMOS devices are available #hich provide the full dd -A /:4 voltage s#ing

There is a common theme underlying all BiCMOS gates 6

all have a common basic structure of a MOS78T *p or n+ driving a bipolar

transistor *npn or pnp+ #hich drives the output

BiCMOS can provide applications #ith CMOS po#er densities at speeds #hich #ere

previously the e)clusive domain of bipolar$ This has been demonstrated in applications ranging

from static 5Ms to gate arrays to u-processors$

BiCMOS fills the mar'et niche bet#een3 very high speed, but po#er hungry bipolar 8C! *8mitter Coupled !ogic+

and3 very high density, medium speed CMOS



12-11More advanced BiCMOS structures

hen the po#er budget is unconstrained, a bipolar technology optimised for speed #ill almost

al#ays be faster than BiCMOS and #ill most li'ely be selected$

&o#ever, #hen a finite po#er budget e)ists, the ability to focus po#er #here it is re0uired

usually allo#s BiCMOS speed performance to surpass that of bipolar

The concept of system on a chipD becomes a reality #ith BiCMOS$

Most gates in 5OM, !E, register subsystems etc do not have to drive large capacitive loads$&ence the use of BiCMOS technology #ould give no speed advantage$

To ta'e ma)imum advantage of available silicon technologies, the follo#ing mi) of

technologies in a silicon system might be used 6

CMOS for logic

BiCMOS for "O and driver circuits

8C! for critical high speed parts of the system$



12-12

Comparison of logic familiese$g$, =.BCT have similar speeds to =.7 but #ith greatly reduced po#er consumption



12-1%7urther advantages of BiCMOS Technology

nalogue amplifier design is facilitated and improved

&igh impedance CMOS transistors may be used for the input circuitry #hile the remaining

stages and output drivers are realised using bipolar transistors

"n general, BiCMOS devices offer many advantages #here high load current sin'ing and

sourcing is re0uired$ The high current gain of the :F: transistor greatly improves the output

drive capability of a conventional CMOS device$

MOS speed depends on device parameters such as saturation current and capacitance$ These in

turn depend on o)ide thic'ness, substrate doping and channel length$

Compared to CMOS, BiCMOSDs reduced dependence on capacitive load and the multiple

circuit and "Os configurations possible greatly enhance design fle)ibility and can lead to

reduced cycle time *i$e$, faster circuits+$

G ea bipolar speed is less dependent on circ$it capacitance .evice parameters f t , / and 0b determine

*ipolar circ$it speed performance (not covered here) and depend on process parameters s$ch as base

width, epita1ial layer profile, emitter width and e1trinsic base formationH



12-1.7urther advantages of BiCMOS Technology

BiCMOS is inherently robust #ith respect to temperature and process variations, resulting in

less variability in final electrical parameters, resulting in higher yield, an important economic

consideration$

!arge circuits can impose severe performance penalties due to simultaneously s#itching noise,

internal cloc' s'e#s and high nodal capacitances in critical paths - BiCMOS has demonstrated

superiority over CMOS in all of these factors$

BiCMOS can ta'e advantage of any advances in CMOS andor bipolar technology, greatly

accelerating the learning curve normally associated #ith ne# technologies$

12 1



12-1re there disadvantages #ith BiCMOS technology I

Main disadvantage 6 greater process comple)ity compared to CMOS

5esults in a 1$2 -A 1$. times increase in die costs over conventional CMOS$

Ta'ing into account pac'aging costs, the total manufacturing costs of supplying a BiCMOS

chip ranges from 1$1-A 1$% times that of CMOS$

&o#ever, as CMOS comple)ity has increased, the percentage difference bet#een CMOS and

BiCMOS mas' steps has decreased$

Therefore, Just as po#er dissipation constraints motivated the s#itch from nMOS to CMOS in

the late =;s, performance re0uirements motivated a s#itch from CMOS to BiCMOS in the late

?;s for !S" products re0uiring the highest speed levels$

Capital costs of investing in continually smaller *K1um+ CMOS technology rises e)ponentially,

#hile the re0uirement of lo# po#er supplies for sub-;$um CMOS results in degradation of

performance$Since BiCMOS does not have to be scaled as aggressively as CMOS, e)isting fabs can be

utilised resulting in lo#er capital costs$ 8)tra costs incurred in developing a BiCMOS

technology is more than offset by the fact that the enhanced chip performance obtained e)tends

the usefulness of manufacturing e0uipment clean rooms by at least one technology

generation$

12 19



12-19BiCMOS - Brief &istorical Ferspective

Most early BiCMOS applications #ere analogueL BiCMOS operational amplifiers #ere

introduced in the mid-=;s follo#ed by BiCMOS po#er "Cs$

4igital !S" BiCMOS devices #ere introduced in the mid-?;s, motivated by high po#erdissipation of bipolar circuits, speed limitations of MOS circuits a need for high "O

throughput$

4evelopment of !S" BiCMOS resulted in very high performance memories, gate arrays

micro-processors

BiCMOS follo#s the same scaling curve as mainstream CMOS technology resulting in

e)plosive gro#th in BiCMOS product gro#th$

BiCMOS has been established as the technology of choice for high speed !S"$

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17/17BiCMOS Technolog

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2rran#ement of *iMOS npn transistor ($m MOS) for reference

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BiCMOS Technology.ppt

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