Blackfin FPGA EZ-Extender Manual

Revision 10 October 2005

Part Number 82-000920-01

Analog Devices IncOne Technology WayNorwood Mass 02062-9106 a

Copyright Informationcopy 2005 Analog Devices Inc ALL RIGHTS RESERVED This docu-ment may not be reproduced in any form without prior express written consent from Analog Devices Inc

Printed in the USA

Limited WarrantyThe Blackfin FPGA EZ-Extender is warranted against defects in materials and workmanship for a period of one year from the date of purchase from Analog Devices or from an authorized dealer

DisclaimerAnalog Devices Inc reserves the right to change this product without prior notice Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringement of patents or other rights of third parties which may result from its use No license is granted by impli-cation or otherwise under the patent rights of Analog Devices Inc

Trademark and Service Mark NoticeThe Analog Devices logo Blackfin VisualDSP++ and EZ-KIT Lite are registered trademarks of Analog Devices Inc

All other brand and product names are trademarks or service marks of their respective owners

Regulatory Compliance The Blackfin FPGA EZ-Extender has been certified to comply with the essential requirements of the European EMC directive 89336EEC (inclusive 9368EEC) and therefore carries the ldquoCErdquo mark

The Blackfin FPGA EZ-Extender had been appended to Analog Devices Development Tools Technical Construction File referenced ldquoDSPTOOLS1rdquo dated December 21 1997 and was awarded CE Certifi-cation by an appointed European Competent Body and is on file

The EZ-KIT Lite evaluation system contains ESD (electrostatic discharge) sensitive devices Electro-static charges readily accumulate on the human body and equipment and can discharge without detection Permanent damage may occur on devices subjected to high-energy discharges Proper ESD precautions are recommended to avoid performance degradation or loss of functionality Store unused EZ-KIT Lite boards in the protective shipping package

CONTENTS

PREFACE

Product Overview ix

Purpose of This Manual xi

Intended Audience xi

Manual Contents xii

Whatrsquos New in This Manual xii

Technical or Customer Support xiii

Supported Products xiii

Product Information xiv

Related Documents xiv

Notation Conventions xvi

FPGA EZ-EXTENDER INTERFACES

FPGA EZ-Extender Setup 1-1

FPGA Software and Firmware 1-2

FPGA EZ-Extender Overview 1-3

FPGA EZ-EXTENDER HARDWARE REFERENCE

System Architecture 2-2

Programming the FPGA 2-3

Blackfin FPGA EZ-Extender Manual v

CONTENTS

FPGA Programming via JTAG 2-4

FPGA Programming via Serial ROM 2-5

FPGA Programming via Blackfin Application 2-6

Programming the Serial ROM 2-7

Serial ROM via JTAG Header 2-7

Power 2-8

Power In Header (P12) 2-9

33V Header (P13) 2-9

25V Header (P42) 2-10

12V Header (P43) 2-10

Jumpers 2-11

Serial ROM Boot Jumper (JP1) 2-12

Config Done Jumper (JP2) 2-12

Config Program Jumper (JP3) 2-13

Boot Jumper (JP4) 2-14

FPGA Input Jumpers (JP5) 2-14

Push Buttons and LEDs 2-15

Program Push Button (SW1) 2-15

PB1 Push Button (SW3) 2-15

PB2 Push Button (SW4) 2-16

Status LEDs (LED1ndash8) 2-17

Power LED (LED9) 2-17

Done LED (LED10) 2-17

Connectors 2-18

vi Blackfin FPGA EZ-Extender Manual

CONTENTS

Expansion Interface (P1ndash3 and J1ndash3) 2-19

IDC Connectors (P8 P14 P16 and P17) 2-19

IDC Connectors (P5 and P7) 2-20

High-Speed Connector (P4) 2-20

BILL OF MATERIALS

SCHEMATICS

INDEX

Blackfin FPGA EZ-Extender Manual vii

CONTENTS

viii Blackfin FPGA EZ-Extender Manual

PREFACE

Thank you for purchasing the Blackfinreg Field-Programmable Gate Array

(FPGA) EZ-Extender Analog Devices Inc (ADI) extension board to the EZ-KIT Litereg evaluation system for ADSP-BF533 ADSP-BF537 and ADSP-BF561 Blackfin processors

The Blackfin processors are embedded processors that support a Media Instruction Set Computing (MISC) architecture This architecture is the natural merging of RISC media functions and digital signal processing characteristics towards delivering signal processing performance in a microprocessor-like environment

The EZ-KIT Lite and FPGA EZ-Extender are designed to be used in con-junction with the VisualDSP++reg development environment VisualDSP++ offers a powerful programming tool with new flexibility that significantly decreases the time required to port software code to a proces-sor reducing time-to-market

To learn more about Analog Devices development software go to httpwwwanalogcomprocessorstools

Product OverviewThe Blackfin FPGA EZ-Extender is a separately sold extension board that plugs onto the expansion interface of the ADSP-BF533 ADSP-BF537 or ADSP-BF561 EZ-KIT Lite evaluation system The extension board aids the design and prototyping phases of ADSP-BF533 ADSP-BF537 or ADSP-BF561 processor targeted applications

Blackfin FPGA EZ-Extender Manual ix

Copyright Informationcopy 2005 Analog Devices Inc ALL RIGHTS RESERVED This docu-ment may not be reproduced in any form without prior express written consent from Analog Devices Inc

Printed in the USA

Limited WarrantyThe Blackfin FPGA EZ-Extender is warranted against defects in materials and workmanship for a period of one year from the date of purchase from Analog Devices or from an authorized dealer

DisclaimerAnalog Devices Inc reserves the right to change this product without prior notice Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringement of patents or other rights of third parties which may result from its use No license is granted by impli-cation or otherwise under the patent rights of Analog Devices Inc

Trademark and Service Mark NoticeThe Analog Devices logo Blackfin VisualDSP++ and EZ-KIT Lite are registered trademarks of Analog Devices Inc

All other brand and product names are trademarks or service marks of their respective owners

Regulatory Compliance The Blackfin FPGA EZ-Extender has been certified to comply with the essential requirements of the European EMC directive 89336EEC (inclusive 9368EEC) and therefore carries the ldquoCErdquo mark

The Blackfin FPGA EZ-Extender had been appended to Analog Devices Development Tools Technical Construction File referenced ldquoDSPTOOLS1rdquo dated December 21 1997 and was awarded CE Certifi-cation by an appointed European Competent Body and is on file

The EZ-KIT Lite evaluation system contains ESD (electrostatic discharge) sensitive devices Electro-static charges readily accumulate on the human body and equipment and can discharge without detection Permanent damage may occur on devices subjected to high-energy discharges Proper ESD precautions are recommended to avoid performance degradation or loss of functionality Store unused EZ-KIT Lite boards in the protective shipping package

CONTENTS

PREFACE

Product Overview ix

Purpose of This Manual xi

Intended Audience xi

Manual Contents xii

Whatrsquos New in This Manual xii

Technical or Customer Support xiii

Supported Products xiii

Product Information xiv

Related Documents xiv

Notation Conventions xvi

FPGA EZ-EXTENDER INTERFACES

FPGA EZ-Extender Setup 1-1

FPGA Software and Firmware 1-2

FPGA EZ-Extender Overview 1-3

FPGA EZ-EXTENDER HARDWARE REFERENCE

System Architecture 2-2

Programming the FPGA 2-3

Blackfin FPGA EZ-Extender Manual v

CONTENTS

FPGA Programming via JTAG 2-4

FPGA Programming via Serial ROM 2-5

FPGA Programming via Blackfin Application 2-6

Programming the Serial ROM 2-7

Serial ROM via JTAG Header 2-7

Power 2-8

Power In Header (P12) 2-9

33V Header (P13) 2-9

25V Header (P42) 2-10

12V Header (P43) 2-10

Jumpers 2-11

Serial ROM Boot Jumper (JP1) 2-12

Config Done Jumper (JP2) 2-12

Config Program Jumper (JP3) 2-13

Boot Jumper (JP4) 2-14

FPGA Input Jumpers (JP5) 2-14

Push Buttons and LEDs 2-15

Program Push Button (SW1) 2-15

PB1 Push Button (SW3) 2-15

PB2 Push Button (SW4) 2-16

Status LEDs (LED1ndash8) 2-17

Power LED (LED9) 2-17

Done LED (LED10) 2-17

Connectors 2-18

vi Blackfin FPGA EZ-Extender Manual

CONTENTS

Expansion Interface (P1ndash3 and J1ndash3) 2-19

IDC Connectors (P8 P14 P16 and P17) 2-19

IDC Connectors (P5 and P7) 2-20

High-Speed Connector (P4) 2-20

BILL OF MATERIALS

SCHEMATICS

INDEX

Blackfin FPGA EZ-Extender Manual vii

CONTENTS

viii Blackfin FPGA EZ-Extender Manual

PREFACE

Thank you for purchasing the Blackfinreg Field-Programmable Gate Array

(FPGA) EZ-Extender Analog Devices Inc (ADI) extension board to the EZ-KIT Litereg evaluation system for ADSP-BF533 ADSP-BF537 and ADSP-BF561 Blackfin processors

The Blackfin processors are embedded processors that support a Media Instruction Set Computing (MISC) architecture This architecture is the natural merging of RISC media functions and digital signal processing characteristics towards delivering signal processing performance in a microprocessor-like environment

The EZ-KIT Lite and FPGA EZ-Extender are designed to be used in con-junction with the VisualDSP++reg development environment VisualDSP++ offers a powerful programming tool with new flexibility that significantly decreases the time required to port software code to a proces-sor reducing time-to-market

To learn more about Analog Devices development software go to httpwwwanalogcomprocessorstools

Product OverviewThe Blackfin FPGA EZ-Extender is a separately sold extension board that plugs onto the expansion interface of the ADSP-BF533 ADSP-BF537 or ADSP-BF561 EZ-KIT Lite evaluation system The extension board aids the design and prototyping phases of ADSP-BF533 ADSP-BF537 or ADSP-BF561 processor targeted applications

Blackfin FPGA EZ-Extender Manual ix

Regulatory Compliance The Blackfin FPGA EZ-Extender has been certified to comply with the essential requirements of the European EMC directive 89336EEC (inclusive 9368EEC) and therefore carries the ldquoCErdquo mark

The Blackfin FPGA EZ-Extender had been appended to Analog Devices Development Tools Technical Construction File referenced ldquoDSPTOOLS1rdquo dated December 21 1997 and was awarded CE Certifi-cation by an appointed European Competent Body and is on file

The EZ-KIT Lite evaluation system contains ESD (electrostatic discharge) sensitive devices Electro-static charges readily accumulate on the human body and equipment and can discharge without detection Permanent damage may occur on devices subjected to high-energy discharges Proper ESD precautions are recommended to avoid performance degradation or loss of functionality Store unused EZ-KIT Lite boards in the protective shipping package

CONTENTS

PREFACE

Product Overview ix

Purpose of This Manual xi

Intended Audience xi

Manual Contents xii

Whatrsquos New in This Manual xii

Technical or Customer Support xiii

Supported Products xiii

Product Information xiv

Related Documents xiv

Notation Conventions xvi

FPGA EZ-EXTENDER INTERFACES

FPGA EZ-Extender Setup 1-1

FPGA Software and Firmware 1-2

FPGA EZ-Extender Overview 1-3

FPGA EZ-EXTENDER HARDWARE REFERENCE

System Architecture 2-2

Programming the FPGA 2-3

Blackfin FPGA EZ-Extender Manual v

CONTENTS

FPGA Programming via JTAG 2-4

FPGA Programming via Serial ROM 2-5

FPGA Programming via Blackfin Application 2-6

Programming the Serial ROM 2-7

Serial ROM via JTAG Header 2-7

Power 2-8

Power In Header (P12) 2-9

33V Header (P13) 2-9

25V Header (P42) 2-10

12V Header (P43) 2-10

Jumpers 2-11

Serial ROM Boot Jumper (JP1) 2-12

Config Done Jumper (JP2) 2-12

Config Program Jumper (JP3) 2-13

Boot Jumper (JP4) 2-14

FPGA Input Jumpers (JP5) 2-14

Push Buttons and LEDs 2-15

Program Push Button (SW1) 2-15

PB1 Push Button (SW3) 2-15

PB2 Push Button (SW4) 2-16

Status LEDs (LED1ndash8) 2-17

Power LED (LED9) 2-17

Done LED (LED10) 2-17

Connectors 2-18

vi Blackfin FPGA EZ-Extender Manual

CONTENTS

Expansion Interface (P1ndash3 and J1ndash3) 2-19

IDC Connectors (P8 P14 P16 and P17) 2-19

IDC Connectors (P5 and P7) 2-20

High-Speed Connector (P4) 2-20

BILL OF MATERIALS

SCHEMATICS

INDEX

Blackfin FPGA EZ-Extender Manual vii

CONTENTS

viii Blackfin FPGA EZ-Extender Manual

PREFACE

Thank you for purchasing the Blackfinreg Field-Programmable Gate Array

(FPGA) EZ-Extender Analog Devices Inc (ADI) extension board to the EZ-KIT Litereg evaluation system for ADSP-BF533 ADSP-BF537 and ADSP-BF561 Blackfin processors

The Blackfin processors are embedded processors that support a Media Instruction Set Computing (MISC) architecture This architecture is the natural merging of RISC media functions and digital signal processing characteristics towards delivering signal processing performance in a microprocessor-like environment

The EZ-KIT Lite and FPGA EZ-Extender are designed to be used in con-junction with the VisualDSP++reg development environment VisualDSP++ offers a powerful programming tool with new flexibility that significantly decreases the time required to port software code to a proces-sor reducing time-to-market

To learn more about Analog Devices development software go to httpwwwanalogcomprocessorstools

Product OverviewThe Blackfin FPGA EZ-Extender is a separately sold extension board that plugs onto the expansion interface of the ADSP-BF533 ADSP-BF537 or ADSP-BF561 EZ-KIT Lite evaluation system The extension board aids the design and prototyping phases of ADSP-BF533 ADSP-BF537 or ADSP-BF561 processor targeted applications

Blackfin FPGA EZ-Extender Manual ix

CONTENTS

PREFACE

Product Overview ix

Purpose of This Manual xi

Intended Audience xi

Manual Contents xii

Whatrsquos New in This Manual xii

Technical or Customer Support xiii

Supported Products xiii

Product Information xiv

Related Documents xiv

Notation Conventions xvi

FPGA EZ-EXTENDER INTERFACES

FPGA EZ-Extender Setup 1-1

FPGA Software and Firmware 1-2

FPGA EZ-Extender Overview 1-3

FPGA EZ-EXTENDER HARDWARE REFERENCE

System Architecture 2-2

Programming the FPGA 2-3

Blackfin FPGA EZ-Extender Manual v

CONTENTS

FPGA Programming via JTAG 2-4

FPGA Programming via Serial ROM 2-5

FPGA Programming via Blackfin Application 2-6

Programming the Serial ROM 2-7

Serial ROM via JTAG Header 2-7

Power 2-8

Power In Header (P12) 2-9

33V Header (P13) 2-9

25V Header (P42) 2-10

12V Header (P43) 2-10

Jumpers 2-11

Serial ROM Boot Jumper (JP1) 2-12

Config Done Jumper (JP2) 2-12

Config Program Jumper (JP3) 2-13

Boot Jumper (JP4) 2-14

FPGA Input Jumpers (JP5) 2-14

Push Buttons and LEDs 2-15

Program Push Button (SW1) 2-15

PB1 Push Button (SW3) 2-15

PB2 Push Button (SW4) 2-16

Status LEDs (LED1ndash8) 2-17

Power LED (LED9) 2-17

Done LED (LED10) 2-17

Connectors 2-18

vi Blackfin FPGA EZ-Extender Manual

CONTENTS

Expansion Interface (P1ndash3 and J1ndash3) 2-19

IDC Connectors (P8 P14 P16 and P17) 2-19

IDC Connectors (P5 and P7) 2-20

High-Speed Connector (P4) 2-20

BILL OF MATERIALS

SCHEMATICS

INDEX

Blackfin FPGA EZ-Extender Manual vii

CONTENTS

viii Blackfin FPGA EZ-Extender Manual

PREFACE

Thank you for purchasing the Blackfinreg Field-Programmable Gate Array

(FPGA) EZ-Extender Analog Devices Inc (ADI) extension board to the EZ-KIT Litereg evaluation system for ADSP-BF533 ADSP-BF537 and ADSP-BF561 Blackfin processors

The Blackfin processors are embedded processors that support a Media Instruction Set Computing (MISC) architecture This architecture is the natural merging of RISC media functions and digital signal processing characteristics towards delivering signal processing performance in a microprocessor-like environment

The EZ-KIT Lite and FPGA EZ-Extender are designed to be used in con-junction with the VisualDSP++reg development environment VisualDSP++ offers a powerful programming tool with new flexibility that significantly decreases the time required to port software code to a proces-sor reducing time-to-market

To learn more about Analog Devices development software go to httpwwwanalogcomprocessorstools

Product OverviewThe Blackfin FPGA EZ-Extender is a separately sold extension board that plugs onto the expansion interface of the ADSP-BF533 ADSP-BF537 or ADSP-BF561 EZ-KIT Lite evaluation system The extension board aids the design and prototyping phases of ADSP-BF533 ADSP-BF537 or ADSP-BF561 processor targeted applications

Blackfin FPGA EZ-Extender Manual ix

CONTENTS

FPGA Programming via JTAG 2-4

FPGA Programming via Serial ROM 2-5

FPGA Programming via Blackfin Application 2-6

Programming the Serial ROM 2-7

Serial ROM via JTAG Header 2-7

Power 2-8

Power In Header (P12) 2-9

33V Header (P13) 2-9

25V Header (P42) 2-10

12V Header (P43) 2-10

Jumpers 2-11

Serial ROM Boot Jumper (JP1) 2-12

Config Done Jumper (JP2) 2-12

Config Program Jumper (JP3) 2-13

Boot Jumper (JP4) 2-14

FPGA Input Jumpers (JP5) 2-14

Push Buttons and LEDs 2-15

Program Push Button (SW1) 2-15

PB1 Push Button (SW3) 2-15

PB2 Push Button (SW4) 2-16

Status LEDs (LED1ndash8) 2-17

Power LED (LED9) 2-17

Done LED (LED10) 2-17

Connectors 2-18

vi Blackfin FPGA EZ-Extender Manual

CONTENTS

Expansion Interface (P1ndash3 and J1ndash3) 2-19

IDC Connectors (P8 P14 P16 and P17) 2-19

IDC Connectors (P5 and P7) 2-20

High-Speed Connector (P4) 2-20

BILL OF MATERIALS

SCHEMATICS

INDEX

Blackfin FPGA EZ-Extender Manual vii

CONTENTS

viii Blackfin FPGA EZ-Extender Manual

PREFACE

Thank you for purchasing the Blackfinreg Field-Programmable Gate Array

(FPGA) EZ-Extender Analog Devices Inc (ADI) extension board to the EZ-KIT Litereg evaluation system for ADSP-BF533 ADSP-BF537 and ADSP-BF561 Blackfin processors

The Blackfin processors are embedded processors that support a Media Instruction Set Computing (MISC) architecture This architecture is the natural merging of RISC media functions and digital signal processing characteristics towards delivering signal processing performance in a microprocessor-like environment

The EZ-KIT Lite and FPGA EZ-Extender are designed to be used in con-junction with the VisualDSP++reg development environment VisualDSP++ offers a powerful programming tool with new flexibility that significantly decreases the time required to port software code to a proces-sor reducing time-to-market

To learn more about Analog Devices development software go to httpwwwanalogcomprocessorstools

Product OverviewThe Blackfin FPGA EZ-Extender is a separately sold extension board that plugs onto the expansion interface of the ADSP-BF533 ADSP-BF537 or ADSP-BF561 EZ-KIT Lite evaluation system The extension board aids the design and prototyping phases of ADSP-BF533 ADSP-BF537 or ADSP-BF561 processor targeted applications

Blackfin FPGA EZ-Extender Manual ix

CONTENTS

Expansion Interface (P1ndash3 and J1ndash3) 2-19

IDC Connectors (P8 P14 P16 and P17) 2-19

IDC Connectors (P5 and P7) 2-20

High-Speed Connector (P4) 2-20

BILL OF MATERIALS

SCHEMATICS

INDEX

Blackfin FPGA EZ-Extender Manual vii

CONTENTS

viii Blackfin FPGA EZ-Extender Manual

PREFACE

Thank you for purchasing the Blackfinreg Field-Programmable Gate Array

(FPGA) EZ-Extender Analog Devices Inc (ADI) extension board to the EZ-KIT Litereg evaluation system for ADSP-BF533 ADSP-BF537 and ADSP-BF561 Blackfin processors

The Blackfin processors are embedded processors that support a Media Instruction Set Computing (MISC) architecture This architecture is the natural merging of RISC media functions and digital signal processing characteristics towards delivering signal processing performance in a microprocessor-like environment

The EZ-KIT Lite and FPGA EZ-Extender are designed to be used in con-junction with the VisualDSP++reg development environment VisualDSP++ offers a powerful programming tool with new flexibility that significantly decreases the time required to port software code to a proces-sor reducing time-to-market

To learn more about Analog Devices development software go to httpwwwanalogcomprocessorstools

Product OverviewThe Blackfin FPGA EZ-Extender is a separately sold extension board that plugs onto the expansion interface of the ADSP-BF533 ADSP-BF537 or ADSP-BF561 EZ-KIT Lite evaluation system The extension board aids the design and prototyping phases of ADSP-BF533 ADSP-BF537 or ADSP-BF561 processor targeted applications

Blackfin FPGA EZ-Extender Manual ix

CONTENTS

viii Blackfin FPGA EZ-Extender Manual

PREFACE

Thank you for purchasing the Blackfinreg Field-Programmable Gate Array

(FPGA) EZ-Extender Analog Devices Inc (ADI) extension board to the EZ-KIT Litereg evaluation system for ADSP-BF533 ADSP-BF537 and ADSP-BF561 Blackfin processors

The Blackfin processors are embedded processors that support a Media Instruction Set Computing (MISC) architecture This architecture is the natural merging of RISC media functions and digital signal processing characteristics towards delivering signal processing performance in a microprocessor-like environment

The EZ-KIT Lite and FPGA EZ-Extender are designed to be used in con-junction with the VisualDSP++reg development environment VisualDSP++ offers a powerful programming tool with new flexibility that significantly decreases the time required to port software code to a proces-sor reducing time-to-market

To learn more about Analog Devices development software go to httpwwwanalogcomprocessorstools

Product OverviewThe Blackfin FPGA EZ-Extender is a separately sold extension board that plugs onto the expansion interface of the ADSP-BF533 ADSP-BF537 or ADSP-BF561 EZ-KIT Lite evaluation system The extension board aids the design and prototyping phases of ADSP-BF533 ADSP-BF537 or ADSP-BF561 processor targeted applications

Blackfin FPGA EZ-Extender Manual ix

PREFACE

Thank you for purchasing the Blackfinreg Field-Programmable Gate Array

(FPGA) EZ-Extender Analog Devices Inc (ADI) extension board to the EZ-KIT Litereg evaluation system for ADSP-BF533 ADSP-BF537 and ADSP-BF561 Blackfin processors

The Blackfin processors are embedded processors that support a Media Instruction Set Computing (MISC) architecture This architecture is the natural merging of RISC media functions and digital signal processing characteristics towards delivering signal processing performance in a microprocessor-like environment

The EZ-KIT Lite and FPGA EZ-Extender are designed to be used in con-junction with the VisualDSP++reg development environment VisualDSP++ offers a powerful programming tool with new flexibility that significantly decreases the time required to port software code to a proces-sor reducing time-to-market

To learn more about Analog Devices development software go to httpwwwanalogcomprocessorstools

Product OverviewThe Blackfin FPGA EZ-Extender is a separately sold extension board that plugs onto the expansion interface of the ADSP-BF533 ADSP-BF537 or ADSP-BF561 EZ-KIT Lite evaluation system The extension board aids the design and prototyping phases of ADSP-BF533 ADSP-BF537 or ADSP-BF561 processor targeted applications

Blackfin FPGA EZ-Extender Manual ix

Product Overview

The board extends the capabilities of the evaluation system by providing a Xilinx FPGA with external memory IDC connectors for off-board con-nections and a small bread board area

The Blackfin FPGA EZ-Extender features

bull Xilinx Spartan III Field-Programmable Gate Array

XC3S1000FG456 package

bull Asynchronous static random access memory (SRAM)

Directly connected to FPGA2 MB (512K x 16 bits x 2 chips)TSOP44 package

bull 25 MHz oscillator

Directly connected to global clock of FPGA

bull Socket for auxiliary oscillator

Directly connected to global clock of FPGA

bull IDC thru-hole connectors

Allows quick access to Blackfin and FPGA pins for probing Allows access to Blackfin and FPGA pins for off-board connections

bull High-speed connector

Allows access to Blackfin and FPGA pins for high-speed application

bull Expansion interface connectors

Allows access to ADIrsquos family of Blackfin EZ-Extenders

x Blackfin FPGA EZ-Extender Manual

Preface

bull Two push buttons

Directly connected to FPGAOne with external debounce circuitry and one without

bull Eight flag LEDs

Directly connected to FPGA

Before using any of the interfaces follow the setup procedure in ldquoFPGA EZ-Extender Setuprdquo on page 1-1

Example programs are available to demonstrate the capabilities of the Blackfin FPGA EZ-Extender board

Purpose of This Manual The Blackfin FPGA EZ-Extender Manual describes the operation and con-figuration of the components on the extension board A schematic and a bill of materials are provided as a reference for future Blackfin processor board designs

Intended AudienceThis manual is a userrsquos guide and reference to the Blackfin FPGA EZ-Extender Programmers who are familiar with the Analog Devices Blackfin processor architecture operation and development tools are the primary audience for this manual The user should also be familiar with basic FPGA development and Xilinxrsquos Spartan III family of FPGAs

Programmers who are unfamiliar with VisualDSP++ or EZ-KIT Lite eval-uation software should refer to the ADSP-BF533 ADSP-BF537 or ADSP-BF561 Evaluation System Manual VisualDSP++ online Help and userrsquos or getting started guides For the locations of these documents refer to ldquoRelated Documentsrdquo

Blackfin FPGA EZ-Extender Manual xi

Manual Contents

Manual ContentsThe manual consists of

bull Chapter 1 ldquoFPGA EZ-Extender Interfacesrdquo on page 1-1Provides basic board information

bull Chapter 2 ldquoFPGA EZ-Extender Hardware Referencerdquo on page 2-1Provides information on the hardware aspects of the board

bull Appendix A ldquoBill Of Materialsrdquo on page A-1Provides a list of components used to manufacture the EZ-Extender board

bull Appendix B ldquoSchematicsrdquo on page B-1Provides the resources to allow EZ-KIT Lite board-level debugging or to use as a reference design

This appendix is not part of the online Help The online Help viewers should go to the PDF version of the Blackfin FPGA EZ-Extender Manual located in the DocsEZ-KIT Lite Manuals folder on the installation CD to see the schematics Alternatively the schematics can be found on the Analog Devices Web site wwwanalogcomprocessors

Whatrsquos New in This Manual This is the first edition of the Blackfin FPGA EZ-Extender Manual

xii Blackfin FPGA EZ-Extender Manual

Preface

bull Two push buttons

Directly connected to FPGAOne with external debounce circuitry and one without

bull Eight flag LEDs

Directly connected to FPGA

Before using any of the interfaces follow the setup procedure in ldquoFPGA EZ-Extender Setuprdquo on page 1-1

Example programs are available to demonstrate the capabilities of the Blackfin FPGA EZ-Extender board

Purpose of This Manual The Blackfin FPGA EZ-Extender Manual describes the operation and con-figuration of the components on the extension board A schematic and a bill of materials are provided as a reference for future Blackfin processor board designs

Intended AudienceThis manual is a userrsquos guide and reference to the Blackfin FPGA EZ-Extender Programmers who are familiar with the Analog Devices Blackfin processor architecture operation and development tools are the primary audience for this manual The user should also be familiar with basic FPGA development and Xilinxrsquos Spartan III family of FPGAs

Programmers who are unfamiliar with VisualDSP++ or EZ-KIT Lite eval-uation software should refer to the ADSP-BF533 ADSP-BF537 or ADSP-BF561 Evaluation System Manual VisualDSP++ online Help and userrsquos or getting started guides For the locations of these documents refer to ldquoRelated Documentsrdquo

Blackfin FPGA EZ-Extender Manual xi

Manual Contents

Manual ContentsThe manual consists of

bull Chapter 1 ldquoFPGA EZ-Extender Interfacesrdquo on page 1-1Provides basic board information

bull Chapter 2 ldquoFPGA EZ-Extender Hardware Referencerdquo on page 2-1Provides information on the hardware aspects of the board

bull Appendix A ldquoBill Of Materialsrdquo on page A-1Provides a list of components used to manufacture the EZ-Extender board

bull Appendix B ldquoSchematicsrdquo on page B-1Provides the resources to allow EZ-KIT Lite board-level debugging or to use as a reference design

This appendix is not part of the online Help The online Help viewers should go to the PDF version of the Blackfin FPGA EZ-Extender Manual located in the DocsEZ-KIT Lite Manuals folder on the installation CD to see the schematics Alternatively the schematics can be found on the Analog Devices Web site wwwanalogcomprocessors

Whatrsquos New in This Manual This is the first edition of the Blackfin FPGA EZ-Extender Manual

xii Blackfin FPGA EZ-Extender Manual

Manual Contents

Manual ContentsThe manual consists of

bull Chapter 1 ldquoFPGA EZ-Extender Interfacesrdquo on page 1-1Provides basic board information

bull Chapter 2 ldquoFPGA EZ-Extender Hardware Referencerdquo on page 2-1Provides information on the hardware aspects of the board

bull Appendix A ldquoBill Of Materialsrdquo on page A-1Provides a list of components used to manufacture the EZ-Extender board

bull Appendix B ldquoSchematicsrdquo on page B-1Provides the resources to allow EZ-KIT Lite board-level debugging or to use as a reference design

This appendix is not part of the online Help The online Help viewers should go to the PDF version of the Blackfin FPGA EZ-Extender Manual located in the DocsEZ-KIT Lite Manuals folder on the installation CD to see the schematics Alternatively the schematics can be found on the Analog Devices Web site wwwanalogcomprocessors

Whatrsquos New in This Manual This is the first edition of the Blackfin FPGA EZ-Extender Manual

xii Blackfin FPGA EZ-Extender Manual

Preface

Technical or Customer SupportYou can reach Analog Devices Inc Customer Support in the following ways

bull Visit the Embedded Processing and DSP products Web site athttpwwwanalogcomprocessorstechnicalSupport

bull E-mail tools questions toprocessortoolssupportanalogcom

bull E-mail processor questions toprocessorsupportanalogcom (World wide support)

processoreuropeanalogcom (Europe support)

processorchinaanalogcom (China support)

bull Phone questions to 1-800-ANALOGD

bull Contact your Analog Devices Inc local sales office or authorized distributor

bull Send questions by mail toAnalog Devices Inc

One Technology Way

PO Box 9106

Norwood MA 02062-9106

USA

Supported ProductsThe Blackfin FPGA EZ-Extender is designed as an extension board to the ADSP-BF533 ADSP-BF537 and ADSP-BF561 EZ-KIT Lite evaluation systems

Blackfin FPGA EZ-Extender Manual xiii

Product Information

Product InformationYou can obtain product information from the Analog Devices Web site from the product CD-ROM or from the printed publications (manuals)

Analog Devices is online at wwwanalogcom Our Web site provides infor-mation about a broad range of productsmdashanalog integrated circuits amplifiers converters and digital signal processors

Related DocumentsFor information on product related development software see the follow-ing publications

Table 1 Related Processor Publications

Title Description

bull ADSP-BF533 Embedded Processor Datasheet bull ADSP-BF536ADSP-BF537 Embedded Pro-

cessor Datasheetbull ASP-BF561 Blackfin Embedded Symmetric

Multi-Processor Datasheet

General functional description pinout and timing

bull ADSP-BF533 Blackfin Processor Hardware Reference

bull ADSP-BF537 Blackfin Processor Hardware Reference

bull ASP-BF561 Blackfin Processor Hardware Reference

Description of internal processor architecture and all register functions

Blackfin Processor Instruction Set Reference Description of all allowed processor assembly instructions

xiv Blackfin FPGA EZ-Extender Manual

Preface

All documentation is available online Most documentation is available in printed form

Visit the Technical Library Web site to access all processor and tools man-uals and data sheetshttpwwwanalogcomprocessorsresourcestechnicalLibrary

For more information on the Xilinx Spartan III FPGA refer to the datasheet located at wwwxilinxcom

Table 2 Related VisualDSP++ Publications

Title Description

bull ADSP-BF533 EZ-KIT Lite Evaluation Sys-tem Manual

bull ADSP-BF537 EZ-KIT Lite Evaluation Sys-tem Manual

bull ADSP-BF561 EZ-KIT Lite Evaluation Sys-tem Manual

Description of the EZ-KIT Lite features and usageNote For the ADSP-BF537 EZ-KIT Lite there is additional Getting Started with ADSP-BF537 EZ-KIT Lite

VisualDSP++ Userrsquos Guide Description of VisualDSP++ features and usage

VisualDSP++ Assembler and Preprocessor Man-ual

Description of the assembler function and commands

VisualDSP++ CC++ Complier and Library Manual for Blackfin Processors

Description of the complier function and com-mands for Blackfin processors

VisualDSP++ Linker and Utilities Manual Description of the linker function and com-mands

VisualDSP++ Loader Manual Description of the loader function and com-mands

Blackfin FPGA EZ-Extender Manual xv

Notation Conventions

Notation ConventionsText conventions used in this manual are identified and described as follows

Additional conventions which apply only to specific chapters may appear throughout this document

Example Description

this | that Alternative required items in syntax descriptions appear within curly brackets and separated by vertical bars read the example as this or that One or the other is required

[this | that] Optional items in syntax descriptions appear within brackets and sepa-rated by vertical bars read the example as an optional this or that

[thishellip] Optional item lists in syntax descriptions appear within brackets delimited by commas and terminated with an ellipse read the example as an optional comma-separated list of this

SECTION Commands directives keywords and feature names are in text with letter gothic font

filename Non-keyword placeholders appear in text with italic style format

Note For correct operation A Note provides supplementary information on a related topic In the online version of this book the word Note appears instead of this symbol

Caution Incorrect device operation may result if Caution Device damage may result if A Caution identifies conditions or inappropriate usage of the product that could lead to undesirable results or product damage In the online version of this book the word Caution appears instead of this symbol

Warning Injury to device users may result if A Warning identifies conditions or inappropriate usage of the product that could lead to conditions that are potentially hazardous for the devices users In the online version of this book the word Warning appears instead of this symbol

xvi Blackfin FPGA EZ-Extender Manual

1 FPGA EZ-EXTENDER INTERFACES

This chapter provides the setup procedures for both the Blackfin

Field-Programmable Gate Array (FPGA) EZ-Extender and EZ-KIT Lite (ADSP-BF533 ADSP-BF537 or ADSP-BF561) It also provides an over-view of the extender board

The information is presented in the following order

bull ldquoFPGA EZ-Extender Setuprdquo on page 1-1

bull ldquoFPGA Software and Firmwarerdquo on page 1-2

bull ldquoFPGA EZ-Extender Overviewrdquo on page 1-3

FPGA EZ-Extender SetupIt is very important to set up all of the components of the system contain-ing the FPGA EZ-Extender before applying power to that system The following procedure is recommended

Power your system when these steps are completed

1 Read the applicable design interface section in this chaptermdashthe text provides an overview of the capabilities of the EZ-Extender

2 Read ldquoSystem Architecturerdquo on page 2-2 to understand the physical connections of the extender board For detailed information refer to ldquoSchematics on page B-1rdquo

Blackfin FPGA EZ-Extender Manual 1-1

FPGA Software and Firmware

3 Remove any rubber feet attached to the EZ-KIT Lite if the feet cover the printed circuit board (PCB) mounting holes In place of the rubber feet install the four nylon feet and screws provided with the FPGA EZ-Extender Install the nylon feet in the mounting holes of the EZ-KIT Litersquos PCB Flip the EZ-KIT Lite upside down so that the three expansion headers (J1ndash3) are facing up

4 Set the switches and jumpers on the FPGA EZ-Extender board Use the block diagram in Figure 2-1 on page 2-2 in conjunction with ldquoJumpersrdquo on page 2-11

5 Set the switches and jumpers on the EZ-KIT Lite board If not already familiarize yourself with the documentation and schemat-ics of the EZ-KIT Lite (see ldquoRelated Documentsrdquo on page -xiv) Compare the expansion interface signals of the FPGA EZ-Extender board with the signals of the EZ-KIT Lite board to ensure there is no contention For example it may be necessary to disable other devices connected to the expansion interface of the processor and disable the push buttons on the EZ-KIT Lite

6 Install the FPGA EZ-Extender on the EZ-KIT Lite via the three-connector expansion interface Figure 1-1 shows how an FPGA EZ-Extender plugs onto an EZ-KIT Lite

7 Configure any other interfacing boards for example another EZ-Extender

FPGA Software and FirmwareFor information on the FPGA software refer to the FPGA Software Readmetxt file located in the hellipBlackfinEZ-KITsFPGA EZ-EXTENDER subdirectory of the VisualDSP++ installation directory

1-2 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Interfaces

FPGA EZ-Extender OverviewThe Blackfin FPGA EZ-Extender connects a Xilinxreg Spartan III Field-Programmable Gate Array (FPGA for short) to the ADSP-BF533 ADSP-BF537 or the ADSP-BF561 EZ-KIT Lite The FPGA connects to the Blackfin processor via the expansion interface

The extender board by default is powered by an external 7V power sup-ply provided with the product You can also power the FPGA EZ-Extender by the expansion interface of the EZ-KIT Lite or an external power supply An external supply must be used whenever application code exceeds the recommended core and IO power supported by the FPGA EZ-Extender For more information on the jumper and connector settings required to power the extender review ldquoPowerrdquo on page 2-8 as well as the schematics in Appendix C

Figure 1-1 FPGA EZ-Extender Setup

Blackfin FPGA EZ-Extender Manual 1-3

FPGA EZ-Extender Overview

The FPGA EZ-Extender contains 2 MB of asynchronous SRAM memory powered by a 33V supply The SRAM memory connects to banks 6 and 7 of the FPGA and can perform simple data storage instructions in applica-tion-specific code

The FPGA EZ-Extender includes a 25 MHz oscillator (U6) connected to the FPGA via the dedicated global clock 1 (GCLK1) pin facilitating devel-opment of applications that require a clock A second clock socket (U7) is left unpopulated to allow a user to place an oscillator with a specific fre-quency for the FPGA The second clock socket connects to the global clock 6 (GCLK6) pin of the FPGA

The extender has eight LEDs (LED1ndash8) and two push buttons (SW3ndash4) for applications that require status reporting and user control The push but-tons are active low and when pressed provide a logic 0 to the respective FPGA nets For inputs that require a permanent input low use the jumper inputs on JP4 When a jumper is populated on one of the four nets of JP4 the respective pin is hard wired to a logic 0 For more information about the LEDs push button switches and jumper inputs refer to ldquoFPGA EZ-Extender Hardware Referencerdquo on page 2-1

There are various ways to program the FPGA By default the FPGA is programmed in its slave serial mode by the flash programming utility in VisualDSP++ The program configures the FPGA using the Blackfin pro-cessorrsquos flag pins andor serial port pins For more information on how to use the flash programming utility within VisualDSP++ refer to the FPGA Software Readmetxt file located in the hellipBlackfinEZ-KITsFPGA EZ-EXTENDER subdirectory of the VisualDSP++ installation directory

A second method of programming the FPGA is by using a Xilinx JTAG cable and software The Xilinx JTAG cable connects to the FPGA JTAG header (P15) For more information about programming the FPGA via a Xilinx JTAG cable refer to the manufacturerrsquos website at wwwxilinxcom

1-4 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Interfaces

The third and final way to program the FPGA is via the Xilinx serial ROM on the FPGA EZ-Extender The serial ROM used for FPGA is shipped with the extender and is pre-programmed If the serial ROM needs to be re-programmed with new code use an Xilinx JTAG cable and software and connect the Xilinx JTAG cable to the flash JTAG header (P6)

More information about programming the serial ROM can be found at wwwxilinxcom More details about the different ways to program the FPGA can be found in ldquoFPGA EZ-Extender Hardware Referencerdquo on page 2-1

Blackfin FPGA EZ-Extender Manual 1-5

FPGA EZ-Extender Overview

1-6 Blackfin FPGA EZ-Extender Manual

2 FPGA EZ-EXTENDER HARDWARE REFERENCE

This chapter describes the hardware design of the Field-Programmable

Gate Array (FPGA) EZ-Extender

The following topics are covered

bull ldquoSystem Architecturerdquo on page 2-2Describes the configuration of the extender board and explains how the board components interface with the processor and EZ-KIT Lite

bull ldquoProgramming the FPGArdquo on page 2-3Describes the different methods of programming the FPGA

bull ldquoProgramming the Serial ROMrdquo on page 2-7Describes the method of programming the serial ROM

bull ldquoPowerrdquo on page 2-8Describes the methods to power the extender board

bull ldquoJumpersrdquo on page 2-11Describes the function of the configuration jumpers

bull ldquoPush Buttons and LEDsrdquo on page 2-15Describes the function of the push buttons and LEDs

bull ldquoConnectorsrdquo on page 2-18Describes the function of the extender connectors

Blackfin FPGA EZ-Extender Manual 2-1

System Architecture

System ArchitectureA block diagram of the Blackfin FPGA EZ-Extender is shown in Figure 2-1

Figure 2-1 Block Diagram

X ilin xS p a rta n 3

X C 3 S 1 0 0 0 -4 F G 4 5 6 C F P G A2 M B S R A M

(5 1 2 k x 3 2 -b its )

M e m o ry In te rfa c e

S P I S P O R T (2 x ) P P I(2 x ) G P IO

T im e rs T W I

P rim a ry E x p a n s io n In te rfa c e ( to B la c k F in E Z -K IT )

S e c o n d a ry E x p a n s io n In te rfa c e (to T e s t p o in ts a n d o th e r E Z -

E x te n d e rs )

P o w e r C o n n e c to r

R e g u la to rs

3 3 V 2 5 V 1 2 V

1 in c h h e a d e rs

2 5 M H z

O s c illa to r S o c k e t

L E D D IP S w itc h P u s h B u tto n s

S P I S P O R T (2 x ) P P I(2 x ) G P IO

T im e rs T W I

S e ria l F la s h

H ig h S p e e d C o n n e c to r

J T A G C o n n e c to r

J T A G C o n n e c to r

2-2 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Hardware Reference

Programming the FPGABefore using the Blackfin FPGA EZ-Extender follow the steps in ldquoFPGA EZ-Extender Setuprdquo on page 1-1

Figure 2-2 is a block diagram of the FPGA programming connections

Figure 2-2 FPGA Programming Block Diagram

Blackfin FPGA EZ-Extender Manual 2-3

Programming the FPGA

There are three ways to program the FPGA

bull Using the FPGA JTAG header as described in ldquoFPGA Program-ming via JTAGrdquo on page 2-4

bull Using the Xilinx serial ROM as described in ldquoFPGA Programming via Serial ROMrdquo on page 2-5

bull Using the Blackfin processor as described in ldquoFPGA Programming via Blackfin Applicationrdquo on page 2-6

The done LED (LED10) lights up once the FPGA is programmed signifying that the task is complete To erase the contents of the FPGA at any time de-press the program switch SW1

FPGA Programming via JTAGTo program the FPGA via the JTAG header create the appropriate pro-gram file using the Xilinx ISE software provided at wwwxilinxcom Once the program file is created use a Xilinx JTAG cable and connect it to P15 of the FPGA EZ-Extender (the P15 connections are shown in Table 2-1)

Table 2-1 P15 Connections for PFGA Programming via JTAG

P15 Pin Number Signal Name

1 33V

2 GND

3 TCK

4 TDO

5 TDI

6 TMS

2-4 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Hardware Reference

In addition to removing JP1 (serial ROM boot jumper) as shown in Table 2-2 set the boot jumper JP4 to JTAG mode The JP4 settings for JTAG boot are shown in Table 2-3 See ldquoBoot Jumper (JP4)rdquo on page 2-14 for more information

FPGA Programming via Serial ROMTo program the FPGA with the contents of the serial ROM populate the JP1 jumper When populated JP1 connects the chip enable pin of the serial ROM to the done bit of the FPGA Once the FPGA is programmed the done bit automatically goes high and the enable pin of the serial ROM chip becomes a logic 1 The JP1 settings for serial ROM boot are shown in Table 2-4 See ldquoProgramming the Serial ROMrdquo on page 2-7 for more information

The done LED (LED10) remains lit to signify that the FPGA is pro-grammed See ldquoDone LED (LED10)rdquo on page 2-17 for more information

Table 2-2 JP1 Settings for FPGA Programming via JTAG

JP1 Pin Name Pins Connected Jumper Setting

Flash done JP11 and JP12 Unpopulated

Table 2-3 JP4 Settings for FPGA Programming via JTAG

JP4 Pin Name Pins Connected Jumper Setting

M0 JP41 and JP42 Unpopulated

M1 JP43 and JP44 Populated

M2 JP45 and JP46 Unpopulated

Table 2-4 JP1 Settings for FPGA Programming via Serial ROM

JP1 Pin Name Pins Connected Jumper Setting

Flash done JP11 and JP12 Populated

Blackfin FPGA EZ-Extender Manual 2-5

Programming the FPGA

In addition to JP1 set the boot mode jumper JP4 to master serial mode The JP4 settings for serial ROM boot are shown in Table 2-5 See ldquoBoot Jumper (JP4)rdquo on page 2-14 for more information

FPGA Programming via Blackfin ApplicationBy default the FPGA EZ-Extender is configured by the flash program-ming utility within VisualDSP++ The software is located in the hellipBlackfinEZ-KITsFPGA EZ-EXTENDER subdirectory of the VisualDSP++ installation directory The FPGA Software Readmetxt file located in the same subdirectory provides all the necessary instructions required for run-ning the application

When generating a program file using the Xilinx software tools remember to generate a slave serial program file in the Intel MCS-86 Hexadecimal Object (mcs) file format

To boot the FPGA from the Blackfin processor unpopulate jumper JP1 and set jumper JP4 to slave serial mode as shown in Table 2-6 and Table 2-7 See ldquoSerial ROM Boot Jumper (JP1)rdquo on page 2-12 and ldquoBoot Jumper (JP4)rdquo on page 2-14 for more information

Table 2-5 JP4 Settings for FPGA Programming in Master Serial Mode

JP4 Pin Name Pins Connected Jumper Setting

M0 JP41 and JP42 Populated

M1 JP43 and JP44 Populated

M2 JP45 and JP46 Populated

Table 2-6 JP1 Settings for FPGA Programming via Blackfin Processor

JP1 Pin Name Pins Connected Jumper Setting

Flash done JP11 and JP12 Unpopulated

2-6 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Hardware Reference

Programming the Serial ROMThe FPGA EZ-Extender allows the user to program the serial ROM The serial ROM can be programmed by using a Xilinx JTAG cable ISE soft-ware and the flash JTAG header on the FPGA EZ-Extender

Serial ROM via JTAG HeaderTo program the serial ROM via the JTAG header create the appropriate program file using the Xilinx software provided at wwwxilinxcom Once the program file is created use a Xilinx JTAG cable and connect it to P6 The P6 connections are shown in Table 2-8

Table 2-7 JP4 Settings for FPGA Programming via Blackfin Processor

JP4 Pin Name Pins Connected Jumper Setting

M0 JP41 and JP42 Unpopulated

M1 JP43 and JP44 Unpopulated

M2 JP45 and JP46 Unpopulated

Table 2-8 P6 Connections for Serial ROM

P6 Pin Number Signal Name P6 Pin Number Signal Name

1 33V 4 TDO

2 GND 5 TDI

3 TCK 6 TMS

Blackfin FPGA EZ-Extender Manual 2-7

Power

PowerThe FPGA EZ-Extender can be powered from the enclosed power supply EZ-KIT Lite or external power supply The power source for the extender is selected based on the power requirements of the application

An external 7V power supply is shipped with the extender board The power supply uses three switching regulators VR1 is used to power the 25V power plane VR2 is used to power the 12V power plane and VR3 is used to power the 33V plane All of the regulators can supply a maximum current of 2 Amps To understand the power requirements of your appli-cation run the Xilinx power estimator software The software can be located at wwwxilinxcom

Table 2-9 states the current limitations of each method Each method requires a correctly configured header described in the following sections

Table 2-9 Power Limitations

Power Source 12V Supply 25V Supply 33V Supply

ADSP-BF533 ADSP-BF537 or ADSP-BF561 EZ-KIT Lite

500 mA 500 mA 500 mA

FPGA EZ-Extender power supply1

1 Default setting

2A 2A 2A

External power supply 2A 2A 2A

2-8 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Hardware Reference

Power In Header (P12)The P12 header supplies the power to the on board 12V and the 25V reg-ulators The P42 and P43 headers supply the power to the external 12V and 25V planes as described in ldquo25V Header (P42)rdquo and ldquo12V Header (P43)rdquo on page 2-10

33V Header (P13)

When using an external power supply do not plug in the power supply shipped with the FPGA EZ-Extender This can seriously damage the board As an extra measure of precaution remove all jumpers from P12

Power Source P12 Setting

FPGA EZ-Extender power supply1

1 Default setting

Jumper on P121 and P122

ADSP-BF533 ADSP-BF537 or ADSP-BF561 EZ-KIT Lite 5V power supply

Jumper on P122 and P123

Power Source P13 Setting

ADSP-BF533 ADSP-BF537 or ADSP-BF561 EZ-KIT Lite 33V power supply

Jumper on P131 and P132

FPGA EZ-Extender power supply1

1 Default setting

Jumper on P132 and P133

External power supply No jumper connect supply to P132 and GND

Blackfin FPGA EZ-Extender Manual 2-9

Power

25V Header (P42)

When using an external power supply do not plug in the power supply shipped with the FPGA EZ-Extender This can seriously damage the board As an extra measure of precaution remove all jumpers from P12

12V Header (P43)

When using an external power supply do not plug in the power supply shipped with the FPGA EZ-Extender This can seriously damage the board As an extra measure of precaution remove all jumpers from P12

Power Source P42 Setting

FPGA EZ-Extender Power Supply1

1 Default setting

No Jumper

External power supply Connect P421 to external 25VConnect P422 to external GND

Power Source P43 Setting

FPGA EZ-Extender power supply1

1 Default setting

No Jumper

External power supply Connect P421 to external 25VConnect P422 to external GND

2-10 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Hardware Reference

JumpersBefore using the Blackfin FPGA EZ-Extender follow the steps in ldquoFPGA EZ-Extender Setuprdquo on page 1-1

Figure 2-3 shows the locations of all jumper headers A two-pin jumper can be placed on the respective jumper header for different functionality The following sections describe all possible jumper settings and associated functionality

Figure 2-3 Jumper Locations

Blackfin FPGA EZ-Extender Manual 2-11

Jumpers

Serial ROM Boot Jumper (JP1)By default the serial ROM boot jumper JP1 is unpopulated When unpopulated the FPGA EZ-Extender programs via the Blackfin processor or the Xilinx JTAG header

When JP1 is left populated the jumper connects the serial ROM chip enable pin to the done bit of the FPGA At power-up the done bit is driven low by the FPGA causing the FPGA to enable the serial ROM as a programming source After the FPGA is programmed the done bit is driven high by the FPGA causing the FPGA to drive high the chip enable pin of the serial ROM

Both JP1 and JP4 must be set up for correct FPGA programming ldquoBoot Jumper (JP4)rdquo on page 2-14 summarizes the JP4 settings Table 2-10 sum-marizes the JP1 settings See Table 2-4 on page 2-5 and Table 2-6 on page 2-6 for more information on JP1

Config Done Jumper (JP2) The configuration done jumper JP2 connects the done bit of the FPGA to the Blackfin processorrsquos PF3 flag pin of the ADSP-BF533 and ADSP-BF561 EZ-KIT Lites or PF14 flag pin of the ADSP-BF537 EZ-KIT

Table 2-10 JP1 Settings

Boot Source JP1 Setting

ADSP-BF533 ADSP-BF537 or ADSP-BF561 processor via VisualDSP++1

1 Default setting

Unpopulated

JTAG header Unpopulated

Serial ROM Populated

2-12 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Hardware Reference

Lite By default the jumper is populated and acts as a monitor for the done bit by the Blackfin processor (the bit indicates that the FPGA pro-gramming is complete)

Table 2-11 summarizes the jumper settings

Config Program Jumper (JP3) The configuration program jumper JP3 connects the program bit of the FPGA to the Blackfin processorrsquos flag pin By default JP3 is populated The jumper assures that the program bit is asserted by the Blackfin proces-sor to initiate the FPGA programming through VisualDSP++ software

Table 2-12 summarizes the jumper settings

Table 2-11 JP2 Settings

Functionality JP2 Setting

Done bit connected to Blackfin processorrsquos PF3 flag pin1

1 Default setting

Populated

Done bit disconnected from Blackfin processorrsquos PF3 flag pin

Unpopulated

Table 2-12 JP3 Settings

Functionality JP3 Setting

Program bit connected to the Blackfin processorrsquos flag pin1

1 Default setting

Populated

Program bit disconnected from the Blackfin proces-sorrsquos flag pin

Unpopulated

Blackfin FPGA EZ-Extender Manual 2-13

Jumpers

Boot Jumper (JP4) The boot jumper JP4 configures the FPGA mode pins (M[20]) Based on the jumper settings the FPGA is set to be programmed by the JTAG header serial ROM or Blackfin processor

Table 2-13 summarizes the jumper settings See Table 2-3 on page 2-5 for the JTAG header boot settings Table 2-5 on page 2-6 for the serial ROM boot settings and Table 2-7 on page 2-7 for the Blackfin processor boot settings

FPGA Input Jumpers (JP5) The FPGA input jumpers JP52ndash58 drive select FPGA nets to a logic 0 and can be used for any user logic that requires a steady state input You can set internal pull-ups on these nets in the FPGA and when a low is required populate the respective jumper

Table 2-14 summarizes the jumper settings

Table 2-13 JP4 Settings

Boot Source JP41 and JP42M0

JP43 and JP44M1

JP45 and JP46M2

ADSP-BF533ADSP-BF537 orADSP-BF561 processor1

1 Default setting

Unpopulated Unpopulated Unpopulated

JTAG header Unpopulated Populated Unpopulated

Serial ROM Populated Populated Populated

2-14 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Hardware Reference

Push Buttons and LEDsBefore using the Blackfin FPGA EZ-Extender follow the steps in ldquoFPGA EZ-Extender Setuprdquo on page 1-1

Figure 2-4 shows the locations of all push buttons and LEDs The follow-ing sections describe the associated functionality of all the push buttons and LEDs

Program Push Button (SW1)The program push button SW1 erases the contents of the FPGA The push button can be used as a hard resetmdashthe FPGA must be completely re-programmed once SW1 is de-pressed See ldquoProgramming the FPGArdquo on page 2-3 for more information

PB1 Push Button (SW3)The PB1 push button SW3 is a general-purpose input push button The switch with a connected debounce circuit eliminates the need to re-create it in the FPGA The push button connects to pin C11 of the FPGA

Table 2-14 JP5 Settings

Reference Designator FPGA Pin Number

JP52 Y3

JP54 Y2

JP56 U10

JP58 AB11

Blackfin FPGA EZ-Extender Manual 2-15

Push Buttons and LEDs

PB2 Push Button (SW4) The PB2 push button SW4 is a general-purpose input push button The switch does not have a connected debounce circuit you may need to cre-ate it in the FPGA if required by a specific application The push button connects to pin H5 of the FPGA

Figure 2-4 Push Button and LED Locations

2-16 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Hardware Reference

Status LEDs (LED1ndash8) Eight status LEDs LED1ndash8 connect to the FPGA and act as status flags in any application that requires it Table 2-15 shows the LEDFPGA connections

Power LED (LED9) The power LED LED9 connects to the 25V power supply and when lit signifies that the FPGA EZ-Extender is powered properly

Done LED (LED10) The done LED LED10 connects to the done pin of the FPGA At power-up the FPGA is blank and needs to be programmed When lit the LED indicates that the FPGA is programmed successfully

Table 2-15 Status LED (LED1ndash8) Settings

Reference Designator FPGA Pin Number

LED1 U11

LED2 W11

LED3 AB10

LED4 Y10

LED5 AB9

LED6 W9

LED7 AB8

LED8 V10

Blackfin FPGA EZ-Extender Manual 2-17

Connectors

ConnectorsBefore using the Blackfin FPGA EZ-Extender follow the steps in ldquoFPGA EZ-Extender Setuprdquo on page 1-1

This section describes the connector functionality and provides informa-tion about the mating connectors The connector locations are shown in Figure 2-5

Figure 2-5 Connector Locations

2-18 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Hardware Reference

Expansion Interface (P1ndash3 and J1ndash3) Connectors P1ndash3 of the expansion interface are used to plug in the EZ-Extender to the ADSP-BF533 ADSP-BF537 or ADSP-BF561 EZ-KIT Lite

Connectors J1ndash3 of the expansion interface are used to plug in another extender board such as the Blackfin USB-LAN EZ-Extender Your own custom board can be plugged into J1ndash3 as well

Plugging in another EZ-Extender or a customer board to the expansion interface can de-grade the overall system performance The extra overall load can cause the user to add wait states or slow down the system bus to get all of the boards to work properly

For the J1ndash3 and P1ndash3 connector availability and pricing contact Samtec

IDC Connectors (P8 P14 P16 and P17) The P8 P14 P16 and P17 connectors are standard 01rdquo IDC headers The connectors are in a 13 x 2 configuration and designed for signal probing bread boarding and other signal accesses

Part Description Manufacturer Part Number

90-position 005rdquo spacing SMT(J1 J2 J3)

Samtec SFC-145-T2-F-D-A

90-position 005rdquo spacing (P1 P2 P3)

Samtec TFC-145-32-F-D

Part Description Manufacturer Part Number

IDC13x2 01rdquo header Berg 54102-T08-13

Mating Connector

IDC 13x2 01rdquo plug Samtec SSW-113-01-T-D

Blackfin FPGA EZ-Extender Manual 2-19

Connectors

IDC Connectors (P5 and P7) The P5 and P7 connectors are standard 01rdquo IDC headers The connectors are in a 14 x 2 configuration and designed for signal probing bread boarding and other signal accesses

High-Speed Connector (P4) The high-speed connector P4 facilitates development of applications where use of the standard IDC connectors is complicated due to signal integrity issues

For the P4 connector and cable assembly availability and pricing contact Samtec

Part Description Manufacturer Part Number

IDC14x2 01rdquo header FCI 68737-428HLF

IDC14x2 01rdquo header Sullins GEC14DAAN

Mating Connector

IDC 14x2 01rdquo plug Samtec SSW-114-01-T-D

Part Description Manufacturer Part Number

QTS 25x2 high-speed connector Samtec QTS-025-01-F-D-A

Mating Connector

QSS 25x2 high-speed connector Samtec QSS-025-01-F-D-A

2-20 Blackfin FPGA EZ-Extender Manual

A BILL OF MATERIALS

The bill of materials corresponds to the board schematics on page B-1

Please check the latest schematics on the Analog Devices website httpwwwanalogcomProcessorsProcessorsDevelopmentToolstec

hnicalLibrarymanualsDevToolsIndexhtmlEvalua-

tion20Kit20Manuals

Blackfin FPGA EZ-Extender Manual A-1

1 FPGA EZ-EXTENDER INTERFACES

This chapter provides the setup procedures for both the Blackfin

Field-Programmable Gate Array (FPGA) EZ-Extender and EZ-KIT Lite (ADSP-BF533 ADSP-BF537 or ADSP-BF561) It also provides an over-view of the extender board

The information is presented in the following order

bull ldquoFPGA EZ-Extender Setuprdquo on page 1-1

bull ldquoFPGA Software and Firmwarerdquo on page 1-2

bull ldquoFPGA EZ-Extender Overviewrdquo on page 1-3

FPGA EZ-Extender SetupIt is very important to set up all of the components of the system contain-ing the FPGA EZ-Extender before applying power to that system The following procedure is recommended

Power your system when these steps are completed

1 Read the applicable design interface section in this chaptermdashthe text provides an overview of the capabilities of the EZ-Extender

2 Read ldquoSystem Architecturerdquo on page 2-2 to understand the physical connections of the extender board For detailed information refer to ldquoSchematics on page B-1rdquo

Blackfin FPGA EZ-Extender Manual 1-1

FPGA Software and Firmware

3 Remove any rubber feet attached to the EZ-KIT Lite if the feet cover the printed circuit board (PCB) mounting holes In place of the rubber feet install the four nylon feet and screws provided with the FPGA EZ-Extender Install the nylon feet in the mounting holes of the EZ-KIT Litersquos PCB Flip the EZ-KIT Lite upside down so that the three expansion headers (J1ndash3) are facing up

4 Set the switches and jumpers on the FPGA EZ-Extender board Use the block diagram in Figure 2-1 on page 2-2 in conjunction with ldquoJumpersrdquo on page 2-11

5 Set the switches and jumpers on the EZ-KIT Lite board If not already familiarize yourself with the documentation and schemat-ics of the EZ-KIT Lite (see ldquoRelated Documentsrdquo on page -xiv) Compare the expansion interface signals of the FPGA EZ-Extender board with the signals of the EZ-KIT Lite board to ensure there is no contention For example it may be necessary to disable other devices connected to the expansion interface of the processor and disable the push buttons on the EZ-KIT Lite

6 Install the FPGA EZ-Extender on the EZ-KIT Lite via the three-connector expansion interface Figure 1-1 shows how an FPGA EZ-Extender plugs onto an EZ-KIT Lite

7 Configure any other interfacing boards for example another EZ-Extender

FPGA Software and FirmwareFor information on the FPGA software refer to the FPGA Software Readmetxt file located in the hellipBlackfinEZ-KITsFPGA EZ-EXTENDER subdirectory of the VisualDSP++ installation directory

1-2 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Interfaces

FPGA EZ-Extender OverviewThe Blackfin FPGA EZ-Extender connects a Xilinxreg Spartan III Field-Programmable Gate Array (FPGA for short) to the ADSP-BF533 ADSP-BF537 or the ADSP-BF561 EZ-KIT Lite The FPGA connects to the Blackfin processor via the expansion interface

The extender board by default is powered by an external 7V power sup-ply provided with the product You can also power the FPGA EZ-Extender by the expansion interface of the EZ-KIT Lite or an external power supply An external supply must be used whenever application code exceeds the recommended core and IO power supported by the FPGA EZ-Extender For more information on the jumper and connector settings required to power the extender review ldquoPowerrdquo on page 2-8 as well as the schematics in Appendix C

Figure 1-1 FPGA EZ-Extender Setup

Blackfin FPGA EZ-Extender Manual 1-3

FPGA EZ-Extender Overview

The FPGA EZ-Extender contains 2 MB of asynchronous SRAM memory powered by a 33V supply The SRAM memory connects to banks 6 and 7 of the FPGA and can perform simple data storage instructions in applica-tion-specific code

The FPGA EZ-Extender includes a 25 MHz oscillator (U6) connected to the FPGA via the dedicated global clock 1 (GCLK1) pin facilitating devel-opment of applications that require a clock A second clock socket (U7) is left unpopulated to allow a user to place an oscillator with a specific fre-quency for the FPGA The second clock socket connects to the global clock 6 (GCLK6) pin of the FPGA

The extender has eight LEDs (LED1ndash8) and two push buttons (SW3ndash4) for applications that require status reporting and user control The push but-tons are active low and when pressed provide a logic 0 to the respective FPGA nets For inputs that require a permanent input low use the jumper inputs on JP4 When a jumper is populated on one of the four nets of JP4 the respective pin is hard wired to a logic 0 For more information about the LEDs push button switches and jumper inputs refer to ldquoFPGA EZ-Extender Hardware Referencerdquo on page 2-1

There are various ways to program the FPGA By default the FPGA is programmed in its slave serial mode by the flash programming utility in VisualDSP++ The program configures the FPGA using the Blackfin pro-cessorrsquos flag pins andor serial port pins For more information on how to use the flash programming utility within VisualDSP++ refer to the FPGA Software Readmetxt file located in the hellipBlackfinEZ-KITsFPGA EZ-EXTENDER subdirectory of the VisualDSP++ installation directory

A second method of programming the FPGA is by using a Xilinx JTAG cable and software The Xilinx JTAG cable connects to the FPGA JTAG header (P15) For more information about programming the FPGA via a Xilinx JTAG cable refer to the manufacturerrsquos website at wwwxilinxcom

1-4 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Interfaces

The third and final way to program the FPGA is via the Xilinx serial ROM on the FPGA EZ-Extender The serial ROM used for FPGA is shipped with the extender and is pre-programmed If the serial ROM needs to be re-programmed with new code use an Xilinx JTAG cable and software and connect the Xilinx JTAG cable to the flash JTAG header (P6)

More information about programming the serial ROM can be found at wwwxilinxcom More details about the different ways to program the FPGA can be found in ldquoFPGA EZ-Extender Hardware Referencerdquo on page 2-1

Blackfin FPGA EZ-Extender Manual 1-5

FPGA EZ-Extender Overview

1-6 Blackfin FPGA EZ-Extender Manual

2 FPGA EZ-EXTENDER HARDWARE REFERENCE

This chapter describes the hardware design of the Field-Programmable

Gate Array (FPGA) EZ-Extender

The following topics are covered

bull ldquoSystem Architecturerdquo on page 2-2Describes the configuration of the extender board and explains how the board components interface with the processor and EZ-KIT Lite

bull ldquoProgramming the FPGArdquo on page 2-3Describes the different methods of programming the FPGA

bull ldquoProgramming the Serial ROMrdquo on page 2-7Describes the method of programming the serial ROM

bull ldquoPowerrdquo on page 2-8Describes the methods to power the extender board

bull ldquoJumpersrdquo on page 2-11Describes the function of the configuration jumpers

bull ldquoPush Buttons and LEDsrdquo on page 2-15Describes the function of the push buttons and LEDs

bull ldquoConnectorsrdquo on page 2-18Describes the function of the extender connectors

Blackfin FPGA EZ-Extender Manual 2-1

System Architecture

System ArchitectureA block diagram of the Blackfin FPGA EZ-Extender is shown in Figure 2-1

Figure 2-1 Block Diagram

X ilin xS p a rta n 3

X C 3 S 1 0 0 0 -4 F G 4 5 6 C F P G A2 M B S R A M

(5 1 2 k x 3 2 -b its )

M e m o ry In te rfa c e

S P I S P O R T (2 x ) P P I(2 x ) G P IO

T im e rs T W I

P rim a ry E x p a n s io n In te rfa c e ( to B la c k F in E Z -K IT )

S e c o n d a ry E x p a n s io n In te rfa c e (to T e s t p o in ts a n d o th e r E Z -

E x te n d e rs )

P o w e r C o n n e c to r

R e g u la to rs

3 3 V 2 5 V 1 2 V

1 in c h h e a d e rs

2 5 M H z

O s c illa to r S o c k e t

L E D D IP S w itc h P u s h B u tto n s

S P I S P O R T (2 x ) P P I(2 x ) G P IO

T im e rs T W I

S e ria l F la s h

H ig h S p e e d C o n n e c to r

J T A G C o n n e c to r

J T A G C o n n e c to r

2-2 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Hardware Reference

Programming the FPGABefore using the Blackfin FPGA EZ-Extender follow the steps in ldquoFPGA EZ-Extender Setuprdquo on page 1-1

Figure 2-2 is a block diagram of the FPGA programming connections

Figure 2-2 FPGA Programming Block Diagram

Blackfin FPGA EZ-Extender Manual 2-3

Programming the FPGA

There are three ways to program the FPGA

bull Using the FPGA JTAG header as described in ldquoFPGA Program-ming via JTAGrdquo on page 2-4

bull Using the Xilinx serial ROM as described in ldquoFPGA Programming via Serial ROMrdquo on page 2-5

bull Using the Blackfin processor as described in ldquoFPGA Programming via Blackfin Applicationrdquo on page 2-6

The done LED (LED10) lights up once the FPGA is programmed signifying that the task is complete To erase the contents of the FPGA at any time de-press the program switch SW1

FPGA Programming via JTAGTo program the FPGA via the JTAG header create the appropriate pro-gram file using the Xilinx ISE software provided at wwwxilinxcom Once the program file is created use a Xilinx JTAG cable and connect it to P15 of the FPGA EZ-Extender (the P15 connections are shown in Table 2-1)

Table 2-1 P15 Connections for PFGA Programming via JTAG

P15 Pin Number Signal Name

1 33V

2 GND

3 TCK

4 TDO

5 TDI

6 TMS

2-4 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Hardware Reference

In addition to removing JP1 (serial ROM boot jumper) as shown in Table 2-2 set the boot jumper JP4 to JTAG mode The JP4 settings for JTAG boot are shown in Table 2-3 See ldquoBoot Jumper (JP4)rdquo on page 2-14 for more information

FPGA Programming via Serial ROMTo program the FPGA with the contents of the serial ROM populate the JP1 jumper When populated JP1 connects the chip enable pin of the serial ROM to the done bit of the FPGA Once the FPGA is programmed the done bit automatically goes high and the enable pin of the serial ROM chip becomes a logic 1 The JP1 settings for serial ROM boot are shown in Table 2-4 See ldquoProgramming the Serial ROMrdquo on page 2-7 for more information

The done LED (LED10) remains lit to signify that the FPGA is pro-grammed See ldquoDone LED (LED10)rdquo on page 2-17 for more information

Table 2-2 JP1 Settings for FPGA Programming via JTAG

JP1 Pin Name Pins Connected Jumper Setting

Flash done JP11 and JP12 Unpopulated

Table 2-3 JP4 Settings for FPGA Programming via JTAG

JP4 Pin Name Pins Connected Jumper Setting

M0 JP41 and JP42 Unpopulated

M1 JP43 and JP44 Populated

M2 JP45 and JP46 Unpopulated

Table 2-4 JP1 Settings for FPGA Programming via Serial ROM

JP1 Pin Name Pins Connected Jumper Setting

Flash done JP11 and JP12 Populated

Blackfin FPGA EZ-Extender Manual 2-5

Programming the FPGA

In addition to JP1 set the boot mode jumper JP4 to master serial mode The JP4 settings for serial ROM boot are shown in Table 2-5 See ldquoBoot Jumper (JP4)rdquo on page 2-14 for more information

FPGA Programming via Blackfin ApplicationBy default the FPGA EZ-Extender is configured by the flash program-ming utility within VisualDSP++ The software is located in the hellipBlackfinEZ-KITsFPGA EZ-EXTENDER subdirectory of the VisualDSP++ installation directory The FPGA Software Readmetxt file located in the same subdirectory provides all the necessary instructions required for run-ning the application

When generating a program file using the Xilinx software tools remember to generate a slave serial program file in the Intel MCS-86 Hexadecimal Object (mcs) file format

To boot the FPGA from the Blackfin processor unpopulate jumper JP1 and set jumper JP4 to slave serial mode as shown in Table 2-6 and Table 2-7 See ldquoSerial ROM Boot Jumper (JP1)rdquo on page 2-12 and ldquoBoot Jumper (JP4)rdquo on page 2-14 for more information

Table 2-5 JP4 Settings for FPGA Programming in Master Serial Mode

JP4 Pin Name Pins Connected Jumper Setting

M0 JP41 and JP42 Populated

M1 JP43 and JP44 Populated

M2 JP45 and JP46 Populated

Table 2-6 JP1 Settings for FPGA Programming via Blackfin Processor

JP1 Pin Name Pins Connected Jumper Setting

Flash done JP11 and JP12 Unpopulated

2-6 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Hardware Reference

Programming the Serial ROMThe FPGA EZ-Extender allows the user to program the serial ROM The serial ROM can be programmed by using a Xilinx JTAG cable ISE soft-ware and the flash JTAG header on the FPGA EZ-Extender

Serial ROM via JTAG HeaderTo program the serial ROM via the JTAG header create the appropriate program file using the Xilinx software provided at wwwxilinxcom Once the program file is created use a Xilinx JTAG cable and connect it to P6 The P6 connections are shown in Table 2-8

Table 2-7 JP4 Settings for FPGA Programming via Blackfin Processor

JP4 Pin Name Pins Connected Jumper Setting

M0 JP41 and JP42 Unpopulated

M1 JP43 and JP44 Unpopulated

M2 JP45 and JP46 Unpopulated

Table 2-8 P6 Connections for Serial ROM

P6 Pin Number Signal Name P6 Pin Number Signal Name

1 33V 4 TDO

2 GND 5 TDI

3 TCK 6 TMS

Blackfin FPGA EZ-Extender Manual 2-7

Power

PowerThe FPGA EZ-Extender can be powered from the enclosed power supply EZ-KIT Lite or external power supply The power source for the extender is selected based on the power requirements of the application

An external 7V power supply is shipped with the extender board The power supply uses three switching regulators VR1 is used to power the 25V power plane VR2 is used to power the 12V power plane and VR3 is used to power the 33V plane All of the regulators can supply a maximum current of 2 Amps To understand the power requirements of your appli-cation run the Xilinx power estimator software The software can be located at wwwxilinxcom

Table 2-9 states the current limitations of each method Each method requires a correctly configured header described in the following sections

Table 2-9 Power Limitations

Power Source 12V Supply 25V Supply 33V Supply

ADSP-BF533 ADSP-BF537 or ADSP-BF561 EZ-KIT Lite

500 mA 500 mA 500 mA

FPGA EZ-Extender power supply1

1 Default setting

2A 2A 2A

External power supply 2A 2A 2A

2-8 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Hardware Reference

Power In Header (P12)The P12 header supplies the power to the on board 12V and the 25V reg-ulators The P42 and P43 headers supply the power to the external 12V and 25V planes as described in ldquo25V Header (P42)rdquo and ldquo12V Header (P43)rdquo on page 2-10

33V Header (P13)

When using an external power supply do not plug in the power supply shipped with the FPGA EZ-Extender This can seriously damage the board As an extra measure of precaution remove all jumpers from P12

Power Source P12 Setting

FPGA EZ-Extender power supply1

1 Default setting

Jumper on P121 and P122

ADSP-BF533 ADSP-BF537 or ADSP-BF561 EZ-KIT Lite 5V power supply

Jumper on P122 and P123

Power Source P13 Setting

ADSP-BF533 ADSP-BF537 or ADSP-BF561 EZ-KIT Lite 33V power supply

Jumper on P131 and P132

FPGA EZ-Extender power supply1

1 Default setting

Jumper on P132 and P133

External power supply No jumper connect supply to P132 and GND

Blackfin FPGA EZ-Extender Manual 2-9

Power

25V Header (P42)

When using an external power supply do not plug in the power supply shipped with the FPGA EZ-Extender This can seriously damage the board As an extra measure of precaution remove all jumpers from P12

12V Header (P43)

When using an external power supply do not plug in the power supply shipped with the FPGA EZ-Extender This can seriously damage the board As an extra measure of precaution remove all jumpers from P12

Power Source P42 Setting

FPGA EZ-Extender Power Supply1

1 Default setting

No Jumper

External power supply Connect P421 to external 25VConnect P422 to external GND

Power Source P43 Setting

FPGA EZ-Extender power supply1

1 Default setting

No Jumper

External power supply Connect P421 to external 25VConnect P422 to external GND

2-10 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Hardware Reference

JumpersBefore using the Blackfin FPGA EZ-Extender follow the steps in ldquoFPGA EZ-Extender Setuprdquo on page 1-1

Figure 2-3 shows the locations of all jumper headers A two-pin jumper can be placed on the respective jumper header for different functionality The following sections describe all possible jumper settings and associated functionality

Figure 2-3 Jumper Locations

Blackfin FPGA EZ-Extender Manual 2-11

Jumpers

Serial ROM Boot Jumper (JP1)By default the serial ROM boot jumper JP1 is unpopulated When unpopulated the FPGA EZ-Extender programs via the Blackfin processor or the Xilinx JTAG header

When JP1 is left populated the jumper connects the serial ROM chip enable pin to the done bit of the FPGA At power-up the done bit is driven low by the FPGA causing the FPGA to enable the serial ROM as a programming source After the FPGA is programmed the done bit is driven high by the FPGA causing the FPGA to drive high the chip enable pin of the serial ROM

Both JP1 and JP4 must be set up for correct FPGA programming ldquoBoot Jumper (JP4)rdquo on page 2-14 summarizes the JP4 settings Table 2-10 sum-marizes the JP1 settings See Table 2-4 on page 2-5 and Table 2-6 on page 2-6 for more information on JP1

Config Done Jumper (JP2) The configuration done jumper JP2 connects the done bit of the FPGA to the Blackfin processorrsquos PF3 flag pin of the ADSP-BF533 and ADSP-BF561 EZ-KIT Lites or PF14 flag pin of the ADSP-BF537 EZ-KIT

Table 2-10 JP1 Settings

Boot Source JP1 Setting

ADSP-BF533 ADSP-BF537 or ADSP-BF561 processor via VisualDSP++1

1 Default setting

Unpopulated

JTAG header Unpopulated

Serial ROM Populated

2-12 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Hardware Reference

Lite By default the jumper is populated and acts as a monitor for the done bit by the Blackfin processor (the bit indicates that the FPGA pro-gramming is complete)

Table 2-11 summarizes the jumper settings

Config Program Jumper (JP3) The configuration program jumper JP3 connects the program bit of the FPGA to the Blackfin processorrsquos flag pin By default JP3 is populated The jumper assures that the program bit is asserted by the Blackfin proces-sor to initiate the FPGA programming through VisualDSP++ software

Table 2-12 summarizes the jumper settings

Table 2-11 JP2 Settings

Functionality JP2 Setting

Done bit connected to Blackfin processorrsquos PF3 flag pin1

1 Default setting

Populated

Done bit disconnected from Blackfin processorrsquos PF3 flag pin

Unpopulated

Table 2-12 JP3 Settings

Functionality JP3 Setting

Program bit connected to the Blackfin processorrsquos flag pin1

1 Default setting

Populated

Program bit disconnected from the Blackfin proces-sorrsquos flag pin

Unpopulated

Blackfin FPGA EZ-Extender Manual 2-13

Jumpers

Boot Jumper (JP4) The boot jumper JP4 configures the FPGA mode pins (M[20]) Based on the jumper settings the FPGA is set to be programmed by the JTAG header serial ROM or Blackfin processor

Table 2-13 summarizes the jumper settings See Table 2-3 on page 2-5 for the JTAG header boot settings Table 2-5 on page 2-6 for the serial ROM boot settings and Table 2-7 on page 2-7 for the Blackfin processor boot settings

FPGA Input Jumpers (JP5) The FPGA input jumpers JP52ndash58 drive select FPGA nets to a logic 0 and can be used for any user logic that requires a steady state input You can set internal pull-ups on these nets in the FPGA and when a low is required populate the respective jumper

Table 2-14 summarizes the jumper settings

Table 2-13 JP4 Settings

Boot Source JP41 and JP42M0

JP43 and JP44M1

JP45 and JP46M2

ADSP-BF533ADSP-BF537 orADSP-BF561 processor1

1 Default setting

Unpopulated Unpopulated Unpopulated

JTAG header Unpopulated Populated Unpopulated

Serial ROM Populated Populated Populated

2-14 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Hardware Reference

Push Buttons and LEDsBefore using the Blackfin FPGA EZ-Extender follow the steps in ldquoFPGA EZ-Extender Setuprdquo on page 1-1

Figure 2-4 shows the locations of all push buttons and LEDs The follow-ing sections describe the associated functionality of all the push buttons and LEDs

Program Push Button (SW1)The program push button SW1 erases the contents of the FPGA The push button can be used as a hard resetmdashthe FPGA must be completely re-programmed once SW1 is de-pressed See ldquoProgramming the FPGArdquo on page 2-3 for more information

PB1 Push Button (SW3)The PB1 push button SW3 is a general-purpose input push button The switch with a connected debounce circuit eliminates the need to re-create it in the FPGA The push button connects to pin C11 of the FPGA

Table 2-14 JP5 Settings

Reference Designator FPGA Pin Number

JP52 Y3

JP54 Y2

JP56 U10

JP58 AB11

Blackfin FPGA EZ-Extender Manual 2-15

Push Buttons and LEDs

PB2 Push Button (SW4) The PB2 push button SW4 is a general-purpose input push button The switch does not have a connected debounce circuit you may need to cre-ate it in the FPGA if required by a specific application The push button connects to pin H5 of the FPGA

Figure 2-4 Push Button and LED Locations

2-16 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Hardware Reference

Status LEDs (LED1ndash8) Eight status LEDs LED1ndash8 connect to the FPGA and act as status flags in any application that requires it Table 2-15 shows the LEDFPGA connections

Power LED (LED9) The power LED LED9 connects to the 25V power supply and when lit signifies that the FPGA EZ-Extender is powered properly

Done LED (LED10) The done LED LED10 connects to the done pin of the FPGA At power-up the FPGA is blank and needs to be programmed When lit the LED indicates that the FPGA is programmed successfully

Table 2-15 Status LED (LED1ndash8) Settings

Reference Designator FPGA Pin Number

LED1 U11

LED2 W11

LED3 AB10

LED4 Y10

LED5 AB9

LED6 W9

LED7 AB8

LED8 V10

Blackfin FPGA EZ-Extender Manual 2-17

Connectors

ConnectorsBefore using the Blackfin FPGA EZ-Extender follow the steps in ldquoFPGA EZ-Extender Setuprdquo on page 1-1

This section describes the connector functionality and provides informa-tion about the mating connectors The connector locations are shown in Figure 2-5

Figure 2-5 Connector Locations

2-18 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Hardware Reference

Expansion Interface (P1ndash3 and J1ndash3) Connectors P1ndash3 of the expansion interface are used to plug in the EZ-Extender to the ADSP-BF533 ADSP-BF537 or ADSP-BF561 EZ-KIT Lite

Connectors J1ndash3 of the expansion interface are used to plug in another extender board such as the Blackfin USB-LAN EZ-Extender Your own custom board can be plugged into J1ndash3 as well

Plugging in another EZ-Extender or a customer board to the expansion interface can de-grade the overall system performance The extra overall load can cause the user to add wait states or slow down the system bus to get all of the boards to work properly

For the J1ndash3 and P1ndash3 connector availability and pricing contact Samtec

IDC Connectors (P8 P14 P16 and P17) The P8 P14 P16 and P17 connectors are standard 01rdquo IDC headers The connectors are in a 13 x 2 configuration and designed for signal probing bread boarding and other signal accesses

Part Description Manufacturer Part Number

90-position 005rdquo spacing SMT(J1 J2 J3)

Samtec SFC-145-T2-F-D-A

90-position 005rdquo spacing (P1 P2 P3)

Samtec TFC-145-32-F-D

Part Description Manufacturer Part Number

IDC13x2 01rdquo header Berg 54102-T08-13

Mating Connector

IDC 13x2 01rdquo plug Samtec SSW-113-01-T-D

Blackfin FPGA EZ-Extender Manual 2-19

Connectors

IDC Connectors (P5 and P7) The P5 and P7 connectors are standard 01rdquo IDC headers The connectors are in a 14 x 2 configuration and designed for signal probing bread boarding and other signal accesses

High-Speed Connector (P4) The high-speed connector P4 facilitates development of applications where use of the standard IDC connectors is complicated due to signal integrity issues

For the P4 connector and cable assembly availability and pricing contact Samtec

Part Description Manufacturer Part Number

IDC14x2 01rdquo header FCI 68737-428HLF

IDC14x2 01rdquo header Sullins GEC14DAAN

Mating Connector

IDC 14x2 01rdquo plug Samtec SSW-114-01-T-D

Part Description Manufacturer Part Number

QTS 25x2 high-speed connector Samtec QTS-025-01-F-D-A

Mating Connector

QSS 25x2 high-speed connector Samtec QSS-025-01-F-D-A

2-20 Blackfin FPGA EZ-Extender Manual

A BILL OF MATERIALS

The bill of materials corresponds to the board schematics on page B-1

Please check the latest schematics on the Analog Devices website httpwwwanalogcomProcessorsProcessorsDevelopmentToolstec

hnicalLibrarymanualsDevToolsIndexhtmlEvalua-

tion20Kit20Manuals

Blackfin FPGA EZ-Extender Manual A-1

FPGA Software and Firmware

3 Remove any rubber feet attached to the EZ-KIT Lite if the feet cover the printed circuit board (PCB) mounting holes In place of the rubber feet install the four nylon feet and screws provided with the FPGA EZ-Extender Install the nylon feet in the mounting holes of the EZ-KIT Litersquos PCB Flip the EZ-KIT Lite upside down so that the three expansion headers (J1ndash3) are facing up

4 Set the switches and jumpers on the FPGA EZ-Extender board Use the block diagram in Figure 2-1 on page 2-2 in conjunction with ldquoJumpersrdquo on page 2-11

5 Set the switches and jumpers on the EZ-KIT Lite board If not already familiarize yourself with the documentation and schemat-ics of the EZ-KIT Lite (see ldquoRelated Documentsrdquo on page -xiv) Compare the expansion interface signals of the FPGA EZ-Extender board with the signals of the EZ-KIT Lite board to ensure there is no contention For example it may be necessary to disable other devices connected to the expansion interface of the processor and disable the push buttons on the EZ-KIT Lite

6 Install the FPGA EZ-Extender on the EZ-KIT Lite via the three-connector expansion interface Figure 1-1 shows how an FPGA EZ-Extender plugs onto an EZ-KIT Lite

7 Configure any other interfacing boards for example another EZ-Extender

FPGA Software and FirmwareFor information on the FPGA software refer to the FPGA Software Readmetxt file located in the hellipBlackfinEZ-KITsFPGA EZ-EXTENDER subdirectory of the VisualDSP++ installation directory

1-2 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Interfaces

FPGA EZ-Extender OverviewThe Blackfin FPGA EZ-Extender connects a Xilinxreg Spartan III Field-Programmable Gate Array (FPGA for short) to the ADSP-BF533 ADSP-BF537 or the ADSP-BF561 EZ-KIT Lite The FPGA connects to the Blackfin processor via the expansion interface

The extender board by default is powered by an external 7V power sup-ply provided with the product You can also power the FPGA EZ-Extender by the expansion interface of the EZ-KIT Lite or an external power supply An external supply must be used whenever application code exceeds the recommended core and IO power supported by the FPGA EZ-Extender For more information on the jumper and connector settings required to power the extender review ldquoPowerrdquo on page 2-8 as well as the schematics in Appendix C

Figure 1-1 FPGA EZ-Extender Setup

Blackfin FPGA EZ-Extender Manual 1-3

FPGA EZ-Extender Overview

The FPGA EZ-Extender contains 2 MB of asynchronous SRAM memory powered by a 33V supply The SRAM memory connects to banks 6 and 7 of the FPGA and can perform simple data storage instructions in applica-tion-specific code

The FPGA EZ-Extender includes a 25 MHz oscillator (U6) connected to the FPGA via the dedicated global clock 1 (GCLK1) pin facilitating devel-opment of applications that require a clock A second clock socket (U7) is left unpopulated to allow a user to place an oscillator with a specific fre-quency for the FPGA The second clock socket connects to the global clock 6 (GCLK6) pin of the FPGA

The extender has eight LEDs (LED1ndash8) and two push buttons (SW3ndash4) for applications that require status reporting and user control The push but-tons are active low and when pressed provide a logic 0 to the respective FPGA nets For inputs that require a permanent input low use the jumper inputs on JP4 When a jumper is populated on one of the four nets of JP4 the respective pin is hard wired to a logic 0 For more information about the LEDs push button switches and jumper inputs refer to ldquoFPGA EZ-Extender Hardware Referencerdquo on page 2-1

There are various ways to program the FPGA By default the FPGA is programmed in its slave serial mode by the flash programming utility in VisualDSP++ The program configures the FPGA using the Blackfin pro-cessorrsquos flag pins andor serial port pins For more information on how to use the flash programming utility within VisualDSP++ refer to the FPGA Software Readmetxt file located in the hellipBlackfinEZ-KITsFPGA EZ-EXTENDER subdirectory of the VisualDSP++ installation directory

A second method of programming the FPGA is by using a Xilinx JTAG cable and software The Xilinx JTAG cable connects to the FPGA JTAG header (P15) For more information about programming the FPGA via a Xilinx JTAG cable refer to the manufacturerrsquos website at wwwxilinxcom

1-4 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Interfaces

The third and final way to program the FPGA is via the Xilinx serial ROM on the FPGA EZ-Extender The serial ROM used for FPGA is shipped with the extender and is pre-programmed If the serial ROM needs to be re-programmed with new code use an Xilinx JTAG cable and software and connect the Xilinx JTAG cable to the flash JTAG header (P6)

More information about programming the serial ROM can be found at wwwxilinxcom More details about the different ways to program the FPGA can be found in ldquoFPGA EZ-Extender Hardware Referencerdquo on page 2-1

Blackfin FPGA EZ-Extender Manual 1-5

FPGA EZ-Extender Overview

1-6 Blackfin FPGA EZ-Extender Manual

2 FPGA EZ-EXTENDER HARDWARE REFERENCE

This chapter describes the hardware design of the Field-Programmable

Gate Array (FPGA) EZ-Extender

The following topics are covered

bull ldquoSystem Architecturerdquo on page 2-2Describes the configuration of the extender board and explains how the board components interface with the processor and EZ-KIT Lite

bull ldquoProgramming the FPGArdquo on page 2-3Describes the different methods of programming the FPGA

bull ldquoProgramming the Serial ROMrdquo on page 2-7Describes the method of programming the serial ROM

bull ldquoPowerrdquo on page 2-8Describes the methods to power the extender board

bull ldquoJumpersrdquo on page 2-11Describes the function of the configuration jumpers

bull ldquoPush Buttons and LEDsrdquo on page 2-15Describes the function of the push buttons and LEDs

bull ldquoConnectorsrdquo on page 2-18Describes the function of the extender connectors

Blackfin FPGA EZ-Extender Manual 2-1

System Architecture

System ArchitectureA block diagram of the Blackfin FPGA EZ-Extender is shown in Figure 2-1

Figure 2-1 Block Diagram

X ilin xS p a rta n 3

X C 3 S 1 0 0 0 -4 F G 4 5 6 C F P G A2 M B S R A M

(5 1 2 k x 3 2 -b its )

M e m o ry In te rfa c e

S P I S P O R T (2 x ) P P I(2 x ) G P IO

T im e rs T W I

P rim a ry E x p a n s io n In te rfa c e ( to B la c k F in E Z -K IT )

S e c o n d a ry E x p a n s io n In te rfa c e (to T e s t p o in ts a n d o th e r E Z -

E x te n d e rs )

P o w e r C o n n e c to r

R e g u la to rs

3 3 V 2 5 V 1 2 V

1 in c h h e a d e rs

2 5 M H z

O s c illa to r S o c k e t

L E D D IP S w itc h P u s h B u tto n s

S P I S P O R T (2 x ) P P I(2 x ) G P IO

T im e rs T W I

S e ria l F la s h

H ig h S p e e d C o n n e c to r

J T A G C o n n e c to r

J T A G C o n n e c to r

2-2 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Hardware Reference

Programming the FPGABefore using the Blackfin FPGA EZ-Extender follow the steps in ldquoFPGA EZ-Extender Setuprdquo on page 1-1

Figure 2-2 is a block diagram of the FPGA programming connections

Figure 2-2 FPGA Programming Block Diagram

Blackfin FPGA EZ-Extender Manual 2-3

Programming the FPGA

There are three ways to program the FPGA

bull Using the FPGA JTAG header as described in ldquoFPGA Program-ming via JTAGrdquo on page 2-4

bull Using the Xilinx serial ROM as described in ldquoFPGA Programming via Serial ROMrdquo on page 2-5

bull Using the Blackfin processor as described in ldquoFPGA Programming via Blackfin Applicationrdquo on page 2-6

The done LED (LED10) lights up once the FPGA is programmed signifying that the task is complete To erase the contents of the FPGA at any time de-press the program switch SW1

FPGA Programming via JTAGTo program the FPGA via the JTAG header create the appropriate pro-gram file using the Xilinx ISE software provided at wwwxilinxcom Once the program file is created use a Xilinx JTAG cable and connect it to P15 of the FPGA EZ-Extender (the P15 connections are shown in Table 2-1)

Table 2-1 P15 Connections for PFGA Programming via JTAG

P15 Pin Number Signal Name

1 33V

2 GND

3 TCK

4 TDO

5 TDI

6 TMS

2-4 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Hardware Reference

In addition to removing JP1 (serial ROM boot jumper) as shown in Table 2-2 set the boot jumper JP4 to JTAG mode The JP4 settings for JTAG boot are shown in Table 2-3 See ldquoBoot Jumper (JP4)rdquo on page 2-14 for more information

FPGA Programming via Serial ROMTo program the FPGA with the contents of the serial ROM populate the JP1 jumper When populated JP1 connects the chip enable pin of the serial ROM to the done bit of the FPGA Once the FPGA is programmed the done bit automatically goes high and the enable pin of the serial ROM chip becomes a logic 1 The JP1 settings for serial ROM boot are shown in Table 2-4 See ldquoProgramming the Serial ROMrdquo on page 2-7 for more information

The done LED (LED10) remains lit to signify that the FPGA is pro-grammed See ldquoDone LED (LED10)rdquo on page 2-17 for more information

Table 2-2 JP1 Settings for FPGA Programming via JTAG

JP1 Pin Name Pins Connected Jumper Setting

Flash done JP11 and JP12 Unpopulated

Table 2-3 JP4 Settings for FPGA Programming via JTAG

JP4 Pin Name Pins Connected Jumper Setting

M0 JP41 and JP42 Unpopulated

M1 JP43 and JP44 Populated

M2 JP45 and JP46 Unpopulated

Table 2-4 JP1 Settings for FPGA Programming via Serial ROM

JP1 Pin Name Pins Connected Jumper Setting

Flash done JP11 and JP12 Populated

Blackfin FPGA EZ-Extender Manual 2-5

Programming the FPGA

In addition to JP1 set the boot mode jumper JP4 to master serial mode The JP4 settings for serial ROM boot are shown in Table 2-5 See ldquoBoot Jumper (JP4)rdquo on page 2-14 for more information

FPGA Programming via Blackfin ApplicationBy default the FPGA EZ-Extender is configured by the flash program-ming utility within VisualDSP++ The software is located in the hellipBlackfinEZ-KITsFPGA EZ-EXTENDER subdirectory of the VisualDSP++ installation directory The FPGA Software Readmetxt file located in the same subdirectory provides all the necessary instructions required for run-ning the application

When generating a program file using the Xilinx software tools remember to generate a slave serial program file in the Intel MCS-86 Hexadecimal Object (mcs) file format

To boot the FPGA from the Blackfin processor unpopulate jumper JP1 and set jumper JP4 to slave serial mode as shown in Table 2-6 and Table 2-7 See ldquoSerial ROM Boot Jumper (JP1)rdquo on page 2-12 and ldquoBoot Jumper (JP4)rdquo on page 2-14 for more information

Table 2-5 JP4 Settings for FPGA Programming in Master Serial Mode

JP4 Pin Name Pins Connected Jumper Setting

M0 JP41 and JP42 Populated

M1 JP43 and JP44 Populated

M2 JP45 and JP46 Populated

Table 2-6 JP1 Settings for FPGA Programming via Blackfin Processor

JP1 Pin Name Pins Connected Jumper Setting

Flash done JP11 and JP12 Unpopulated

2-6 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Hardware Reference

Programming the Serial ROMThe FPGA EZ-Extender allows the user to program the serial ROM The serial ROM can be programmed by using a Xilinx JTAG cable ISE soft-ware and the flash JTAG header on the FPGA EZ-Extender

Serial ROM via JTAG HeaderTo program the serial ROM via the JTAG header create the appropriate program file using the Xilinx software provided at wwwxilinxcom Once the program file is created use a Xilinx JTAG cable and connect it to P6 The P6 connections are shown in Table 2-8

Table 2-7 JP4 Settings for FPGA Programming via Blackfin Processor

JP4 Pin Name Pins Connected Jumper Setting

M0 JP41 and JP42 Unpopulated

M1 JP43 and JP44 Unpopulated

M2 JP45 and JP46 Unpopulated

Table 2-8 P6 Connections for Serial ROM

P6 Pin Number Signal Name P6 Pin Number Signal Name

1 33V 4 TDO

2 GND 5 TDI

3 TCK 6 TMS

Blackfin FPGA EZ-Extender Manual 2-7

Power

PowerThe FPGA EZ-Extender can be powered from the enclosed power supply EZ-KIT Lite or external power supply The power source for the extender is selected based on the power requirements of the application

An external 7V power supply is shipped with the extender board The power supply uses three switching regulators VR1 is used to power the 25V power plane VR2 is used to power the 12V power plane and VR3 is used to power the 33V plane All of the regulators can supply a maximum current of 2 Amps To understand the power requirements of your appli-cation run the Xilinx power estimator software The software can be located at wwwxilinxcom

Table 2-9 states the current limitations of each method Each method requires a correctly configured header described in the following sections

Table 2-9 Power Limitations

Power Source 12V Supply 25V Supply 33V Supply

ADSP-BF533 ADSP-BF537 or ADSP-BF561 EZ-KIT Lite

500 mA 500 mA 500 mA

FPGA EZ-Extender power supply1

1 Default setting

2A 2A 2A

External power supply 2A 2A 2A

2-8 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Hardware Reference

Power In Header (P12)The P12 header supplies the power to the on board 12V and the 25V reg-ulators The P42 and P43 headers supply the power to the external 12V and 25V planes as described in ldquo25V Header (P42)rdquo and ldquo12V Header (P43)rdquo on page 2-10

33V Header (P13)

When using an external power supply do not plug in the power supply shipped with the FPGA EZ-Extender This can seriously damage the board As an extra measure of precaution remove all jumpers from P12

Power Source P12 Setting

FPGA EZ-Extender power supply1

1 Default setting

Jumper on P121 and P122

ADSP-BF533 ADSP-BF537 or ADSP-BF561 EZ-KIT Lite 5V power supply

Jumper on P122 and P123

Power Source P13 Setting

ADSP-BF533 ADSP-BF537 or ADSP-BF561 EZ-KIT Lite 33V power supply

Jumper on P131 and P132

FPGA EZ-Extender power supply1

1 Default setting

Jumper on P132 and P133

External power supply No jumper connect supply to P132 and GND

Blackfin FPGA EZ-Extender Manual 2-9

Power

25V Header (P42)

When using an external power supply do not plug in the power supply shipped with the FPGA EZ-Extender This can seriously damage the board As an extra measure of precaution remove all jumpers from P12

12V Header (P43)

When using an external power supply do not plug in the power supply shipped with the FPGA EZ-Extender This can seriously damage the board As an extra measure of precaution remove all jumpers from P12

Power Source P42 Setting

FPGA EZ-Extender Power Supply1

1 Default setting

No Jumper

External power supply Connect P421 to external 25VConnect P422 to external GND

Power Source P43 Setting

FPGA EZ-Extender power supply1

1 Default setting

No Jumper

External power supply Connect P421 to external 25VConnect P422 to external GND

2-10 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Hardware Reference

JumpersBefore using the Blackfin FPGA EZ-Extender follow the steps in ldquoFPGA EZ-Extender Setuprdquo on page 1-1

Figure 2-3 shows the locations of all jumper headers A two-pin jumper can be placed on the respective jumper header for different functionality The following sections describe all possible jumper settings and associated functionality

Figure 2-3 Jumper Locations

Blackfin FPGA EZ-Extender Manual 2-11

Jumpers

Serial ROM Boot Jumper (JP1)By default the serial ROM boot jumper JP1 is unpopulated When unpopulated the FPGA EZ-Extender programs via the Blackfin processor or the Xilinx JTAG header

When JP1 is left populated the jumper connects the serial ROM chip enable pin to the done bit of the FPGA At power-up the done bit is driven low by the FPGA causing the FPGA to enable the serial ROM as a programming source After the FPGA is programmed the done bit is driven high by the FPGA causing the FPGA to drive high the chip enable pin of the serial ROM

Both JP1 and JP4 must be set up for correct FPGA programming ldquoBoot Jumper (JP4)rdquo on page 2-14 summarizes the JP4 settings Table 2-10 sum-marizes the JP1 settings See Table 2-4 on page 2-5 and Table 2-6 on page 2-6 for more information on JP1

Config Done Jumper (JP2) The configuration done jumper JP2 connects the done bit of the FPGA to the Blackfin processorrsquos PF3 flag pin of the ADSP-BF533 and ADSP-BF561 EZ-KIT Lites or PF14 flag pin of the ADSP-BF537 EZ-KIT

Table 2-10 JP1 Settings

Boot Source JP1 Setting

ADSP-BF533 ADSP-BF537 or ADSP-BF561 processor via VisualDSP++1

1 Default setting

Unpopulated

JTAG header Unpopulated

Serial ROM Populated

2-12 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Hardware Reference

Lite By default the jumper is populated and acts as a monitor for the done bit by the Blackfin processor (the bit indicates that the FPGA pro-gramming is complete)

Table 2-11 summarizes the jumper settings

Config Program Jumper (JP3) The configuration program jumper JP3 connects the program bit of the FPGA to the Blackfin processorrsquos flag pin By default JP3 is populated The jumper assures that the program bit is asserted by the Blackfin proces-sor to initiate the FPGA programming through VisualDSP++ software

Table 2-12 summarizes the jumper settings

Table 2-11 JP2 Settings

Functionality JP2 Setting

Done bit connected to Blackfin processorrsquos PF3 flag pin1

1 Default setting

Populated

Done bit disconnected from Blackfin processorrsquos PF3 flag pin

Unpopulated

Table 2-12 JP3 Settings

Functionality JP3 Setting

Program bit connected to the Blackfin processorrsquos flag pin1

1 Default setting

Populated

Program bit disconnected from the Blackfin proces-sorrsquos flag pin

Unpopulated

Blackfin FPGA EZ-Extender Manual 2-13

Jumpers

Boot Jumper (JP4) The boot jumper JP4 configures the FPGA mode pins (M[20]) Based on the jumper settings the FPGA is set to be programmed by the JTAG header serial ROM or Blackfin processor

Table 2-13 summarizes the jumper settings See Table 2-3 on page 2-5 for the JTAG header boot settings Table 2-5 on page 2-6 for the serial ROM boot settings and Table 2-7 on page 2-7 for the Blackfin processor boot settings

FPGA Input Jumpers (JP5) The FPGA input jumpers JP52ndash58 drive select FPGA nets to a logic 0 and can be used for any user logic that requires a steady state input You can set internal pull-ups on these nets in the FPGA and when a low is required populate the respective jumper

Table 2-14 summarizes the jumper settings

Table 2-13 JP4 Settings

Boot Source JP41 and JP42M0

JP43 and JP44M1

JP45 and JP46M2

ADSP-BF533ADSP-BF537 orADSP-BF561 processor1

1 Default setting

Unpopulated Unpopulated Unpopulated

JTAG header Unpopulated Populated Unpopulated

Serial ROM Populated Populated Populated

2-14 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Hardware Reference

Push Buttons and LEDsBefore using the Blackfin FPGA EZ-Extender follow the steps in ldquoFPGA EZ-Extender Setuprdquo on page 1-1

Figure 2-4 shows the locations of all push buttons and LEDs The follow-ing sections describe the associated functionality of all the push buttons and LEDs

Program Push Button (SW1)The program push button SW1 erases the contents of the FPGA The push button can be used as a hard resetmdashthe FPGA must be completely re-programmed once SW1 is de-pressed See ldquoProgramming the FPGArdquo on page 2-3 for more information

PB1 Push Button (SW3)The PB1 push button SW3 is a general-purpose input push button The switch with a connected debounce circuit eliminates the need to re-create it in the FPGA The push button connects to pin C11 of the FPGA

Table 2-14 JP5 Settings

Reference Designator FPGA Pin Number

JP52 Y3

JP54 Y2

JP56 U10

JP58 AB11

Blackfin FPGA EZ-Extender Manual 2-15

Push Buttons and LEDs

PB2 Push Button (SW4) The PB2 push button SW4 is a general-purpose input push button The switch does not have a connected debounce circuit you may need to cre-ate it in the FPGA if required by a specific application The push button connects to pin H5 of the FPGA

Figure 2-4 Push Button and LED Locations

2-16 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Hardware Reference

Status LEDs (LED1ndash8) Eight status LEDs LED1ndash8 connect to the FPGA and act as status flags in any application that requires it Table 2-15 shows the LEDFPGA connections

Power LED (LED9) The power LED LED9 connects to the 25V power supply and when lit signifies that the FPGA EZ-Extender is powered properly

Done LED (LED10) The done LED LED10 connects to the done pin of the FPGA At power-up the FPGA is blank and needs to be programmed When lit the LED indicates that the FPGA is programmed successfully

Table 2-15 Status LED (LED1ndash8) Settings

Reference Designator FPGA Pin Number

LED1 U11

LED2 W11

LED3 AB10

LED4 Y10

LED5 AB9

LED6 W9

LED7 AB8

LED8 V10

Blackfin FPGA EZ-Extender Manual 2-17

Connectors

ConnectorsBefore using the Blackfin FPGA EZ-Extender follow the steps in ldquoFPGA EZ-Extender Setuprdquo on page 1-1

This section describes the connector functionality and provides informa-tion about the mating connectors The connector locations are shown in Figure 2-5

Figure 2-5 Connector Locations

2-18 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Hardware Reference

Expansion Interface (P1ndash3 and J1ndash3) Connectors P1ndash3 of the expansion interface are used to plug in the EZ-Extender to the ADSP-BF533 ADSP-BF537 or ADSP-BF561 EZ-KIT Lite

Connectors J1ndash3 of the expansion interface are used to plug in another extender board such as the Blackfin USB-LAN EZ-Extender Your own custom board can be plugged into J1ndash3 as well

Plugging in another EZ-Extender or a customer board to the expansion interface can de-grade the overall system performance The extra overall load can cause the user to add wait states or slow down the system bus to get all of the boards to work properly

For the J1ndash3 and P1ndash3 connector availability and pricing contact Samtec

IDC Connectors (P8 P14 P16 and P17) The P8 P14 P16 and P17 connectors are standard 01rdquo IDC headers The connectors are in a 13 x 2 configuration and designed for signal probing bread boarding and other signal accesses

Part Description Manufacturer Part Number

90-position 005rdquo spacing SMT(J1 J2 J3)

Samtec SFC-145-T2-F-D-A

90-position 005rdquo spacing (P1 P2 P3)

Samtec TFC-145-32-F-D

Part Description Manufacturer Part Number

IDC13x2 01rdquo header Berg 54102-T08-13

Mating Connector

IDC 13x2 01rdquo plug Samtec SSW-113-01-T-D

Blackfin FPGA EZ-Extender Manual 2-19

Connectors

IDC Connectors (P5 and P7) The P5 and P7 connectors are standard 01rdquo IDC headers The connectors are in a 14 x 2 configuration and designed for signal probing bread boarding and other signal accesses

High-Speed Connector (P4) The high-speed connector P4 facilitates development of applications where use of the standard IDC connectors is complicated due to signal integrity issues

For the P4 connector and cable assembly availability and pricing contact Samtec

Part Description Manufacturer Part Number

IDC14x2 01rdquo header FCI 68737-428HLF

IDC14x2 01rdquo header Sullins GEC14DAAN

Mating Connector

IDC 14x2 01rdquo plug Samtec SSW-114-01-T-D

Part Description Manufacturer Part Number

QTS 25x2 high-speed connector Samtec QTS-025-01-F-D-A

Mating Connector

QSS 25x2 high-speed connector Samtec QSS-025-01-F-D-A

2-20 Blackfin FPGA EZ-Extender Manual

A BILL OF MATERIALS

The bill of materials corresponds to the board schematics on page B-1

Please check the latest schematics on the Analog Devices website httpwwwanalogcomProcessorsProcessorsDevelopmentToolstec

hnicalLibrarymanualsDevToolsIndexhtmlEvalua-

tion20Kit20Manuals

Blackfin FPGA EZ-Extender Manual A-1

FPGA EZ-Extender Interfaces

FPGA EZ-Extender OverviewThe Blackfin FPGA EZ-Extender connects a Xilinxreg Spartan III Field-Programmable Gate Array (FPGA for short) to the ADSP-BF533 ADSP-BF537 or the ADSP-BF561 EZ-KIT Lite The FPGA connects to the Blackfin processor via the expansion interface

The extender board by default is powered by an external 7V power sup-ply provided with the product You can also power the FPGA EZ-Extender by the expansion interface of the EZ-KIT Lite or an external power supply An external supply must be used whenever application code exceeds the recommended core and IO power supported by the FPGA EZ-Extender For more information on the jumper and connector settings required to power the extender review ldquoPowerrdquo on page 2-8 as well as the schematics in Appendix C

Figure 1-1 FPGA EZ-Extender Setup

Blackfin FPGA EZ-Extender Manual 1-3

FPGA EZ-Extender Overview

The FPGA EZ-Extender contains 2 MB of asynchronous SRAM memory powered by a 33V supply The SRAM memory connects to banks 6 and 7 of the FPGA and can perform simple data storage instructions in applica-tion-specific code

The FPGA EZ-Extender includes a 25 MHz oscillator (U6) connected to the FPGA via the dedicated global clock 1 (GCLK1) pin facilitating devel-opment of applications that require a clock A second clock socket (U7) is left unpopulated to allow a user to place an oscillator with a specific fre-quency for the FPGA The second clock socket connects to the global clock 6 (GCLK6) pin of the FPGA

The extender has eight LEDs (LED1ndash8) and two push buttons (SW3ndash4) for applications that require status reporting and user control The push but-tons are active low and when pressed provide a logic 0 to the respective FPGA nets For inputs that require a permanent input low use the jumper inputs on JP4 When a jumper is populated on one of the four nets of JP4 the respective pin is hard wired to a logic 0 For more information about the LEDs push button switches and jumper inputs refer to ldquoFPGA EZ-Extender Hardware Referencerdquo on page 2-1

There are various ways to program the FPGA By default the FPGA is programmed in its slave serial mode by the flash programming utility in VisualDSP++ The program configures the FPGA using the Blackfin pro-cessorrsquos flag pins andor serial port pins For more information on how to use the flash programming utility within VisualDSP++ refer to the FPGA Software Readmetxt file located in the hellipBlackfinEZ-KITsFPGA EZ-EXTENDER subdirectory of the VisualDSP++ installation directory

A second method of programming the FPGA is by using a Xilinx JTAG cable and software The Xilinx JTAG cable connects to the FPGA JTAG header (P15) For more information about programming the FPGA via a Xilinx JTAG cable refer to the manufacturerrsquos website at wwwxilinxcom

1-4 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Interfaces

The third and final way to program the FPGA is via the Xilinx serial ROM on the FPGA EZ-Extender The serial ROM used for FPGA is shipped with the extender and is pre-programmed If the serial ROM needs to be re-programmed with new code use an Xilinx JTAG cable and software and connect the Xilinx JTAG cable to the flash JTAG header (P6)

More information about programming the serial ROM can be found at wwwxilinxcom More details about the different ways to program the FPGA can be found in ldquoFPGA EZ-Extender Hardware Referencerdquo on page 2-1

Blackfin FPGA EZ-Extender Manual 1-5

FPGA EZ-Extender Overview

1-6 Blackfin FPGA EZ-Extender Manual

2 FPGA EZ-EXTENDER HARDWARE REFERENCE

This chapter describes the hardware design of the Field-Programmable

Gate Array (FPGA) EZ-Extender

The following topics are covered

bull ldquoSystem Architecturerdquo on page 2-2Describes the configuration of the extender board and explains how the board components interface with the processor and EZ-KIT Lite

bull ldquoProgramming the FPGArdquo on page 2-3Describes the different methods of programming the FPGA

bull ldquoProgramming the Serial ROMrdquo on page 2-7Describes the method of programming the serial ROM

bull ldquoPowerrdquo on page 2-8Describes the methods to power the extender board

bull ldquoJumpersrdquo on page 2-11Describes the function of the configuration jumpers

bull ldquoPush Buttons and LEDsrdquo on page 2-15Describes the function of the push buttons and LEDs

bull ldquoConnectorsrdquo on page 2-18Describes the function of the extender connectors

Blackfin FPGA EZ-Extender Manual 2-1

System Architecture

System ArchitectureA block diagram of the Blackfin FPGA EZ-Extender is shown in Figure 2-1

Figure 2-1 Block Diagram

X ilin xS p a rta n 3

X C 3 S 1 0 0 0 -4 F G 4 5 6 C F P G A2 M B S R A M

(5 1 2 k x 3 2 -b its )

M e m o ry In te rfa c e

S P I S P O R T (2 x ) P P I(2 x ) G P IO

T im e rs T W I

P rim a ry E x p a n s io n In te rfa c e ( to B la c k F in E Z -K IT )

S e c o n d a ry E x p a n s io n In te rfa c e (to T e s t p o in ts a n d o th e r E Z -

E x te n d e rs )

P o w e r C o n n e c to r

R e g u la to rs

3 3 V 2 5 V 1 2 V

1 in c h h e a d e rs

2 5 M H z

O s c illa to r S o c k e t

L E D D IP S w itc h P u s h B u tto n s

S P I S P O R T (2 x ) P P I(2 x ) G P IO

T im e rs T W I

S e ria l F la s h

H ig h S p e e d C o n n e c to r

J T A G C o n n e c to r

J T A G C o n n e c to r

2-2 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Hardware Reference

Programming the FPGABefore using the Blackfin FPGA EZ-Extender follow the steps in ldquoFPGA EZ-Extender Setuprdquo on page 1-1

Figure 2-2 is a block diagram of the FPGA programming connections

Figure 2-2 FPGA Programming Block Diagram

Blackfin FPGA EZ-Extender Manual 2-3

Programming the FPGA

There are three ways to program the FPGA

bull Using the FPGA JTAG header as described in ldquoFPGA Program-ming via JTAGrdquo on page 2-4

bull Using the Xilinx serial ROM as described in ldquoFPGA Programming via Serial ROMrdquo on page 2-5

bull Using the Blackfin processor as described in ldquoFPGA Programming via Blackfin Applicationrdquo on page 2-6

The done LED (LED10) lights up once the FPGA is programmed signifying that the task is complete To erase the contents of the FPGA at any time de-press the program switch SW1

FPGA Programming via JTAGTo program the FPGA via the JTAG header create the appropriate pro-gram file using the Xilinx ISE software provided at wwwxilinxcom Once the program file is created use a Xilinx JTAG cable and connect it to P15 of the FPGA EZ-Extender (the P15 connections are shown in Table 2-1)

Table 2-1 P15 Connections for PFGA Programming via JTAG

P15 Pin Number Signal Name

1 33V

2 GND

3 TCK

4 TDO

5 TDI

6 TMS

2-4 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Hardware Reference

In addition to removing JP1 (serial ROM boot jumper) as shown in Table 2-2 set the boot jumper JP4 to JTAG mode The JP4 settings for JTAG boot are shown in Table 2-3 See ldquoBoot Jumper (JP4)rdquo on page 2-14 for more information

FPGA Programming via Serial ROMTo program the FPGA with the contents of the serial ROM populate the JP1 jumper When populated JP1 connects the chip enable pin of the serial ROM to the done bit of the FPGA Once the FPGA is programmed the done bit automatically goes high and the enable pin of the serial ROM chip becomes a logic 1 The JP1 settings for serial ROM boot are shown in Table 2-4 See ldquoProgramming the Serial ROMrdquo on page 2-7 for more information

The done LED (LED10) remains lit to signify that the FPGA is pro-grammed See ldquoDone LED (LED10)rdquo on page 2-17 for more information

Table 2-2 JP1 Settings for FPGA Programming via JTAG

JP1 Pin Name Pins Connected Jumper Setting

Flash done JP11 and JP12 Unpopulated

Table 2-3 JP4 Settings for FPGA Programming via JTAG

JP4 Pin Name Pins Connected Jumper Setting

M0 JP41 and JP42 Unpopulated

M1 JP43 and JP44 Populated

M2 JP45 and JP46 Unpopulated

Table 2-4 JP1 Settings for FPGA Programming via Serial ROM

JP1 Pin Name Pins Connected Jumper Setting

Flash done JP11 and JP12 Populated

Blackfin FPGA EZ-Extender Manual 2-5

Programming the FPGA

In addition to JP1 set the boot mode jumper JP4 to master serial mode The JP4 settings for serial ROM boot are shown in Table 2-5 See ldquoBoot Jumper (JP4)rdquo on page 2-14 for more information

FPGA Programming via Blackfin ApplicationBy default the FPGA EZ-Extender is configured by the flash program-ming utility within VisualDSP++ The software is located in the hellipBlackfinEZ-KITsFPGA EZ-EXTENDER subdirectory of the VisualDSP++ installation directory The FPGA Software Readmetxt file located in the same subdirectory provides all the necessary instructions required for run-ning the application

When generating a program file using the Xilinx software tools remember to generate a slave serial program file in the Intel MCS-86 Hexadecimal Object (mcs) file format

To boot the FPGA from the Blackfin processor unpopulate jumper JP1 and set jumper JP4 to slave serial mode as shown in Table 2-6 and Table 2-7 See ldquoSerial ROM Boot Jumper (JP1)rdquo on page 2-12 and ldquoBoot Jumper (JP4)rdquo on page 2-14 for more information

Table 2-5 JP4 Settings for FPGA Programming in Master Serial Mode

JP4 Pin Name Pins Connected Jumper Setting

M0 JP41 and JP42 Populated

M1 JP43 and JP44 Populated

M2 JP45 and JP46 Populated

Table 2-6 JP1 Settings for FPGA Programming via Blackfin Processor

JP1 Pin Name Pins Connected Jumper Setting

Flash done JP11 and JP12 Unpopulated

2-6 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Hardware Reference

Programming the Serial ROMThe FPGA EZ-Extender allows the user to program the serial ROM The serial ROM can be programmed by using a Xilinx JTAG cable ISE soft-ware and the flash JTAG header on the FPGA EZ-Extender

Serial ROM via JTAG HeaderTo program the serial ROM via the JTAG header create the appropriate program file using the Xilinx software provided at wwwxilinxcom Once the program file is created use a Xilinx JTAG cable and connect it to P6 The P6 connections are shown in Table 2-8

Table 2-7 JP4 Settings for FPGA Programming via Blackfin Processor

JP4 Pin Name Pins Connected Jumper Setting

M0 JP41 and JP42 Unpopulated

M1 JP43 and JP44 Unpopulated

M2 JP45 and JP46 Unpopulated

Table 2-8 P6 Connections for Serial ROM

P6 Pin Number Signal Name P6 Pin Number Signal Name

1 33V 4 TDO

2 GND 5 TDI

3 TCK 6 TMS

Blackfin FPGA EZ-Extender Manual 2-7

Power

PowerThe FPGA EZ-Extender can be powered from the enclosed power supply EZ-KIT Lite or external power supply The power source for the extender is selected based on the power requirements of the application

An external 7V power supply is shipped with the extender board The power supply uses three switching regulators VR1 is used to power the 25V power plane VR2 is used to power the 12V power plane and VR3 is used to power the 33V plane All of the regulators can supply a maximum current of 2 Amps To understand the power requirements of your appli-cation run the Xilinx power estimator software The software can be located at wwwxilinxcom

Table 2-9 states the current limitations of each method Each method requires a correctly configured header described in the following sections

Table 2-9 Power Limitations

Power Source 12V Supply 25V Supply 33V Supply

ADSP-BF533 ADSP-BF537 or ADSP-BF561 EZ-KIT Lite

500 mA 500 mA 500 mA

FPGA EZ-Extender power supply1

1 Default setting

2A 2A 2A

External power supply 2A 2A 2A

2-8 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Hardware Reference

Power In Header (P12)The P12 header supplies the power to the on board 12V and the 25V reg-ulators The P42 and P43 headers supply the power to the external 12V and 25V planes as described in ldquo25V Header (P42)rdquo and ldquo12V Header (P43)rdquo on page 2-10

33V Header (P13)

When using an external power supply do not plug in the power supply shipped with the FPGA EZ-Extender This can seriously damage the board As an extra measure of precaution remove all jumpers from P12

Power Source P12 Setting

FPGA EZ-Extender power supply1

1 Default setting

Jumper on P121 and P122

ADSP-BF533 ADSP-BF537 or ADSP-BF561 EZ-KIT Lite 5V power supply

Jumper on P122 and P123

Power Source P13 Setting

ADSP-BF533 ADSP-BF537 or ADSP-BF561 EZ-KIT Lite 33V power supply

Jumper on P131 and P132

FPGA EZ-Extender power supply1

1 Default setting

Jumper on P132 and P133

External power supply No jumper connect supply to P132 and GND

Blackfin FPGA EZ-Extender Manual 2-9

Power

25V Header (P42)

When using an external power supply do not plug in the power supply shipped with the FPGA EZ-Extender This can seriously damage the board As an extra measure of precaution remove all jumpers from P12

12V Header (P43)

When using an external power supply do not plug in the power supply shipped with the FPGA EZ-Extender This can seriously damage the board As an extra measure of precaution remove all jumpers from P12

Power Source P42 Setting

FPGA EZ-Extender Power Supply1

1 Default setting

No Jumper

External power supply Connect P421 to external 25VConnect P422 to external GND

Power Source P43 Setting

FPGA EZ-Extender power supply1

1 Default setting

No Jumper

External power supply Connect P421 to external 25VConnect P422 to external GND

2-10 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Hardware Reference

JumpersBefore using the Blackfin FPGA EZ-Extender follow the steps in ldquoFPGA EZ-Extender Setuprdquo on page 1-1

Figure 2-3 shows the locations of all jumper headers A two-pin jumper can be placed on the respective jumper header for different functionality The following sections describe all possible jumper settings and associated functionality

Figure 2-3 Jumper Locations

Blackfin FPGA EZ-Extender Manual 2-11

Jumpers

Serial ROM Boot Jumper (JP1)By default the serial ROM boot jumper JP1 is unpopulated When unpopulated the FPGA EZ-Extender programs via the Blackfin processor or the Xilinx JTAG header

When JP1 is left populated the jumper connects the serial ROM chip enable pin to the done bit of the FPGA At power-up the done bit is driven low by the FPGA causing the FPGA to enable the serial ROM as a programming source After the FPGA is programmed the done bit is driven high by the FPGA causing the FPGA to drive high the chip enable pin of the serial ROM

Both JP1 and JP4 must be set up for correct FPGA programming ldquoBoot Jumper (JP4)rdquo on page 2-14 summarizes the JP4 settings Table 2-10 sum-marizes the JP1 settings See Table 2-4 on page 2-5 and Table 2-6 on page 2-6 for more information on JP1

Config Done Jumper (JP2) The configuration done jumper JP2 connects the done bit of the FPGA to the Blackfin processorrsquos PF3 flag pin of the ADSP-BF533 and ADSP-BF561 EZ-KIT Lites or PF14 flag pin of the ADSP-BF537 EZ-KIT

Table 2-10 JP1 Settings

Boot Source JP1 Setting

ADSP-BF533 ADSP-BF537 or ADSP-BF561 processor via VisualDSP++1

1 Default setting

Unpopulated

JTAG header Unpopulated

Serial ROM Populated

2-12 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Hardware Reference

Lite By default the jumper is populated and acts as a monitor for the done bit by the Blackfin processor (the bit indicates that the FPGA pro-gramming is complete)

Table 2-11 summarizes the jumper settings

Config Program Jumper (JP3) The configuration program jumper JP3 connects the program bit of the FPGA to the Blackfin processorrsquos flag pin By default JP3 is populated The jumper assures that the program bit is asserted by the Blackfin proces-sor to initiate the FPGA programming through VisualDSP++ software

Table 2-12 summarizes the jumper settings

Table 2-11 JP2 Settings

Functionality JP2 Setting

Done bit connected to Blackfin processorrsquos PF3 flag pin1

1 Default setting

Populated

Done bit disconnected from Blackfin processorrsquos PF3 flag pin

Unpopulated

Table 2-12 JP3 Settings

Functionality JP3 Setting

Program bit connected to the Blackfin processorrsquos flag pin1

1 Default setting

Populated

Program bit disconnected from the Blackfin proces-sorrsquos flag pin

Unpopulated

Blackfin FPGA EZ-Extender Manual 2-13

Jumpers

Boot Jumper (JP4) The boot jumper JP4 configures the FPGA mode pins (M[20]) Based on the jumper settings the FPGA is set to be programmed by the JTAG header serial ROM or Blackfin processor

Table 2-13 summarizes the jumper settings See Table 2-3 on page 2-5 for the JTAG header boot settings Table 2-5 on page 2-6 for the serial ROM boot settings and Table 2-7 on page 2-7 for the Blackfin processor boot settings

FPGA Input Jumpers (JP5) The FPGA input jumpers JP52ndash58 drive select FPGA nets to a logic 0 and can be used for any user logic that requires a steady state input You can set internal pull-ups on these nets in the FPGA and when a low is required populate the respective jumper

Table 2-14 summarizes the jumper settings

Table 2-13 JP4 Settings

Boot Source JP41 and JP42M0

JP43 and JP44M1

JP45 and JP46M2

ADSP-BF533ADSP-BF537 orADSP-BF561 processor1

1 Default setting

Unpopulated Unpopulated Unpopulated

JTAG header Unpopulated Populated Unpopulated

Serial ROM Populated Populated Populated

2-14 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Hardware Reference

Push Buttons and LEDsBefore using the Blackfin FPGA EZ-Extender follow the steps in ldquoFPGA EZ-Extender Setuprdquo on page 1-1

Figure 2-4 shows the locations of all push buttons and LEDs The follow-ing sections describe the associated functionality of all the push buttons and LEDs

Program Push Button (SW1)The program push button SW1 erases the contents of the FPGA The push button can be used as a hard resetmdashthe FPGA must be completely re-programmed once SW1 is de-pressed See ldquoProgramming the FPGArdquo on page 2-3 for more information

PB1 Push Button (SW3)The PB1 push button SW3 is a general-purpose input push button The switch with a connected debounce circuit eliminates the need to re-create it in the FPGA The push button connects to pin C11 of the FPGA

Table 2-14 JP5 Settings

Reference Designator FPGA Pin Number

JP52 Y3

JP54 Y2

JP56 U10

JP58 AB11

Blackfin FPGA EZ-Extender Manual 2-15

Push Buttons and LEDs

PB2 Push Button (SW4) The PB2 push button SW4 is a general-purpose input push button The switch does not have a connected debounce circuit you may need to cre-ate it in the FPGA if required by a specific application The push button connects to pin H5 of the FPGA

Figure 2-4 Push Button and LED Locations

2-16 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Hardware Reference

Status LEDs (LED1ndash8) Eight status LEDs LED1ndash8 connect to the FPGA and act as status flags in any application that requires it Table 2-15 shows the LEDFPGA connections

Power LED (LED9) The power LED LED9 connects to the 25V power supply and when lit signifies that the FPGA EZ-Extender is powered properly

Done LED (LED10) The done LED LED10 connects to the done pin of the FPGA At power-up the FPGA is blank and needs to be programmed When lit the LED indicates that the FPGA is programmed successfully

Table 2-15 Status LED (LED1ndash8) Settings

Reference Designator FPGA Pin Number

LED1 U11

LED2 W11

LED3 AB10

LED4 Y10

LED5 AB9

LED6 W9

LED7 AB8

LED8 V10

Blackfin FPGA EZ-Extender Manual 2-17

Connectors

ConnectorsBefore using the Blackfin FPGA EZ-Extender follow the steps in ldquoFPGA EZ-Extender Setuprdquo on page 1-1

This section describes the connector functionality and provides informa-tion about the mating connectors The connector locations are shown in Figure 2-5

Figure 2-5 Connector Locations

2-18 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Hardware Reference

Expansion Interface (P1ndash3 and J1ndash3) Connectors P1ndash3 of the expansion interface are used to plug in the EZ-Extender to the ADSP-BF533 ADSP-BF537 or ADSP-BF561 EZ-KIT Lite

Connectors J1ndash3 of the expansion interface are used to plug in another extender board such as the Blackfin USB-LAN EZ-Extender Your own custom board can be plugged into J1ndash3 as well

Plugging in another EZ-Extender or a customer board to the expansion interface can de-grade the overall system performance The extra overall load can cause the user to add wait states or slow down the system bus to get all of the boards to work properly

For the J1ndash3 and P1ndash3 connector availability and pricing contact Samtec

IDC Connectors (P8 P14 P16 and P17) The P8 P14 P16 and P17 connectors are standard 01rdquo IDC headers The connectors are in a 13 x 2 configuration and designed for signal probing bread boarding and other signal accesses

Part Description Manufacturer Part Number

90-position 005rdquo spacing SMT(J1 J2 J3)

Samtec SFC-145-T2-F-D-A

90-position 005rdquo spacing (P1 P2 P3)

Samtec TFC-145-32-F-D

Part Description Manufacturer Part Number

IDC13x2 01rdquo header Berg 54102-T08-13

Mating Connector

IDC 13x2 01rdquo plug Samtec SSW-113-01-T-D

Blackfin FPGA EZ-Extender Manual 2-19

Connectors

IDC Connectors (P5 and P7) The P5 and P7 connectors are standard 01rdquo IDC headers The connectors are in a 14 x 2 configuration and designed for signal probing bread boarding and other signal accesses

High-Speed Connector (P4) The high-speed connector P4 facilitates development of applications where use of the standard IDC connectors is complicated due to signal integrity issues

For the P4 connector and cable assembly availability and pricing contact Samtec

Part Description Manufacturer Part Number

IDC14x2 01rdquo header FCI 68737-428HLF

IDC14x2 01rdquo header Sullins GEC14DAAN

Mating Connector

IDC 14x2 01rdquo plug Samtec SSW-114-01-T-D

Part Description Manufacturer Part Number

QTS 25x2 high-speed connector Samtec QTS-025-01-F-D-A

Mating Connector

QSS 25x2 high-speed connector Samtec QSS-025-01-F-D-A

2-20 Blackfin FPGA EZ-Extender Manual

A BILL OF MATERIALS

The bill of materials corresponds to the board schematics on page B-1

Please check the latest schematics on the Analog Devices website httpwwwanalogcomProcessorsProcessorsDevelopmentToolstec

hnicalLibrarymanualsDevToolsIndexhtmlEvalua-

tion20Kit20Manuals

Blackfin FPGA EZ-Extender Manual A-1

FPGA EZ-Extender Overview

The FPGA EZ-Extender contains 2 MB of asynchronous SRAM memory powered by a 33V supply The SRAM memory connects to banks 6 and 7 of the FPGA and can perform simple data storage instructions in applica-tion-specific code

The FPGA EZ-Extender includes a 25 MHz oscillator (U6) connected to the FPGA via the dedicated global clock 1 (GCLK1) pin facilitating devel-opment of applications that require a clock A second clock socket (U7) is left unpopulated to allow a user to place an oscillator with a specific fre-quency for the FPGA The second clock socket connects to the global clock 6 (GCLK6) pin of the FPGA

The extender has eight LEDs (LED1ndash8) and two push buttons (SW3ndash4) for applications that require status reporting and user control The push but-tons are active low and when pressed provide a logic 0 to the respective FPGA nets For inputs that require a permanent input low use the jumper inputs on JP4 When a jumper is populated on one of the four nets of JP4 the respective pin is hard wired to a logic 0 For more information about the LEDs push button switches and jumper inputs refer to ldquoFPGA EZ-Extender Hardware Referencerdquo on page 2-1

There are various ways to program the FPGA By default the FPGA is programmed in its slave serial mode by the flash programming utility in VisualDSP++ The program configures the FPGA using the Blackfin pro-cessorrsquos flag pins andor serial port pins For more information on how to use the flash programming utility within VisualDSP++ refer to the FPGA Software Readmetxt file located in the hellipBlackfinEZ-KITsFPGA EZ-EXTENDER subdirectory of the VisualDSP++ installation directory

A second method of programming the FPGA is by using a Xilinx JTAG cable and software The Xilinx JTAG cable connects to the FPGA JTAG header (P15) For more information about programming the FPGA via a Xilinx JTAG cable refer to the manufacturerrsquos website at wwwxilinxcom

1-4 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Interfaces

The third and final way to program the FPGA is via the Xilinx serial ROM on the FPGA EZ-Extender The serial ROM used for FPGA is shipped with the extender and is pre-programmed If the serial ROM needs to be re-programmed with new code use an Xilinx JTAG cable and software and connect the Xilinx JTAG cable to the flash JTAG header (P6)

More information about programming the serial ROM can be found at wwwxilinxcom More details about the different ways to program the FPGA can be found in ldquoFPGA EZ-Extender Hardware Referencerdquo on page 2-1

Blackfin FPGA EZ-Extender Manual 1-5

FPGA EZ-Extender Overview

1-6 Blackfin FPGA EZ-Extender Manual

2 FPGA EZ-EXTENDER HARDWARE REFERENCE

This chapter describes the hardware design of the Field-Programmable

Gate Array (FPGA) EZ-Extender

The following topics are covered

bull ldquoSystem Architecturerdquo on page 2-2Describes the configuration of the extender board and explains how the board components interface with the processor and EZ-KIT Lite

bull ldquoProgramming the FPGArdquo on page 2-3Describes the different methods of programming the FPGA

bull ldquoProgramming the Serial ROMrdquo on page 2-7Describes the method of programming the serial ROM

bull ldquoPowerrdquo on page 2-8Describes the methods to power the extender board

bull ldquoJumpersrdquo on page 2-11Describes the function of the configuration jumpers

bull ldquoPush Buttons and LEDsrdquo on page 2-15Describes the function of the push buttons and LEDs

bull ldquoConnectorsrdquo on page 2-18Describes the function of the extender connectors

Blackfin FPGA EZ-Extender Manual 2-1

System Architecture

System ArchitectureA block diagram of the Blackfin FPGA EZ-Extender is shown in Figure 2-1

Figure 2-1 Block Diagram

X ilin xS p a rta n 3

X C 3 S 1 0 0 0 -4 F G 4 5 6 C F P G A2 M B S R A M

(5 1 2 k x 3 2 -b its )

M e m o ry In te rfa c e

S P I S P O R T (2 x ) P P I(2 x ) G P IO

T im e rs T W I

P rim a ry E x p a n s io n In te rfa c e ( to B la c k F in E Z -K IT )

S e c o n d a ry E x p a n s io n In te rfa c e (to T e s t p o in ts a n d o th e r E Z -

E x te n d e rs )

P o w e r C o n n e c to r

R e g u la to rs

3 3 V 2 5 V 1 2 V

1 in c h h e a d e rs

2 5 M H z

O s c illa to r S o c k e t

L E D D IP S w itc h P u s h B u tto n s

S P I S P O R T (2 x ) P P I(2 x ) G P IO

T im e rs T W I

S e ria l F la s h

H ig h S p e e d C o n n e c to r

J T A G C o n n e c to r

J T A G C o n n e c to r

2-2 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Hardware Reference

Programming the FPGABefore using the Blackfin FPGA EZ-Extender follow the steps in ldquoFPGA EZ-Extender Setuprdquo on page 1-1

Figure 2-2 is a block diagram of the FPGA programming connections

Figure 2-2 FPGA Programming Block Diagram

Blackfin FPGA EZ-Extender Manual 2-3

Programming the FPGA

There are three ways to program the FPGA

bull Using the FPGA JTAG header as described in ldquoFPGA Program-ming via JTAGrdquo on page 2-4

bull Using the Xilinx serial ROM as described in ldquoFPGA Programming via Serial ROMrdquo on page 2-5

bull Using the Blackfin processor as described in ldquoFPGA Programming via Blackfin Applicationrdquo on page 2-6

The done LED (LED10) lights up once the FPGA is programmed signifying that the task is complete To erase the contents of the FPGA at any time de-press the program switch SW1

FPGA Programming via JTAGTo program the FPGA via the JTAG header create the appropriate pro-gram file using the Xilinx ISE software provided at wwwxilinxcom Once the program file is created use a Xilinx JTAG cable and connect it to P15 of the FPGA EZ-Extender (the P15 connections are shown in Table 2-1)

Table 2-1 P15 Connections for PFGA Programming via JTAG

P15 Pin Number Signal Name

1 33V

2 GND

3 TCK

4 TDO

5 TDI

6 TMS

2-4 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Hardware Reference

In addition to removing JP1 (serial ROM boot jumper) as shown in Table 2-2 set the boot jumper JP4 to JTAG mode The JP4 settings for JTAG boot are shown in Table 2-3 See ldquoBoot Jumper (JP4)rdquo on page 2-14 for more information

FPGA Programming via Serial ROMTo program the FPGA with the contents of the serial ROM populate the JP1 jumper When populated JP1 connects the chip enable pin of the serial ROM to the done bit of the FPGA Once the FPGA is programmed the done bit automatically goes high and the enable pin of the serial ROM chip becomes a logic 1 The JP1 settings for serial ROM boot are shown in Table 2-4 See ldquoProgramming the Serial ROMrdquo on page 2-7 for more information

The done LED (LED10) remains lit to signify that the FPGA is pro-grammed See ldquoDone LED (LED10)rdquo on page 2-17 for more information

Table 2-2 JP1 Settings for FPGA Programming via JTAG

JP1 Pin Name Pins Connected Jumper Setting

Flash done JP11 and JP12 Unpopulated

Table 2-3 JP4 Settings for FPGA Programming via JTAG

JP4 Pin Name Pins Connected Jumper Setting

M0 JP41 and JP42 Unpopulated

M1 JP43 and JP44 Populated

M2 JP45 and JP46 Unpopulated

Table 2-4 JP1 Settings for FPGA Programming via Serial ROM

JP1 Pin Name Pins Connected Jumper Setting

Flash done JP11 and JP12 Populated

Blackfin FPGA EZ-Extender Manual 2-5

Programming the FPGA

In addition to JP1 set the boot mode jumper JP4 to master serial mode The JP4 settings for serial ROM boot are shown in Table 2-5 See ldquoBoot Jumper (JP4)rdquo on page 2-14 for more information

FPGA Programming via Blackfin ApplicationBy default the FPGA EZ-Extender is configured by the flash program-ming utility within VisualDSP++ The software is located in the hellipBlackfinEZ-KITsFPGA EZ-EXTENDER subdirectory of the VisualDSP++ installation directory The FPGA Software Readmetxt file located in the same subdirectory provides all the necessary instructions required for run-ning the application

When generating a program file using the Xilinx software tools remember to generate a slave serial program file in the Intel MCS-86 Hexadecimal Object (mcs) file format

To boot the FPGA from the Blackfin processor unpopulate jumper JP1 and set jumper JP4 to slave serial mode as shown in Table 2-6 and Table 2-7 See ldquoSerial ROM Boot Jumper (JP1)rdquo on page 2-12 and ldquoBoot Jumper (JP4)rdquo on page 2-14 for more information

Table 2-5 JP4 Settings for FPGA Programming in Master Serial Mode

JP4 Pin Name Pins Connected Jumper Setting

M0 JP41 and JP42 Populated

M1 JP43 and JP44 Populated

M2 JP45 and JP46 Populated

Table 2-6 JP1 Settings for FPGA Programming via Blackfin Processor

JP1 Pin Name Pins Connected Jumper Setting

Flash done JP11 and JP12 Unpopulated

2-6 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Hardware Reference

Programming the Serial ROMThe FPGA EZ-Extender allows the user to program the serial ROM The serial ROM can be programmed by using a Xilinx JTAG cable ISE soft-ware and the flash JTAG header on the FPGA EZ-Extender

Serial ROM via JTAG HeaderTo program the serial ROM via the JTAG header create the appropriate program file using the Xilinx software provided at wwwxilinxcom Once the program file is created use a Xilinx JTAG cable and connect it to P6 The P6 connections are shown in Table 2-8

Table 2-7 JP4 Settings for FPGA Programming via Blackfin Processor

JP4 Pin Name Pins Connected Jumper Setting

M0 JP41 and JP42 Unpopulated

M1 JP43 and JP44 Unpopulated

M2 JP45 and JP46 Unpopulated

Table 2-8 P6 Connections for Serial ROM

P6 Pin Number Signal Name P6 Pin Number Signal Name

1 33V 4 TDO

2 GND 5 TDI

3 TCK 6 TMS

Blackfin FPGA EZ-Extender Manual 2-7

Power

PowerThe FPGA EZ-Extender can be powered from the enclosed power supply EZ-KIT Lite or external power supply The power source for the extender is selected based on the power requirements of the application

An external 7V power supply is shipped with the extender board The power supply uses three switching regulators VR1 is used to power the 25V power plane VR2 is used to power the 12V power plane and VR3 is used to power the 33V plane All of the regulators can supply a maximum current of 2 Amps To understand the power requirements of your appli-cation run the Xilinx power estimator software The software can be located at wwwxilinxcom

Table 2-9 states the current limitations of each method Each method requires a correctly configured header described in the following sections

Table 2-9 Power Limitations

Power Source 12V Supply 25V Supply 33V Supply

ADSP-BF533 ADSP-BF537 or ADSP-BF561 EZ-KIT Lite

500 mA 500 mA 500 mA

FPGA EZ-Extender power supply1

1 Default setting

2A 2A 2A

External power supply 2A 2A 2A

2-8 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Hardware Reference

Power In Header (P12)The P12 header supplies the power to the on board 12V and the 25V reg-ulators The P42 and P43 headers supply the power to the external 12V and 25V planes as described in ldquo25V Header (P42)rdquo and ldquo12V Header (P43)rdquo on page 2-10

33V Header (P13)

When using an external power supply do not plug in the power supply shipped with the FPGA EZ-Extender This can seriously damage the board As an extra measure of precaution remove all jumpers from P12

Power Source P12 Setting

FPGA EZ-Extender power supply1

1 Default setting

Jumper on P121 and P122

ADSP-BF533 ADSP-BF537 or ADSP-BF561 EZ-KIT Lite 5V power supply

Jumper on P122 and P123

Power Source P13 Setting

ADSP-BF533 ADSP-BF537 or ADSP-BF561 EZ-KIT Lite 33V power supply

Jumper on P131 and P132

FPGA EZ-Extender power supply1

1 Default setting

Jumper on P132 and P133

External power supply No jumper connect supply to P132 and GND

Blackfin FPGA EZ-Extender Manual 2-9

Power

25V Header (P42)

When using an external power supply do not plug in the power supply shipped with the FPGA EZ-Extender This can seriously damage the board As an extra measure of precaution remove all jumpers from P12

12V Header (P43)

When using an external power supply do not plug in the power supply shipped with the FPGA EZ-Extender This can seriously damage the board As an extra measure of precaution remove all jumpers from P12

Power Source P42 Setting

FPGA EZ-Extender Power Supply1

1 Default setting

No Jumper

External power supply Connect P421 to external 25VConnect P422 to external GND

Power Source P43 Setting

FPGA EZ-Extender power supply1

1 Default setting

No Jumper

External power supply Connect P421 to external 25VConnect P422 to external GND

2-10 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Hardware Reference

JumpersBefore using the Blackfin FPGA EZ-Extender follow the steps in ldquoFPGA EZ-Extender Setuprdquo on page 1-1

Figure 2-3 shows the locations of all jumper headers A two-pin jumper can be placed on the respective jumper header for different functionality The following sections describe all possible jumper settings and associated functionality

Figure 2-3 Jumper Locations

Blackfin FPGA EZ-Extender Manual 2-11

Jumpers

Serial ROM Boot Jumper (JP1)By default the serial ROM boot jumper JP1 is unpopulated When unpopulated the FPGA EZ-Extender programs via the Blackfin processor or the Xilinx JTAG header

When JP1 is left populated the jumper connects the serial ROM chip enable pin to the done bit of the FPGA At power-up the done bit is driven low by the FPGA causing the FPGA to enable the serial ROM as a programming source After the FPGA is programmed the done bit is driven high by the FPGA causing the FPGA to drive high the chip enable pin of the serial ROM

Both JP1 and JP4 must be set up for correct FPGA programming ldquoBoot Jumper (JP4)rdquo on page 2-14 summarizes the JP4 settings Table 2-10 sum-marizes the JP1 settings See Table 2-4 on page 2-5 and Table 2-6 on page 2-6 for more information on JP1

Config Done Jumper (JP2) The configuration done jumper JP2 connects the done bit of the FPGA to the Blackfin processorrsquos PF3 flag pin of the ADSP-BF533 and ADSP-BF561 EZ-KIT Lites or PF14 flag pin of the ADSP-BF537 EZ-KIT

Table 2-10 JP1 Settings

Boot Source JP1 Setting

ADSP-BF533 ADSP-BF537 or ADSP-BF561 processor via VisualDSP++1

1 Default setting

Unpopulated

JTAG header Unpopulated

Serial ROM Populated

2-12 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Hardware Reference

Lite By default the jumper is populated and acts as a monitor for the done bit by the Blackfin processor (the bit indicates that the FPGA pro-gramming is complete)

Table 2-11 summarizes the jumper settings

Config Program Jumper (JP3) The configuration program jumper JP3 connects the program bit of the FPGA to the Blackfin processorrsquos flag pin By default JP3 is populated The jumper assures that the program bit is asserted by the Blackfin proces-sor to initiate the FPGA programming through VisualDSP++ software

Table 2-12 summarizes the jumper settings

Table 2-11 JP2 Settings

Functionality JP2 Setting

Done bit connected to Blackfin processorrsquos PF3 flag pin1

1 Default setting

Populated

Done bit disconnected from Blackfin processorrsquos PF3 flag pin

Unpopulated

Table 2-12 JP3 Settings

Functionality JP3 Setting

Program bit connected to the Blackfin processorrsquos flag pin1

1 Default setting

Populated

Program bit disconnected from the Blackfin proces-sorrsquos flag pin

Unpopulated

Blackfin FPGA EZ-Extender Manual 2-13

Jumpers

Boot Jumper (JP4) The boot jumper JP4 configures the FPGA mode pins (M[20]) Based on the jumper settings the FPGA is set to be programmed by the JTAG header serial ROM or Blackfin processor

Table 2-13 summarizes the jumper settings See Table 2-3 on page 2-5 for the JTAG header boot settings Table 2-5 on page 2-6 for the serial ROM boot settings and Table 2-7 on page 2-7 for the Blackfin processor boot settings

FPGA Input Jumpers (JP5) The FPGA input jumpers JP52ndash58 drive select FPGA nets to a logic 0 and can be used for any user logic that requires a steady state input You can set internal pull-ups on these nets in the FPGA and when a low is required populate the respective jumper

Table 2-14 summarizes the jumper settings

Table 2-13 JP4 Settings

Boot Source JP41 and JP42M0

JP43 and JP44M1

JP45 and JP46M2

ADSP-BF533ADSP-BF537 orADSP-BF561 processor1

1 Default setting

Unpopulated Unpopulated Unpopulated

JTAG header Unpopulated Populated Unpopulated

Serial ROM Populated Populated Populated

2-14 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Hardware Reference

Push Buttons and LEDsBefore using the Blackfin FPGA EZ-Extender follow the steps in ldquoFPGA EZ-Extender Setuprdquo on page 1-1

Figure 2-4 shows the locations of all push buttons and LEDs The follow-ing sections describe the associated functionality of all the push buttons and LEDs

Program Push Button (SW1)The program push button SW1 erases the contents of the FPGA The push button can be used as a hard resetmdashthe FPGA must be completely re-programmed once SW1 is de-pressed See ldquoProgramming the FPGArdquo on page 2-3 for more information

PB1 Push Button (SW3)The PB1 push button SW3 is a general-purpose input push button The switch with a connected debounce circuit eliminates the need to re-create it in the FPGA The push button connects to pin C11 of the FPGA

Table 2-14 JP5 Settings

Reference Designator FPGA Pin Number

JP52 Y3

JP54 Y2

JP56 U10

JP58 AB11

Blackfin FPGA EZ-Extender Manual 2-15

Push Buttons and LEDs

PB2 Push Button (SW4) The PB2 push button SW4 is a general-purpose input push button The switch does not have a connected debounce circuit you may need to cre-ate it in the FPGA if required by a specific application The push button connects to pin H5 of the FPGA

Figure 2-4 Push Button and LED Locations

2-16 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Hardware Reference

Status LEDs (LED1ndash8) Eight status LEDs LED1ndash8 connect to the FPGA and act as status flags in any application that requires it Table 2-15 shows the LEDFPGA connections

Power LED (LED9) The power LED LED9 connects to the 25V power supply and when lit signifies that the FPGA EZ-Extender is powered properly

Done LED (LED10) The done LED LED10 connects to the done pin of the FPGA At power-up the FPGA is blank and needs to be programmed When lit the LED indicates that the FPGA is programmed successfully

Table 2-15 Status LED (LED1ndash8) Settings

Reference Designator FPGA Pin Number

LED1 U11

LED2 W11

LED3 AB10

LED4 Y10

LED5 AB9

LED6 W9

LED7 AB8

LED8 V10

Blackfin FPGA EZ-Extender Manual 2-17

Connectors

ConnectorsBefore using the Blackfin FPGA EZ-Extender follow the steps in ldquoFPGA EZ-Extender Setuprdquo on page 1-1

This section describes the connector functionality and provides informa-tion about the mating connectors The connector locations are shown in Figure 2-5

Figure 2-5 Connector Locations

2-18 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Hardware Reference

Expansion Interface (P1ndash3 and J1ndash3) Connectors P1ndash3 of the expansion interface are used to plug in the EZ-Extender to the ADSP-BF533 ADSP-BF537 or ADSP-BF561 EZ-KIT Lite

Connectors J1ndash3 of the expansion interface are used to plug in another extender board such as the Blackfin USB-LAN EZ-Extender Your own custom board can be plugged into J1ndash3 as well

Plugging in another EZ-Extender or a customer board to the expansion interface can de-grade the overall system performance The extra overall load can cause the user to add wait states or slow down the system bus to get all of the boards to work properly

For the J1ndash3 and P1ndash3 connector availability and pricing contact Samtec

IDC Connectors (P8 P14 P16 and P17) The P8 P14 P16 and P17 connectors are standard 01rdquo IDC headers The connectors are in a 13 x 2 configuration and designed for signal probing bread boarding and other signal accesses

Part Description Manufacturer Part Number

90-position 005rdquo spacing SMT(J1 J2 J3)

Samtec SFC-145-T2-F-D-A

90-position 005rdquo spacing (P1 P2 P3)

Samtec TFC-145-32-F-D

Part Description Manufacturer Part Number

IDC13x2 01rdquo header Berg 54102-T08-13

Mating Connector

IDC 13x2 01rdquo plug Samtec SSW-113-01-T-D

Blackfin FPGA EZ-Extender Manual 2-19

Connectors

IDC Connectors (P5 and P7) The P5 and P7 connectors are standard 01rdquo IDC headers The connectors are in a 14 x 2 configuration and designed for signal probing bread boarding and other signal accesses

High-Speed Connector (P4) The high-speed connector P4 facilitates development of applications where use of the standard IDC connectors is complicated due to signal integrity issues

For the P4 connector and cable assembly availability and pricing contact Samtec

Part Description Manufacturer Part Number

IDC14x2 01rdquo header FCI 68737-428HLF

IDC14x2 01rdquo header Sullins GEC14DAAN

Mating Connector

IDC 14x2 01rdquo plug Samtec SSW-114-01-T-D

Part Description Manufacturer Part Number

QTS 25x2 high-speed connector Samtec QTS-025-01-F-D-A

Mating Connector

QSS 25x2 high-speed connector Samtec QSS-025-01-F-D-A

2-20 Blackfin FPGA EZ-Extender Manual

A BILL OF MATERIALS

The bill of materials corresponds to the board schematics on page B-1

Please check the latest schematics on the Analog Devices website httpwwwanalogcomProcessorsProcessorsDevelopmentToolstec

hnicalLibrarymanualsDevToolsIndexhtmlEvalua-

tion20Kit20Manuals

Blackfin FPGA EZ-Extender Manual A-1

FPGA EZ-Extender Interfaces

The third and final way to program the FPGA is via the Xilinx serial ROM on the FPGA EZ-Extender The serial ROM used for FPGA is shipped with the extender and is pre-programmed If the serial ROM needs to be re-programmed with new code use an Xilinx JTAG cable and software and connect the Xilinx JTAG cable to the flash JTAG header (P6)

More information about programming the serial ROM can be found at wwwxilinxcom More details about the different ways to program the FPGA can be found in ldquoFPGA EZ-Extender Hardware Referencerdquo on page 2-1

Blackfin FPGA EZ-Extender Manual 1-5

FPGA EZ-Extender Overview

1-6 Blackfin FPGA EZ-Extender Manual

2 FPGA EZ-EXTENDER HARDWARE REFERENCE

This chapter describes the hardware design of the Field-Programmable

Gate Array (FPGA) EZ-Extender

The following topics are covered

bull ldquoSystem Architecturerdquo on page 2-2Describes the configuration of the extender board and explains how the board components interface with the processor and EZ-KIT Lite

bull ldquoProgramming the FPGArdquo on page 2-3Describes the different methods of programming the FPGA

bull ldquoProgramming the Serial ROMrdquo on page 2-7Describes the method of programming the serial ROM

bull ldquoPowerrdquo on page 2-8Describes the methods to power the extender board

bull ldquoJumpersrdquo on page 2-11Describes the function of the configuration jumpers

bull ldquoPush Buttons and LEDsrdquo on page 2-15Describes the function of the push buttons and LEDs

bull ldquoConnectorsrdquo on page 2-18Describes the function of the extender connectors

Blackfin FPGA EZ-Extender Manual 2-1

System Architecture

System ArchitectureA block diagram of the Blackfin FPGA EZ-Extender is shown in Figure 2-1

Figure 2-1 Block Diagram

X ilin xS p a rta n 3

X C 3 S 1 0 0 0 -4 F G 4 5 6 C F P G A2 M B S R A M

(5 1 2 k x 3 2 -b its )

M e m o ry In te rfa c e

S P I S P O R T (2 x ) P P I(2 x ) G P IO

T im e rs T W I

P rim a ry E x p a n s io n In te rfa c e ( to B la c k F in E Z -K IT )

S e c o n d a ry E x p a n s io n In te rfa c e (to T e s t p o in ts a n d o th e r E Z -

E x te n d e rs )

P o w e r C o n n e c to r

R e g u la to rs

3 3 V 2 5 V 1 2 V

1 in c h h e a d e rs

2 5 M H z

O s c illa to r S o c k e t

L E D D IP S w itc h P u s h B u tto n s

S P I S P O R T (2 x ) P P I(2 x ) G P IO

T im e rs T W I

S e ria l F la s h

H ig h S p e e d C o n n e c to r

J T A G C o n n e c to r

J T A G C o n n e c to r

2-2 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Hardware Reference

Programming the FPGABefore using the Blackfin FPGA EZ-Extender follow the steps in ldquoFPGA EZ-Extender Setuprdquo on page 1-1

Figure 2-2 is a block diagram of the FPGA programming connections

Figure 2-2 FPGA Programming Block Diagram

Blackfin FPGA EZ-Extender Manual 2-3

Programming the FPGA

There are three ways to program the FPGA

bull Using the FPGA JTAG header as described in ldquoFPGA Program-ming via JTAGrdquo on page 2-4

bull Using the Xilinx serial ROM as described in ldquoFPGA Programming via Serial ROMrdquo on page 2-5

bull Using the Blackfin processor as described in ldquoFPGA Programming via Blackfin Applicationrdquo on page 2-6

The done LED (LED10) lights up once the FPGA is programmed signifying that the task is complete To erase the contents of the FPGA at any time de-press the program switch SW1

FPGA Programming via JTAGTo program the FPGA via the JTAG header create the appropriate pro-gram file using the Xilinx ISE software provided at wwwxilinxcom Once the program file is created use a Xilinx JTAG cable and connect it to P15 of the FPGA EZ-Extender (the P15 connections are shown in Table 2-1)

Table 2-1 P15 Connections for PFGA Programming via JTAG

P15 Pin Number Signal Name

1 33V

2 GND

3 TCK

4 TDO

5 TDI

6 TMS

2-4 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Hardware Reference

In addition to removing JP1 (serial ROM boot jumper) as shown in Table 2-2 set the boot jumper JP4 to JTAG mode The JP4 settings for JTAG boot are shown in Table 2-3 See ldquoBoot Jumper (JP4)rdquo on page 2-14 for more information

FPGA Programming via Serial ROMTo program the FPGA with the contents of the serial ROM populate the JP1 jumper When populated JP1 connects the chip enable pin of the serial ROM to the done bit of the FPGA Once the FPGA is programmed the done bit automatically goes high and the enable pin of the serial ROM chip becomes a logic 1 The JP1 settings for serial ROM boot are shown in Table 2-4 See ldquoProgramming the Serial ROMrdquo on page 2-7 for more information

The done LED (LED10) remains lit to signify that the FPGA is pro-grammed See ldquoDone LED (LED10)rdquo on page 2-17 for more information

Table 2-2 JP1 Settings for FPGA Programming via JTAG

JP1 Pin Name Pins Connected Jumper Setting

Flash done JP11 and JP12 Unpopulated

Table 2-3 JP4 Settings for FPGA Programming via JTAG

JP4 Pin Name Pins Connected Jumper Setting

M0 JP41 and JP42 Unpopulated

M1 JP43 and JP44 Populated

M2 JP45 and JP46 Unpopulated

Table 2-4 JP1 Settings for FPGA Programming via Serial ROM

JP1 Pin Name Pins Connected Jumper Setting

Flash done JP11 and JP12 Populated

Blackfin FPGA EZ-Extender Manual 2-5

Programming the FPGA

In addition to JP1 set the boot mode jumper JP4 to master serial mode The JP4 settings for serial ROM boot are shown in Table 2-5 See ldquoBoot Jumper (JP4)rdquo on page 2-14 for more information

FPGA Programming via Blackfin ApplicationBy default the FPGA EZ-Extender is configured by the flash program-ming utility within VisualDSP++ The software is located in the hellipBlackfinEZ-KITsFPGA EZ-EXTENDER subdirectory of the VisualDSP++ installation directory The FPGA Software Readmetxt file located in the same subdirectory provides all the necessary instructions required for run-ning the application

When generating a program file using the Xilinx software tools remember to generate a slave serial program file in the Intel MCS-86 Hexadecimal Object (mcs) file format

To boot the FPGA from the Blackfin processor unpopulate jumper JP1 and set jumper JP4 to slave serial mode as shown in Table 2-6 and Table 2-7 See ldquoSerial ROM Boot Jumper (JP1)rdquo on page 2-12 and ldquoBoot Jumper (JP4)rdquo on page 2-14 for more information

Table 2-5 JP4 Settings for FPGA Programming in Master Serial Mode

JP4 Pin Name Pins Connected Jumper Setting

M0 JP41 and JP42 Populated

M1 JP43 and JP44 Populated

M2 JP45 and JP46 Populated

Table 2-6 JP1 Settings for FPGA Programming via Blackfin Processor

JP1 Pin Name Pins Connected Jumper Setting

Flash done JP11 and JP12 Unpopulated

2-6 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Hardware Reference

Programming the Serial ROMThe FPGA EZ-Extender allows the user to program the serial ROM The serial ROM can be programmed by using a Xilinx JTAG cable ISE soft-ware and the flash JTAG header on the FPGA EZ-Extender

Serial ROM via JTAG HeaderTo program the serial ROM via the JTAG header create the appropriate program file using the Xilinx software provided at wwwxilinxcom Once the program file is created use a Xilinx JTAG cable and connect it to P6 The P6 connections are shown in Table 2-8

Table 2-7 JP4 Settings for FPGA Programming via Blackfin Processor

JP4 Pin Name Pins Connected Jumper Setting

M0 JP41 and JP42 Unpopulated

M1 JP43 and JP44 Unpopulated

M2 JP45 and JP46 Unpopulated

Table 2-8 P6 Connections for Serial ROM

P6 Pin Number Signal Name P6 Pin Number Signal Name

1 33V 4 TDO

2 GND 5 TDI

3 TCK 6 TMS

Blackfin FPGA EZ-Extender Manual 2-7

Power

PowerThe FPGA EZ-Extender can be powered from the enclosed power supply EZ-KIT Lite or external power supply The power source for the extender is selected based on the power requirements of the application

An external 7V power supply is shipped with the extender board The power supply uses three switching regulators VR1 is used to power the 25V power plane VR2 is used to power the 12V power plane and VR3 is used to power the 33V plane All of the regulators can supply a maximum current of 2 Amps To understand the power requirements of your appli-cation run the Xilinx power estimator software The software can be located at wwwxilinxcom

Table 2-9 states the current limitations of each method Each method requires a correctly configured header described in the following sections

Table 2-9 Power Limitations

Power Source 12V Supply 25V Supply 33V Supply

ADSP-BF533 ADSP-BF537 or ADSP-BF561 EZ-KIT Lite

500 mA 500 mA 500 mA

FPGA EZ-Extender power supply1

1 Default setting

2A 2A 2A

External power supply 2A 2A 2A

2-8 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Hardware Reference

Power In Header (P12)The P12 header supplies the power to the on board 12V and the 25V reg-ulators The P42 and P43 headers supply the power to the external 12V and 25V planes as described in ldquo25V Header (P42)rdquo and ldquo12V Header (P43)rdquo on page 2-10

33V Header (P13)

When using an external power supply do not plug in the power supply shipped with the FPGA EZ-Extender This can seriously damage the board As an extra measure of precaution remove all jumpers from P12

Power Source P12 Setting

FPGA EZ-Extender power supply1

1 Default setting

Jumper on P121 and P122

ADSP-BF533 ADSP-BF537 or ADSP-BF561 EZ-KIT Lite 5V power supply

Jumper on P122 and P123

Power Source P13 Setting

ADSP-BF533 ADSP-BF537 or ADSP-BF561 EZ-KIT Lite 33V power supply

Jumper on P131 and P132

FPGA EZ-Extender power supply1

1 Default setting

Jumper on P132 and P133

External power supply No jumper connect supply to P132 and GND

Blackfin FPGA EZ-Extender Manual 2-9

Power

25V Header (P42)

When using an external power supply do not plug in the power supply shipped with the FPGA EZ-Extender This can seriously damage the board As an extra measure of precaution remove all jumpers from P12

12V Header (P43)

When using an external power supply do not plug in the power supply shipped with the FPGA EZ-Extender This can seriously damage the board As an extra measure of precaution remove all jumpers from P12

Power Source P42 Setting

FPGA EZ-Extender Power Supply1

1 Default setting

No Jumper

External power supply Connect P421 to external 25VConnect P422 to external GND

Power Source P43 Setting

FPGA EZ-Extender power supply1

1 Default setting

No Jumper

External power supply Connect P421 to external 25VConnect P422 to external GND

2-10 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Hardware Reference

JumpersBefore using the Blackfin FPGA EZ-Extender follow the steps in ldquoFPGA EZ-Extender Setuprdquo on page 1-1

Figure 2-3 shows the locations of all jumper headers A two-pin jumper can be placed on the respective jumper header for different functionality The following sections describe all possible jumper settings and associated functionality

Figure 2-3 Jumper Locations

Blackfin FPGA EZ-Extender Manual 2-11

Jumpers

Serial ROM Boot Jumper (JP1)By default the serial ROM boot jumper JP1 is unpopulated When unpopulated the FPGA EZ-Extender programs via the Blackfin processor or the Xilinx JTAG header

When JP1 is left populated the jumper connects the serial ROM chip enable pin to the done bit of the FPGA At power-up the done bit is driven low by the FPGA causing the FPGA to enable the serial ROM as a programming source After the FPGA is programmed the done bit is driven high by the FPGA causing the FPGA to drive high the chip enable pin of the serial ROM

Both JP1 and JP4 must be set up for correct FPGA programming ldquoBoot Jumper (JP4)rdquo on page 2-14 summarizes the JP4 settings Table 2-10 sum-marizes the JP1 settings See Table 2-4 on page 2-5 and Table 2-6 on page 2-6 for more information on JP1

Config Done Jumper (JP2) The configuration done jumper JP2 connects the done bit of the FPGA to the Blackfin processorrsquos PF3 flag pin of the ADSP-BF533 and ADSP-BF561 EZ-KIT Lites or PF14 flag pin of the ADSP-BF537 EZ-KIT

Table 2-10 JP1 Settings

Boot Source JP1 Setting

ADSP-BF533 ADSP-BF537 or ADSP-BF561 processor via VisualDSP++1

1 Default setting

Unpopulated

JTAG header Unpopulated

Serial ROM Populated

2-12 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Hardware Reference

Lite By default the jumper is populated and acts as a monitor for the done bit by the Blackfin processor (the bit indicates that the FPGA pro-gramming is complete)

Table 2-11 summarizes the jumper settings

Config Program Jumper (JP3) The configuration program jumper JP3 connects the program bit of the FPGA to the Blackfin processorrsquos flag pin By default JP3 is populated The jumper assures that the program bit is asserted by the Blackfin proces-sor to initiate the FPGA programming through VisualDSP++ software

Table 2-12 summarizes the jumper settings

Table 2-11 JP2 Settings

Functionality JP2 Setting

Done bit connected to Blackfin processorrsquos PF3 flag pin1

1 Default setting

Populated

Done bit disconnected from Blackfin processorrsquos PF3 flag pin

Unpopulated

Table 2-12 JP3 Settings

Functionality JP3 Setting

Program bit connected to the Blackfin processorrsquos flag pin1

1 Default setting

Populated

Program bit disconnected from the Blackfin proces-sorrsquos flag pin

Unpopulated

Blackfin FPGA EZ-Extender Manual 2-13

Jumpers

Boot Jumper (JP4) The boot jumper JP4 configures the FPGA mode pins (M[20]) Based on the jumper settings the FPGA is set to be programmed by the JTAG header serial ROM or Blackfin processor

Table 2-13 summarizes the jumper settings See Table 2-3 on page 2-5 for the JTAG header boot settings Table 2-5 on page 2-6 for the serial ROM boot settings and Table 2-7 on page 2-7 for the Blackfin processor boot settings

FPGA Input Jumpers (JP5) The FPGA input jumpers JP52ndash58 drive select FPGA nets to a logic 0 and can be used for any user logic that requires a steady state input You can set internal pull-ups on these nets in the FPGA and when a low is required populate the respective jumper

Table 2-14 summarizes the jumper settings

Table 2-13 JP4 Settings

Boot Source JP41 and JP42M0

JP43 and JP44M1

JP45 and JP46M2

ADSP-BF533ADSP-BF537 orADSP-BF561 processor1

1 Default setting

Unpopulated Unpopulated Unpopulated

JTAG header Unpopulated Populated Unpopulated

Serial ROM Populated Populated Populated

2-14 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Hardware Reference

Push Buttons and LEDsBefore using the Blackfin FPGA EZ-Extender follow the steps in ldquoFPGA EZ-Extender Setuprdquo on page 1-1

Figure 2-4 shows the locations of all push buttons and LEDs The follow-ing sections describe the associated functionality of all the push buttons and LEDs

Program Push Button (SW1)The program push button SW1 erases the contents of the FPGA The push button can be used as a hard resetmdashthe FPGA must be completely re-programmed once SW1 is de-pressed See ldquoProgramming the FPGArdquo on page 2-3 for more information

PB1 Push Button (SW3)The PB1 push button SW3 is a general-purpose input push button The switch with a connected debounce circuit eliminates the need to re-create it in the FPGA The push button connects to pin C11 of the FPGA

Table 2-14 JP5 Settings

Reference Designator FPGA Pin Number

JP52 Y3

JP54 Y2

JP56 U10

JP58 AB11

Blackfin FPGA EZ-Extender Manual 2-15

Push Buttons and LEDs

PB2 Push Button (SW4) The PB2 push button SW4 is a general-purpose input push button The switch does not have a connected debounce circuit you may need to cre-ate it in the FPGA if required by a specific application The push button connects to pin H5 of the FPGA

Figure 2-4 Push Button and LED Locations

2-16 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Hardware Reference

Status LEDs (LED1ndash8) Eight status LEDs LED1ndash8 connect to the FPGA and act as status flags in any application that requires it Table 2-15 shows the LEDFPGA connections

Power LED (LED9) The power LED LED9 connects to the 25V power supply and when lit signifies that the FPGA EZ-Extender is powered properly

Done LED (LED10) The done LED LED10 connects to the done pin of the FPGA At power-up the FPGA is blank and needs to be programmed When lit the LED indicates that the FPGA is programmed successfully

Table 2-15 Status LED (LED1ndash8) Settings

Reference Designator FPGA Pin Number

LED1 U11

LED2 W11

LED3 AB10

LED4 Y10

LED5 AB9

LED6 W9

LED7 AB8

LED8 V10

Blackfin FPGA EZ-Extender Manual 2-17

Connectors

ConnectorsBefore using the Blackfin FPGA EZ-Extender follow the steps in ldquoFPGA EZ-Extender Setuprdquo on page 1-1

This section describes the connector functionality and provides informa-tion about the mating connectors The connector locations are shown in Figure 2-5

Figure 2-5 Connector Locations

2-18 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Hardware Reference

Expansion Interface (P1ndash3 and J1ndash3) Connectors P1ndash3 of the expansion interface are used to plug in the EZ-Extender to the ADSP-BF533 ADSP-BF537 or ADSP-BF561 EZ-KIT Lite

Connectors J1ndash3 of the expansion interface are used to plug in another extender board such as the Blackfin USB-LAN EZ-Extender Your own custom board can be plugged into J1ndash3 as well

Plugging in another EZ-Extender or a customer board to the expansion interface can de-grade the overall system performance The extra overall load can cause the user to add wait states or slow down the system bus to get all of the boards to work properly

For the J1ndash3 and P1ndash3 connector availability and pricing contact Samtec

IDC Connectors (P8 P14 P16 and P17) The P8 P14 P16 and P17 connectors are standard 01rdquo IDC headers The connectors are in a 13 x 2 configuration and designed for signal probing bread boarding and other signal accesses

Part Description Manufacturer Part Number

90-position 005rdquo spacing SMT(J1 J2 J3)

Samtec SFC-145-T2-F-D-A

90-position 005rdquo spacing (P1 P2 P3)

Samtec TFC-145-32-F-D

Part Description Manufacturer Part Number

IDC13x2 01rdquo header Berg 54102-T08-13

Mating Connector

IDC 13x2 01rdquo plug Samtec SSW-113-01-T-D

Blackfin FPGA EZ-Extender Manual 2-19

Connectors

IDC Connectors (P5 and P7) The P5 and P7 connectors are standard 01rdquo IDC headers The connectors are in a 14 x 2 configuration and designed for signal probing bread boarding and other signal accesses

High-Speed Connector (P4) The high-speed connector P4 facilitates development of applications where use of the standard IDC connectors is complicated due to signal integrity issues

For the P4 connector and cable assembly availability and pricing contact Samtec

Part Description Manufacturer Part Number

IDC14x2 01rdquo header FCI 68737-428HLF

IDC14x2 01rdquo header Sullins GEC14DAAN

Mating Connector

IDC 14x2 01rdquo plug Samtec SSW-114-01-T-D

Part Description Manufacturer Part Number

QTS 25x2 high-speed connector Samtec QTS-025-01-F-D-A

Mating Connector

QSS 25x2 high-speed connector Samtec QSS-025-01-F-D-A

2-20 Blackfin FPGA EZ-Extender Manual

A BILL OF MATERIALS

The bill of materials corresponds to the board schematics on page B-1

Please check the latest schematics on the Analog Devices website httpwwwanalogcomProcessorsProcessorsDevelopmentToolstec

hnicalLibrarymanualsDevToolsIndexhtmlEvalua-

tion20Kit20Manuals

Blackfin FPGA EZ-Extender Manual A-1

FPGA EZ-Extender Overview

1-6 Blackfin FPGA EZ-Extender Manual

2 FPGA EZ-EXTENDER HARDWARE REFERENCE

This chapter describes the hardware design of the Field-Programmable

Gate Array (FPGA) EZ-Extender

The following topics are covered

bull ldquoSystem Architecturerdquo on page 2-2Describes the configuration of the extender board and explains how the board components interface with the processor and EZ-KIT Lite

bull ldquoProgramming the FPGArdquo on page 2-3Describes the different methods of programming the FPGA

bull ldquoProgramming the Serial ROMrdquo on page 2-7Describes the method of programming the serial ROM

bull ldquoPowerrdquo on page 2-8Describes the methods to power the extender board

bull ldquoJumpersrdquo on page 2-11Describes the function of the configuration jumpers

bull ldquoPush Buttons and LEDsrdquo on page 2-15Describes the function of the push buttons and LEDs

bull ldquoConnectorsrdquo on page 2-18Describes the function of the extender connectors

Blackfin FPGA EZ-Extender Manual 2-1

System Architecture

System ArchitectureA block diagram of the Blackfin FPGA EZ-Extender is shown in Figure 2-1

Figure 2-1 Block Diagram

X ilin xS p a rta n 3

X C 3 S 1 0 0 0 -4 F G 4 5 6 C F P G A2 M B S R A M

(5 1 2 k x 3 2 -b its )

M e m o ry In te rfa c e

S P I S P O R T (2 x ) P P I(2 x ) G P IO

T im e rs T W I

P rim a ry E x p a n s io n In te rfa c e ( to B la c k F in E Z -K IT )

S e c o n d a ry E x p a n s io n In te rfa c e (to T e s t p o in ts a n d o th e r E Z -

E x te n d e rs )

P o w e r C o n n e c to r

R e g u la to rs

3 3 V 2 5 V 1 2 V

1 in c h h e a d e rs

2 5 M H z

O s c illa to r S o c k e t

L E D D IP S w itc h P u s h B u tto n s

S P I S P O R T (2 x ) P P I(2 x ) G P IO

T im e rs T W I

S e ria l F la s h

H ig h S p e e d C o n n e c to r

J T A G C o n n e c to r

J T A G C o n n e c to r

2-2 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Hardware Reference

Programming the FPGABefore using the Blackfin FPGA EZ-Extender follow the steps in ldquoFPGA EZ-Extender Setuprdquo on page 1-1

Figure 2-2 is a block diagram of the FPGA programming connections

Figure 2-2 FPGA Programming Block Diagram

Blackfin FPGA EZ-Extender Manual 2-3

Programming the FPGA

There are three ways to program the FPGA

bull Using the FPGA JTAG header as described in ldquoFPGA Program-ming via JTAGrdquo on page 2-4

bull Using the Xilinx serial ROM as described in ldquoFPGA Programming via Serial ROMrdquo on page 2-5

bull Using the Blackfin processor as described in ldquoFPGA Programming via Blackfin Applicationrdquo on page 2-6

The done LED (LED10) lights up once the FPGA is programmed signifying that the task is complete To erase the contents of the FPGA at any time de-press the program switch SW1

FPGA Programming via JTAGTo program the FPGA via the JTAG header create the appropriate pro-gram file using the Xilinx ISE software provided at wwwxilinxcom Once the program file is created use a Xilinx JTAG cable and connect it to P15 of the FPGA EZ-Extender (the P15 connections are shown in Table 2-1)

Table 2-1 P15 Connections for PFGA Programming via JTAG

P15 Pin Number Signal Name

1 33V

2 GND

3 TCK

4 TDO

5 TDI

6 TMS

2-4 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Hardware Reference

In addition to removing JP1 (serial ROM boot jumper) as shown in Table 2-2 set the boot jumper JP4 to JTAG mode The JP4 settings for JTAG boot are shown in Table 2-3 See ldquoBoot Jumper (JP4)rdquo on page 2-14 for more information

FPGA Programming via Serial ROMTo program the FPGA with the contents of the serial ROM populate the JP1 jumper When populated JP1 connects the chip enable pin of the serial ROM to the done bit of the FPGA Once the FPGA is programmed the done bit automatically goes high and the enable pin of the serial ROM chip becomes a logic 1 The JP1 settings for serial ROM boot are shown in Table 2-4 See ldquoProgramming the Serial ROMrdquo on page 2-7 for more information

The done LED (LED10) remains lit to signify that the FPGA is pro-grammed See ldquoDone LED (LED10)rdquo on page 2-17 for more information

Table 2-2 JP1 Settings for FPGA Programming via JTAG

JP1 Pin Name Pins Connected Jumper Setting

Flash done JP11 and JP12 Unpopulated

Table 2-3 JP4 Settings for FPGA Programming via JTAG

JP4 Pin Name Pins Connected Jumper Setting

M0 JP41 and JP42 Unpopulated

M1 JP43 and JP44 Populated

M2 JP45 and JP46 Unpopulated

Table 2-4 JP1 Settings for FPGA Programming via Serial ROM

JP1 Pin Name Pins Connected Jumper Setting

Flash done JP11 and JP12 Populated

Blackfin FPGA EZ-Extender Manual 2-5

Programming the FPGA

In addition to JP1 set the boot mode jumper JP4 to master serial mode The JP4 settings for serial ROM boot are shown in Table 2-5 See ldquoBoot Jumper (JP4)rdquo on page 2-14 for more information

FPGA Programming via Blackfin ApplicationBy default the FPGA EZ-Extender is configured by the flash program-ming utility within VisualDSP++ The software is located in the hellipBlackfinEZ-KITsFPGA EZ-EXTENDER subdirectory of the VisualDSP++ installation directory The FPGA Software Readmetxt file located in the same subdirectory provides all the necessary instructions required for run-ning the application

When generating a program file using the Xilinx software tools remember to generate a slave serial program file in the Intel MCS-86 Hexadecimal Object (mcs) file format

To boot the FPGA from the Blackfin processor unpopulate jumper JP1 and set jumper JP4 to slave serial mode as shown in Table 2-6 and Table 2-7 See ldquoSerial ROM Boot Jumper (JP1)rdquo on page 2-12 and ldquoBoot Jumper (JP4)rdquo on page 2-14 for more information

Table 2-5 JP4 Settings for FPGA Programming in Master Serial Mode

JP4 Pin Name Pins Connected Jumper Setting

M0 JP41 and JP42 Populated

M1 JP43 and JP44 Populated

M2 JP45 and JP46 Populated

Table 2-6 JP1 Settings for FPGA Programming via Blackfin Processor

JP1 Pin Name Pins Connected Jumper Setting

Flash done JP11 and JP12 Unpopulated

2-6 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Hardware Reference

Programming the Serial ROMThe FPGA EZ-Extender allows the user to program the serial ROM The serial ROM can be programmed by using a Xilinx JTAG cable ISE soft-ware and the flash JTAG header on the FPGA EZ-Extender

Serial ROM via JTAG HeaderTo program the serial ROM via the JTAG header create the appropriate program file using the Xilinx software provided at wwwxilinxcom Once the program file is created use a Xilinx JTAG cable and connect it to P6 The P6 connections are shown in Table 2-8

Table 2-7 JP4 Settings for FPGA Programming via Blackfin Processor

JP4 Pin Name Pins Connected Jumper Setting

M0 JP41 and JP42 Unpopulated

M1 JP43 and JP44 Unpopulated

M2 JP45 and JP46 Unpopulated

Table 2-8 P6 Connections for Serial ROM

P6 Pin Number Signal Name P6 Pin Number Signal Name

1 33V 4 TDO

2 GND 5 TDI

3 TCK 6 TMS

Blackfin FPGA EZ-Extender Manual 2-7

Power

PowerThe FPGA EZ-Extender can be powered from the enclosed power supply EZ-KIT Lite or external power supply The power source for the extender is selected based on the power requirements of the application

An external 7V power supply is shipped with the extender board The power supply uses three switching regulators VR1 is used to power the 25V power plane VR2 is used to power the 12V power plane and VR3 is used to power the 33V plane All of the regulators can supply a maximum current of 2 Amps To understand the power requirements of your appli-cation run the Xilinx power estimator software The software can be located at wwwxilinxcom

Table 2-9 states the current limitations of each method Each method requires a correctly configured header described in the following sections

Table 2-9 Power Limitations

Power Source 12V Supply 25V Supply 33V Supply

ADSP-BF533 ADSP-BF537 or ADSP-BF561 EZ-KIT Lite

500 mA 500 mA 500 mA

FPGA EZ-Extender power supply1

1 Default setting

2A 2A 2A

External power supply 2A 2A 2A

2-8 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Hardware Reference

Power In Header (P12)The P12 header supplies the power to the on board 12V and the 25V reg-ulators The P42 and P43 headers supply the power to the external 12V and 25V planes as described in ldquo25V Header (P42)rdquo and ldquo12V Header (P43)rdquo on page 2-10

33V Header (P13)

When using an external power supply do not plug in the power supply shipped with the FPGA EZ-Extender This can seriously damage the board As an extra measure of precaution remove all jumpers from P12

Power Source P12 Setting

FPGA EZ-Extender power supply1

1 Default setting

Jumper on P121 and P122

ADSP-BF533 ADSP-BF537 or ADSP-BF561 EZ-KIT Lite 5V power supply

Jumper on P122 and P123

Power Source P13 Setting

ADSP-BF533 ADSP-BF537 or ADSP-BF561 EZ-KIT Lite 33V power supply

Jumper on P131 and P132

FPGA EZ-Extender power supply1

1 Default setting

Jumper on P132 and P133

External power supply No jumper connect supply to P132 and GND

Blackfin FPGA EZ-Extender Manual 2-9

Power

25V Header (P42)

When using an external power supply do not plug in the power supply shipped with the FPGA EZ-Extender This can seriously damage the board As an extra measure of precaution remove all jumpers from P12

12V Header (P43)

When using an external power supply do not plug in the power supply shipped with the FPGA EZ-Extender This can seriously damage the board As an extra measure of precaution remove all jumpers from P12

Power Source P42 Setting

FPGA EZ-Extender Power Supply1

1 Default setting

No Jumper

External power supply Connect P421 to external 25VConnect P422 to external GND

Power Source P43 Setting

FPGA EZ-Extender power supply1

1 Default setting

No Jumper

External power supply Connect P421 to external 25VConnect P422 to external GND

2-10 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Hardware Reference

JumpersBefore using the Blackfin FPGA EZ-Extender follow the steps in ldquoFPGA EZ-Extender Setuprdquo on page 1-1

Figure 2-3 shows the locations of all jumper headers A two-pin jumper can be placed on the respective jumper header for different functionality The following sections describe all possible jumper settings and associated functionality

Figure 2-3 Jumper Locations

Blackfin FPGA EZ-Extender Manual 2-11

Jumpers

Serial ROM Boot Jumper (JP1)By default the serial ROM boot jumper JP1 is unpopulated When unpopulated the FPGA EZ-Extender programs via the Blackfin processor or the Xilinx JTAG header

When JP1 is left populated the jumper connects the serial ROM chip enable pin to the done bit of the FPGA At power-up the done bit is driven low by the FPGA causing the FPGA to enable the serial ROM as a programming source After the FPGA is programmed the done bit is driven high by the FPGA causing the FPGA to drive high the chip enable pin of the serial ROM

Both JP1 and JP4 must be set up for correct FPGA programming ldquoBoot Jumper (JP4)rdquo on page 2-14 summarizes the JP4 settings Table 2-10 sum-marizes the JP1 settings See Table 2-4 on page 2-5 and Table 2-6 on page 2-6 for more information on JP1

Config Done Jumper (JP2) The configuration done jumper JP2 connects the done bit of the FPGA to the Blackfin processorrsquos PF3 flag pin of the ADSP-BF533 and ADSP-BF561 EZ-KIT Lites or PF14 flag pin of the ADSP-BF537 EZ-KIT

Table 2-10 JP1 Settings

Boot Source JP1 Setting

ADSP-BF533 ADSP-BF537 or ADSP-BF561 processor via VisualDSP++1

1 Default setting

Unpopulated

JTAG header Unpopulated

Serial ROM Populated

2-12 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Hardware Reference

Lite By default the jumper is populated and acts as a monitor for the done bit by the Blackfin processor (the bit indicates that the FPGA pro-gramming is complete)

Table 2-11 summarizes the jumper settings

Config Program Jumper (JP3) The configuration program jumper JP3 connects the program bit of the FPGA to the Blackfin processorrsquos flag pin By default JP3 is populated The jumper assures that the program bit is asserted by the Blackfin proces-sor to initiate the FPGA programming through VisualDSP++ software

Table 2-12 summarizes the jumper settings

Table 2-11 JP2 Settings

Functionality JP2 Setting

Done bit connected to Blackfin processorrsquos PF3 flag pin1

1 Default setting

Populated

Done bit disconnected from Blackfin processorrsquos PF3 flag pin

Unpopulated

Table 2-12 JP3 Settings

Functionality JP3 Setting

Program bit connected to the Blackfin processorrsquos flag pin1

1 Default setting

Populated

Program bit disconnected from the Blackfin proces-sorrsquos flag pin

Unpopulated

Blackfin FPGA EZ-Extender Manual 2-13

Jumpers

Boot Jumper (JP4) The boot jumper JP4 configures the FPGA mode pins (M[20]) Based on the jumper settings the FPGA is set to be programmed by the JTAG header serial ROM or Blackfin processor

Table 2-13 summarizes the jumper settings See Table 2-3 on page 2-5 for the JTAG header boot settings Table 2-5 on page 2-6 for the serial ROM boot settings and Table 2-7 on page 2-7 for the Blackfin processor boot settings

FPGA Input Jumpers (JP5) The FPGA input jumpers JP52ndash58 drive select FPGA nets to a logic 0 and can be used for any user logic that requires a steady state input You can set internal pull-ups on these nets in the FPGA and when a low is required populate the respective jumper

Table 2-14 summarizes the jumper settings

Table 2-13 JP4 Settings

Boot Source JP41 and JP42M0

JP43 and JP44M1

JP45 and JP46M2

ADSP-BF533ADSP-BF537 orADSP-BF561 processor1

1 Default setting

Unpopulated Unpopulated Unpopulated

JTAG header Unpopulated Populated Unpopulated

Serial ROM Populated Populated Populated

2-14 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Hardware Reference

Push Buttons and LEDsBefore using the Blackfin FPGA EZ-Extender follow the steps in ldquoFPGA EZ-Extender Setuprdquo on page 1-1

Figure 2-4 shows the locations of all push buttons and LEDs The follow-ing sections describe the associated functionality of all the push buttons and LEDs

Program Push Button (SW1)The program push button SW1 erases the contents of the FPGA The push button can be used as a hard resetmdashthe FPGA must be completely re-programmed once SW1 is de-pressed See ldquoProgramming the FPGArdquo on page 2-3 for more information

PB1 Push Button (SW3)The PB1 push button SW3 is a general-purpose input push button The switch with a connected debounce circuit eliminates the need to re-create it in the FPGA The push button connects to pin C11 of the FPGA

Table 2-14 JP5 Settings

Reference Designator FPGA Pin Number

JP52 Y3

JP54 Y2

JP56 U10

JP58 AB11

Blackfin FPGA EZ-Extender Manual 2-15

Push Buttons and LEDs

PB2 Push Button (SW4) The PB2 push button SW4 is a general-purpose input push button The switch does not have a connected debounce circuit you may need to cre-ate it in the FPGA if required by a specific application The push button connects to pin H5 of the FPGA

Figure 2-4 Push Button and LED Locations

2-16 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Hardware Reference

Status LEDs (LED1ndash8) Eight status LEDs LED1ndash8 connect to the FPGA and act as status flags in any application that requires it Table 2-15 shows the LEDFPGA connections

Power LED (LED9) The power LED LED9 connects to the 25V power supply and when lit signifies that the FPGA EZ-Extender is powered properly

Done LED (LED10) The done LED LED10 connects to the done pin of the FPGA At power-up the FPGA is blank and needs to be programmed When lit the LED indicates that the FPGA is programmed successfully

Table 2-15 Status LED (LED1ndash8) Settings

Reference Designator FPGA Pin Number

LED1 U11

LED2 W11

LED3 AB10

LED4 Y10

LED5 AB9

LED6 W9

LED7 AB8

LED8 V10

Blackfin FPGA EZ-Extender Manual 2-17

Connectors

ConnectorsBefore using the Blackfin FPGA EZ-Extender follow the steps in ldquoFPGA EZ-Extender Setuprdquo on page 1-1

This section describes the connector functionality and provides informa-tion about the mating connectors The connector locations are shown in Figure 2-5

Figure 2-5 Connector Locations

2-18 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Hardware Reference

Expansion Interface (P1ndash3 and J1ndash3) Connectors P1ndash3 of the expansion interface are used to plug in the EZ-Extender to the ADSP-BF533 ADSP-BF537 or ADSP-BF561 EZ-KIT Lite

Connectors J1ndash3 of the expansion interface are used to plug in another extender board such as the Blackfin USB-LAN EZ-Extender Your own custom board can be plugged into J1ndash3 as well

Plugging in another EZ-Extender or a customer board to the expansion interface can de-grade the overall system performance The extra overall load can cause the user to add wait states or slow down the system bus to get all of the boards to work properly

For the J1ndash3 and P1ndash3 connector availability and pricing contact Samtec

IDC Connectors (P8 P14 P16 and P17) The P8 P14 P16 and P17 connectors are standard 01rdquo IDC headers The connectors are in a 13 x 2 configuration and designed for signal probing bread boarding and other signal accesses

Part Description Manufacturer Part Number

90-position 005rdquo spacing SMT(J1 J2 J3)

Samtec SFC-145-T2-F-D-A

90-position 005rdquo spacing (P1 P2 P3)

Samtec TFC-145-32-F-D

Part Description Manufacturer Part Number

IDC13x2 01rdquo header Berg 54102-T08-13

Mating Connector

IDC 13x2 01rdquo plug Samtec SSW-113-01-T-D

Blackfin FPGA EZ-Extender Manual 2-19

Connectors

IDC Connectors (P5 and P7) The P5 and P7 connectors are standard 01rdquo IDC headers The connectors are in a 14 x 2 configuration and designed for signal probing bread boarding and other signal accesses

High-Speed Connector (P4) The high-speed connector P4 facilitates development of applications where use of the standard IDC connectors is complicated due to signal integrity issues

For the P4 connector and cable assembly availability and pricing contact Samtec

Part Description Manufacturer Part Number

IDC14x2 01rdquo header FCI 68737-428HLF

IDC14x2 01rdquo header Sullins GEC14DAAN

Mating Connector

IDC 14x2 01rdquo plug Samtec SSW-114-01-T-D

Part Description Manufacturer Part Number

QTS 25x2 high-speed connector Samtec QTS-025-01-F-D-A

Mating Connector

QSS 25x2 high-speed connector Samtec QSS-025-01-F-D-A

2-20 Blackfin FPGA EZ-Extender Manual

A BILL OF MATERIALS

The bill of materials corresponds to the board schematics on page B-1

Please check the latest schematics on the Analog Devices website httpwwwanalogcomProcessorsProcessorsDevelopmentToolstec

hnicalLibrarymanualsDevToolsIndexhtmlEvalua-

tion20Kit20Manuals

Blackfin FPGA EZ-Extender Manual A-1

2 FPGA EZ-EXTENDER HARDWARE REFERENCE

This chapter describes the hardware design of the Field-Programmable

Gate Array (FPGA) EZ-Extender

The following topics are covered

bull ldquoSystem Architecturerdquo on page 2-2Describes the configuration of the extender board and explains how the board components interface with the processor and EZ-KIT Lite

bull ldquoProgramming the FPGArdquo on page 2-3Describes the different methods of programming the FPGA

bull ldquoProgramming the Serial ROMrdquo on page 2-7Describes the method of programming the serial ROM

bull ldquoPowerrdquo on page 2-8Describes the methods to power the extender board

bull ldquoJumpersrdquo on page 2-11Describes the function of the configuration jumpers

bull ldquoPush Buttons and LEDsrdquo on page 2-15Describes the function of the push buttons and LEDs

bull ldquoConnectorsrdquo on page 2-18Describes the function of the extender connectors

Blackfin FPGA EZ-Extender Manual 2-1

System Architecture

System ArchitectureA block diagram of the Blackfin FPGA EZ-Extender is shown in Figure 2-1

Figure 2-1 Block Diagram

X ilin xS p a rta n 3

X C 3 S 1 0 0 0 -4 F G 4 5 6 C F P G A2 M B S R A M

(5 1 2 k x 3 2 -b its )

M e m o ry In te rfa c e

S P I S P O R T (2 x ) P P I(2 x ) G P IO

T im e rs T W I

P rim a ry E x p a n s io n In te rfa c e ( to B la c k F in E Z -K IT )

S e c o n d a ry E x p a n s io n In te rfa c e (to T e s t p o in ts a n d o th e r E Z -

E x te n d e rs )

P o w e r C o n n e c to r

R e g u la to rs

3 3 V 2 5 V 1 2 V

1 in c h h e a d e rs

2 5 M H z

O s c illa to r S o c k e t

L E D D IP S w itc h P u s h B u tto n s

S P I S P O R T (2 x ) P P I(2 x ) G P IO

T im e rs T W I

S e ria l F la s h

H ig h S p e e d C o n n e c to r

J T A G C o n n e c to r

J T A G C o n n e c to r

2-2 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Hardware Reference

Programming the FPGABefore using the Blackfin FPGA EZ-Extender follow the steps in ldquoFPGA EZ-Extender Setuprdquo on page 1-1

Figure 2-2 is a block diagram of the FPGA programming connections

Figure 2-2 FPGA Programming Block Diagram

Blackfin FPGA EZ-Extender Manual 2-3

Programming the FPGA

There are three ways to program the FPGA

bull Using the FPGA JTAG header as described in ldquoFPGA Program-ming via JTAGrdquo on page 2-4

bull Using the Xilinx serial ROM as described in ldquoFPGA Programming via Serial ROMrdquo on page 2-5

bull Using the Blackfin processor as described in ldquoFPGA Programming via Blackfin Applicationrdquo on page 2-6

The done LED (LED10) lights up once the FPGA is programmed signifying that the task is complete To erase the contents of the FPGA at any time de-press the program switch SW1

FPGA Programming via JTAGTo program the FPGA via the JTAG header create the appropriate pro-gram file using the Xilinx ISE software provided at wwwxilinxcom Once the program file is created use a Xilinx JTAG cable and connect it to P15 of the FPGA EZ-Extender (the P15 connections are shown in Table 2-1)

Table 2-1 P15 Connections for PFGA Programming via JTAG

P15 Pin Number Signal Name

1 33V

2 GND

3 TCK

4 TDO

5 TDI

6 TMS

2-4 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Hardware Reference

In addition to removing JP1 (serial ROM boot jumper) as shown in Table 2-2 set the boot jumper JP4 to JTAG mode The JP4 settings for JTAG boot are shown in Table 2-3 See ldquoBoot Jumper (JP4)rdquo on page 2-14 for more information

FPGA Programming via Serial ROMTo program the FPGA with the contents of the serial ROM populate the JP1 jumper When populated JP1 connects the chip enable pin of the serial ROM to the done bit of the FPGA Once the FPGA is programmed the done bit automatically goes high and the enable pin of the serial ROM chip becomes a logic 1 The JP1 settings for serial ROM boot are shown in Table 2-4 See ldquoProgramming the Serial ROMrdquo on page 2-7 for more information

The done LED (LED10) remains lit to signify that the FPGA is pro-grammed See ldquoDone LED (LED10)rdquo on page 2-17 for more information

Table 2-2 JP1 Settings for FPGA Programming via JTAG

JP1 Pin Name Pins Connected Jumper Setting

Flash done JP11 and JP12 Unpopulated

Table 2-3 JP4 Settings for FPGA Programming via JTAG

JP4 Pin Name Pins Connected Jumper Setting

M0 JP41 and JP42 Unpopulated

M1 JP43 and JP44 Populated

M2 JP45 and JP46 Unpopulated

Table 2-4 JP1 Settings for FPGA Programming via Serial ROM

JP1 Pin Name Pins Connected Jumper Setting

Flash done JP11 and JP12 Populated

Blackfin FPGA EZ-Extender Manual 2-5

Programming the FPGA

In addition to JP1 set the boot mode jumper JP4 to master serial mode The JP4 settings for serial ROM boot are shown in Table 2-5 See ldquoBoot Jumper (JP4)rdquo on page 2-14 for more information

FPGA Programming via Blackfin ApplicationBy default the FPGA EZ-Extender is configured by the flash program-ming utility within VisualDSP++ The software is located in the hellipBlackfinEZ-KITsFPGA EZ-EXTENDER subdirectory of the VisualDSP++ installation directory The FPGA Software Readmetxt file located in the same subdirectory provides all the necessary instructions required for run-ning the application

When generating a program file using the Xilinx software tools remember to generate a slave serial program file in the Intel MCS-86 Hexadecimal Object (mcs) file format

To boot the FPGA from the Blackfin processor unpopulate jumper JP1 and set jumper JP4 to slave serial mode as shown in Table 2-6 and Table 2-7 See ldquoSerial ROM Boot Jumper (JP1)rdquo on page 2-12 and ldquoBoot Jumper (JP4)rdquo on page 2-14 for more information

Table 2-5 JP4 Settings for FPGA Programming in Master Serial Mode

JP4 Pin Name Pins Connected Jumper Setting

M0 JP41 and JP42 Populated

M1 JP43 and JP44 Populated

M2 JP45 and JP46 Populated

Table 2-6 JP1 Settings for FPGA Programming via Blackfin Processor

JP1 Pin Name Pins Connected Jumper Setting

Flash done JP11 and JP12 Unpopulated

2-6 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Hardware Reference

Programming the Serial ROMThe FPGA EZ-Extender allows the user to program the serial ROM The serial ROM can be programmed by using a Xilinx JTAG cable ISE soft-ware and the flash JTAG header on the FPGA EZ-Extender

Serial ROM via JTAG HeaderTo program the serial ROM via the JTAG header create the appropriate program file using the Xilinx software provided at wwwxilinxcom Once the program file is created use a Xilinx JTAG cable and connect it to P6 The P6 connections are shown in Table 2-8

Table 2-7 JP4 Settings for FPGA Programming via Blackfin Processor

JP4 Pin Name Pins Connected Jumper Setting

M0 JP41 and JP42 Unpopulated

M1 JP43 and JP44 Unpopulated

M2 JP45 and JP46 Unpopulated

Table 2-8 P6 Connections for Serial ROM

P6 Pin Number Signal Name P6 Pin Number Signal Name

1 33V 4 TDO

2 GND 5 TDI

3 TCK 6 TMS

Blackfin FPGA EZ-Extender Manual 2-7

Power

PowerThe FPGA EZ-Extender can be powered from the enclosed power supply EZ-KIT Lite or external power supply The power source for the extender is selected based on the power requirements of the application

An external 7V power supply is shipped with the extender board The power supply uses three switching regulators VR1 is used to power the 25V power plane VR2 is used to power the 12V power plane and VR3 is used to power the 33V plane All of the regulators can supply a maximum current of 2 Amps To understand the power requirements of your appli-cation run the Xilinx power estimator software The software can be located at wwwxilinxcom

Table 2-9 states the current limitations of each method Each method requires a correctly configured header described in the following sections

Table 2-9 Power Limitations

Power Source 12V Supply 25V Supply 33V Supply

ADSP-BF533 ADSP-BF537 or ADSP-BF561 EZ-KIT Lite

500 mA 500 mA 500 mA

FPGA EZ-Extender power supply1

1 Default setting

2A 2A 2A

External power supply 2A 2A 2A

2-8 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Hardware Reference

Power In Header (P12)The P12 header supplies the power to the on board 12V and the 25V reg-ulators The P42 and P43 headers supply the power to the external 12V and 25V planes as described in ldquo25V Header (P42)rdquo and ldquo12V Header (P43)rdquo on page 2-10

33V Header (P13)

When using an external power supply do not plug in the power supply shipped with the FPGA EZ-Extender This can seriously damage the board As an extra measure of precaution remove all jumpers from P12

Power Source P12 Setting

FPGA EZ-Extender power supply1

1 Default setting

Jumper on P121 and P122

ADSP-BF533 ADSP-BF537 or ADSP-BF561 EZ-KIT Lite 5V power supply

Jumper on P122 and P123

Power Source P13 Setting

ADSP-BF533 ADSP-BF537 or ADSP-BF561 EZ-KIT Lite 33V power supply

Jumper on P131 and P132

FPGA EZ-Extender power supply1

1 Default setting

Jumper on P132 and P133

External power supply No jumper connect supply to P132 and GND

Blackfin FPGA EZ-Extender Manual 2-9

Power

25V Header (P42)

When using an external power supply do not plug in the power supply shipped with the FPGA EZ-Extender This can seriously damage the board As an extra measure of precaution remove all jumpers from P12

12V Header (P43)

When using an external power supply do not plug in the power supply shipped with the FPGA EZ-Extender This can seriously damage the board As an extra measure of precaution remove all jumpers from P12

Power Source P42 Setting

FPGA EZ-Extender Power Supply1

1 Default setting

No Jumper

External power supply Connect P421 to external 25VConnect P422 to external GND

Power Source P43 Setting

FPGA EZ-Extender power supply1

1 Default setting

No Jumper

External power supply Connect P421 to external 25VConnect P422 to external GND

2-10 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Hardware Reference

JumpersBefore using the Blackfin FPGA EZ-Extender follow the steps in ldquoFPGA EZ-Extender Setuprdquo on page 1-1

Figure 2-3 shows the locations of all jumper headers A two-pin jumper can be placed on the respective jumper header for different functionality The following sections describe all possible jumper settings and associated functionality

Figure 2-3 Jumper Locations

Blackfin FPGA EZ-Extender Manual 2-11

Jumpers

Serial ROM Boot Jumper (JP1)By default the serial ROM boot jumper JP1 is unpopulated When unpopulated the FPGA EZ-Extender programs via the Blackfin processor or the Xilinx JTAG header

When JP1 is left populated the jumper connects the serial ROM chip enable pin to the done bit of the FPGA At power-up the done bit is driven low by the FPGA causing the FPGA to enable the serial ROM as a programming source After the FPGA is programmed the done bit is driven high by the FPGA causing the FPGA to drive high the chip enable pin of the serial ROM

Both JP1 and JP4 must be set up for correct FPGA programming ldquoBoot Jumper (JP4)rdquo on page 2-14 summarizes the JP4 settings Table 2-10 sum-marizes the JP1 settings See Table 2-4 on page 2-5 and Table 2-6 on page 2-6 for more information on JP1

Config Done Jumper (JP2) The configuration done jumper JP2 connects the done bit of the FPGA to the Blackfin processorrsquos PF3 flag pin of the ADSP-BF533 and ADSP-BF561 EZ-KIT Lites or PF14 flag pin of the ADSP-BF537 EZ-KIT

Table 2-10 JP1 Settings

Boot Source JP1 Setting

ADSP-BF533 ADSP-BF537 or ADSP-BF561 processor via VisualDSP++1

1 Default setting

Unpopulated

JTAG header Unpopulated

Serial ROM Populated

2-12 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Hardware Reference

Lite By default the jumper is populated and acts as a monitor for the done bit by the Blackfin processor (the bit indicates that the FPGA pro-gramming is complete)

Table 2-11 summarizes the jumper settings

Config Program Jumper (JP3) The configuration program jumper JP3 connects the program bit of the FPGA to the Blackfin processorrsquos flag pin By default JP3 is populated The jumper assures that the program bit is asserted by the Blackfin proces-sor to initiate the FPGA programming through VisualDSP++ software

Table 2-12 summarizes the jumper settings

Table 2-11 JP2 Settings

Functionality JP2 Setting

Done bit connected to Blackfin processorrsquos PF3 flag pin1

1 Default setting

Populated

Done bit disconnected from Blackfin processorrsquos PF3 flag pin

Unpopulated

Table 2-12 JP3 Settings

Functionality JP3 Setting

Program bit connected to the Blackfin processorrsquos flag pin1

1 Default setting

Populated

Program bit disconnected from the Blackfin proces-sorrsquos flag pin

Unpopulated

Blackfin FPGA EZ-Extender Manual 2-13

Jumpers

Boot Jumper (JP4) The boot jumper JP4 configures the FPGA mode pins (M[20]) Based on the jumper settings the FPGA is set to be programmed by the JTAG header serial ROM or Blackfin processor

Table 2-13 summarizes the jumper settings See Table 2-3 on page 2-5 for the JTAG header boot settings Table 2-5 on page 2-6 for the serial ROM boot settings and Table 2-7 on page 2-7 for the Blackfin processor boot settings

FPGA Input Jumpers (JP5) The FPGA input jumpers JP52ndash58 drive select FPGA nets to a logic 0 and can be used for any user logic that requires a steady state input You can set internal pull-ups on these nets in the FPGA and when a low is required populate the respective jumper

Table 2-14 summarizes the jumper settings

Table 2-13 JP4 Settings

Boot Source JP41 and JP42M0

JP43 and JP44M1

JP45 and JP46M2

ADSP-BF533ADSP-BF537 orADSP-BF561 processor1

1 Default setting

Unpopulated Unpopulated Unpopulated

JTAG header Unpopulated Populated Unpopulated

Serial ROM Populated Populated Populated

2-14 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Hardware Reference

Push Buttons and LEDsBefore using the Blackfin FPGA EZ-Extender follow the steps in ldquoFPGA EZ-Extender Setuprdquo on page 1-1

Figure 2-4 shows the locations of all push buttons and LEDs The follow-ing sections describe the associated functionality of all the push buttons and LEDs

Program Push Button (SW1)The program push button SW1 erases the contents of the FPGA The push button can be used as a hard resetmdashthe FPGA must be completely re-programmed once SW1 is de-pressed See ldquoProgramming the FPGArdquo on page 2-3 for more information

PB1 Push Button (SW3)The PB1 push button SW3 is a general-purpose input push button The switch with a connected debounce circuit eliminates the need to re-create it in the FPGA The push button connects to pin C11 of the FPGA

Table 2-14 JP5 Settings

Reference Designator FPGA Pin Number

JP52 Y3

JP54 Y2

JP56 U10

JP58 AB11

Blackfin FPGA EZ-Extender Manual 2-15

Push Buttons and LEDs

PB2 Push Button (SW4) The PB2 push button SW4 is a general-purpose input push button The switch does not have a connected debounce circuit you may need to cre-ate it in the FPGA if required by a specific application The push button connects to pin H5 of the FPGA

Figure 2-4 Push Button and LED Locations

2-16 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Hardware Reference

Status LEDs (LED1ndash8) Eight status LEDs LED1ndash8 connect to the FPGA and act as status flags in any application that requires it Table 2-15 shows the LEDFPGA connections

Power LED (LED9) The power LED LED9 connects to the 25V power supply and when lit signifies that the FPGA EZ-Extender is powered properly

Done LED (LED10) The done LED LED10 connects to the done pin of the FPGA At power-up the FPGA is blank and needs to be programmed When lit the LED indicates that the FPGA is programmed successfully

Table 2-15 Status LED (LED1ndash8) Settings

Reference Designator FPGA Pin Number

LED1 U11

LED2 W11

LED3 AB10

LED4 Y10

LED5 AB9

LED6 W9

LED7 AB8

LED8 V10

Blackfin FPGA EZ-Extender Manual 2-17

Connectors

ConnectorsBefore using the Blackfin FPGA EZ-Extender follow the steps in ldquoFPGA EZ-Extender Setuprdquo on page 1-1

This section describes the connector functionality and provides informa-tion about the mating connectors The connector locations are shown in Figure 2-5

Figure 2-5 Connector Locations

2-18 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Hardware Reference

Expansion Interface (P1ndash3 and J1ndash3) Connectors P1ndash3 of the expansion interface are used to plug in the EZ-Extender to the ADSP-BF533 ADSP-BF537 or ADSP-BF561 EZ-KIT Lite

Connectors J1ndash3 of the expansion interface are used to plug in another extender board such as the Blackfin USB-LAN EZ-Extender Your own custom board can be plugged into J1ndash3 as well

Plugging in another EZ-Extender or a customer board to the expansion interface can de-grade the overall system performance The extra overall load can cause the user to add wait states or slow down the system bus to get all of the boards to work properly

For the J1ndash3 and P1ndash3 connector availability and pricing contact Samtec

IDC Connectors (P8 P14 P16 and P17) The P8 P14 P16 and P17 connectors are standard 01rdquo IDC headers The connectors are in a 13 x 2 configuration and designed for signal probing bread boarding and other signal accesses

Part Description Manufacturer Part Number

90-position 005rdquo spacing SMT(J1 J2 J3)

Samtec SFC-145-T2-F-D-A

90-position 005rdquo spacing (P1 P2 P3)

Samtec TFC-145-32-F-D

Part Description Manufacturer Part Number

IDC13x2 01rdquo header Berg 54102-T08-13

Mating Connector

IDC 13x2 01rdquo plug Samtec SSW-113-01-T-D

Blackfin FPGA EZ-Extender Manual 2-19

Connectors

IDC Connectors (P5 and P7) The P5 and P7 connectors are standard 01rdquo IDC headers The connectors are in a 14 x 2 configuration and designed for signal probing bread boarding and other signal accesses

High-Speed Connector (P4) The high-speed connector P4 facilitates development of applications where use of the standard IDC connectors is complicated due to signal integrity issues

For the P4 connector and cable assembly availability and pricing contact Samtec

Part Description Manufacturer Part Number

IDC14x2 01rdquo header FCI 68737-428HLF

IDC14x2 01rdquo header Sullins GEC14DAAN

Mating Connector

IDC 14x2 01rdquo plug Samtec SSW-114-01-T-D

Part Description Manufacturer Part Number

QTS 25x2 high-speed connector Samtec QTS-025-01-F-D-A

Mating Connector

QSS 25x2 high-speed connector Samtec QSS-025-01-F-D-A

2-20 Blackfin FPGA EZ-Extender Manual

A BILL OF MATERIALS

The bill of materials corresponds to the board schematics on page B-1

Please check the latest schematics on the Analog Devices website httpwwwanalogcomProcessorsProcessorsDevelopmentToolstec

hnicalLibrarymanualsDevToolsIndexhtmlEvalua-

tion20Kit20Manuals

Blackfin FPGA EZ-Extender Manual A-1

System Architecture

System ArchitectureA block diagram of the Blackfin FPGA EZ-Extender is shown in Figure 2-1

Figure 2-1 Block Diagram

X ilin xS p a rta n 3

X C 3 S 1 0 0 0 -4 F G 4 5 6 C F P G A2 M B S R A M

(5 1 2 k x 3 2 -b its )

M e m o ry In te rfa c e

S P I S P O R T (2 x ) P P I(2 x ) G P IO

T im e rs T W I

P rim a ry E x p a n s io n In te rfa c e ( to B la c k F in E Z -K IT )

S e c o n d a ry E x p a n s io n In te rfa c e (to T e s t p o in ts a n d o th e r E Z -

E x te n d e rs )

P o w e r C o n n e c to r

R e g u la to rs

3 3 V 2 5 V 1 2 V

1 in c h h e a d e rs

2 5 M H z

O s c illa to r S o c k e t

L E D D IP S w itc h P u s h B u tto n s

S P I S P O R T (2 x ) P P I(2 x ) G P IO

T im e rs T W I

S e ria l F la s h

H ig h S p e e d C o n n e c to r

J T A G C o n n e c to r

J T A G C o n n e c to r

2-2 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Hardware Reference

Programming the FPGABefore using the Blackfin FPGA EZ-Extender follow the steps in ldquoFPGA EZ-Extender Setuprdquo on page 1-1

Figure 2-2 is a block diagram of the FPGA programming connections

Figure 2-2 FPGA Programming Block Diagram

Blackfin FPGA EZ-Extender Manual 2-3

Programming the FPGA

There are three ways to program the FPGA

bull Using the FPGA JTAG header as described in ldquoFPGA Program-ming via JTAGrdquo on page 2-4

bull Using the Xilinx serial ROM as described in ldquoFPGA Programming via Serial ROMrdquo on page 2-5

bull Using the Blackfin processor as described in ldquoFPGA Programming via Blackfin Applicationrdquo on page 2-6

The done LED (LED10) lights up once the FPGA is programmed signifying that the task is complete To erase the contents of the FPGA at any time de-press the program switch SW1

FPGA Programming via JTAGTo program the FPGA via the JTAG header create the appropriate pro-gram file using the Xilinx ISE software provided at wwwxilinxcom Once the program file is created use a Xilinx JTAG cable and connect it to P15 of the FPGA EZ-Extender (the P15 connections are shown in Table 2-1)

Table 2-1 P15 Connections for PFGA Programming via JTAG

P15 Pin Number Signal Name

1 33V

2 GND

3 TCK

4 TDO

5 TDI

6 TMS

2-4 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Hardware Reference

In addition to removing JP1 (serial ROM boot jumper) as shown in Table 2-2 set the boot jumper JP4 to JTAG mode The JP4 settings for JTAG boot are shown in Table 2-3 See ldquoBoot Jumper (JP4)rdquo on page 2-14 for more information

FPGA Programming via Serial ROMTo program the FPGA with the contents of the serial ROM populate the JP1 jumper When populated JP1 connects the chip enable pin of the serial ROM to the done bit of the FPGA Once the FPGA is programmed the done bit automatically goes high and the enable pin of the serial ROM chip becomes a logic 1 The JP1 settings for serial ROM boot are shown in Table 2-4 See ldquoProgramming the Serial ROMrdquo on page 2-7 for more information

The done LED (LED10) remains lit to signify that the FPGA is pro-grammed See ldquoDone LED (LED10)rdquo on page 2-17 for more information

Table 2-2 JP1 Settings for FPGA Programming via JTAG

JP1 Pin Name Pins Connected Jumper Setting

Flash done JP11 and JP12 Unpopulated

Table 2-3 JP4 Settings for FPGA Programming via JTAG

JP4 Pin Name Pins Connected Jumper Setting

M0 JP41 and JP42 Unpopulated

M1 JP43 and JP44 Populated

M2 JP45 and JP46 Unpopulated

Table 2-4 JP1 Settings for FPGA Programming via Serial ROM

JP1 Pin Name Pins Connected Jumper Setting

Flash done JP11 and JP12 Populated

Blackfin FPGA EZ-Extender Manual 2-5

Programming the FPGA

In addition to JP1 set the boot mode jumper JP4 to master serial mode The JP4 settings for serial ROM boot are shown in Table 2-5 See ldquoBoot Jumper (JP4)rdquo on page 2-14 for more information

FPGA Programming via Blackfin ApplicationBy default the FPGA EZ-Extender is configured by the flash program-ming utility within VisualDSP++ The software is located in the hellipBlackfinEZ-KITsFPGA EZ-EXTENDER subdirectory of the VisualDSP++ installation directory The FPGA Software Readmetxt file located in the same subdirectory provides all the necessary instructions required for run-ning the application

When generating a program file using the Xilinx software tools remember to generate a slave serial program file in the Intel MCS-86 Hexadecimal Object (mcs) file format

To boot the FPGA from the Blackfin processor unpopulate jumper JP1 and set jumper JP4 to slave serial mode as shown in Table 2-6 and Table 2-7 See ldquoSerial ROM Boot Jumper (JP1)rdquo on page 2-12 and ldquoBoot Jumper (JP4)rdquo on page 2-14 for more information

Table 2-5 JP4 Settings for FPGA Programming in Master Serial Mode

JP4 Pin Name Pins Connected Jumper Setting

M0 JP41 and JP42 Populated

M1 JP43 and JP44 Populated

M2 JP45 and JP46 Populated

Table 2-6 JP1 Settings for FPGA Programming via Blackfin Processor

JP1 Pin Name Pins Connected Jumper Setting

Flash done JP11 and JP12 Unpopulated

2-6 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Hardware Reference

Programming the Serial ROMThe FPGA EZ-Extender allows the user to program the serial ROM The serial ROM can be programmed by using a Xilinx JTAG cable ISE soft-ware and the flash JTAG header on the FPGA EZ-Extender

Serial ROM via JTAG HeaderTo program the serial ROM via the JTAG header create the appropriate program file using the Xilinx software provided at wwwxilinxcom Once the program file is created use a Xilinx JTAG cable and connect it to P6 The P6 connections are shown in Table 2-8

Table 2-7 JP4 Settings for FPGA Programming via Blackfin Processor

JP4 Pin Name Pins Connected Jumper Setting

M0 JP41 and JP42 Unpopulated

M1 JP43 and JP44 Unpopulated

M2 JP45 and JP46 Unpopulated

Table 2-8 P6 Connections for Serial ROM

P6 Pin Number Signal Name P6 Pin Number Signal Name

1 33V 4 TDO

2 GND 5 TDI

3 TCK 6 TMS

Blackfin FPGA EZ-Extender Manual 2-7

Power

PowerThe FPGA EZ-Extender can be powered from the enclosed power supply EZ-KIT Lite or external power supply The power source for the extender is selected based on the power requirements of the application

An external 7V power supply is shipped with the extender board The power supply uses three switching regulators VR1 is used to power the 25V power plane VR2 is used to power the 12V power plane and VR3 is used to power the 33V plane All of the regulators can supply a maximum current of 2 Amps To understand the power requirements of your appli-cation run the Xilinx power estimator software The software can be located at wwwxilinxcom

Table 2-9 states the current limitations of each method Each method requires a correctly configured header described in the following sections

Table 2-9 Power Limitations

Power Source 12V Supply 25V Supply 33V Supply

ADSP-BF533 ADSP-BF537 or ADSP-BF561 EZ-KIT Lite

500 mA 500 mA 500 mA

FPGA EZ-Extender power supply1

1 Default setting

2A 2A 2A

External power supply 2A 2A 2A

2-8 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Hardware Reference

Power In Header (P12)The P12 header supplies the power to the on board 12V and the 25V reg-ulators The P42 and P43 headers supply the power to the external 12V and 25V planes as described in ldquo25V Header (P42)rdquo and ldquo12V Header (P43)rdquo on page 2-10

33V Header (P13)

When using an external power supply do not plug in the power supply shipped with the FPGA EZ-Extender This can seriously damage the board As an extra measure of precaution remove all jumpers from P12

Power Source P12 Setting

FPGA EZ-Extender power supply1

1 Default setting

Jumper on P121 and P122

ADSP-BF533 ADSP-BF537 or ADSP-BF561 EZ-KIT Lite 5V power supply

Jumper on P122 and P123

Power Source P13 Setting

ADSP-BF533 ADSP-BF537 or ADSP-BF561 EZ-KIT Lite 33V power supply

Jumper on P131 and P132

FPGA EZ-Extender power supply1

1 Default setting

Jumper on P132 and P133

External power supply No jumper connect supply to P132 and GND

Blackfin FPGA EZ-Extender Manual 2-9

Power

25V Header (P42)

When using an external power supply do not plug in the power supply shipped with the FPGA EZ-Extender This can seriously damage the board As an extra measure of precaution remove all jumpers from P12

12V Header (P43)

When using an external power supply do not plug in the power supply shipped with the FPGA EZ-Extender This can seriously damage the board As an extra measure of precaution remove all jumpers from P12

Power Source P42 Setting

FPGA EZ-Extender Power Supply1

1 Default setting

No Jumper

External power supply Connect P421 to external 25VConnect P422 to external GND

Power Source P43 Setting

FPGA EZ-Extender power supply1

1 Default setting

No Jumper

External power supply Connect P421 to external 25VConnect P422 to external GND

2-10 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Hardware Reference

JumpersBefore using the Blackfin FPGA EZ-Extender follow the steps in ldquoFPGA EZ-Extender Setuprdquo on page 1-1

Figure 2-3 shows the locations of all jumper headers A two-pin jumper can be placed on the respective jumper header for different functionality The following sections describe all possible jumper settings and associated functionality

Figure 2-3 Jumper Locations

Blackfin FPGA EZ-Extender Manual 2-11

Jumpers

Serial ROM Boot Jumper (JP1)By default the serial ROM boot jumper JP1 is unpopulated When unpopulated the FPGA EZ-Extender programs via the Blackfin processor or the Xilinx JTAG header

When JP1 is left populated the jumper connects the serial ROM chip enable pin to the done bit of the FPGA At power-up the done bit is driven low by the FPGA causing the FPGA to enable the serial ROM as a programming source After the FPGA is programmed the done bit is driven high by the FPGA causing the FPGA to drive high the chip enable pin of the serial ROM

Both JP1 and JP4 must be set up for correct FPGA programming ldquoBoot Jumper (JP4)rdquo on page 2-14 summarizes the JP4 settings Table 2-10 sum-marizes the JP1 settings See Table 2-4 on page 2-5 and Table 2-6 on page 2-6 for more information on JP1

Config Done Jumper (JP2) The configuration done jumper JP2 connects the done bit of the FPGA to the Blackfin processorrsquos PF3 flag pin of the ADSP-BF533 and ADSP-BF561 EZ-KIT Lites or PF14 flag pin of the ADSP-BF537 EZ-KIT

Table 2-10 JP1 Settings

Boot Source JP1 Setting

ADSP-BF533 ADSP-BF537 or ADSP-BF561 processor via VisualDSP++1

1 Default setting

Unpopulated

JTAG header Unpopulated

Serial ROM Populated

2-12 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Hardware Reference

Lite By default the jumper is populated and acts as a monitor for the done bit by the Blackfin processor (the bit indicates that the FPGA pro-gramming is complete)

Table 2-11 summarizes the jumper settings

Config Program Jumper (JP3) The configuration program jumper JP3 connects the program bit of the FPGA to the Blackfin processorrsquos flag pin By default JP3 is populated The jumper assures that the program bit is asserted by the Blackfin proces-sor to initiate the FPGA programming through VisualDSP++ software

Table 2-12 summarizes the jumper settings

Table 2-11 JP2 Settings

Functionality JP2 Setting

Done bit connected to Blackfin processorrsquos PF3 flag pin1

1 Default setting

Populated

Done bit disconnected from Blackfin processorrsquos PF3 flag pin

Unpopulated

Table 2-12 JP3 Settings

Functionality JP3 Setting

Program bit connected to the Blackfin processorrsquos flag pin1

1 Default setting

Populated

Program bit disconnected from the Blackfin proces-sorrsquos flag pin

Unpopulated

Blackfin FPGA EZ-Extender Manual 2-13

Jumpers

Boot Jumper (JP4) The boot jumper JP4 configures the FPGA mode pins (M[20]) Based on the jumper settings the FPGA is set to be programmed by the JTAG header serial ROM or Blackfin processor

Table 2-13 summarizes the jumper settings See Table 2-3 on page 2-5 for the JTAG header boot settings Table 2-5 on page 2-6 for the serial ROM boot settings and Table 2-7 on page 2-7 for the Blackfin processor boot settings

FPGA Input Jumpers (JP5) The FPGA input jumpers JP52ndash58 drive select FPGA nets to a logic 0 and can be used for any user logic that requires a steady state input You can set internal pull-ups on these nets in the FPGA and when a low is required populate the respective jumper

Table 2-14 summarizes the jumper settings

Table 2-13 JP4 Settings

Boot Source JP41 and JP42M0

JP43 and JP44M1

JP45 and JP46M2

ADSP-BF533ADSP-BF537 orADSP-BF561 processor1

1 Default setting

Unpopulated Unpopulated Unpopulated

JTAG header Unpopulated Populated Unpopulated

Serial ROM Populated Populated Populated

2-14 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Hardware Reference

Push Buttons and LEDsBefore using the Blackfin FPGA EZ-Extender follow the steps in ldquoFPGA EZ-Extender Setuprdquo on page 1-1

Figure 2-4 shows the locations of all push buttons and LEDs The follow-ing sections describe the associated functionality of all the push buttons and LEDs

Program Push Button (SW1)The program push button SW1 erases the contents of the FPGA The push button can be used as a hard resetmdashthe FPGA must be completely re-programmed once SW1 is de-pressed See ldquoProgramming the FPGArdquo on page 2-3 for more information

PB1 Push Button (SW3)The PB1 push button SW3 is a general-purpose input push button The switch with a connected debounce circuit eliminates the need to re-create it in the FPGA The push button connects to pin C11 of the FPGA

Table 2-14 JP5 Settings

Reference Designator FPGA Pin Number

JP52 Y3

JP54 Y2

JP56 U10

JP58 AB11

Blackfin FPGA EZ-Extender Manual 2-15

Push Buttons and LEDs

PB2 Push Button (SW4) The PB2 push button SW4 is a general-purpose input push button The switch does not have a connected debounce circuit you may need to cre-ate it in the FPGA if required by a specific application The push button connects to pin H5 of the FPGA

Figure 2-4 Push Button and LED Locations

2-16 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Hardware Reference

Status LEDs (LED1ndash8) Eight status LEDs LED1ndash8 connect to the FPGA and act as status flags in any application that requires it Table 2-15 shows the LEDFPGA connections

Power LED (LED9) The power LED LED9 connects to the 25V power supply and when lit signifies that the FPGA EZ-Extender is powered properly

Done LED (LED10) The done LED LED10 connects to the done pin of the FPGA At power-up the FPGA is blank and needs to be programmed When lit the LED indicates that the FPGA is programmed successfully

Table 2-15 Status LED (LED1ndash8) Settings

Reference Designator FPGA Pin Number

LED1 U11

LED2 W11

LED3 AB10

LED4 Y10

LED5 AB9

LED6 W9

LED7 AB8

LED8 V10

Blackfin FPGA EZ-Extender Manual 2-17

Connectors

ConnectorsBefore using the Blackfin FPGA EZ-Extender follow the steps in ldquoFPGA EZ-Extender Setuprdquo on page 1-1

This section describes the connector functionality and provides informa-tion about the mating connectors The connector locations are shown in Figure 2-5

Figure 2-5 Connector Locations

2-18 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Hardware Reference

Expansion Interface (P1ndash3 and J1ndash3) Connectors P1ndash3 of the expansion interface are used to plug in the EZ-Extender to the ADSP-BF533 ADSP-BF537 or ADSP-BF561 EZ-KIT Lite

Connectors J1ndash3 of the expansion interface are used to plug in another extender board such as the Blackfin USB-LAN EZ-Extender Your own custom board can be plugged into J1ndash3 as well

Plugging in another EZ-Extender or a customer board to the expansion interface can de-grade the overall system performance The extra overall load can cause the user to add wait states or slow down the system bus to get all of the boards to work properly

For the J1ndash3 and P1ndash3 connector availability and pricing contact Samtec

IDC Connectors (P8 P14 P16 and P17) The P8 P14 P16 and P17 connectors are standard 01rdquo IDC headers The connectors are in a 13 x 2 configuration and designed for signal probing bread boarding and other signal accesses

Part Description Manufacturer Part Number

90-position 005rdquo spacing SMT(J1 J2 J3)

Samtec SFC-145-T2-F-D-A

90-position 005rdquo spacing (P1 P2 P3)

Samtec TFC-145-32-F-D

Part Description Manufacturer Part Number

IDC13x2 01rdquo header Berg 54102-T08-13

Mating Connector

IDC 13x2 01rdquo plug Samtec SSW-113-01-T-D

Blackfin FPGA EZ-Extender Manual 2-19

Connectors

IDC Connectors (P5 and P7) The P5 and P7 connectors are standard 01rdquo IDC headers The connectors are in a 14 x 2 configuration and designed for signal probing bread boarding and other signal accesses

High-Speed Connector (P4) The high-speed connector P4 facilitates development of applications where use of the standard IDC connectors is complicated due to signal integrity issues

For the P4 connector and cable assembly availability and pricing contact Samtec

Part Description Manufacturer Part Number

IDC14x2 01rdquo header FCI 68737-428HLF

IDC14x2 01rdquo header Sullins GEC14DAAN

Mating Connector

IDC 14x2 01rdquo plug Samtec SSW-114-01-T-D

Part Description Manufacturer Part Number

QTS 25x2 high-speed connector Samtec QTS-025-01-F-D-A

Mating Connector

QSS 25x2 high-speed connector Samtec QSS-025-01-F-D-A

2-20 Blackfin FPGA EZ-Extender Manual

A BILL OF MATERIALS

The bill of materials corresponds to the board schematics on page B-1

Please check the latest schematics on the Analog Devices website httpwwwanalogcomProcessorsProcessorsDevelopmentToolstec

hnicalLibrarymanualsDevToolsIndexhtmlEvalua-

tion20Kit20Manuals

Blackfin FPGA EZ-Extender Manual A-1

FPGA EZ-Extender Hardware Reference

Programming the FPGABefore using the Blackfin FPGA EZ-Extender follow the steps in ldquoFPGA EZ-Extender Setuprdquo on page 1-1

Figure 2-2 is a block diagram of the FPGA programming connections

Figure 2-2 FPGA Programming Block Diagram

Blackfin FPGA EZ-Extender Manual 2-3

Programming the FPGA

There are three ways to program the FPGA

bull Using the FPGA JTAG header as described in ldquoFPGA Program-ming via JTAGrdquo on page 2-4

bull Using the Xilinx serial ROM as described in ldquoFPGA Programming via Serial ROMrdquo on page 2-5

bull Using the Blackfin processor as described in ldquoFPGA Programming via Blackfin Applicationrdquo on page 2-6

The done LED (LED10) lights up once the FPGA is programmed signifying that the task is complete To erase the contents of the FPGA at any time de-press the program switch SW1

FPGA Programming via JTAGTo program the FPGA via the JTAG header create the appropriate pro-gram file using the Xilinx ISE software provided at wwwxilinxcom Once the program file is created use a Xilinx JTAG cable and connect it to P15 of the FPGA EZ-Extender (the P15 connections are shown in Table 2-1)

Table 2-1 P15 Connections for PFGA Programming via JTAG

P15 Pin Number Signal Name

1 33V

2 GND

3 TCK

4 TDO

5 TDI

6 TMS

2-4 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Hardware Reference

In addition to removing JP1 (serial ROM boot jumper) as shown in Table 2-2 set the boot jumper JP4 to JTAG mode The JP4 settings for JTAG boot are shown in Table 2-3 See ldquoBoot Jumper (JP4)rdquo on page 2-14 for more information

FPGA Programming via Serial ROMTo program the FPGA with the contents of the serial ROM populate the JP1 jumper When populated JP1 connects the chip enable pin of the serial ROM to the done bit of the FPGA Once the FPGA is programmed the done bit automatically goes high and the enable pin of the serial ROM chip becomes a logic 1 The JP1 settings for serial ROM boot are shown in Table 2-4 See ldquoProgramming the Serial ROMrdquo on page 2-7 for more information

The done LED (LED10) remains lit to signify that the FPGA is pro-grammed See ldquoDone LED (LED10)rdquo on page 2-17 for more information

Table 2-2 JP1 Settings for FPGA Programming via JTAG

JP1 Pin Name Pins Connected Jumper Setting

Flash done JP11 and JP12 Unpopulated

Table 2-3 JP4 Settings for FPGA Programming via JTAG

JP4 Pin Name Pins Connected Jumper Setting

M0 JP41 and JP42 Unpopulated

M1 JP43 and JP44 Populated

M2 JP45 and JP46 Unpopulated

Table 2-4 JP1 Settings for FPGA Programming via Serial ROM

JP1 Pin Name Pins Connected Jumper Setting

Flash done JP11 and JP12 Populated

Blackfin FPGA EZ-Extender Manual 2-5

Programming the FPGA

In addition to JP1 set the boot mode jumper JP4 to master serial mode The JP4 settings for serial ROM boot are shown in Table 2-5 See ldquoBoot Jumper (JP4)rdquo on page 2-14 for more information

FPGA Programming via Blackfin ApplicationBy default the FPGA EZ-Extender is configured by the flash program-ming utility within VisualDSP++ The software is located in the hellipBlackfinEZ-KITsFPGA EZ-EXTENDER subdirectory of the VisualDSP++ installation directory The FPGA Software Readmetxt file located in the same subdirectory provides all the necessary instructions required for run-ning the application

When generating a program file using the Xilinx software tools remember to generate a slave serial program file in the Intel MCS-86 Hexadecimal Object (mcs) file format

To boot the FPGA from the Blackfin processor unpopulate jumper JP1 and set jumper JP4 to slave serial mode as shown in Table 2-6 and Table 2-7 See ldquoSerial ROM Boot Jumper (JP1)rdquo on page 2-12 and ldquoBoot Jumper (JP4)rdquo on page 2-14 for more information

Table 2-5 JP4 Settings for FPGA Programming in Master Serial Mode

JP4 Pin Name Pins Connected Jumper Setting

M0 JP41 and JP42 Populated

M1 JP43 and JP44 Populated

M2 JP45 and JP46 Populated

Table 2-6 JP1 Settings for FPGA Programming via Blackfin Processor

JP1 Pin Name Pins Connected Jumper Setting

Flash done JP11 and JP12 Unpopulated

2-6 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Hardware Reference

Programming the Serial ROMThe FPGA EZ-Extender allows the user to program the serial ROM The serial ROM can be programmed by using a Xilinx JTAG cable ISE soft-ware and the flash JTAG header on the FPGA EZ-Extender

Serial ROM via JTAG HeaderTo program the serial ROM via the JTAG header create the appropriate program file using the Xilinx software provided at wwwxilinxcom Once the program file is created use a Xilinx JTAG cable and connect it to P6 The P6 connections are shown in Table 2-8

Table 2-7 JP4 Settings for FPGA Programming via Blackfin Processor

JP4 Pin Name Pins Connected Jumper Setting

M0 JP41 and JP42 Unpopulated

M1 JP43 and JP44 Unpopulated

M2 JP45 and JP46 Unpopulated

Table 2-8 P6 Connections for Serial ROM

P6 Pin Number Signal Name P6 Pin Number Signal Name

1 33V 4 TDO

2 GND 5 TDI

3 TCK 6 TMS

Blackfin FPGA EZ-Extender Manual 2-7

Power

PowerThe FPGA EZ-Extender can be powered from the enclosed power supply EZ-KIT Lite or external power supply The power source for the extender is selected based on the power requirements of the application

An external 7V power supply is shipped with the extender board The power supply uses three switching regulators VR1 is used to power the 25V power plane VR2 is used to power the 12V power plane and VR3 is used to power the 33V plane All of the regulators can supply a maximum current of 2 Amps To understand the power requirements of your appli-cation run the Xilinx power estimator software The software can be located at wwwxilinxcom

Table 2-9 states the current limitations of each method Each method requires a correctly configured header described in the following sections

Table 2-9 Power Limitations

Power Source 12V Supply 25V Supply 33V Supply

ADSP-BF533 ADSP-BF537 or ADSP-BF561 EZ-KIT Lite

500 mA 500 mA 500 mA

FPGA EZ-Extender power supply1

1 Default setting

2A 2A 2A

External power supply 2A 2A 2A

2-8 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Hardware Reference

Power In Header (P12)The P12 header supplies the power to the on board 12V and the 25V reg-ulators The P42 and P43 headers supply the power to the external 12V and 25V planes as described in ldquo25V Header (P42)rdquo and ldquo12V Header (P43)rdquo on page 2-10

33V Header (P13)

When using an external power supply do not plug in the power supply shipped with the FPGA EZ-Extender This can seriously damage the board As an extra measure of precaution remove all jumpers from P12

Power Source P12 Setting

FPGA EZ-Extender power supply1

1 Default setting

Jumper on P121 and P122

ADSP-BF533 ADSP-BF537 or ADSP-BF561 EZ-KIT Lite 5V power supply

Jumper on P122 and P123

Power Source P13 Setting

ADSP-BF533 ADSP-BF537 or ADSP-BF561 EZ-KIT Lite 33V power supply

Jumper on P131 and P132

FPGA EZ-Extender power supply1

1 Default setting

Jumper on P132 and P133

External power supply No jumper connect supply to P132 and GND

Blackfin FPGA EZ-Extender Manual 2-9

Power

25V Header (P42)

When using an external power supply do not plug in the power supply shipped with the FPGA EZ-Extender This can seriously damage the board As an extra measure of precaution remove all jumpers from P12

12V Header (P43)

When using an external power supply do not plug in the power supply shipped with the FPGA EZ-Extender This can seriously damage the board As an extra measure of precaution remove all jumpers from P12

Power Source P42 Setting

FPGA EZ-Extender Power Supply1

1 Default setting

No Jumper

External power supply Connect P421 to external 25VConnect P422 to external GND

Power Source P43 Setting

FPGA EZ-Extender power supply1

1 Default setting

No Jumper

External power supply Connect P421 to external 25VConnect P422 to external GND

2-10 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Hardware Reference

JumpersBefore using the Blackfin FPGA EZ-Extender follow the steps in ldquoFPGA EZ-Extender Setuprdquo on page 1-1

Figure 2-3 shows the locations of all jumper headers A two-pin jumper can be placed on the respective jumper header for different functionality The following sections describe all possible jumper settings and associated functionality

Figure 2-3 Jumper Locations

Blackfin FPGA EZ-Extender Manual 2-11

Jumpers

Serial ROM Boot Jumper (JP1)By default the serial ROM boot jumper JP1 is unpopulated When unpopulated the FPGA EZ-Extender programs via the Blackfin processor or the Xilinx JTAG header

When JP1 is left populated the jumper connects the serial ROM chip enable pin to the done bit of the FPGA At power-up the done bit is driven low by the FPGA causing the FPGA to enable the serial ROM as a programming source After the FPGA is programmed the done bit is driven high by the FPGA causing the FPGA to drive high the chip enable pin of the serial ROM

Both JP1 and JP4 must be set up for correct FPGA programming ldquoBoot Jumper (JP4)rdquo on page 2-14 summarizes the JP4 settings Table 2-10 sum-marizes the JP1 settings See Table 2-4 on page 2-5 and Table 2-6 on page 2-6 for more information on JP1

Config Done Jumper (JP2) The configuration done jumper JP2 connects the done bit of the FPGA to the Blackfin processorrsquos PF3 flag pin of the ADSP-BF533 and ADSP-BF561 EZ-KIT Lites or PF14 flag pin of the ADSP-BF537 EZ-KIT

Table 2-10 JP1 Settings

Boot Source JP1 Setting

ADSP-BF533 ADSP-BF537 or ADSP-BF561 processor via VisualDSP++1

1 Default setting

Unpopulated

JTAG header Unpopulated

Serial ROM Populated

2-12 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Hardware Reference

Lite By default the jumper is populated and acts as a monitor for the done bit by the Blackfin processor (the bit indicates that the FPGA pro-gramming is complete)

Table 2-11 summarizes the jumper settings

Config Program Jumper (JP3) The configuration program jumper JP3 connects the program bit of the FPGA to the Blackfin processorrsquos flag pin By default JP3 is populated The jumper assures that the program bit is asserted by the Blackfin proces-sor to initiate the FPGA programming through VisualDSP++ software

Table 2-12 summarizes the jumper settings

Table 2-11 JP2 Settings

Functionality JP2 Setting

Done bit connected to Blackfin processorrsquos PF3 flag pin1

1 Default setting

Populated

Done bit disconnected from Blackfin processorrsquos PF3 flag pin

Unpopulated

Table 2-12 JP3 Settings

Functionality JP3 Setting

Program bit connected to the Blackfin processorrsquos flag pin1

1 Default setting

Populated

Program bit disconnected from the Blackfin proces-sorrsquos flag pin

Unpopulated

Blackfin FPGA EZ-Extender Manual 2-13

Jumpers

Boot Jumper (JP4) The boot jumper JP4 configures the FPGA mode pins (M[20]) Based on the jumper settings the FPGA is set to be programmed by the JTAG header serial ROM or Blackfin processor

Table 2-13 summarizes the jumper settings See Table 2-3 on page 2-5 for the JTAG header boot settings Table 2-5 on page 2-6 for the serial ROM boot settings and Table 2-7 on page 2-7 for the Blackfin processor boot settings

FPGA Input Jumpers (JP5) The FPGA input jumpers JP52ndash58 drive select FPGA nets to a logic 0 and can be used for any user logic that requires a steady state input You can set internal pull-ups on these nets in the FPGA and when a low is required populate the respective jumper

Table 2-14 summarizes the jumper settings

Table 2-13 JP4 Settings

Boot Source JP41 and JP42M0

JP43 and JP44M1

JP45 and JP46M2

ADSP-BF533ADSP-BF537 orADSP-BF561 processor1

1 Default setting

Unpopulated Unpopulated Unpopulated

JTAG header Unpopulated Populated Unpopulated

Serial ROM Populated Populated Populated

2-14 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Hardware Reference

Push Buttons and LEDsBefore using the Blackfin FPGA EZ-Extender follow the steps in ldquoFPGA EZ-Extender Setuprdquo on page 1-1

Figure 2-4 shows the locations of all push buttons and LEDs The follow-ing sections describe the associated functionality of all the push buttons and LEDs

Program Push Button (SW1)The program push button SW1 erases the contents of the FPGA The push button can be used as a hard resetmdashthe FPGA must be completely re-programmed once SW1 is de-pressed See ldquoProgramming the FPGArdquo on page 2-3 for more information

PB1 Push Button (SW3)The PB1 push button SW3 is a general-purpose input push button The switch with a connected debounce circuit eliminates the need to re-create it in the FPGA The push button connects to pin C11 of the FPGA

Table 2-14 JP5 Settings

Reference Designator FPGA Pin Number

JP52 Y3

JP54 Y2

JP56 U10

JP58 AB11

Blackfin FPGA EZ-Extender Manual 2-15

Push Buttons and LEDs

PB2 Push Button (SW4) The PB2 push button SW4 is a general-purpose input push button The switch does not have a connected debounce circuit you may need to cre-ate it in the FPGA if required by a specific application The push button connects to pin H5 of the FPGA

Figure 2-4 Push Button and LED Locations

2-16 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Hardware Reference

Status LEDs (LED1ndash8) Eight status LEDs LED1ndash8 connect to the FPGA and act as status flags in any application that requires it Table 2-15 shows the LEDFPGA connections

Power LED (LED9) The power LED LED9 connects to the 25V power supply and when lit signifies that the FPGA EZ-Extender is powered properly

Done LED (LED10) The done LED LED10 connects to the done pin of the FPGA At power-up the FPGA is blank and needs to be programmed When lit the LED indicates that the FPGA is programmed successfully

Table 2-15 Status LED (LED1ndash8) Settings

Reference Designator FPGA Pin Number

LED1 U11

LED2 W11

LED3 AB10

LED4 Y10

LED5 AB9

LED6 W9

LED7 AB8

LED8 V10

Blackfin FPGA EZ-Extender Manual 2-17

Connectors

ConnectorsBefore using the Blackfin FPGA EZ-Extender follow the steps in ldquoFPGA EZ-Extender Setuprdquo on page 1-1

This section describes the connector functionality and provides informa-tion about the mating connectors The connector locations are shown in Figure 2-5

Figure 2-5 Connector Locations

2-18 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Hardware Reference

Expansion Interface (P1ndash3 and J1ndash3) Connectors P1ndash3 of the expansion interface are used to plug in the EZ-Extender to the ADSP-BF533 ADSP-BF537 or ADSP-BF561 EZ-KIT Lite

Connectors J1ndash3 of the expansion interface are used to plug in another extender board such as the Blackfin USB-LAN EZ-Extender Your own custom board can be plugged into J1ndash3 as well

Plugging in another EZ-Extender or a customer board to the expansion interface can de-grade the overall system performance The extra overall load can cause the user to add wait states or slow down the system bus to get all of the boards to work properly

For the J1ndash3 and P1ndash3 connector availability and pricing contact Samtec

IDC Connectors (P8 P14 P16 and P17) The P8 P14 P16 and P17 connectors are standard 01rdquo IDC headers The connectors are in a 13 x 2 configuration and designed for signal probing bread boarding and other signal accesses

Part Description Manufacturer Part Number

90-position 005rdquo spacing SMT(J1 J2 J3)

Samtec SFC-145-T2-F-D-A

90-position 005rdquo spacing (P1 P2 P3)

Samtec TFC-145-32-F-D

Part Description Manufacturer Part Number

IDC13x2 01rdquo header Berg 54102-T08-13

Mating Connector

IDC 13x2 01rdquo plug Samtec SSW-113-01-T-D

Blackfin FPGA EZ-Extender Manual 2-19

Connectors

IDC Connectors (P5 and P7) The P5 and P7 connectors are standard 01rdquo IDC headers The connectors are in a 14 x 2 configuration and designed for signal probing bread boarding and other signal accesses

High-Speed Connector (P4) The high-speed connector P4 facilitates development of applications where use of the standard IDC connectors is complicated due to signal integrity issues

For the P4 connector and cable assembly availability and pricing contact Samtec

Part Description Manufacturer Part Number

IDC14x2 01rdquo header FCI 68737-428HLF

IDC14x2 01rdquo header Sullins GEC14DAAN

Mating Connector

IDC 14x2 01rdquo plug Samtec SSW-114-01-T-D

Part Description Manufacturer Part Number

QTS 25x2 high-speed connector Samtec QTS-025-01-F-D-A

Mating Connector

QSS 25x2 high-speed connector Samtec QSS-025-01-F-D-A

2-20 Blackfin FPGA EZ-Extender Manual

A BILL OF MATERIALS

The bill of materials corresponds to the board schematics on page B-1

Please check the latest schematics on the Analog Devices website httpwwwanalogcomProcessorsProcessorsDevelopmentToolstec

hnicalLibrarymanualsDevToolsIndexhtmlEvalua-

tion20Kit20Manuals

Blackfin FPGA EZ-Extender Manual A-1

Programming the FPGA

There are three ways to program the FPGA

bull Using the FPGA JTAG header as described in ldquoFPGA Program-ming via JTAGrdquo on page 2-4

bull Using the Xilinx serial ROM as described in ldquoFPGA Programming via Serial ROMrdquo on page 2-5

bull Using the Blackfin processor as described in ldquoFPGA Programming via Blackfin Applicationrdquo on page 2-6

The done LED (LED10) lights up once the FPGA is programmed signifying that the task is complete To erase the contents of the FPGA at any time de-press the program switch SW1

FPGA Programming via JTAGTo program the FPGA via the JTAG header create the appropriate pro-gram file using the Xilinx ISE software provided at wwwxilinxcom Once the program file is created use a Xilinx JTAG cable and connect it to P15 of the FPGA EZ-Extender (the P15 connections are shown in Table 2-1)

Table 2-1 P15 Connections for PFGA Programming via JTAG

P15 Pin Number Signal Name

1 33V

2 GND

3 TCK

4 TDO

5 TDI

6 TMS

2-4 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Hardware Reference

In addition to removing JP1 (serial ROM boot jumper) as shown in Table 2-2 set the boot jumper JP4 to JTAG mode The JP4 settings for JTAG boot are shown in Table 2-3 See ldquoBoot Jumper (JP4)rdquo on page 2-14 for more information

FPGA Programming via Serial ROMTo program the FPGA with the contents of the serial ROM populate the JP1 jumper When populated JP1 connects the chip enable pin of the serial ROM to the done bit of the FPGA Once the FPGA is programmed the done bit automatically goes high and the enable pin of the serial ROM chip becomes a logic 1 The JP1 settings for serial ROM boot are shown in Table 2-4 See ldquoProgramming the Serial ROMrdquo on page 2-7 for more information

The done LED (LED10) remains lit to signify that the FPGA is pro-grammed See ldquoDone LED (LED10)rdquo on page 2-17 for more information

Table 2-2 JP1 Settings for FPGA Programming via JTAG

JP1 Pin Name Pins Connected Jumper Setting

Flash done JP11 and JP12 Unpopulated

Table 2-3 JP4 Settings for FPGA Programming via JTAG

JP4 Pin Name Pins Connected Jumper Setting

M0 JP41 and JP42 Unpopulated

M1 JP43 and JP44 Populated

M2 JP45 and JP46 Unpopulated

Table 2-4 JP1 Settings for FPGA Programming via Serial ROM

JP1 Pin Name Pins Connected Jumper Setting

Flash done JP11 and JP12 Populated

Blackfin FPGA EZ-Extender Manual 2-5

Programming the FPGA

In addition to JP1 set the boot mode jumper JP4 to master serial mode The JP4 settings for serial ROM boot are shown in Table 2-5 See ldquoBoot Jumper (JP4)rdquo on page 2-14 for more information

FPGA Programming via Blackfin ApplicationBy default the FPGA EZ-Extender is configured by the flash program-ming utility within VisualDSP++ The software is located in the hellipBlackfinEZ-KITsFPGA EZ-EXTENDER subdirectory of the VisualDSP++ installation directory The FPGA Software Readmetxt file located in the same subdirectory provides all the necessary instructions required for run-ning the application

When generating a program file using the Xilinx software tools remember to generate a slave serial program file in the Intel MCS-86 Hexadecimal Object (mcs) file format

To boot the FPGA from the Blackfin processor unpopulate jumper JP1 and set jumper JP4 to slave serial mode as shown in Table 2-6 and Table 2-7 See ldquoSerial ROM Boot Jumper (JP1)rdquo on page 2-12 and ldquoBoot Jumper (JP4)rdquo on page 2-14 for more information

Table 2-5 JP4 Settings for FPGA Programming in Master Serial Mode

JP4 Pin Name Pins Connected Jumper Setting

M0 JP41 and JP42 Populated

M1 JP43 and JP44 Populated

M2 JP45 and JP46 Populated

Table 2-6 JP1 Settings for FPGA Programming via Blackfin Processor

JP1 Pin Name Pins Connected Jumper Setting

Flash done JP11 and JP12 Unpopulated

2-6 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Hardware Reference

Programming the Serial ROMThe FPGA EZ-Extender allows the user to program the serial ROM The serial ROM can be programmed by using a Xilinx JTAG cable ISE soft-ware and the flash JTAG header on the FPGA EZ-Extender

Serial ROM via JTAG HeaderTo program the serial ROM via the JTAG header create the appropriate program file using the Xilinx software provided at wwwxilinxcom Once the program file is created use a Xilinx JTAG cable and connect it to P6 The P6 connections are shown in Table 2-8

Table 2-7 JP4 Settings for FPGA Programming via Blackfin Processor

JP4 Pin Name Pins Connected Jumper Setting

M0 JP41 and JP42 Unpopulated

M1 JP43 and JP44 Unpopulated

M2 JP45 and JP46 Unpopulated

Table 2-8 P6 Connections for Serial ROM

P6 Pin Number Signal Name P6 Pin Number Signal Name

1 33V 4 TDO

2 GND 5 TDI

3 TCK 6 TMS

Blackfin FPGA EZ-Extender Manual 2-7

Power

PowerThe FPGA EZ-Extender can be powered from the enclosed power supply EZ-KIT Lite or external power supply The power source for the extender is selected based on the power requirements of the application

An external 7V power supply is shipped with the extender board The power supply uses three switching regulators VR1 is used to power the 25V power plane VR2 is used to power the 12V power plane and VR3 is used to power the 33V plane All of the regulators can supply a maximum current of 2 Amps To understand the power requirements of your appli-cation run the Xilinx power estimator software The software can be located at wwwxilinxcom

Table 2-9 states the current limitations of each method Each method requires a correctly configured header described in the following sections

Table 2-9 Power Limitations

Power Source 12V Supply 25V Supply 33V Supply

ADSP-BF533 ADSP-BF537 or ADSP-BF561 EZ-KIT Lite

500 mA 500 mA 500 mA

FPGA EZ-Extender power supply1

1 Default setting

2A 2A 2A

External power supply 2A 2A 2A

2-8 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Hardware Reference

Power In Header (P12)The P12 header supplies the power to the on board 12V and the 25V reg-ulators The P42 and P43 headers supply the power to the external 12V and 25V planes as described in ldquo25V Header (P42)rdquo and ldquo12V Header (P43)rdquo on page 2-10

33V Header (P13)

When using an external power supply do not plug in the power supply shipped with the FPGA EZ-Extender This can seriously damage the board As an extra measure of precaution remove all jumpers from P12

Power Source P12 Setting

FPGA EZ-Extender power supply1

1 Default setting

Jumper on P121 and P122

ADSP-BF533 ADSP-BF537 or ADSP-BF561 EZ-KIT Lite 5V power supply

Jumper on P122 and P123

Power Source P13 Setting

ADSP-BF533 ADSP-BF537 or ADSP-BF561 EZ-KIT Lite 33V power supply

Jumper on P131 and P132

FPGA EZ-Extender power supply1

1 Default setting

Jumper on P132 and P133

External power supply No jumper connect supply to P132 and GND

Blackfin FPGA EZ-Extender Manual 2-9

Power

25V Header (P42)

When using an external power supply do not plug in the power supply shipped with the FPGA EZ-Extender This can seriously damage the board As an extra measure of precaution remove all jumpers from P12

12V Header (P43)

When using an external power supply do not plug in the power supply shipped with the FPGA EZ-Extender This can seriously damage the board As an extra measure of precaution remove all jumpers from P12

Power Source P42 Setting

FPGA EZ-Extender Power Supply1

1 Default setting

No Jumper

External power supply Connect P421 to external 25VConnect P422 to external GND

Power Source P43 Setting

FPGA EZ-Extender power supply1

1 Default setting

No Jumper

External power supply Connect P421 to external 25VConnect P422 to external GND

2-10 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Hardware Reference

JumpersBefore using the Blackfin FPGA EZ-Extender follow the steps in ldquoFPGA EZ-Extender Setuprdquo on page 1-1

Figure 2-3 shows the locations of all jumper headers A two-pin jumper can be placed on the respective jumper header for different functionality The following sections describe all possible jumper settings and associated functionality

Figure 2-3 Jumper Locations

Blackfin FPGA EZ-Extender Manual 2-11

Jumpers

Serial ROM Boot Jumper (JP1)By default the serial ROM boot jumper JP1 is unpopulated When unpopulated the FPGA EZ-Extender programs via the Blackfin processor or the Xilinx JTAG header

When JP1 is left populated the jumper connects the serial ROM chip enable pin to the done bit of the FPGA At power-up the done bit is driven low by the FPGA causing the FPGA to enable the serial ROM as a programming source After the FPGA is programmed the done bit is driven high by the FPGA causing the FPGA to drive high the chip enable pin of the serial ROM

Both JP1 and JP4 must be set up for correct FPGA programming ldquoBoot Jumper (JP4)rdquo on page 2-14 summarizes the JP4 settings Table 2-10 sum-marizes the JP1 settings See Table 2-4 on page 2-5 and Table 2-6 on page 2-6 for more information on JP1

Config Done Jumper (JP2) The configuration done jumper JP2 connects the done bit of the FPGA to the Blackfin processorrsquos PF3 flag pin of the ADSP-BF533 and ADSP-BF561 EZ-KIT Lites or PF14 flag pin of the ADSP-BF537 EZ-KIT

Table 2-10 JP1 Settings

Boot Source JP1 Setting

ADSP-BF533 ADSP-BF537 or ADSP-BF561 processor via VisualDSP++1

1 Default setting

Unpopulated

JTAG header Unpopulated

Serial ROM Populated

2-12 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Hardware Reference

Lite By default the jumper is populated and acts as a monitor for the done bit by the Blackfin processor (the bit indicates that the FPGA pro-gramming is complete)

Table 2-11 summarizes the jumper settings

Config Program Jumper (JP3) The configuration program jumper JP3 connects the program bit of the FPGA to the Blackfin processorrsquos flag pin By default JP3 is populated The jumper assures that the program bit is asserted by the Blackfin proces-sor to initiate the FPGA programming through VisualDSP++ software

Table 2-12 summarizes the jumper settings

Table 2-11 JP2 Settings

Functionality JP2 Setting

Done bit connected to Blackfin processorrsquos PF3 flag pin1

1 Default setting

Populated

Done bit disconnected from Blackfin processorrsquos PF3 flag pin

Unpopulated

Table 2-12 JP3 Settings

Functionality JP3 Setting

Program bit connected to the Blackfin processorrsquos flag pin1

1 Default setting

Populated

Program bit disconnected from the Blackfin proces-sorrsquos flag pin

Unpopulated

Blackfin FPGA EZ-Extender Manual 2-13

Jumpers

Boot Jumper (JP4) The boot jumper JP4 configures the FPGA mode pins (M[20]) Based on the jumper settings the FPGA is set to be programmed by the JTAG header serial ROM or Blackfin processor

Table 2-13 summarizes the jumper settings See Table 2-3 on page 2-5 for the JTAG header boot settings Table 2-5 on page 2-6 for the serial ROM boot settings and Table 2-7 on page 2-7 for the Blackfin processor boot settings

FPGA Input Jumpers (JP5) The FPGA input jumpers JP52ndash58 drive select FPGA nets to a logic 0 and can be used for any user logic that requires a steady state input You can set internal pull-ups on these nets in the FPGA and when a low is required populate the respective jumper

Table 2-14 summarizes the jumper settings

Table 2-13 JP4 Settings

Boot Source JP41 and JP42M0

JP43 and JP44M1

JP45 and JP46M2

ADSP-BF533ADSP-BF537 orADSP-BF561 processor1

1 Default setting

Unpopulated Unpopulated Unpopulated

JTAG header Unpopulated Populated Unpopulated

Serial ROM Populated Populated Populated

2-14 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Hardware Reference

Push Buttons and LEDsBefore using the Blackfin FPGA EZ-Extender follow the steps in ldquoFPGA EZ-Extender Setuprdquo on page 1-1

Figure 2-4 shows the locations of all push buttons and LEDs The follow-ing sections describe the associated functionality of all the push buttons and LEDs

Program Push Button (SW1)The program push button SW1 erases the contents of the FPGA The push button can be used as a hard resetmdashthe FPGA must be completely re-programmed once SW1 is de-pressed See ldquoProgramming the FPGArdquo on page 2-3 for more information

PB1 Push Button (SW3)The PB1 push button SW3 is a general-purpose input push button The switch with a connected debounce circuit eliminates the need to re-create it in the FPGA The push button connects to pin C11 of the FPGA

Table 2-14 JP5 Settings

Reference Designator FPGA Pin Number

JP52 Y3

JP54 Y2

JP56 U10

JP58 AB11

Blackfin FPGA EZ-Extender Manual 2-15

Push Buttons and LEDs

PB2 Push Button (SW4) The PB2 push button SW4 is a general-purpose input push button The switch does not have a connected debounce circuit you may need to cre-ate it in the FPGA if required by a specific application The push button connects to pin H5 of the FPGA

Figure 2-4 Push Button and LED Locations

2-16 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Hardware Reference

Status LEDs (LED1ndash8) Eight status LEDs LED1ndash8 connect to the FPGA and act as status flags in any application that requires it Table 2-15 shows the LEDFPGA connections

Power LED (LED9) The power LED LED9 connects to the 25V power supply and when lit signifies that the FPGA EZ-Extender is powered properly

Done LED (LED10) The done LED LED10 connects to the done pin of the FPGA At power-up the FPGA is blank and needs to be programmed When lit the LED indicates that the FPGA is programmed successfully

Table 2-15 Status LED (LED1ndash8) Settings

Reference Designator FPGA Pin Number

LED1 U11

LED2 W11

LED3 AB10

LED4 Y10

LED5 AB9

LED6 W9

LED7 AB8

LED8 V10

Blackfin FPGA EZ-Extender Manual 2-17

Connectors

ConnectorsBefore using the Blackfin FPGA EZ-Extender follow the steps in ldquoFPGA EZ-Extender Setuprdquo on page 1-1

This section describes the connector functionality and provides informa-tion about the mating connectors The connector locations are shown in Figure 2-5

Figure 2-5 Connector Locations

2-18 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Hardware Reference

Expansion Interface (P1ndash3 and J1ndash3) Connectors P1ndash3 of the expansion interface are used to plug in the EZ-Extender to the ADSP-BF533 ADSP-BF537 or ADSP-BF561 EZ-KIT Lite

Connectors J1ndash3 of the expansion interface are used to plug in another extender board such as the Blackfin USB-LAN EZ-Extender Your own custom board can be plugged into J1ndash3 as well

Plugging in another EZ-Extender or a customer board to the expansion interface can de-grade the overall system performance The extra overall load can cause the user to add wait states or slow down the system bus to get all of the boards to work properly

For the J1ndash3 and P1ndash3 connector availability and pricing contact Samtec

IDC Connectors (P8 P14 P16 and P17) The P8 P14 P16 and P17 connectors are standard 01rdquo IDC headers The connectors are in a 13 x 2 configuration and designed for signal probing bread boarding and other signal accesses

Part Description Manufacturer Part Number

90-position 005rdquo spacing SMT(J1 J2 J3)

Samtec SFC-145-T2-F-D-A

90-position 005rdquo spacing (P1 P2 P3)

Samtec TFC-145-32-F-D

Part Description Manufacturer Part Number

IDC13x2 01rdquo header Berg 54102-T08-13

Mating Connector

IDC 13x2 01rdquo plug Samtec SSW-113-01-T-D

Blackfin FPGA EZ-Extender Manual 2-19

Connectors

IDC Connectors (P5 and P7) The P5 and P7 connectors are standard 01rdquo IDC headers The connectors are in a 14 x 2 configuration and designed for signal probing bread boarding and other signal accesses

High-Speed Connector (P4) The high-speed connector P4 facilitates development of applications where use of the standard IDC connectors is complicated due to signal integrity issues

For the P4 connector and cable assembly availability and pricing contact Samtec

Part Description Manufacturer Part Number

IDC14x2 01rdquo header FCI 68737-428HLF

IDC14x2 01rdquo header Sullins GEC14DAAN

Mating Connector

IDC 14x2 01rdquo plug Samtec SSW-114-01-T-D

Part Description Manufacturer Part Number

QTS 25x2 high-speed connector Samtec QTS-025-01-F-D-A

Mating Connector

QSS 25x2 high-speed connector Samtec QSS-025-01-F-D-A

2-20 Blackfin FPGA EZ-Extender Manual

A BILL OF MATERIALS

The bill of materials corresponds to the board schematics on page B-1

Please check the latest schematics on the Analog Devices website httpwwwanalogcomProcessorsProcessorsDevelopmentToolstec

hnicalLibrarymanualsDevToolsIndexhtmlEvalua-

tion20Kit20Manuals

Blackfin FPGA EZ-Extender Manual A-1

FPGA EZ-Extender Hardware Reference

In addition to removing JP1 (serial ROM boot jumper) as shown in Table 2-2 set the boot jumper JP4 to JTAG mode The JP4 settings for JTAG boot are shown in Table 2-3 See ldquoBoot Jumper (JP4)rdquo on page 2-14 for more information

FPGA Programming via Serial ROMTo program the FPGA with the contents of the serial ROM populate the JP1 jumper When populated JP1 connects the chip enable pin of the serial ROM to the done bit of the FPGA Once the FPGA is programmed the done bit automatically goes high and the enable pin of the serial ROM chip becomes a logic 1 The JP1 settings for serial ROM boot are shown in Table 2-4 See ldquoProgramming the Serial ROMrdquo on page 2-7 for more information

The done LED (LED10) remains lit to signify that the FPGA is pro-grammed See ldquoDone LED (LED10)rdquo on page 2-17 for more information

Table 2-2 JP1 Settings for FPGA Programming via JTAG

JP1 Pin Name Pins Connected Jumper Setting

Flash done JP11 and JP12 Unpopulated

Table 2-3 JP4 Settings for FPGA Programming via JTAG

JP4 Pin Name Pins Connected Jumper Setting

M0 JP41 and JP42 Unpopulated

M1 JP43 and JP44 Populated

M2 JP45 and JP46 Unpopulated

Table 2-4 JP1 Settings for FPGA Programming via Serial ROM

JP1 Pin Name Pins Connected Jumper Setting

Flash done JP11 and JP12 Populated

Blackfin FPGA EZ-Extender Manual 2-5

Programming the FPGA

In addition to JP1 set the boot mode jumper JP4 to master serial mode The JP4 settings for serial ROM boot are shown in Table 2-5 See ldquoBoot Jumper (JP4)rdquo on page 2-14 for more information

FPGA Programming via Blackfin ApplicationBy default the FPGA EZ-Extender is configured by the flash program-ming utility within VisualDSP++ The software is located in the hellipBlackfinEZ-KITsFPGA EZ-EXTENDER subdirectory of the VisualDSP++ installation directory The FPGA Software Readmetxt file located in the same subdirectory provides all the necessary instructions required for run-ning the application

When generating a program file using the Xilinx software tools remember to generate a slave serial program file in the Intel MCS-86 Hexadecimal Object (mcs) file format

To boot the FPGA from the Blackfin processor unpopulate jumper JP1 and set jumper JP4 to slave serial mode as shown in Table 2-6 and Table 2-7 See ldquoSerial ROM Boot Jumper (JP1)rdquo on page 2-12 and ldquoBoot Jumper (JP4)rdquo on page 2-14 for more information

Table 2-5 JP4 Settings for FPGA Programming in Master Serial Mode

JP4 Pin Name Pins Connected Jumper Setting

M0 JP41 and JP42 Populated

M1 JP43 and JP44 Populated

M2 JP45 and JP46 Populated

Table 2-6 JP1 Settings for FPGA Programming via Blackfin Processor

JP1 Pin Name Pins Connected Jumper Setting

Flash done JP11 and JP12 Unpopulated

2-6 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Hardware Reference

Programming the Serial ROMThe FPGA EZ-Extender allows the user to program the serial ROM The serial ROM can be programmed by using a Xilinx JTAG cable ISE soft-ware and the flash JTAG header on the FPGA EZ-Extender

Serial ROM via JTAG HeaderTo program the serial ROM via the JTAG header create the appropriate program file using the Xilinx software provided at wwwxilinxcom Once the program file is created use a Xilinx JTAG cable and connect it to P6 The P6 connections are shown in Table 2-8

Table 2-7 JP4 Settings for FPGA Programming via Blackfin Processor

JP4 Pin Name Pins Connected Jumper Setting

M0 JP41 and JP42 Unpopulated

M1 JP43 and JP44 Unpopulated

M2 JP45 and JP46 Unpopulated

Table 2-8 P6 Connections for Serial ROM

P6 Pin Number Signal Name P6 Pin Number Signal Name

1 33V 4 TDO

2 GND 5 TDI

3 TCK 6 TMS

Blackfin FPGA EZ-Extender Manual 2-7

Power

PowerThe FPGA EZ-Extender can be powered from the enclosed power supply EZ-KIT Lite or external power supply The power source for the extender is selected based on the power requirements of the application

An external 7V power supply is shipped with the extender board The power supply uses three switching regulators VR1 is used to power the 25V power plane VR2 is used to power the 12V power plane and VR3 is used to power the 33V plane All of the regulators can supply a maximum current of 2 Amps To understand the power requirements of your appli-cation run the Xilinx power estimator software The software can be located at wwwxilinxcom

Table 2-9 states the current limitations of each method Each method requires a correctly configured header described in the following sections

Table 2-9 Power Limitations

Power Source 12V Supply 25V Supply 33V Supply

ADSP-BF533 ADSP-BF537 or ADSP-BF561 EZ-KIT Lite

500 mA 500 mA 500 mA

FPGA EZ-Extender power supply1

1 Default setting

2A 2A 2A

External power supply 2A 2A 2A

2-8 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Hardware Reference

Power In Header (P12)The P12 header supplies the power to the on board 12V and the 25V reg-ulators The P42 and P43 headers supply the power to the external 12V and 25V planes as described in ldquo25V Header (P42)rdquo and ldquo12V Header (P43)rdquo on page 2-10

33V Header (P13)

When using an external power supply do not plug in the power supply shipped with the FPGA EZ-Extender This can seriously damage the board As an extra measure of precaution remove all jumpers from P12

Power Source P12 Setting

FPGA EZ-Extender power supply1

1 Default setting

Jumper on P121 and P122

ADSP-BF533 ADSP-BF537 or ADSP-BF561 EZ-KIT Lite 5V power supply

Jumper on P122 and P123

Power Source P13 Setting

ADSP-BF533 ADSP-BF537 or ADSP-BF561 EZ-KIT Lite 33V power supply

Jumper on P131 and P132

FPGA EZ-Extender power supply1

1 Default setting

Jumper on P132 and P133

External power supply No jumper connect supply to P132 and GND

Blackfin FPGA EZ-Extender Manual 2-9

Power

25V Header (P42)

When using an external power supply do not plug in the power supply shipped with the FPGA EZ-Extender This can seriously damage the board As an extra measure of precaution remove all jumpers from P12

12V Header (P43)

When using an external power supply do not plug in the power supply shipped with the FPGA EZ-Extender This can seriously damage the board As an extra measure of precaution remove all jumpers from P12

Power Source P42 Setting

FPGA EZ-Extender Power Supply1

1 Default setting

No Jumper

External power supply Connect P421 to external 25VConnect P422 to external GND

Power Source P43 Setting

FPGA EZ-Extender power supply1

1 Default setting

No Jumper

External power supply Connect P421 to external 25VConnect P422 to external GND

2-10 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Hardware Reference

JumpersBefore using the Blackfin FPGA EZ-Extender follow the steps in ldquoFPGA EZ-Extender Setuprdquo on page 1-1

Figure 2-3 shows the locations of all jumper headers A two-pin jumper can be placed on the respective jumper header for different functionality The following sections describe all possible jumper settings and associated functionality

Figure 2-3 Jumper Locations

Blackfin FPGA EZ-Extender Manual 2-11

Jumpers

Serial ROM Boot Jumper (JP1)By default the serial ROM boot jumper JP1 is unpopulated When unpopulated the FPGA EZ-Extender programs via the Blackfin processor or the Xilinx JTAG header

When JP1 is left populated the jumper connects the serial ROM chip enable pin to the done bit of the FPGA At power-up the done bit is driven low by the FPGA causing the FPGA to enable the serial ROM as a programming source After the FPGA is programmed the done bit is driven high by the FPGA causing the FPGA to drive high the chip enable pin of the serial ROM

Both JP1 and JP4 must be set up for correct FPGA programming ldquoBoot Jumper (JP4)rdquo on page 2-14 summarizes the JP4 settings Table 2-10 sum-marizes the JP1 settings See Table 2-4 on page 2-5 and Table 2-6 on page 2-6 for more information on JP1

Config Done Jumper (JP2) The configuration done jumper JP2 connects the done bit of the FPGA to the Blackfin processorrsquos PF3 flag pin of the ADSP-BF533 and ADSP-BF561 EZ-KIT Lites or PF14 flag pin of the ADSP-BF537 EZ-KIT

Table 2-10 JP1 Settings

Boot Source JP1 Setting

ADSP-BF533 ADSP-BF537 or ADSP-BF561 processor via VisualDSP++1

1 Default setting

Unpopulated

JTAG header Unpopulated

Serial ROM Populated

2-12 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Hardware Reference

Lite By default the jumper is populated and acts as a monitor for the done bit by the Blackfin processor (the bit indicates that the FPGA pro-gramming is complete)

Table 2-11 summarizes the jumper settings

Config Program Jumper (JP3) The configuration program jumper JP3 connects the program bit of the FPGA to the Blackfin processorrsquos flag pin By default JP3 is populated The jumper assures that the program bit is asserted by the Blackfin proces-sor to initiate the FPGA programming through VisualDSP++ software

Table 2-12 summarizes the jumper settings

Table 2-11 JP2 Settings

Functionality JP2 Setting

Done bit connected to Blackfin processorrsquos PF3 flag pin1

1 Default setting

Populated

Done bit disconnected from Blackfin processorrsquos PF3 flag pin

Unpopulated

Table 2-12 JP3 Settings

Functionality JP3 Setting

Program bit connected to the Blackfin processorrsquos flag pin1

1 Default setting

Populated

Program bit disconnected from the Blackfin proces-sorrsquos flag pin

Unpopulated

Blackfin FPGA EZ-Extender Manual 2-13

Jumpers

Boot Jumper (JP4) The boot jumper JP4 configures the FPGA mode pins (M[20]) Based on the jumper settings the FPGA is set to be programmed by the JTAG header serial ROM or Blackfin processor

Table 2-13 summarizes the jumper settings See Table 2-3 on page 2-5 for the JTAG header boot settings Table 2-5 on page 2-6 for the serial ROM boot settings and Table 2-7 on page 2-7 for the Blackfin processor boot settings

FPGA Input Jumpers (JP5) The FPGA input jumpers JP52ndash58 drive select FPGA nets to a logic 0 and can be used for any user logic that requires a steady state input You can set internal pull-ups on these nets in the FPGA and when a low is required populate the respective jumper

Table 2-14 summarizes the jumper settings

Table 2-13 JP4 Settings

Boot Source JP41 and JP42M0

JP43 and JP44M1

JP45 and JP46M2

ADSP-BF533ADSP-BF537 orADSP-BF561 processor1

1 Default setting

Unpopulated Unpopulated Unpopulated

JTAG header Unpopulated Populated Unpopulated

Serial ROM Populated Populated Populated

2-14 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Hardware Reference

Push Buttons and LEDsBefore using the Blackfin FPGA EZ-Extender follow the steps in ldquoFPGA EZ-Extender Setuprdquo on page 1-1

Figure 2-4 shows the locations of all push buttons and LEDs The follow-ing sections describe the associated functionality of all the push buttons and LEDs

Program Push Button (SW1)The program push button SW1 erases the contents of the FPGA The push button can be used as a hard resetmdashthe FPGA must be completely re-programmed once SW1 is de-pressed See ldquoProgramming the FPGArdquo on page 2-3 for more information

PB1 Push Button (SW3)The PB1 push button SW3 is a general-purpose input push button The switch with a connected debounce circuit eliminates the need to re-create it in the FPGA The push button connects to pin C11 of the FPGA

Table 2-14 JP5 Settings

Reference Designator FPGA Pin Number

JP52 Y3

JP54 Y2

JP56 U10

JP58 AB11

Blackfin FPGA EZ-Extender Manual 2-15

Push Buttons and LEDs

PB2 Push Button (SW4) The PB2 push button SW4 is a general-purpose input push button The switch does not have a connected debounce circuit you may need to cre-ate it in the FPGA if required by a specific application The push button connects to pin H5 of the FPGA

Figure 2-4 Push Button and LED Locations

2-16 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Hardware Reference

Status LEDs (LED1ndash8) Eight status LEDs LED1ndash8 connect to the FPGA and act as status flags in any application that requires it Table 2-15 shows the LEDFPGA connections

Power LED (LED9) The power LED LED9 connects to the 25V power supply and when lit signifies that the FPGA EZ-Extender is powered properly

Done LED (LED10) The done LED LED10 connects to the done pin of the FPGA At power-up the FPGA is blank and needs to be programmed When lit the LED indicates that the FPGA is programmed successfully

Table 2-15 Status LED (LED1ndash8) Settings

Reference Designator FPGA Pin Number

LED1 U11

LED2 W11

LED3 AB10

LED4 Y10

LED5 AB9

LED6 W9

LED7 AB8

LED8 V10

Blackfin FPGA EZ-Extender Manual 2-17

Connectors

ConnectorsBefore using the Blackfin FPGA EZ-Extender follow the steps in ldquoFPGA EZ-Extender Setuprdquo on page 1-1

This section describes the connector functionality and provides informa-tion about the mating connectors The connector locations are shown in Figure 2-5

Figure 2-5 Connector Locations

2-18 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Hardware Reference

Expansion Interface (P1ndash3 and J1ndash3) Connectors P1ndash3 of the expansion interface are used to plug in the EZ-Extender to the ADSP-BF533 ADSP-BF537 or ADSP-BF561 EZ-KIT Lite

Connectors J1ndash3 of the expansion interface are used to plug in another extender board such as the Blackfin USB-LAN EZ-Extender Your own custom board can be plugged into J1ndash3 as well

Plugging in another EZ-Extender or a customer board to the expansion interface can de-grade the overall system performance The extra overall load can cause the user to add wait states or slow down the system bus to get all of the boards to work properly

For the J1ndash3 and P1ndash3 connector availability and pricing contact Samtec

IDC Connectors (P8 P14 P16 and P17) The P8 P14 P16 and P17 connectors are standard 01rdquo IDC headers The connectors are in a 13 x 2 configuration and designed for signal probing bread boarding and other signal accesses

Part Description Manufacturer Part Number

90-position 005rdquo spacing SMT(J1 J2 J3)

Samtec SFC-145-T2-F-D-A

90-position 005rdquo spacing (P1 P2 P3)

Samtec TFC-145-32-F-D

Part Description Manufacturer Part Number

IDC13x2 01rdquo header Berg 54102-T08-13

Mating Connector

IDC 13x2 01rdquo plug Samtec SSW-113-01-T-D

Blackfin FPGA EZ-Extender Manual 2-19

Connectors

IDC Connectors (P5 and P7) The P5 and P7 connectors are standard 01rdquo IDC headers The connectors are in a 14 x 2 configuration and designed for signal probing bread boarding and other signal accesses

High-Speed Connector (P4) The high-speed connector P4 facilitates development of applications where use of the standard IDC connectors is complicated due to signal integrity issues

For the P4 connector and cable assembly availability and pricing contact Samtec

Part Description Manufacturer Part Number

IDC14x2 01rdquo header FCI 68737-428HLF

IDC14x2 01rdquo header Sullins GEC14DAAN

Mating Connector

IDC 14x2 01rdquo plug Samtec SSW-114-01-T-D

Part Description Manufacturer Part Number

QTS 25x2 high-speed connector Samtec QTS-025-01-F-D-A

Mating Connector

QSS 25x2 high-speed connector Samtec QSS-025-01-F-D-A

2-20 Blackfin FPGA EZ-Extender Manual

A BILL OF MATERIALS

The bill of materials corresponds to the board schematics on page B-1

Please check the latest schematics on the Analog Devices website httpwwwanalogcomProcessorsProcessorsDevelopmentToolstec

hnicalLibrarymanualsDevToolsIndexhtmlEvalua-

tion20Kit20Manuals

Blackfin FPGA EZ-Extender Manual A-1

Programming the FPGA

In addition to JP1 set the boot mode jumper JP4 to master serial mode The JP4 settings for serial ROM boot are shown in Table 2-5 See ldquoBoot Jumper (JP4)rdquo on page 2-14 for more information

FPGA Programming via Blackfin ApplicationBy default the FPGA EZ-Extender is configured by the flash program-ming utility within VisualDSP++ The software is located in the hellipBlackfinEZ-KITsFPGA EZ-EXTENDER subdirectory of the VisualDSP++ installation directory The FPGA Software Readmetxt file located in the same subdirectory provides all the necessary instructions required for run-ning the application

When generating a program file using the Xilinx software tools remember to generate a slave serial program file in the Intel MCS-86 Hexadecimal Object (mcs) file format

To boot the FPGA from the Blackfin processor unpopulate jumper JP1 and set jumper JP4 to slave serial mode as shown in Table 2-6 and Table 2-7 See ldquoSerial ROM Boot Jumper (JP1)rdquo on page 2-12 and ldquoBoot Jumper (JP4)rdquo on page 2-14 for more information

Table 2-5 JP4 Settings for FPGA Programming in Master Serial Mode

JP4 Pin Name Pins Connected Jumper Setting

M0 JP41 and JP42 Populated

M1 JP43 and JP44 Populated

M2 JP45 and JP46 Populated

Table 2-6 JP1 Settings for FPGA Programming via Blackfin Processor

JP1 Pin Name Pins Connected Jumper Setting

Flash done JP11 and JP12 Unpopulated

2-6 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Hardware Reference

Programming the Serial ROMThe FPGA EZ-Extender allows the user to program the serial ROM The serial ROM can be programmed by using a Xilinx JTAG cable ISE soft-ware and the flash JTAG header on the FPGA EZ-Extender

Serial ROM via JTAG HeaderTo program the serial ROM via the JTAG header create the appropriate program file using the Xilinx software provided at wwwxilinxcom Once the program file is created use a Xilinx JTAG cable and connect it to P6 The P6 connections are shown in Table 2-8

Table 2-7 JP4 Settings for FPGA Programming via Blackfin Processor

JP4 Pin Name Pins Connected Jumper Setting

M0 JP41 and JP42 Unpopulated

M1 JP43 and JP44 Unpopulated

M2 JP45 and JP46 Unpopulated

Table 2-8 P6 Connections for Serial ROM

P6 Pin Number Signal Name P6 Pin Number Signal Name

1 33V 4 TDO

2 GND 5 TDI

3 TCK 6 TMS

Blackfin FPGA EZ-Extender Manual 2-7

Power

PowerThe FPGA EZ-Extender can be powered from the enclosed power supply EZ-KIT Lite or external power supply The power source for the extender is selected based on the power requirements of the application

An external 7V power supply is shipped with the extender board The power supply uses three switching regulators VR1 is used to power the 25V power plane VR2 is used to power the 12V power plane and VR3 is used to power the 33V plane All of the regulators can supply a maximum current of 2 Amps To understand the power requirements of your appli-cation run the Xilinx power estimator software The software can be located at wwwxilinxcom

Table 2-9 states the current limitations of each method Each method requires a correctly configured header described in the following sections

Table 2-9 Power Limitations

Power Source 12V Supply 25V Supply 33V Supply

ADSP-BF533 ADSP-BF537 or ADSP-BF561 EZ-KIT Lite

500 mA 500 mA 500 mA

FPGA EZ-Extender power supply1

1 Default setting

2A 2A 2A

External power supply 2A 2A 2A

2-8 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Hardware Reference

Power In Header (P12)The P12 header supplies the power to the on board 12V and the 25V reg-ulators The P42 and P43 headers supply the power to the external 12V and 25V planes as described in ldquo25V Header (P42)rdquo and ldquo12V Header (P43)rdquo on page 2-10

33V Header (P13)

When using an external power supply do not plug in the power supply shipped with the FPGA EZ-Extender This can seriously damage the board As an extra measure of precaution remove all jumpers from P12

Power Source P12 Setting

FPGA EZ-Extender power supply1

1 Default setting

Jumper on P121 and P122

ADSP-BF533 ADSP-BF537 or ADSP-BF561 EZ-KIT Lite 5V power supply

Jumper on P122 and P123

Power Source P13 Setting

ADSP-BF533 ADSP-BF537 or ADSP-BF561 EZ-KIT Lite 33V power supply

Jumper on P131 and P132

FPGA EZ-Extender power supply1

1 Default setting

Jumper on P132 and P133

External power supply No jumper connect supply to P132 and GND

Blackfin FPGA EZ-Extender Manual 2-9

Power

25V Header (P42)

When using an external power supply do not plug in the power supply shipped with the FPGA EZ-Extender This can seriously damage the board As an extra measure of precaution remove all jumpers from P12

12V Header (P43)

When using an external power supply do not plug in the power supply shipped with the FPGA EZ-Extender This can seriously damage the board As an extra measure of precaution remove all jumpers from P12

Power Source P42 Setting

FPGA EZ-Extender Power Supply1

1 Default setting

No Jumper

External power supply Connect P421 to external 25VConnect P422 to external GND

Power Source P43 Setting

FPGA EZ-Extender power supply1

1 Default setting

No Jumper

External power supply Connect P421 to external 25VConnect P422 to external GND

2-10 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Hardware Reference

JumpersBefore using the Blackfin FPGA EZ-Extender follow the steps in ldquoFPGA EZ-Extender Setuprdquo on page 1-1

Figure 2-3 shows the locations of all jumper headers A two-pin jumper can be placed on the respective jumper header for different functionality The following sections describe all possible jumper settings and associated functionality

Figure 2-3 Jumper Locations

Blackfin FPGA EZ-Extender Manual 2-11

Jumpers

Serial ROM Boot Jumper (JP1)By default the serial ROM boot jumper JP1 is unpopulated When unpopulated the FPGA EZ-Extender programs via the Blackfin processor or the Xilinx JTAG header

When JP1 is left populated the jumper connects the serial ROM chip enable pin to the done bit of the FPGA At power-up the done bit is driven low by the FPGA causing the FPGA to enable the serial ROM as a programming source After the FPGA is programmed the done bit is driven high by the FPGA causing the FPGA to drive high the chip enable pin of the serial ROM

Both JP1 and JP4 must be set up for correct FPGA programming ldquoBoot Jumper (JP4)rdquo on page 2-14 summarizes the JP4 settings Table 2-10 sum-marizes the JP1 settings See Table 2-4 on page 2-5 and Table 2-6 on page 2-6 for more information on JP1

Config Done Jumper (JP2) The configuration done jumper JP2 connects the done bit of the FPGA to the Blackfin processorrsquos PF3 flag pin of the ADSP-BF533 and ADSP-BF561 EZ-KIT Lites or PF14 flag pin of the ADSP-BF537 EZ-KIT

Table 2-10 JP1 Settings

Boot Source JP1 Setting

ADSP-BF533 ADSP-BF537 or ADSP-BF561 processor via VisualDSP++1

1 Default setting

Unpopulated

JTAG header Unpopulated

Serial ROM Populated

2-12 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Hardware Reference

Lite By default the jumper is populated and acts as a monitor for the done bit by the Blackfin processor (the bit indicates that the FPGA pro-gramming is complete)

Table 2-11 summarizes the jumper settings

Config Program Jumper (JP3) The configuration program jumper JP3 connects the program bit of the FPGA to the Blackfin processorrsquos flag pin By default JP3 is populated The jumper assures that the program bit is asserted by the Blackfin proces-sor to initiate the FPGA programming through VisualDSP++ software

Table 2-12 summarizes the jumper settings

Table 2-11 JP2 Settings

Functionality JP2 Setting

Done bit connected to Blackfin processorrsquos PF3 flag pin1

1 Default setting

Populated

Done bit disconnected from Blackfin processorrsquos PF3 flag pin

Unpopulated

Table 2-12 JP3 Settings

Functionality JP3 Setting

Program bit connected to the Blackfin processorrsquos flag pin1

1 Default setting

Populated

Program bit disconnected from the Blackfin proces-sorrsquos flag pin

Unpopulated

Blackfin FPGA EZ-Extender Manual 2-13

Jumpers

Boot Jumper (JP4) The boot jumper JP4 configures the FPGA mode pins (M[20]) Based on the jumper settings the FPGA is set to be programmed by the JTAG header serial ROM or Blackfin processor

Table 2-13 summarizes the jumper settings See Table 2-3 on page 2-5 for the JTAG header boot settings Table 2-5 on page 2-6 for the serial ROM boot settings and Table 2-7 on page 2-7 for the Blackfin processor boot settings

FPGA Input Jumpers (JP5) The FPGA input jumpers JP52ndash58 drive select FPGA nets to a logic 0 and can be used for any user logic that requires a steady state input You can set internal pull-ups on these nets in the FPGA and when a low is required populate the respective jumper

Table 2-14 summarizes the jumper settings

Table 2-13 JP4 Settings

Boot Source JP41 and JP42M0

JP43 and JP44M1

JP45 and JP46M2

ADSP-BF533ADSP-BF537 orADSP-BF561 processor1

1 Default setting

Unpopulated Unpopulated Unpopulated

JTAG header Unpopulated Populated Unpopulated

Serial ROM Populated Populated Populated

2-14 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Hardware Reference

Push Buttons and LEDsBefore using the Blackfin FPGA EZ-Extender follow the steps in ldquoFPGA EZ-Extender Setuprdquo on page 1-1

Figure 2-4 shows the locations of all push buttons and LEDs The follow-ing sections describe the associated functionality of all the push buttons and LEDs

Program Push Button (SW1)The program push button SW1 erases the contents of the FPGA The push button can be used as a hard resetmdashthe FPGA must be completely re-programmed once SW1 is de-pressed See ldquoProgramming the FPGArdquo on page 2-3 for more information

PB1 Push Button (SW3)The PB1 push button SW3 is a general-purpose input push button The switch with a connected debounce circuit eliminates the need to re-create it in the FPGA The push button connects to pin C11 of the FPGA

Table 2-14 JP5 Settings

Reference Designator FPGA Pin Number

JP52 Y3

JP54 Y2

JP56 U10

JP58 AB11

Blackfin FPGA EZ-Extender Manual 2-15

Push Buttons and LEDs

PB2 Push Button (SW4) The PB2 push button SW4 is a general-purpose input push button The switch does not have a connected debounce circuit you may need to cre-ate it in the FPGA if required by a specific application The push button connects to pin H5 of the FPGA

Figure 2-4 Push Button and LED Locations

2-16 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Hardware Reference

Status LEDs (LED1ndash8) Eight status LEDs LED1ndash8 connect to the FPGA and act as status flags in any application that requires it Table 2-15 shows the LEDFPGA connections

Power LED (LED9) The power LED LED9 connects to the 25V power supply and when lit signifies that the FPGA EZ-Extender is powered properly

Done LED (LED10) The done LED LED10 connects to the done pin of the FPGA At power-up the FPGA is blank and needs to be programmed When lit the LED indicates that the FPGA is programmed successfully

Table 2-15 Status LED (LED1ndash8) Settings

Reference Designator FPGA Pin Number

LED1 U11

LED2 W11

LED3 AB10

LED4 Y10

LED5 AB9

LED6 W9

LED7 AB8

LED8 V10

Blackfin FPGA EZ-Extender Manual 2-17

Connectors

ConnectorsBefore using the Blackfin FPGA EZ-Extender follow the steps in ldquoFPGA EZ-Extender Setuprdquo on page 1-1

This section describes the connector functionality and provides informa-tion about the mating connectors The connector locations are shown in Figure 2-5

Figure 2-5 Connector Locations

2-18 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Hardware Reference

Expansion Interface (P1ndash3 and J1ndash3) Connectors P1ndash3 of the expansion interface are used to plug in the EZ-Extender to the ADSP-BF533 ADSP-BF537 or ADSP-BF561 EZ-KIT Lite

Connectors J1ndash3 of the expansion interface are used to plug in another extender board such as the Blackfin USB-LAN EZ-Extender Your own custom board can be plugged into J1ndash3 as well

Plugging in another EZ-Extender or a customer board to the expansion interface can de-grade the overall system performance The extra overall load can cause the user to add wait states or slow down the system bus to get all of the boards to work properly

For the J1ndash3 and P1ndash3 connector availability and pricing contact Samtec

IDC Connectors (P8 P14 P16 and P17) The P8 P14 P16 and P17 connectors are standard 01rdquo IDC headers The connectors are in a 13 x 2 configuration and designed for signal probing bread boarding and other signal accesses

Part Description Manufacturer Part Number

90-position 005rdquo spacing SMT(J1 J2 J3)

Samtec SFC-145-T2-F-D-A

90-position 005rdquo spacing (P1 P2 P3)

Samtec TFC-145-32-F-D

Part Description Manufacturer Part Number

IDC13x2 01rdquo header Berg 54102-T08-13

Mating Connector

IDC 13x2 01rdquo plug Samtec SSW-113-01-T-D

Blackfin FPGA EZ-Extender Manual 2-19

Connectors

IDC Connectors (P5 and P7) The P5 and P7 connectors are standard 01rdquo IDC headers The connectors are in a 14 x 2 configuration and designed for signal probing bread boarding and other signal accesses

High-Speed Connector (P4) The high-speed connector P4 facilitates development of applications where use of the standard IDC connectors is complicated due to signal integrity issues

For the P4 connector and cable assembly availability and pricing contact Samtec

Part Description Manufacturer Part Number

IDC14x2 01rdquo header FCI 68737-428HLF

IDC14x2 01rdquo header Sullins GEC14DAAN

Mating Connector

IDC 14x2 01rdquo plug Samtec SSW-114-01-T-D

Part Description Manufacturer Part Number

QTS 25x2 high-speed connector Samtec QTS-025-01-F-D-A

Mating Connector

QSS 25x2 high-speed connector Samtec QSS-025-01-F-D-A

2-20 Blackfin FPGA EZ-Extender Manual

A BILL OF MATERIALS

The bill of materials corresponds to the board schematics on page B-1

Please check the latest schematics on the Analog Devices website httpwwwanalogcomProcessorsProcessorsDevelopmentToolstec

hnicalLibrarymanualsDevToolsIndexhtmlEvalua-

tion20Kit20Manuals

Blackfin FPGA EZ-Extender Manual A-1

FPGA EZ-Extender Hardware Reference

Programming the Serial ROMThe FPGA EZ-Extender allows the user to program the serial ROM The serial ROM can be programmed by using a Xilinx JTAG cable ISE soft-ware and the flash JTAG header on the FPGA EZ-Extender

Serial ROM via JTAG HeaderTo program the serial ROM via the JTAG header create the appropriate program file using the Xilinx software provided at wwwxilinxcom Once the program file is created use a Xilinx JTAG cable and connect it to P6 The P6 connections are shown in Table 2-8

Table 2-7 JP4 Settings for FPGA Programming via Blackfin Processor

JP4 Pin Name Pins Connected Jumper Setting

M0 JP41 and JP42 Unpopulated

M1 JP43 and JP44 Unpopulated

M2 JP45 and JP46 Unpopulated

Table 2-8 P6 Connections for Serial ROM

P6 Pin Number Signal Name P6 Pin Number Signal Name

1 33V 4 TDO

2 GND 5 TDI

3 TCK 6 TMS

Blackfin FPGA EZ-Extender Manual 2-7

Power

PowerThe FPGA EZ-Extender can be powered from the enclosed power supply EZ-KIT Lite or external power supply The power source for the extender is selected based on the power requirements of the application

An external 7V power supply is shipped with the extender board The power supply uses three switching regulators VR1 is used to power the 25V power plane VR2 is used to power the 12V power plane and VR3 is used to power the 33V plane All of the regulators can supply a maximum current of 2 Amps To understand the power requirements of your appli-cation run the Xilinx power estimator software The software can be located at wwwxilinxcom

Table 2-9 states the current limitations of each method Each method requires a correctly configured header described in the following sections

Table 2-9 Power Limitations

Power Source 12V Supply 25V Supply 33V Supply

ADSP-BF533 ADSP-BF537 or ADSP-BF561 EZ-KIT Lite

500 mA 500 mA 500 mA

FPGA EZ-Extender power supply1

1 Default setting

2A 2A 2A

External power supply 2A 2A 2A

2-8 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Hardware Reference

Power In Header (P12)The P12 header supplies the power to the on board 12V and the 25V reg-ulators The P42 and P43 headers supply the power to the external 12V and 25V planes as described in ldquo25V Header (P42)rdquo and ldquo12V Header (P43)rdquo on page 2-10

33V Header (P13)

When using an external power supply do not plug in the power supply shipped with the FPGA EZ-Extender This can seriously damage the board As an extra measure of precaution remove all jumpers from P12

Power Source P12 Setting

FPGA EZ-Extender power supply1

1 Default setting

Jumper on P121 and P122

ADSP-BF533 ADSP-BF537 or ADSP-BF561 EZ-KIT Lite 5V power supply

Jumper on P122 and P123

Power Source P13 Setting

ADSP-BF533 ADSP-BF537 or ADSP-BF561 EZ-KIT Lite 33V power supply

Jumper on P131 and P132

FPGA EZ-Extender power supply1

1 Default setting

Jumper on P132 and P133

External power supply No jumper connect supply to P132 and GND

Blackfin FPGA EZ-Extender Manual 2-9

Power

25V Header (P42)

When using an external power supply do not plug in the power supply shipped with the FPGA EZ-Extender This can seriously damage the board As an extra measure of precaution remove all jumpers from P12

12V Header (P43)

When using an external power supply do not plug in the power supply shipped with the FPGA EZ-Extender This can seriously damage the board As an extra measure of precaution remove all jumpers from P12

Power Source P42 Setting

FPGA EZ-Extender Power Supply1

1 Default setting

No Jumper

External power supply Connect P421 to external 25VConnect P422 to external GND

Power Source P43 Setting

FPGA EZ-Extender power supply1

1 Default setting

No Jumper

External power supply Connect P421 to external 25VConnect P422 to external GND

2-10 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Hardware Reference

JumpersBefore using the Blackfin FPGA EZ-Extender follow the steps in ldquoFPGA EZ-Extender Setuprdquo on page 1-1

Figure 2-3 shows the locations of all jumper headers A two-pin jumper can be placed on the respective jumper header for different functionality The following sections describe all possible jumper settings and associated functionality

Figure 2-3 Jumper Locations

Blackfin FPGA EZ-Extender Manual 2-11

Jumpers

Serial ROM Boot Jumper (JP1)By default the serial ROM boot jumper JP1 is unpopulated When unpopulated the FPGA EZ-Extender programs via the Blackfin processor or the Xilinx JTAG header

When JP1 is left populated the jumper connects the serial ROM chip enable pin to the done bit of the FPGA At power-up the done bit is driven low by the FPGA causing the FPGA to enable the serial ROM as a programming source After the FPGA is programmed the done bit is driven high by the FPGA causing the FPGA to drive high the chip enable pin of the serial ROM

Both JP1 and JP4 must be set up for correct FPGA programming ldquoBoot Jumper (JP4)rdquo on page 2-14 summarizes the JP4 settings Table 2-10 sum-marizes the JP1 settings See Table 2-4 on page 2-5 and Table 2-6 on page 2-6 for more information on JP1

Config Done Jumper (JP2) The configuration done jumper JP2 connects the done bit of the FPGA to the Blackfin processorrsquos PF3 flag pin of the ADSP-BF533 and ADSP-BF561 EZ-KIT Lites or PF14 flag pin of the ADSP-BF537 EZ-KIT

Table 2-10 JP1 Settings

Boot Source JP1 Setting

ADSP-BF533 ADSP-BF537 or ADSP-BF561 processor via VisualDSP++1

1 Default setting

Unpopulated

JTAG header Unpopulated

Serial ROM Populated

2-12 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Hardware Reference

Lite By default the jumper is populated and acts as a monitor for the done bit by the Blackfin processor (the bit indicates that the FPGA pro-gramming is complete)

Table 2-11 summarizes the jumper settings

Config Program Jumper (JP3) The configuration program jumper JP3 connects the program bit of the FPGA to the Blackfin processorrsquos flag pin By default JP3 is populated The jumper assures that the program bit is asserted by the Blackfin proces-sor to initiate the FPGA programming through VisualDSP++ software

Table 2-12 summarizes the jumper settings

Table 2-11 JP2 Settings

Functionality JP2 Setting

Done bit connected to Blackfin processorrsquos PF3 flag pin1

1 Default setting

Populated

Done bit disconnected from Blackfin processorrsquos PF3 flag pin

Unpopulated

Table 2-12 JP3 Settings

Functionality JP3 Setting

Program bit connected to the Blackfin processorrsquos flag pin1

1 Default setting

Populated

Program bit disconnected from the Blackfin proces-sorrsquos flag pin

Unpopulated

Blackfin FPGA EZ-Extender Manual 2-13

Jumpers

Boot Jumper (JP4) The boot jumper JP4 configures the FPGA mode pins (M[20]) Based on the jumper settings the FPGA is set to be programmed by the JTAG header serial ROM or Blackfin processor

Table 2-13 summarizes the jumper settings See Table 2-3 on page 2-5 for the JTAG header boot settings Table 2-5 on page 2-6 for the serial ROM boot settings and Table 2-7 on page 2-7 for the Blackfin processor boot settings

FPGA Input Jumpers (JP5) The FPGA input jumpers JP52ndash58 drive select FPGA nets to a logic 0 and can be used for any user logic that requires a steady state input You can set internal pull-ups on these nets in the FPGA and when a low is required populate the respective jumper

Table 2-14 summarizes the jumper settings

Table 2-13 JP4 Settings

Boot Source JP41 and JP42M0

JP43 and JP44M1

JP45 and JP46M2

ADSP-BF533ADSP-BF537 orADSP-BF561 processor1

1 Default setting

Unpopulated Unpopulated Unpopulated

JTAG header Unpopulated Populated Unpopulated

Serial ROM Populated Populated Populated

2-14 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Hardware Reference

Push Buttons and LEDsBefore using the Blackfin FPGA EZ-Extender follow the steps in ldquoFPGA EZ-Extender Setuprdquo on page 1-1

Figure 2-4 shows the locations of all push buttons and LEDs The follow-ing sections describe the associated functionality of all the push buttons and LEDs

Program Push Button (SW1)The program push button SW1 erases the contents of the FPGA The push button can be used as a hard resetmdashthe FPGA must be completely re-programmed once SW1 is de-pressed See ldquoProgramming the FPGArdquo on page 2-3 for more information

PB1 Push Button (SW3)The PB1 push button SW3 is a general-purpose input push button The switch with a connected debounce circuit eliminates the need to re-create it in the FPGA The push button connects to pin C11 of the FPGA

Table 2-14 JP5 Settings

Reference Designator FPGA Pin Number

JP52 Y3

JP54 Y2

JP56 U10

JP58 AB11

Blackfin FPGA EZ-Extender Manual 2-15

Push Buttons and LEDs

PB2 Push Button (SW4) The PB2 push button SW4 is a general-purpose input push button The switch does not have a connected debounce circuit you may need to cre-ate it in the FPGA if required by a specific application The push button connects to pin H5 of the FPGA

Figure 2-4 Push Button and LED Locations

2-16 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Hardware Reference

Status LEDs (LED1ndash8) Eight status LEDs LED1ndash8 connect to the FPGA and act as status flags in any application that requires it Table 2-15 shows the LEDFPGA connections

Power LED (LED9) The power LED LED9 connects to the 25V power supply and when lit signifies that the FPGA EZ-Extender is powered properly

Done LED (LED10) The done LED LED10 connects to the done pin of the FPGA At power-up the FPGA is blank and needs to be programmed When lit the LED indicates that the FPGA is programmed successfully

Table 2-15 Status LED (LED1ndash8) Settings

Reference Designator FPGA Pin Number

LED1 U11

LED2 W11

LED3 AB10

LED4 Y10

LED5 AB9

LED6 W9

LED7 AB8

LED8 V10

Blackfin FPGA EZ-Extender Manual 2-17

Connectors

ConnectorsBefore using the Blackfin FPGA EZ-Extender follow the steps in ldquoFPGA EZ-Extender Setuprdquo on page 1-1

This section describes the connector functionality and provides informa-tion about the mating connectors The connector locations are shown in Figure 2-5

Figure 2-5 Connector Locations

2-18 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Hardware Reference

Expansion Interface (P1ndash3 and J1ndash3) Connectors P1ndash3 of the expansion interface are used to plug in the EZ-Extender to the ADSP-BF533 ADSP-BF537 or ADSP-BF561 EZ-KIT Lite

Connectors J1ndash3 of the expansion interface are used to plug in another extender board such as the Blackfin USB-LAN EZ-Extender Your own custom board can be plugged into J1ndash3 as well

Plugging in another EZ-Extender or a customer board to the expansion interface can de-grade the overall system performance The extra overall load can cause the user to add wait states or slow down the system bus to get all of the boards to work properly

For the J1ndash3 and P1ndash3 connector availability and pricing contact Samtec

IDC Connectors (P8 P14 P16 and P17) The P8 P14 P16 and P17 connectors are standard 01rdquo IDC headers The connectors are in a 13 x 2 configuration and designed for signal probing bread boarding and other signal accesses

Part Description Manufacturer Part Number

90-position 005rdquo spacing SMT(J1 J2 J3)

Samtec SFC-145-T2-F-D-A

90-position 005rdquo spacing (P1 P2 P3)

Samtec TFC-145-32-F-D

Part Description Manufacturer Part Number

IDC13x2 01rdquo header Berg 54102-T08-13

Mating Connector

IDC 13x2 01rdquo plug Samtec SSW-113-01-T-D

Blackfin FPGA EZ-Extender Manual 2-19

Connectors

IDC Connectors (P5 and P7) The P5 and P7 connectors are standard 01rdquo IDC headers The connectors are in a 14 x 2 configuration and designed for signal probing bread boarding and other signal accesses

High-Speed Connector (P4) The high-speed connector P4 facilitates development of applications where use of the standard IDC connectors is complicated due to signal integrity issues

For the P4 connector and cable assembly availability and pricing contact Samtec

Part Description Manufacturer Part Number

IDC14x2 01rdquo header FCI 68737-428HLF

IDC14x2 01rdquo header Sullins GEC14DAAN

Mating Connector

IDC 14x2 01rdquo plug Samtec SSW-114-01-T-D

Part Description Manufacturer Part Number

QTS 25x2 high-speed connector Samtec QTS-025-01-F-D-A

Mating Connector

QSS 25x2 high-speed connector Samtec QSS-025-01-F-D-A

2-20 Blackfin FPGA EZ-Extender Manual

A BILL OF MATERIALS

The bill of materials corresponds to the board schematics on page B-1

Please check the latest schematics on the Analog Devices website httpwwwanalogcomProcessorsProcessorsDevelopmentToolstec

hnicalLibrarymanualsDevToolsIndexhtmlEvalua-

tion20Kit20Manuals

Blackfin FPGA EZ-Extender Manual A-1

Power

PowerThe FPGA EZ-Extender can be powered from the enclosed power supply EZ-KIT Lite or external power supply The power source for the extender is selected based on the power requirements of the application

An external 7V power supply is shipped with the extender board The power supply uses three switching regulators VR1 is used to power the 25V power plane VR2 is used to power the 12V power plane and VR3 is used to power the 33V plane All of the regulators can supply a maximum current of 2 Amps To understand the power requirements of your appli-cation run the Xilinx power estimator software The software can be located at wwwxilinxcom

Table 2-9 states the current limitations of each method Each method requires a correctly configured header described in the following sections

Table 2-9 Power Limitations

Power Source 12V Supply 25V Supply 33V Supply

ADSP-BF533 ADSP-BF537 or ADSP-BF561 EZ-KIT Lite

500 mA 500 mA 500 mA

FPGA EZ-Extender power supply1

1 Default setting

2A 2A 2A

External power supply 2A 2A 2A

2-8 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Hardware Reference

Power In Header (P12)The P12 header supplies the power to the on board 12V and the 25V reg-ulators The P42 and P43 headers supply the power to the external 12V and 25V planes as described in ldquo25V Header (P42)rdquo and ldquo12V Header (P43)rdquo on page 2-10

33V Header (P13)

When using an external power supply do not plug in the power supply shipped with the FPGA EZ-Extender This can seriously damage the board As an extra measure of precaution remove all jumpers from P12

Power Source P12 Setting

FPGA EZ-Extender power supply1

1 Default setting

Jumper on P121 and P122

ADSP-BF533 ADSP-BF537 or ADSP-BF561 EZ-KIT Lite 5V power supply

Jumper on P122 and P123

Power Source P13 Setting

ADSP-BF533 ADSP-BF537 or ADSP-BF561 EZ-KIT Lite 33V power supply

Jumper on P131 and P132

FPGA EZ-Extender power supply1

1 Default setting

Jumper on P132 and P133

External power supply No jumper connect supply to P132 and GND

Blackfin FPGA EZ-Extender Manual 2-9

Power

25V Header (P42)

When using an external power supply do not plug in the power supply shipped with the FPGA EZ-Extender This can seriously damage the board As an extra measure of precaution remove all jumpers from P12

12V Header (P43)

When using an external power supply do not plug in the power supply shipped with the FPGA EZ-Extender This can seriously damage the board As an extra measure of precaution remove all jumpers from P12

Power Source P42 Setting

FPGA EZ-Extender Power Supply1

1 Default setting

No Jumper

External power supply Connect P421 to external 25VConnect P422 to external GND

Power Source P43 Setting

FPGA EZ-Extender power supply1

1 Default setting

No Jumper

External power supply Connect P421 to external 25VConnect P422 to external GND

2-10 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Hardware Reference

JumpersBefore using the Blackfin FPGA EZ-Extender follow the steps in ldquoFPGA EZ-Extender Setuprdquo on page 1-1

Figure 2-3 shows the locations of all jumper headers A two-pin jumper can be placed on the respective jumper header for different functionality The following sections describe all possible jumper settings and associated functionality

Figure 2-3 Jumper Locations

Blackfin FPGA EZ-Extender Manual 2-11

Jumpers

Serial ROM Boot Jumper (JP1)By default the serial ROM boot jumper JP1 is unpopulated When unpopulated the FPGA EZ-Extender programs via the Blackfin processor or the Xilinx JTAG header

When JP1 is left populated the jumper connects the serial ROM chip enable pin to the done bit of the FPGA At power-up the done bit is driven low by the FPGA causing the FPGA to enable the serial ROM as a programming source After the FPGA is programmed the done bit is driven high by the FPGA causing the FPGA to drive high the chip enable pin of the serial ROM

Both JP1 and JP4 must be set up for correct FPGA programming ldquoBoot Jumper (JP4)rdquo on page 2-14 summarizes the JP4 settings Table 2-10 sum-marizes the JP1 settings See Table 2-4 on page 2-5 and Table 2-6 on page 2-6 for more information on JP1

Config Done Jumper (JP2) The configuration done jumper JP2 connects the done bit of the FPGA to the Blackfin processorrsquos PF3 flag pin of the ADSP-BF533 and ADSP-BF561 EZ-KIT Lites or PF14 flag pin of the ADSP-BF537 EZ-KIT

Table 2-10 JP1 Settings

Boot Source JP1 Setting

ADSP-BF533 ADSP-BF537 or ADSP-BF561 processor via VisualDSP++1

1 Default setting

Unpopulated

JTAG header Unpopulated

Serial ROM Populated

2-12 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Hardware Reference

Lite By default the jumper is populated and acts as a monitor for the done bit by the Blackfin processor (the bit indicates that the FPGA pro-gramming is complete)

Table 2-11 summarizes the jumper settings

Config Program Jumper (JP3) The configuration program jumper JP3 connects the program bit of the FPGA to the Blackfin processorrsquos flag pin By default JP3 is populated The jumper assures that the program bit is asserted by the Blackfin proces-sor to initiate the FPGA programming through VisualDSP++ software

Table 2-12 summarizes the jumper settings

Table 2-11 JP2 Settings

Functionality JP2 Setting

Done bit connected to Blackfin processorrsquos PF3 flag pin1

1 Default setting

Populated

Done bit disconnected from Blackfin processorrsquos PF3 flag pin

Unpopulated

Table 2-12 JP3 Settings

Functionality JP3 Setting

Program bit connected to the Blackfin processorrsquos flag pin1

1 Default setting

Populated

Program bit disconnected from the Blackfin proces-sorrsquos flag pin

Unpopulated

Blackfin FPGA EZ-Extender Manual 2-13

Jumpers

Boot Jumper (JP4) The boot jumper JP4 configures the FPGA mode pins (M[20]) Based on the jumper settings the FPGA is set to be programmed by the JTAG header serial ROM or Blackfin processor

Table 2-13 summarizes the jumper settings See Table 2-3 on page 2-5 for the JTAG header boot settings Table 2-5 on page 2-6 for the serial ROM boot settings and Table 2-7 on page 2-7 for the Blackfin processor boot settings

FPGA Input Jumpers (JP5) The FPGA input jumpers JP52ndash58 drive select FPGA nets to a logic 0 and can be used for any user logic that requires a steady state input You can set internal pull-ups on these nets in the FPGA and when a low is required populate the respective jumper

Table 2-14 summarizes the jumper settings

Table 2-13 JP4 Settings

Boot Source JP41 and JP42M0

JP43 and JP44M1

JP45 and JP46M2

ADSP-BF533ADSP-BF537 orADSP-BF561 processor1

1 Default setting

Unpopulated Unpopulated Unpopulated

JTAG header Unpopulated Populated Unpopulated

Serial ROM Populated Populated Populated

2-14 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Hardware Reference

Push Buttons and LEDsBefore using the Blackfin FPGA EZ-Extender follow the steps in ldquoFPGA EZ-Extender Setuprdquo on page 1-1

Figure 2-4 shows the locations of all push buttons and LEDs The follow-ing sections describe the associated functionality of all the push buttons and LEDs

Program Push Button (SW1)The program push button SW1 erases the contents of the FPGA The push button can be used as a hard resetmdashthe FPGA must be completely re-programmed once SW1 is de-pressed See ldquoProgramming the FPGArdquo on page 2-3 for more information

PB1 Push Button (SW3)The PB1 push button SW3 is a general-purpose input push button The switch with a connected debounce circuit eliminates the need to re-create it in the FPGA The push button connects to pin C11 of the FPGA

Table 2-14 JP5 Settings

Reference Designator FPGA Pin Number

JP52 Y3

JP54 Y2

JP56 U10

JP58 AB11

Blackfin FPGA EZ-Extender Manual 2-15

Push Buttons and LEDs

PB2 Push Button (SW4) The PB2 push button SW4 is a general-purpose input push button The switch does not have a connected debounce circuit you may need to cre-ate it in the FPGA if required by a specific application The push button connects to pin H5 of the FPGA

Figure 2-4 Push Button and LED Locations

2-16 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Hardware Reference

Status LEDs (LED1ndash8) Eight status LEDs LED1ndash8 connect to the FPGA and act as status flags in any application that requires it Table 2-15 shows the LEDFPGA connections

Power LED (LED9) The power LED LED9 connects to the 25V power supply and when lit signifies that the FPGA EZ-Extender is powered properly

Done LED (LED10) The done LED LED10 connects to the done pin of the FPGA At power-up the FPGA is blank and needs to be programmed When lit the LED indicates that the FPGA is programmed successfully

Table 2-15 Status LED (LED1ndash8) Settings

Reference Designator FPGA Pin Number

LED1 U11

LED2 W11

LED3 AB10

LED4 Y10

LED5 AB9

LED6 W9

LED7 AB8

LED8 V10

Blackfin FPGA EZ-Extender Manual 2-17

Connectors

ConnectorsBefore using the Blackfin FPGA EZ-Extender follow the steps in ldquoFPGA EZ-Extender Setuprdquo on page 1-1

This section describes the connector functionality and provides informa-tion about the mating connectors The connector locations are shown in Figure 2-5

Figure 2-5 Connector Locations

2-18 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Hardware Reference

Expansion Interface (P1ndash3 and J1ndash3) Connectors P1ndash3 of the expansion interface are used to plug in the EZ-Extender to the ADSP-BF533 ADSP-BF537 or ADSP-BF561 EZ-KIT Lite

Connectors J1ndash3 of the expansion interface are used to plug in another extender board such as the Blackfin USB-LAN EZ-Extender Your own custom board can be plugged into J1ndash3 as well

Plugging in another EZ-Extender or a customer board to the expansion interface can de-grade the overall system performance The extra overall load can cause the user to add wait states or slow down the system bus to get all of the boards to work properly

For the J1ndash3 and P1ndash3 connector availability and pricing contact Samtec

IDC Connectors (P8 P14 P16 and P17) The P8 P14 P16 and P17 connectors are standard 01rdquo IDC headers The connectors are in a 13 x 2 configuration and designed for signal probing bread boarding and other signal accesses

Part Description Manufacturer Part Number

90-position 005rdquo spacing SMT(J1 J2 J3)

Samtec SFC-145-T2-F-D-A

90-position 005rdquo spacing (P1 P2 P3)

Samtec TFC-145-32-F-D

Part Description Manufacturer Part Number

IDC13x2 01rdquo header Berg 54102-T08-13

Mating Connector

IDC 13x2 01rdquo plug Samtec SSW-113-01-T-D

Blackfin FPGA EZ-Extender Manual 2-19

Connectors

IDC Connectors (P5 and P7) The P5 and P7 connectors are standard 01rdquo IDC headers The connectors are in a 14 x 2 configuration and designed for signal probing bread boarding and other signal accesses

High-Speed Connector (P4) The high-speed connector P4 facilitates development of applications where use of the standard IDC connectors is complicated due to signal integrity issues

For the P4 connector and cable assembly availability and pricing contact Samtec

Part Description Manufacturer Part Number

IDC14x2 01rdquo header FCI 68737-428HLF

IDC14x2 01rdquo header Sullins GEC14DAAN

Mating Connector

IDC 14x2 01rdquo plug Samtec SSW-114-01-T-D

Part Description Manufacturer Part Number

QTS 25x2 high-speed connector Samtec QTS-025-01-F-D-A

Mating Connector

QSS 25x2 high-speed connector Samtec QSS-025-01-F-D-A

2-20 Blackfin FPGA EZ-Extender Manual

A BILL OF MATERIALS

The bill of materials corresponds to the board schematics on page B-1

Please check the latest schematics on the Analog Devices website httpwwwanalogcomProcessorsProcessorsDevelopmentToolstec

hnicalLibrarymanualsDevToolsIndexhtmlEvalua-

tion20Kit20Manuals

Blackfin FPGA EZ-Extender Manual A-1

FPGA EZ-Extender Hardware Reference

Power In Header (P12)The P12 header supplies the power to the on board 12V and the 25V reg-ulators The P42 and P43 headers supply the power to the external 12V and 25V planes as described in ldquo25V Header (P42)rdquo and ldquo12V Header (P43)rdquo on page 2-10

33V Header (P13)

When using an external power supply do not plug in the power supply shipped with the FPGA EZ-Extender This can seriously damage the board As an extra measure of precaution remove all jumpers from P12

Power Source P12 Setting

FPGA EZ-Extender power supply1

1 Default setting

Jumper on P121 and P122

ADSP-BF533 ADSP-BF537 or ADSP-BF561 EZ-KIT Lite 5V power supply

Jumper on P122 and P123

Power Source P13 Setting

ADSP-BF533 ADSP-BF537 or ADSP-BF561 EZ-KIT Lite 33V power supply

Jumper on P131 and P132

FPGA EZ-Extender power supply1

1 Default setting

Jumper on P132 and P133

External power supply No jumper connect supply to P132 and GND

Blackfin FPGA EZ-Extender Manual 2-9

Power

25V Header (P42)

When using an external power supply do not plug in the power supply shipped with the FPGA EZ-Extender This can seriously damage the board As an extra measure of precaution remove all jumpers from P12

12V Header (P43)

When using an external power supply do not plug in the power supply shipped with the FPGA EZ-Extender This can seriously damage the board As an extra measure of precaution remove all jumpers from P12

Power Source P42 Setting

FPGA EZ-Extender Power Supply1

1 Default setting

No Jumper

External power supply Connect P421 to external 25VConnect P422 to external GND

Power Source P43 Setting

FPGA EZ-Extender power supply1

1 Default setting

No Jumper

External power supply Connect P421 to external 25VConnect P422 to external GND

2-10 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Hardware Reference

JumpersBefore using the Blackfin FPGA EZ-Extender follow the steps in ldquoFPGA EZ-Extender Setuprdquo on page 1-1

Figure 2-3 shows the locations of all jumper headers A two-pin jumper can be placed on the respective jumper header for different functionality The following sections describe all possible jumper settings and associated functionality

Figure 2-3 Jumper Locations

Blackfin FPGA EZ-Extender Manual 2-11

Jumpers

Serial ROM Boot Jumper (JP1)By default the serial ROM boot jumper JP1 is unpopulated When unpopulated the FPGA EZ-Extender programs via the Blackfin processor or the Xilinx JTAG header

When JP1 is left populated the jumper connects the serial ROM chip enable pin to the done bit of the FPGA At power-up the done bit is driven low by the FPGA causing the FPGA to enable the serial ROM as a programming source After the FPGA is programmed the done bit is driven high by the FPGA causing the FPGA to drive high the chip enable pin of the serial ROM

Both JP1 and JP4 must be set up for correct FPGA programming ldquoBoot Jumper (JP4)rdquo on page 2-14 summarizes the JP4 settings Table 2-10 sum-marizes the JP1 settings See Table 2-4 on page 2-5 and Table 2-6 on page 2-6 for more information on JP1

Config Done Jumper (JP2) The configuration done jumper JP2 connects the done bit of the FPGA to the Blackfin processorrsquos PF3 flag pin of the ADSP-BF533 and ADSP-BF561 EZ-KIT Lites or PF14 flag pin of the ADSP-BF537 EZ-KIT

Table 2-10 JP1 Settings

Boot Source JP1 Setting

ADSP-BF533 ADSP-BF537 or ADSP-BF561 processor via VisualDSP++1

1 Default setting

Unpopulated

JTAG header Unpopulated

Serial ROM Populated

2-12 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Hardware Reference

Lite By default the jumper is populated and acts as a monitor for the done bit by the Blackfin processor (the bit indicates that the FPGA pro-gramming is complete)

Table 2-11 summarizes the jumper settings

Config Program Jumper (JP3) The configuration program jumper JP3 connects the program bit of the FPGA to the Blackfin processorrsquos flag pin By default JP3 is populated The jumper assures that the program bit is asserted by the Blackfin proces-sor to initiate the FPGA programming through VisualDSP++ software

Table 2-12 summarizes the jumper settings

Table 2-11 JP2 Settings

Functionality JP2 Setting

Done bit connected to Blackfin processorrsquos PF3 flag pin1

1 Default setting

Populated

Done bit disconnected from Blackfin processorrsquos PF3 flag pin

Unpopulated

Table 2-12 JP3 Settings

Functionality JP3 Setting

Program bit connected to the Blackfin processorrsquos flag pin1

1 Default setting

Populated

Program bit disconnected from the Blackfin proces-sorrsquos flag pin

Unpopulated

Blackfin FPGA EZ-Extender Manual 2-13

Jumpers

Boot Jumper (JP4) The boot jumper JP4 configures the FPGA mode pins (M[20]) Based on the jumper settings the FPGA is set to be programmed by the JTAG header serial ROM or Blackfin processor

Table 2-13 summarizes the jumper settings See Table 2-3 on page 2-5 for the JTAG header boot settings Table 2-5 on page 2-6 for the serial ROM boot settings and Table 2-7 on page 2-7 for the Blackfin processor boot settings

FPGA Input Jumpers (JP5) The FPGA input jumpers JP52ndash58 drive select FPGA nets to a logic 0 and can be used for any user logic that requires a steady state input You can set internal pull-ups on these nets in the FPGA and when a low is required populate the respective jumper

Table 2-14 summarizes the jumper settings

Table 2-13 JP4 Settings

Boot Source JP41 and JP42M0

JP43 and JP44M1

JP45 and JP46M2

ADSP-BF533ADSP-BF537 orADSP-BF561 processor1

1 Default setting

Unpopulated Unpopulated Unpopulated

JTAG header Unpopulated Populated Unpopulated

Serial ROM Populated Populated Populated

2-14 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Hardware Reference

Push Buttons and LEDsBefore using the Blackfin FPGA EZ-Extender follow the steps in ldquoFPGA EZ-Extender Setuprdquo on page 1-1

Figure 2-4 shows the locations of all push buttons and LEDs The follow-ing sections describe the associated functionality of all the push buttons and LEDs

Program Push Button (SW1)The program push button SW1 erases the contents of the FPGA The push button can be used as a hard resetmdashthe FPGA must be completely re-programmed once SW1 is de-pressed See ldquoProgramming the FPGArdquo on page 2-3 for more information

PB1 Push Button (SW3)The PB1 push button SW3 is a general-purpose input push button The switch with a connected debounce circuit eliminates the need to re-create it in the FPGA The push button connects to pin C11 of the FPGA

Table 2-14 JP5 Settings

Reference Designator FPGA Pin Number

JP52 Y3

JP54 Y2

JP56 U10

JP58 AB11

Blackfin FPGA EZ-Extender Manual 2-15

Push Buttons and LEDs

PB2 Push Button (SW4) The PB2 push button SW4 is a general-purpose input push button The switch does not have a connected debounce circuit you may need to cre-ate it in the FPGA if required by a specific application The push button connects to pin H5 of the FPGA

Figure 2-4 Push Button and LED Locations

2-16 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Hardware Reference

Status LEDs (LED1ndash8) Eight status LEDs LED1ndash8 connect to the FPGA and act as status flags in any application that requires it Table 2-15 shows the LEDFPGA connections

Power LED (LED9) The power LED LED9 connects to the 25V power supply and when lit signifies that the FPGA EZ-Extender is powered properly

Done LED (LED10) The done LED LED10 connects to the done pin of the FPGA At power-up the FPGA is blank and needs to be programmed When lit the LED indicates that the FPGA is programmed successfully

Table 2-15 Status LED (LED1ndash8) Settings

Reference Designator FPGA Pin Number

LED1 U11

LED2 W11

LED3 AB10

LED4 Y10

LED5 AB9

LED6 W9

LED7 AB8

LED8 V10

Blackfin FPGA EZ-Extender Manual 2-17

Connectors

ConnectorsBefore using the Blackfin FPGA EZ-Extender follow the steps in ldquoFPGA EZ-Extender Setuprdquo on page 1-1

This section describes the connector functionality and provides informa-tion about the mating connectors The connector locations are shown in Figure 2-5

Figure 2-5 Connector Locations

2-18 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Hardware Reference

Expansion Interface (P1ndash3 and J1ndash3) Connectors P1ndash3 of the expansion interface are used to plug in the EZ-Extender to the ADSP-BF533 ADSP-BF537 or ADSP-BF561 EZ-KIT Lite

Connectors J1ndash3 of the expansion interface are used to plug in another extender board such as the Blackfin USB-LAN EZ-Extender Your own custom board can be plugged into J1ndash3 as well

Plugging in another EZ-Extender or a customer board to the expansion interface can de-grade the overall system performance The extra overall load can cause the user to add wait states or slow down the system bus to get all of the boards to work properly

For the J1ndash3 and P1ndash3 connector availability and pricing contact Samtec

IDC Connectors (P8 P14 P16 and P17) The P8 P14 P16 and P17 connectors are standard 01rdquo IDC headers The connectors are in a 13 x 2 configuration and designed for signal probing bread boarding and other signal accesses

Part Description Manufacturer Part Number

90-position 005rdquo spacing SMT(J1 J2 J3)

Samtec SFC-145-T2-F-D-A

90-position 005rdquo spacing (P1 P2 P3)

Samtec TFC-145-32-F-D

Part Description Manufacturer Part Number

IDC13x2 01rdquo header Berg 54102-T08-13

Mating Connector

IDC 13x2 01rdquo plug Samtec SSW-113-01-T-D

Blackfin FPGA EZ-Extender Manual 2-19

Connectors

IDC Connectors (P5 and P7) The P5 and P7 connectors are standard 01rdquo IDC headers The connectors are in a 14 x 2 configuration and designed for signal probing bread boarding and other signal accesses

High-Speed Connector (P4) The high-speed connector P4 facilitates development of applications where use of the standard IDC connectors is complicated due to signal integrity issues

For the P4 connector and cable assembly availability and pricing contact Samtec

Part Description Manufacturer Part Number

IDC14x2 01rdquo header FCI 68737-428HLF

IDC14x2 01rdquo header Sullins GEC14DAAN

Mating Connector

IDC 14x2 01rdquo plug Samtec SSW-114-01-T-D

Part Description Manufacturer Part Number

QTS 25x2 high-speed connector Samtec QTS-025-01-F-D-A

Mating Connector

QSS 25x2 high-speed connector Samtec QSS-025-01-F-D-A

2-20 Blackfin FPGA EZ-Extender Manual

A BILL OF MATERIALS

The bill of materials corresponds to the board schematics on page B-1

Please check the latest schematics on the Analog Devices website httpwwwanalogcomProcessorsProcessorsDevelopmentToolstec

hnicalLibrarymanualsDevToolsIndexhtmlEvalua-

tion20Kit20Manuals

Blackfin FPGA EZ-Extender Manual A-1

Power

25V Header (P42)

When using an external power supply do not plug in the power supply shipped with the FPGA EZ-Extender This can seriously damage the board As an extra measure of precaution remove all jumpers from P12

12V Header (P43)

When using an external power supply do not plug in the power supply shipped with the FPGA EZ-Extender This can seriously damage the board As an extra measure of precaution remove all jumpers from P12

Power Source P42 Setting

FPGA EZ-Extender Power Supply1

1 Default setting

No Jumper

External power supply Connect P421 to external 25VConnect P422 to external GND

Power Source P43 Setting

FPGA EZ-Extender power supply1

1 Default setting

No Jumper

External power supply Connect P421 to external 25VConnect P422 to external GND

2-10 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Hardware Reference

JumpersBefore using the Blackfin FPGA EZ-Extender follow the steps in ldquoFPGA EZ-Extender Setuprdquo on page 1-1

Figure 2-3 shows the locations of all jumper headers A two-pin jumper can be placed on the respective jumper header for different functionality The following sections describe all possible jumper settings and associated functionality

Figure 2-3 Jumper Locations

Blackfin FPGA EZ-Extender Manual 2-11

Jumpers

Serial ROM Boot Jumper (JP1)By default the serial ROM boot jumper JP1 is unpopulated When unpopulated the FPGA EZ-Extender programs via the Blackfin processor or the Xilinx JTAG header

When JP1 is left populated the jumper connects the serial ROM chip enable pin to the done bit of the FPGA At power-up the done bit is driven low by the FPGA causing the FPGA to enable the serial ROM as a programming source After the FPGA is programmed the done bit is driven high by the FPGA causing the FPGA to drive high the chip enable pin of the serial ROM

Both JP1 and JP4 must be set up for correct FPGA programming ldquoBoot Jumper (JP4)rdquo on page 2-14 summarizes the JP4 settings Table 2-10 sum-marizes the JP1 settings See Table 2-4 on page 2-5 and Table 2-6 on page 2-6 for more information on JP1

Config Done Jumper (JP2) The configuration done jumper JP2 connects the done bit of the FPGA to the Blackfin processorrsquos PF3 flag pin of the ADSP-BF533 and ADSP-BF561 EZ-KIT Lites or PF14 flag pin of the ADSP-BF537 EZ-KIT

Table 2-10 JP1 Settings

Boot Source JP1 Setting

ADSP-BF533 ADSP-BF537 or ADSP-BF561 processor via VisualDSP++1

1 Default setting

Unpopulated

JTAG header Unpopulated

Serial ROM Populated

2-12 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Hardware Reference

Lite By default the jumper is populated and acts as a monitor for the done bit by the Blackfin processor (the bit indicates that the FPGA pro-gramming is complete)

Table 2-11 summarizes the jumper settings

Config Program Jumper (JP3) The configuration program jumper JP3 connects the program bit of the FPGA to the Blackfin processorrsquos flag pin By default JP3 is populated The jumper assures that the program bit is asserted by the Blackfin proces-sor to initiate the FPGA programming through VisualDSP++ software

Table 2-12 summarizes the jumper settings

Table 2-11 JP2 Settings

Functionality JP2 Setting

Done bit connected to Blackfin processorrsquos PF3 flag pin1

1 Default setting

Populated

Done bit disconnected from Blackfin processorrsquos PF3 flag pin

Unpopulated

Table 2-12 JP3 Settings

Functionality JP3 Setting

Program bit connected to the Blackfin processorrsquos flag pin1

1 Default setting

Populated

Program bit disconnected from the Blackfin proces-sorrsquos flag pin

Unpopulated

Blackfin FPGA EZ-Extender Manual 2-13

Jumpers

Boot Jumper (JP4) The boot jumper JP4 configures the FPGA mode pins (M[20]) Based on the jumper settings the FPGA is set to be programmed by the JTAG header serial ROM or Blackfin processor

Table 2-13 summarizes the jumper settings See Table 2-3 on page 2-5 for the JTAG header boot settings Table 2-5 on page 2-6 for the serial ROM boot settings and Table 2-7 on page 2-7 for the Blackfin processor boot settings

FPGA Input Jumpers (JP5) The FPGA input jumpers JP52ndash58 drive select FPGA nets to a logic 0 and can be used for any user logic that requires a steady state input You can set internal pull-ups on these nets in the FPGA and when a low is required populate the respective jumper

Table 2-14 summarizes the jumper settings

Table 2-13 JP4 Settings

Boot Source JP41 and JP42M0

JP43 and JP44M1

JP45 and JP46M2

ADSP-BF533ADSP-BF537 orADSP-BF561 processor1

1 Default setting

Unpopulated Unpopulated Unpopulated

JTAG header Unpopulated Populated Unpopulated

Serial ROM Populated Populated Populated

2-14 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Hardware Reference

Push Buttons and LEDsBefore using the Blackfin FPGA EZ-Extender follow the steps in ldquoFPGA EZ-Extender Setuprdquo on page 1-1

Figure 2-4 shows the locations of all push buttons and LEDs The follow-ing sections describe the associated functionality of all the push buttons and LEDs

Program Push Button (SW1)The program push button SW1 erases the contents of the FPGA The push button can be used as a hard resetmdashthe FPGA must be completely re-programmed once SW1 is de-pressed See ldquoProgramming the FPGArdquo on page 2-3 for more information

PB1 Push Button (SW3)The PB1 push button SW3 is a general-purpose input push button The switch with a connected debounce circuit eliminates the need to re-create it in the FPGA The push button connects to pin C11 of the FPGA

Table 2-14 JP5 Settings

Reference Designator FPGA Pin Number

JP52 Y3

JP54 Y2

JP56 U10

JP58 AB11

Blackfin FPGA EZ-Extender Manual 2-15

Push Buttons and LEDs

PB2 Push Button (SW4) The PB2 push button SW4 is a general-purpose input push button The switch does not have a connected debounce circuit you may need to cre-ate it in the FPGA if required by a specific application The push button connects to pin H5 of the FPGA

Figure 2-4 Push Button and LED Locations

2-16 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Hardware Reference

Status LEDs (LED1ndash8) Eight status LEDs LED1ndash8 connect to the FPGA and act as status flags in any application that requires it Table 2-15 shows the LEDFPGA connections

Power LED (LED9) The power LED LED9 connects to the 25V power supply and when lit signifies that the FPGA EZ-Extender is powered properly

Done LED (LED10) The done LED LED10 connects to the done pin of the FPGA At power-up the FPGA is blank and needs to be programmed When lit the LED indicates that the FPGA is programmed successfully

Table 2-15 Status LED (LED1ndash8) Settings

Reference Designator FPGA Pin Number

LED1 U11

LED2 W11

LED3 AB10

LED4 Y10

LED5 AB9

LED6 W9

LED7 AB8

LED8 V10

Blackfin FPGA EZ-Extender Manual 2-17

Connectors

ConnectorsBefore using the Blackfin FPGA EZ-Extender follow the steps in ldquoFPGA EZ-Extender Setuprdquo on page 1-1

This section describes the connector functionality and provides informa-tion about the mating connectors The connector locations are shown in Figure 2-5

Figure 2-5 Connector Locations

2-18 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Hardware Reference

Expansion Interface (P1ndash3 and J1ndash3) Connectors P1ndash3 of the expansion interface are used to plug in the EZ-Extender to the ADSP-BF533 ADSP-BF537 or ADSP-BF561 EZ-KIT Lite

Connectors J1ndash3 of the expansion interface are used to plug in another extender board such as the Blackfin USB-LAN EZ-Extender Your own custom board can be plugged into J1ndash3 as well

Plugging in another EZ-Extender or a customer board to the expansion interface can de-grade the overall system performance The extra overall load can cause the user to add wait states or slow down the system bus to get all of the boards to work properly

For the J1ndash3 and P1ndash3 connector availability and pricing contact Samtec

IDC Connectors (P8 P14 P16 and P17) The P8 P14 P16 and P17 connectors are standard 01rdquo IDC headers The connectors are in a 13 x 2 configuration and designed for signal probing bread boarding and other signal accesses

Part Description Manufacturer Part Number

90-position 005rdquo spacing SMT(J1 J2 J3)

Samtec SFC-145-T2-F-D-A

90-position 005rdquo spacing (P1 P2 P3)

Samtec TFC-145-32-F-D

Part Description Manufacturer Part Number

IDC13x2 01rdquo header Berg 54102-T08-13

Mating Connector

IDC 13x2 01rdquo plug Samtec SSW-113-01-T-D

Blackfin FPGA EZ-Extender Manual 2-19

Connectors

IDC Connectors (P5 and P7) The P5 and P7 connectors are standard 01rdquo IDC headers The connectors are in a 14 x 2 configuration and designed for signal probing bread boarding and other signal accesses

High-Speed Connector (P4) The high-speed connector P4 facilitates development of applications where use of the standard IDC connectors is complicated due to signal integrity issues

For the P4 connector and cable assembly availability and pricing contact Samtec

Part Description Manufacturer Part Number

IDC14x2 01rdquo header FCI 68737-428HLF

IDC14x2 01rdquo header Sullins GEC14DAAN

Mating Connector

IDC 14x2 01rdquo plug Samtec SSW-114-01-T-D

Part Description Manufacturer Part Number

QTS 25x2 high-speed connector Samtec QTS-025-01-F-D-A

Mating Connector

QSS 25x2 high-speed connector Samtec QSS-025-01-F-D-A

2-20 Blackfin FPGA EZ-Extender Manual

A BILL OF MATERIALS

The bill of materials corresponds to the board schematics on page B-1

Please check the latest schematics on the Analog Devices website httpwwwanalogcomProcessorsProcessorsDevelopmentToolstec

hnicalLibrarymanualsDevToolsIndexhtmlEvalua-

tion20Kit20Manuals

Blackfin FPGA EZ-Extender Manual A-1

FPGA EZ-Extender Hardware Reference

JumpersBefore using the Blackfin FPGA EZ-Extender follow the steps in ldquoFPGA EZ-Extender Setuprdquo on page 1-1

Figure 2-3 shows the locations of all jumper headers A two-pin jumper can be placed on the respective jumper header for different functionality The following sections describe all possible jumper settings and associated functionality

Figure 2-3 Jumper Locations

Blackfin FPGA EZ-Extender Manual 2-11

Jumpers

Serial ROM Boot Jumper (JP1)By default the serial ROM boot jumper JP1 is unpopulated When unpopulated the FPGA EZ-Extender programs via the Blackfin processor or the Xilinx JTAG header

When JP1 is left populated the jumper connects the serial ROM chip enable pin to the done bit of the FPGA At power-up the done bit is driven low by the FPGA causing the FPGA to enable the serial ROM as a programming source After the FPGA is programmed the done bit is driven high by the FPGA causing the FPGA to drive high the chip enable pin of the serial ROM

Both JP1 and JP4 must be set up for correct FPGA programming ldquoBoot Jumper (JP4)rdquo on page 2-14 summarizes the JP4 settings Table 2-10 sum-marizes the JP1 settings See Table 2-4 on page 2-5 and Table 2-6 on page 2-6 for more information on JP1

Config Done Jumper (JP2) The configuration done jumper JP2 connects the done bit of the FPGA to the Blackfin processorrsquos PF3 flag pin of the ADSP-BF533 and ADSP-BF561 EZ-KIT Lites or PF14 flag pin of the ADSP-BF537 EZ-KIT

Table 2-10 JP1 Settings

Boot Source JP1 Setting

ADSP-BF533 ADSP-BF537 or ADSP-BF561 processor via VisualDSP++1

1 Default setting

Unpopulated

JTAG header Unpopulated

Serial ROM Populated

2-12 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Hardware Reference

Lite By default the jumper is populated and acts as a monitor for the done bit by the Blackfin processor (the bit indicates that the FPGA pro-gramming is complete)

Table 2-11 summarizes the jumper settings

Config Program Jumper (JP3) The configuration program jumper JP3 connects the program bit of the FPGA to the Blackfin processorrsquos flag pin By default JP3 is populated The jumper assures that the program bit is asserted by the Blackfin proces-sor to initiate the FPGA programming through VisualDSP++ software

Table 2-12 summarizes the jumper settings

Table 2-11 JP2 Settings

Functionality JP2 Setting

Done bit connected to Blackfin processorrsquos PF3 flag pin1

1 Default setting

Populated

Done bit disconnected from Blackfin processorrsquos PF3 flag pin

Unpopulated

Table 2-12 JP3 Settings

Functionality JP3 Setting

Program bit connected to the Blackfin processorrsquos flag pin1

1 Default setting

Populated

Program bit disconnected from the Blackfin proces-sorrsquos flag pin

Unpopulated

Blackfin FPGA EZ-Extender Manual 2-13

Jumpers

Boot Jumper (JP4) The boot jumper JP4 configures the FPGA mode pins (M[20]) Based on the jumper settings the FPGA is set to be programmed by the JTAG header serial ROM or Blackfin processor

Table 2-13 summarizes the jumper settings See Table 2-3 on page 2-5 for the JTAG header boot settings Table 2-5 on page 2-6 for the serial ROM boot settings and Table 2-7 on page 2-7 for the Blackfin processor boot settings

FPGA Input Jumpers (JP5) The FPGA input jumpers JP52ndash58 drive select FPGA nets to a logic 0 and can be used for any user logic that requires a steady state input You can set internal pull-ups on these nets in the FPGA and when a low is required populate the respective jumper

Table 2-14 summarizes the jumper settings

Table 2-13 JP4 Settings

Boot Source JP41 and JP42M0

JP43 and JP44M1

JP45 and JP46M2

ADSP-BF533ADSP-BF537 orADSP-BF561 processor1

1 Default setting

Unpopulated Unpopulated Unpopulated

JTAG header Unpopulated Populated Unpopulated

Serial ROM Populated Populated Populated

2-14 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Hardware Reference

Push Buttons and LEDsBefore using the Blackfin FPGA EZ-Extender follow the steps in ldquoFPGA EZ-Extender Setuprdquo on page 1-1

Figure 2-4 shows the locations of all push buttons and LEDs The follow-ing sections describe the associated functionality of all the push buttons and LEDs

Program Push Button (SW1)The program push button SW1 erases the contents of the FPGA The push button can be used as a hard resetmdashthe FPGA must be completely re-programmed once SW1 is de-pressed See ldquoProgramming the FPGArdquo on page 2-3 for more information

PB1 Push Button (SW3)The PB1 push button SW3 is a general-purpose input push button The switch with a connected debounce circuit eliminates the need to re-create it in the FPGA The push button connects to pin C11 of the FPGA

Table 2-14 JP5 Settings

Reference Designator FPGA Pin Number

JP52 Y3

JP54 Y2

JP56 U10

JP58 AB11

Blackfin FPGA EZ-Extender Manual 2-15

Push Buttons and LEDs

PB2 Push Button (SW4) The PB2 push button SW4 is a general-purpose input push button The switch does not have a connected debounce circuit you may need to cre-ate it in the FPGA if required by a specific application The push button connects to pin H5 of the FPGA

Figure 2-4 Push Button and LED Locations

2-16 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Hardware Reference

Status LEDs (LED1ndash8) Eight status LEDs LED1ndash8 connect to the FPGA and act as status flags in any application that requires it Table 2-15 shows the LEDFPGA connections

Power LED (LED9) The power LED LED9 connects to the 25V power supply and when lit signifies that the FPGA EZ-Extender is powered properly

Done LED (LED10) The done LED LED10 connects to the done pin of the FPGA At power-up the FPGA is blank and needs to be programmed When lit the LED indicates that the FPGA is programmed successfully

Table 2-15 Status LED (LED1ndash8) Settings

Reference Designator FPGA Pin Number

LED1 U11

LED2 W11

LED3 AB10

LED4 Y10

LED5 AB9

LED6 W9

LED7 AB8

LED8 V10

Blackfin FPGA EZ-Extender Manual 2-17

Connectors

ConnectorsBefore using the Blackfin FPGA EZ-Extender follow the steps in ldquoFPGA EZ-Extender Setuprdquo on page 1-1

This section describes the connector functionality and provides informa-tion about the mating connectors The connector locations are shown in Figure 2-5

Figure 2-5 Connector Locations

2-18 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Hardware Reference

Expansion Interface (P1ndash3 and J1ndash3) Connectors P1ndash3 of the expansion interface are used to plug in the EZ-Extender to the ADSP-BF533 ADSP-BF537 or ADSP-BF561 EZ-KIT Lite

Connectors J1ndash3 of the expansion interface are used to plug in another extender board such as the Blackfin USB-LAN EZ-Extender Your own custom board can be plugged into J1ndash3 as well

Plugging in another EZ-Extender or a customer board to the expansion interface can de-grade the overall system performance The extra overall load can cause the user to add wait states or slow down the system bus to get all of the boards to work properly

For the J1ndash3 and P1ndash3 connector availability and pricing contact Samtec

IDC Connectors (P8 P14 P16 and P17) The P8 P14 P16 and P17 connectors are standard 01rdquo IDC headers The connectors are in a 13 x 2 configuration and designed for signal probing bread boarding and other signal accesses

Part Description Manufacturer Part Number

90-position 005rdquo spacing SMT(J1 J2 J3)

Samtec SFC-145-T2-F-D-A

90-position 005rdquo spacing (P1 P2 P3)

Samtec TFC-145-32-F-D

Part Description Manufacturer Part Number

IDC13x2 01rdquo header Berg 54102-T08-13

Mating Connector

IDC 13x2 01rdquo plug Samtec SSW-113-01-T-D

Blackfin FPGA EZ-Extender Manual 2-19

Connectors

IDC Connectors (P5 and P7) The P5 and P7 connectors are standard 01rdquo IDC headers The connectors are in a 14 x 2 configuration and designed for signal probing bread boarding and other signal accesses

High-Speed Connector (P4) The high-speed connector P4 facilitates development of applications where use of the standard IDC connectors is complicated due to signal integrity issues

For the P4 connector and cable assembly availability and pricing contact Samtec

Part Description Manufacturer Part Number

IDC14x2 01rdquo header FCI 68737-428HLF

IDC14x2 01rdquo header Sullins GEC14DAAN

Mating Connector

IDC 14x2 01rdquo plug Samtec SSW-114-01-T-D

Part Description Manufacturer Part Number

QTS 25x2 high-speed connector Samtec QTS-025-01-F-D-A

Mating Connector

QSS 25x2 high-speed connector Samtec QSS-025-01-F-D-A

2-20 Blackfin FPGA EZ-Extender Manual

A BILL OF MATERIALS

The bill of materials corresponds to the board schematics on page B-1

Please check the latest schematics on the Analog Devices website httpwwwanalogcomProcessorsProcessorsDevelopmentToolstec

hnicalLibrarymanualsDevToolsIndexhtmlEvalua-

tion20Kit20Manuals

Blackfin FPGA EZ-Extender Manual A-1

Jumpers

Serial ROM Boot Jumper (JP1)By default the serial ROM boot jumper JP1 is unpopulated When unpopulated the FPGA EZ-Extender programs via the Blackfin processor or the Xilinx JTAG header

When JP1 is left populated the jumper connects the serial ROM chip enable pin to the done bit of the FPGA At power-up the done bit is driven low by the FPGA causing the FPGA to enable the serial ROM as a programming source After the FPGA is programmed the done bit is driven high by the FPGA causing the FPGA to drive high the chip enable pin of the serial ROM

Both JP1 and JP4 must be set up for correct FPGA programming ldquoBoot Jumper (JP4)rdquo on page 2-14 summarizes the JP4 settings Table 2-10 sum-marizes the JP1 settings See Table 2-4 on page 2-5 and Table 2-6 on page 2-6 for more information on JP1

Config Done Jumper (JP2) The configuration done jumper JP2 connects the done bit of the FPGA to the Blackfin processorrsquos PF3 flag pin of the ADSP-BF533 and ADSP-BF561 EZ-KIT Lites or PF14 flag pin of the ADSP-BF537 EZ-KIT

Table 2-10 JP1 Settings

Boot Source JP1 Setting

ADSP-BF533 ADSP-BF537 or ADSP-BF561 processor via VisualDSP++1

1 Default setting

Unpopulated

JTAG header Unpopulated

Serial ROM Populated

2-12 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Hardware Reference

Lite By default the jumper is populated and acts as a monitor for the done bit by the Blackfin processor (the bit indicates that the FPGA pro-gramming is complete)

Table 2-11 summarizes the jumper settings

Config Program Jumper (JP3) The configuration program jumper JP3 connects the program bit of the FPGA to the Blackfin processorrsquos flag pin By default JP3 is populated The jumper assures that the program bit is asserted by the Blackfin proces-sor to initiate the FPGA programming through VisualDSP++ software

Table 2-12 summarizes the jumper settings

Table 2-11 JP2 Settings

Functionality JP2 Setting

Done bit connected to Blackfin processorrsquos PF3 flag pin1

1 Default setting

Populated

Done bit disconnected from Blackfin processorrsquos PF3 flag pin

Unpopulated

Table 2-12 JP3 Settings

Functionality JP3 Setting

Program bit connected to the Blackfin processorrsquos flag pin1

1 Default setting

Populated

Program bit disconnected from the Blackfin proces-sorrsquos flag pin

Unpopulated

Blackfin FPGA EZ-Extender Manual 2-13

Jumpers

Boot Jumper (JP4) The boot jumper JP4 configures the FPGA mode pins (M[20]) Based on the jumper settings the FPGA is set to be programmed by the JTAG header serial ROM or Blackfin processor

Table 2-13 summarizes the jumper settings See Table 2-3 on page 2-5 for the JTAG header boot settings Table 2-5 on page 2-6 for the serial ROM boot settings and Table 2-7 on page 2-7 for the Blackfin processor boot settings

FPGA Input Jumpers (JP5) The FPGA input jumpers JP52ndash58 drive select FPGA nets to a logic 0 and can be used for any user logic that requires a steady state input You can set internal pull-ups on these nets in the FPGA and when a low is required populate the respective jumper

Table 2-14 summarizes the jumper settings

Table 2-13 JP4 Settings

Boot Source JP41 and JP42M0

JP43 and JP44M1

JP45 and JP46M2

ADSP-BF533ADSP-BF537 orADSP-BF561 processor1

1 Default setting

Unpopulated Unpopulated Unpopulated

JTAG header Unpopulated Populated Unpopulated

Serial ROM Populated Populated Populated

2-14 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Hardware Reference

Push Buttons and LEDsBefore using the Blackfin FPGA EZ-Extender follow the steps in ldquoFPGA EZ-Extender Setuprdquo on page 1-1

Figure 2-4 shows the locations of all push buttons and LEDs The follow-ing sections describe the associated functionality of all the push buttons and LEDs

Program Push Button (SW1)The program push button SW1 erases the contents of the FPGA The push button can be used as a hard resetmdashthe FPGA must be completely re-programmed once SW1 is de-pressed See ldquoProgramming the FPGArdquo on page 2-3 for more information

PB1 Push Button (SW3)The PB1 push button SW3 is a general-purpose input push button The switch with a connected debounce circuit eliminates the need to re-create it in the FPGA The push button connects to pin C11 of the FPGA

Table 2-14 JP5 Settings

Reference Designator FPGA Pin Number

JP52 Y3

JP54 Y2

JP56 U10

JP58 AB11

Blackfin FPGA EZ-Extender Manual 2-15

Push Buttons and LEDs

PB2 Push Button (SW4) The PB2 push button SW4 is a general-purpose input push button The switch does not have a connected debounce circuit you may need to cre-ate it in the FPGA if required by a specific application The push button connects to pin H5 of the FPGA

Figure 2-4 Push Button and LED Locations

2-16 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Hardware Reference

Status LEDs (LED1ndash8) Eight status LEDs LED1ndash8 connect to the FPGA and act as status flags in any application that requires it Table 2-15 shows the LEDFPGA connections

Power LED (LED9) The power LED LED9 connects to the 25V power supply and when lit signifies that the FPGA EZ-Extender is powered properly

Done LED (LED10) The done LED LED10 connects to the done pin of the FPGA At power-up the FPGA is blank and needs to be programmed When lit the LED indicates that the FPGA is programmed successfully

Table 2-15 Status LED (LED1ndash8) Settings

Reference Designator FPGA Pin Number

LED1 U11

LED2 W11

LED3 AB10

LED4 Y10

LED5 AB9

LED6 W9

LED7 AB8

LED8 V10

Blackfin FPGA EZ-Extender Manual 2-17

Connectors

ConnectorsBefore using the Blackfin FPGA EZ-Extender follow the steps in ldquoFPGA EZ-Extender Setuprdquo on page 1-1

This section describes the connector functionality and provides informa-tion about the mating connectors The connector locations are shown in Figure 2-5

Figure 2-5 Connector Locations

2-18 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Hardware Reference

Expansion Interface (P1ndash3 and J1ndash3) Connectors P1ndash3 of the expansion interface are used to plug in the EZ-Extender to the ADSP-BF533 ADSP-BF537 or ADSP-BF561 EZ-KIT Lite

Connectors J1ndash3 of the expansion interface are used to plug in another extender board such as the Blackfin USB-LAN EZ-Extender Your own custom board can be plugged into J1ndash3 as well

Plugging in another EZ-Extender or a customer board to the expansion interface can de-grade the overall system performance The extra overall load can cause the user to add wait states or slow down the system bus to get all of the boards to work properly

For the J1ndash3 and P1ndash3 connector availability and pricing contact Samtec

IDC Connectors (P8 P14 P16 and P17) The P8 P14 P16 and P17 connectors are standard 01rdquo IDC headers The connectors are in a 13 x 2 configuration and designed for signal probing bread boarding and other signal accesses

Part Description Manufacturer Part Number

90-position 005rdquo spacing SMT(J1 J2 J3)

Samtec SFC-145-T2-F-D-A

90-position 005rdquo spacing (P1 P2 P3)

Samtec TFC-145-32-F-D

Part Description Manufacturer Part Number

IDC13x2 01rdquo header Berg 54102-T08-13

Mating Connector

IDC 13x2 01rdquo plug Samtec SSW-113-01-T-D

Blackfin FPGA EZ-Extender Manual 2-19

Connectors

IDC Connectors (P5 and P7) The P5 and P7 connectors are standard 01rdquo IDC headers The connectors are in a 14 x 2 configuration and designed for signal probing bread boarding and other signal accesses

High-Speed Connector (P4) The high-speed connector P4 facilitates development of applications where use of the standard IDC connectors is complicated due to signal integrity issues

For the P4 connector and cable assembly availability and pricing contact Samtec

Part Description Manufacturer Part Number

IDC14x2 01rdquo header FCI 68737-428HLF

IDC14x2 01rdquo header Sullins GEC14DAAN

Mating Connector

IDC 14x2 01rdquo plug Samtec SSW-114-01-T-D

Part Description Manufacturer Part Number

QTS 25x2 high-speed connector Samtec QTS-025-01-F-D-A

Mating Connector

QSS 25x2 high-speed connector Samtec QSS-025-01-F-D-A

2-20 Blackfin FPGA EZ-Extender Manual

A BILL OF MATERIALS

The bill of materials corresponds to the board schematics on page B-1

Please check the latest schematics on the Analog Devices website httpwwwanalogcomProcessorsProcessorsDevelopmentToolstec

hnicalLibrarymanualsDevToolsIndexhtmlEvalua-

tion20Kit20Manuals

Blackfin FPGA EZ-Extender Manual A-1

FPGA EZ-Extender Hardware Reference

Lite By default the jumper is populated and acts as a monitor for the done bit by the Blackfin processor (the bit indicates that the FPGA pro-gramming is complete)

Table 2-11 summarizes the jumper settings

Config Program Jumper (JP3) The configuration program jumper JP3 connects the program bit of the FPGA to the Blackfin processorrsquos flag pin By default JP3 is populated The jumper assures that the program bit is asserted by the Blackfin proces-sor to initiate the FPGA programming through VisualDSP++ software

Table 2-12 summarizes the jumper settings

Table 2-11 JP2 Settings

Functionality JP2 Setting

Done bit connected to Blackfin processorrsquos PF3 flag pin1

1 Default setting

Populated

Done bit disconnected from Blackfin processorrsquos PF3 flag pin

Unpopulated

Table 2-12 JP3 Settings

Functionality JP3 Setting

Program bit connected to the Blackfin processorrsquos flag pin1

1 Default setting

Populated

Program bit disconnected from the Blackfin proces-sorrsquos flag pin

Unpopulated

Blackfin FPGA EZ-Extender Manual 2-13

Jumpers

Boot Jumper (JP4) The boot jumper JP4 configures the FPGA mode pins (M[20]) Based on the jumper settings the FPGA is set to be programmed by the JTAG header serial ROM or Blackfin processor

Table 2-13 summarizes the jumper settings See Table 2-3 on page 2-5 for the JTAG header boot settings Table 2-5 on page 2-6 for the serial ROM boot settings and Table 2-7 on page 2-7 for the Blackfin processor boot settings

FPGA Input Jumpers (JP5) The FPGA input jumpers JP52ndash58 drive select FPGA nets to a logic 0 and can be used for any user logic that requires a steady state input You can set internal pull-ups on these nets in the FPGA and when a low is required populate the respective jumper

Table 2-14 summarizes the jumper settings

Table 2-13 JP4 Settings

Boot Source JP41 and JP42M0

JP43 and JP44M1

JP45 and JP46M2

ADSP-BF533ADSP-BF537 orADSP-BF561 processor1

1 Default setting

Unpopulated Unpopulated Unpopulated

JTAG header Unpopulated Populated Unpopulated

Serial ROM Populated Populated Populated

2-14 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Hardware Reference

Push Buttons and LEDsBefore using the Blackfin FPGA EZ-Extender follow the steps in ldquoFPGA EZ-Extender Setuprdquo on page 1-1

Figure 2-4 shows the locations of all push buttons and LEDs The follow-ing sections describe the associated functionality of all the push buttons and LEDs

Program Push Button (SW1)The program push button SW1 erases the contents of the FPGA The push button can be used as a hard resetmdashthe FPGA must be completely re-programmed once SW1 is de-pressed See ldquoProgramming the FPGArdquo on page 2-3 for more information

PB1 Push Button (SW3)The PB1 push button SW3 is a general-purpose input push button The switch with a connected debounce circuit eliminates the need to re-create it in the FPGA The push button connects to pin C11 of the FPGA

Table 2-14 JP5 Settings

Reference Designator FPGA Pin Number

JP52 Y3

JP54 Y2

JP56 U10

JP58 AB11

Blackfin FPGA EZ-Extender Manual 2-15

Push Buttons and LEDs

PB2 Push Button (SW4) The PB2 push button SW4 is a general-purpose input push button The switch does not have a connected debounce circuit you may need to cre-ate it in the FPGA if required by a specific application The push button connects to pin H5 of the FPGA

Figure 2-4 Push Button and LED Locations

2-16 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Hardware Reference

Status LEDs (LED1ndash8) Eight status LEDs LED1ndash8 connect to the FPGA and act as status flags in any application that requires it Table 2-15 shows the LEDFPGA connections

Power LED (LED9) The power LED LED9 connects to the 25V power supply and when lit signifies that the FPGA EZ-Extender is powered properly

Done LED (LED10) The done LED LED10 connects to the done pin of the FPGA At power-up the FPGA is blank and needs to be programmed When lit the LED indicates that the FPGA is programmed successfully

Table 2-15 Status LED (LED1ndash8) Settings

Reference Designator FPGA Pin Number

LED1 U11

LED2 W11

LED3 AB10

LED4 Y10

LED5 AB9

LED6 W9

LED7 AB8

LED8 V10

Blackfin FPGA EZ-Extender Manual 2-17

Connectors

ConnectorsBefore using the Blackfin FPGA EZ-Extender follow the steps in ldquoFPGA EZ-Extender Setuprdquo on page 1-1

This section describes the connector functionality and provides informa-tion about the mating connectors The connector locations are shown in Figure 2-5

Figure 2-5 Connector Locations

2-18 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Hardware Reference

Expansion Interface (P1ndash3 and J1ndash3) Connectors P1ndash3 of the expansion interface are used to plug in the EZ-Extender to the ADSP-BF533 ADSP-BF537 or ADSP-BF561 EZ-KIT Lite

Connectors J1ndash3 of the expansion interface are used to plug in another extender board such as the Blackfin USB-LAN EZ-Extender Your own custom board can be plugged into J1ndash3 as well

Plugging in another EZ-Extender or a customer board to the expansion interface can de-grade the overall system performance The extra overall load can cause the user to add wait states or slow down the system bus to get all of the boards to work properly

For the J1ndash3 and P1ndash3 connector availability and pricing contact Samtec

IDC Connectors (P8 P14 P16 and P17) The P8 P14 P16 and P17 connectors are standard 01rdquo IDC headers The connectors are in a 13 x 2 configuration and designed for signal probing bread boarding and other signal accesses

Part Description Manufacturer Part Number

90-position 005rdquo spacing SMT(J1 J2 J3)

Samtec SFC-145-T2-F-D-A

90-position 005rdquo spacing (P1 P2 P3)

Samtec TFC-145-32-F-D

Part Description Manufacturer Part Number

IDC13x2 01rdquo header Berg 54102-T08-13

Mating Connector

IDC 13x2 01rdquo plug Samtec SSW-113-01-T-D

Blackfin FPGA EZ-Extender Manual 2-19

Connectors

IDC Connectors (P5 and P7) The P5 and P7 connectors are standard 01rdquo IDC headers The connectors are in a 14 x 2 configuration and designed for signal probing bread boarding and other signal accesses

High-Speed Connector (P4) The high-speed connector P4 facilitates development of applications where use of the standard IDC connectors is complicated due to signal integrity issues

For the P4 connector and cable assembly availability and pricing contact Samtec

Part Description Manufacturer Part Number

IDC14x2 01rdquo header FCI 68737-428HLF

IDC14x2 01rdquo header Sullins GEC14DAAN

Mating Connector

IDC 14x2 01rdquo plug Samtec SSW-114-01-T-D

Part Description Manufacturer Part Number

QTS 25x2 high-speed connector Samtec QTS-025-01-F-D-A

Mating Connector

QSS 25x2 high-speed connector Samtec QSS-025-01-F-D-A

2-20 Blackfin FPGA EZ-Extender Manual

A BILL OF MATERIALS

The bill of materials corresponds to the board schematics on page B-1

Please check the latest schematics on the Analog Devices website httpwwwanalogcomProcessorsProcessorsDevelopmentToolstec

hnicalLibrarymanualsDevToolsIndexhtmlEvalua-

tion20Kit20Manuals

Blackfin FPGA EZ-Extender Manual A-1

Jumpers

Boot Jumper (JP4) The boot jumper JP4 configures the FPGA mode pins (M[20]) Based on the jumper settings the FPGA is set to be programmed by the JTAG header serial ROM or Blackfin processor

Table 2-13 summarizes the jumper settings See Table 2-3 on page 2-5 for the JTAG header boot settings Table 2-5 on page 2-6 for the serial ROM boot settings and Table 2-7 on page 2-7 for the Blackfin processor boot settings

FPGA Input Jumpers (JP5) The FPGA input jumpers JP52ndash58 drive select FPGA nets to a logic 0 and can be used for any user logic that requires a steady state input You can set internal pull-ups on these nets in the FPGA and when a low is required populate the respective jumper

Table 2-14 summarizes the jumper settings

Table 2-13 JP4 Settings

Boot Source JP41 and JP42M0

JP43 and JP44M1

JP45 and JP46M2

ADSP-BF533ADSP-BF537 orADSP-BF561 processor1

1 Default setting

Unpopulated Unpopulated Unpopulated

JTAG header Unpopulated Populated Unpopulated

Serial ROM Populated Populated Populated

2-14 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Hardware Reference

Push Buttons and LEDsBefore using the Blackfin FPGA EZ-Extender follow the steps in ldquoFPGA EZ-Extender Setuprdquo on page 1-1

Figure 2-4 shows the locations of all push buttons and LEDs The follow-ing sections describe the associated functionality of all the push buttons and LEDs

Program Push Button (SW1)The program push button SW1 erases the contents of the FPGA The push button can be used as a hard resetmdashthe FPGA must be completely re-programmed once SW1 is de-pressed See ldquoProgramming the FPGArdquo on page 2-3 for more information

PB1 Push Button (SW3)The PB1 push button SW3 is a general-purpose input push button The switch with a connected debounce circuit eliminates the need to re-create it in the FPGA The push button connects to pin C11 of the FPGA

Table 2-14 JP5 Settings

Reference Designator FPGA Pin Number

JP52 Y3

JP54 Y2

JP56 U10

JP58 AB11

Blackfin FPGA EZ-Extender Manual 2-15

Push Buttons and LEDs

PB2 Push Button (SW4) The PB2 push button SW4 is a general-purpose input push button The switch does not have a connected debounce circuit you may need to cre-ate it in the FPGA if required by a specific application The push button connects to pin H5 of the FPGA

Figure 2-4 Push Button and LED Locations

2-16 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Hardware Reference

Status LEDs (LED1ndash8) Eight status LEDs LED1ndash8 connect to the FPGA and act as status flags in any application that requires it Table 2-15 shows the LEDFPGA connections

Power LED (LED9) The power LED LED9 connects to the 25V power supply and when lit signifies that the FPGA EZ-Extender is powered properly

Done LED (LED10) The done LED LED10 connects to the done pin of the FPGA At power-up the FPGA is blank and needs to be programmed When lit the LED indicates that the FPGA is programmed successfully

Table 2-15 Status LED (LED1ndash8) Settings

Reference Designator FPGA Pin Number

LED1 U11

LED2 W11

LED3 AB10

LED4 Y10

LED5 AB9

LED6 W9

LED7 AB8

LED8 V10

Blackfin FPGA EZ-Extender Manual 2-17

Connectors

ConnectorsBefore using the Blackfin FPGA EZ-Extender follow the steps in ldquoFPGA EZ-Extender Setuprdquo on page 1-1

This section describes the connector functionality and provides informa-tion about the mating connectors The connector locations are shown in Figure 2-5

Figure 2-5 Connector Locations

2-18 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Hardware Reference

Expansion Interface (P1ndash3 and J1ndash3) Connectors P1ndash3 of the expansion interface are used to plug in the EZ-Extender to the ADSP-BF533 ADSP-BF537 or ADSP-BF561 EZ-KIT Lite

Connectors J1ndash3 of the expansion interface are used to plug in another extender board such as the Blackfin USB-LAN EZ-Extender Your own custom board can be plugged into J1ndash3 as well

Plugging in another EZ-Extender or a customer board to the expansion interface can de-grade the overall system performance The extra overall load can cause the user to add wait states or slow down the system bus to get all of the boards to work properly

For the J1ndash3 and P1ndash3 connector availability and pricing contact Samtec

IDC Connectors (P8 P14 P16 and P17) The P8 P14 P16 and P17 connectors are standard 01rdquo IDC headers The connectors are in a 13 x 2 configuration and designed for signal probing bread boarding and other signal accesses

Part Description Manufacturer Part Number

90-position 005rdquo spacing SMT(J1 J2 J3)

Samtec SFC-145-T2-F-D-A

90-position 005rdquo spacing (P1 P2 P3)

Samtec TFC-145-32-F-D

Part Description Manufacturer Part Number

IDC13x2 01rdquo header Berg 54102-T08-13

Mating Connector

IDC 13x2 01rdquo plug Samtec SSW-113-01-T-D

Blackfin FPGA EZ-Extender Manual 2-19

Connectors

IDC Connectors (P5 and P7) The P5 and P7 connectors are standard 01rdquo IDC headers The connectors are in a 14 x 2 configuration and designed for signal probing bread boarding and other signal accesses

High-Speed Connector (P4) The high-speed connector P4 facilitates development of applications where use of the standard IDC connectors is complicated due to signal integrity issues

For the P4 connector and cable assembly availability and pricing contact Samtec

Part Description Manufacturer Part Number

IDC14x2 01rdquo header FCI 68737-428HLF

IDC14x2 01rdquo header Sullins GEC14DAAN

Mating Connector

IDC 14x2 01rdquo plug Samtec SSW-114-01-T-D

Part Description Manufacturer Part Number

QTS 25x2 high-speed connector Samtec QTS-025-01-F-D-A

Mating Connector

QSS 25x2 high-speed connector Samtec QSS-025-01-F-D-A

2-20 Blackfin FPGA EZ-Extender Manual

A BILL OF MATERIALS

The bill of materials corresponds to the board schematics on page B-1

Please check the latest schematics on the Analog Devices website httpwwwanalogcomProcessorsProcessorsDevelopmentToolstec

hnicalLibrarymanualsDevToolsIndexhtmlEvalua-

tion20Kit20Manuals

Blackfin FPGA EZ-Extender Manual A-1

FPGA EZ-Extender Hardware Reference

Push Buttons and LEDsBefore using the Blackfin FPGA EZ-Extender follow the steps in ldquoFPGA EZ-Extender Setuprdquo on page 1-1

Figure 2-4 shows the locations of all push buttons and LEDs The follow-ing sections describe the associated functionality of all the push buttons and LEDs

Program Push Button (SW1)The program push button SW1 erases the contents of the FPGA The push button can be used as a hard resetmdashthe FPGA must be completely re-programmed once SW1 is de-pressed See ldquoProgramming the FPGArdquo on page 2-3 for more information

PB1 Push Button (SW3)The PB1 push button SW3 is a general-purpose input push button The switch with a connected debounce circuit eliminates the need to re-create it in the FPGA The push button connects to pin C11 of the FPGA

Table 2-14 JP5 Settings

Reference Designator FPGA Pin Number

JP52 Y3

JP54 Y2

JP56 U10

JP58 AB11

Blackfin FPGA EZ-Extender Manual 2-15

Push Buttons and LEDs

PB2 Push Button (SW4) The PB2 push button SW4 is a general-purpose input push button The switch does not have a connected debounce circuit you may need to cre-ate it in the FPGA if required by a specific application The push button connects to pin H5 of the FPGA

Figure 2-4 Push Button and LED Locations

2-16 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Hardware Reference

Status LEDs (LED1ndash8) Eight status LEDs LED1ndash8 connect to the FPGA and act as status flags in any application that requires it Table 2-15 shows the LEDFPGA connections

Power LED (LED9) The power LED LED9 connects to the 25V power supply and when lit signifies that the FPGA EZ-Extender is powered properly

Done LED (LED10) The done LED LED10 connects to the done pin of the FPGA At power-up the FPGA is blank and needs to be programmed When lit the LED indicates that the FPGA is programmed successfully

Table 2-15 Status LED (LED1ndash8) Settings

Reference Designator FPGA Pin Number

LED1 U11

LED2 W11

LED3 AB10

LED4 Y10

LED5 AB9

LED6 W9

LED7 AB8

LED8 V10

Blackfin FPGA EZ-Extender Manual 2-17

Connectors

ConnectorsBefore using the Blackfin FPGA EZ-Extender follow the steps in ldquoFPGA EZ-Extender Setuprdquo on page 1-1

This section describes the connector functionality and provides informa-tion about the mating connectors The connector locations are shown in Figure 2-5

Figure 2-5 Connector Locations

2-18 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Hardware Reference

Expansion Interface (P1ndash3 and J1ndash3) Connectors P1ndash3 of the expansion interface are used to plug in the EZ-Extender to the ADSP-BF533 ADSP-BF537 or ADSP-BF561 EZ-KIT Lite

Connectors J1ndash3 of the expansion interface are used to plug in another extender board such as the Blackfin USB-LAN EZ-Extender Your own custom board can be plugged into J1ndash3 as well

Plugging in another EZ-Extender or a customer board to the expansion interface can de-grade the overall system performance The extra overall load can cause the user to add wait states or slow down the system bus to get all of the boards to work properly

For the J1ndash3 and P1ndash3 connector availability and pricing contact Samtec

IDC Connectors (P8 P14 P16 and P17) The P8 P14 P16 and P17 connectors are standard 01rdquo IDC headers The connectors are in a 13 x 2 configuration and designed for signal probing bread boarding and other signal accesses

Part Description Manufacturer Part Number

90-position 005rdquo spacing SMT(J1 J2 J3)

Samtec SFC-145-T2-F-D-A

90-position 005rdquo spacing (P1 P2 P3)

Samtec TFC-145-32-F-D

Part Description Manufacturer Part Number

IDC13x2 01rdquo header Berg 54102-T08-13

Mating Connector

IDC 13x2 01rdquo plug Samtec SSW-113-01-T-D

Blackfin FPGA EZ-Extender Manual 2-19

Connectors

IDC Connectors (P5 and P7) The P5 and P7 connectors are standard 01rdquo IDC headers The connectors are in a 14 x 2 configuration and designed for signal probing bread boarding and other signal accesses

High-Speed Connector (P4) The high-speed connector P4 facilitates development of applications where use of the standard IDC connectors is complicated due to signal integrity issues

For the P4 connector and cable assembly availability and pricing contact Samtec

Part Description Manufacturer Part Number

IDC14x2 01rdquo header FCI 68737-428HLF

IDC14x2 01rdquo header Sullins GEC14DAAN

Mating Connector

IDC 14x2 01rdquo plug Samtec SSW-114-01-T-D

Part Description Manufacturer Part Number

QTS 25x2 high-speed connector Samtec QTS-025-01-F-D-A

Mating Connector

QSS 25x2 high-speed connector Samtec QSS-025-01-F-D-A

2-20 Blackfin FPGA EZ-Extender Manual

A BILL OF MATERIALS

The bill of materials corresponds to the board schematics on page B-1

Please check the latest schematics on the Analog Devices website httpwwwanalogcomProcessorsProcessorsDevelopmentToolstec

hnicalLibrarymanualsDevToolsIndexhtmlEvalua-

tion20Kit20Manuals

Blackfin FPGA EZ-Extender Manual A-1

Push Buttons and LEDs

PB2 Push Button (SW4) The PB2 push button SW4 is a general-purpose input push button The switch does not have a connected debounce circuit you may need to cre-ate it in the FPGA if required by a specific application The push button connects to pin H5 of the FPGA

Figure 2-4 Push Button and LED Locations

2-16 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Hardware Reference

Status LEDs (LED1ndash8) Eight status LEDs LED1ndash8 connect to the FPGA and act as status flags in any application that requires it Table 2-15 shows the LEDFPGA connections

Power LED (LED9) The power LED LED9 connects to the 25V power supply and when lit signifies that the FPGA EZ-Extender is powered properly

Done LED (LED10) The done LED LED10 connects to the done pin of the FPGA At power-up the FPGA is blank and needs to be programmed When lit the LED indicates that the FPGA is programmed successfully

Table 2-15 Status LED (LED1ndash8) Settings

Reference Designator FPGA Pin Number

LED1 U11

LED2 W11

LED3 AB10

LED4 Y10

LED5 AB9

LED6 W9

LED7 AB8

LED8 V10

Blackfin FPGA EZ-Extender Manual 2-17

Connectors

ConnectorsBefore using the Blackfin FPGA EZ-Extender follow the steps in ldquoFPGA EZ-Extender Setuprdquo on page 1-1

This section describes the connector functionality and provides informa-tion about the mating connectors The connector locations are shown in Figure 2-5

Figure 2-5 Connector Locations

2-18 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Hardware Reference

Expansion Interface (P1ndash3 and J1ndash3) Connectors P1ndash3 of the expansion interface are used to plug in the EZ-Extender to the ADSP-BF533 ADSP-BF537 or ADSP-BF561 EZ-KIT Lite

Connectors J1ndash3 of the expansion interface are used to plug in another extender board such as the Blackfin USB-LAN EZ-Extender Your own custom board can be plugged into J1ndash3 as well

Plugging in another EZ-Extender or a customer board to the expansion interface can de-grade the overall system performance The extra overall load can cause the user to add wait states or slow down the system bus to get all of the boards to work properly

For the J1ndash3 and P1ndash3 connector availability and pricing contact Samtec

IDC Connectors (P8 P14 P16 and P17) The P8 P14 P16 and P17 connectors are standard 01rdquo IDC headers The connectors are in a 13 x 2 configuration and designed for signal probing bread boarding and other signal accesses

Part Description Manufacturer Part Number

90-position 005rdquo spacing SMT(J1 J2 J3)

Samtec SFC-145-T2-F-D-A

90-position 005rdquo spacing (P1 P2 P3)

Samtec TFC-145-32-F-D

Part Description Manufacturer Part Number

IDC13x2 01rdquo header Berg 54102-T08-13

Mating Connector

IDC 13x2 01rdquo plug Samtec SSW-113-01-T-D

Blackfin FPGA EZ-Extender Manual 2-19

Connectors

IDC Connectors (P5 and P7) The P5 and P7 connectors are standard 01rdquo IDC headers The connectors are in a 14 x 2 configuration and designed for signal probing bread boarding and other signal accesses

High-Speed Connector (P4) The high-speed connector P4 facilitates development of applications where use of the standard IDC connectors is complicated due to signal integrity issues

For the P4 connector and cable assembly availability and pricing contact Samtec

Part Description Manufacturer Part Number

IDC14x2 01rdquo header FCI 68737-428HLF

IDC14x2 01rdquo header Sullins GEC14DAAN

Mating Connector

IDC 14x2 01rdquo plug Samtec SSW-114-01-T-D

Part Description Manufacturer Part Number

QTS 25x2 high-speed connector Samtec QTS-025-01-F-D-A

Mating Connector

QSS 25x2 high-speed connector Samtec QSS-025-01-F-D-A

2-20 Blackfin FPGA EZ-Extender Manual

A BILL OF MATERIALS

The bill of materials corresponds to the board schematics on page B-1

Please check the latest schematics on the Analog Devices website httpwwwanalogcomProcessorsProcessorsDevelopmentToolstec

hnicalLibrarymanualsDevToolsIndexhtmlEvalua-

tion20Kit20Manuals

Blackfin FPGA EZ-Extender Manual A-1

FPGA EZ-Extender Hardware Reference

Status LEDs (LED1ndash8) Eight status LEDs LED1ndash8 connect to the FPGA and act as status flags in any application that requires it Table 2-15 shows the LEDFPGA connections

Power LED (LED9) The power LED LED9 connects to the 25V power supply and when lit signifies that the FPGA EZ-Extender is powered properly

Done LED (LED10) The done LED LED10 connects to the done pin of the FPGA At power-up the FPGA is blank and needs to be programmed When lit the LED indicates that the FPGA is programmed successfully

Table 2-15 Status LED (LED1ndash8) Settings

Reference Designator FPGA Pin Number

LED1 U11

LED2 W11

LED3 AB10

LED4 Y10

LED5 AB9

LED6 W9

LED7 AB8

LED8 V10

Blackfin FPGA EZ-Extender Manual 2-17

Connectors

ConnectorsBefore using the Blackfin FPGA EZ-Extender follow the steps in ldquoFPGA EZ-Extender Setuprdquo on page 1-1

This section describes the connector functionality and provides informa-tion about the mating connectors The connector locations are shown in Figure 2-5

Figure 2-5 Connector Locations

2-18 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Hardware Reference

Expansion Interface (P1ndash3 and J1ndash3) Connectors P1ndash3 of the expansion interface are used to plug in the EZ-Extender to the ADSP-BF533 ADSP-BF537 or ADSP-BF561 EZ-KIT Lite

Connectors J1ndash3 of the expansion interface are used to plug in another extender board such as the Blackfin USB-LAN EZ-Extender Your own custom board can be plugged into J1ndash3 as well

Plugging in another EZ-Extender or a customer board to the expansion interface can de-grade the overall system performance The extra overall load can cause the user to add wait states or slow down the system bus to get all of the boards to work properly

For the J1ndash3 and P1ndash3 connector availability and pricing contact Samtec

IDC Connectors (P8 P14 P16 and P17) The P8 P14 P16 and P17 connectors are standard 01rdquo IDC headers The connectors are in a 13 x 2 configuration and designed for signal probing bread boarding and other signal accesses

Part Description Manufacturer Part Number

90-position 005rdquo spacing SMT(J1 J2 J3)

Samtec SFC-145-T2-F-D-A

90-position 005rdquo spacing (P1 P2 P3)

Samtec TFC-145-32-F-D

Part Description Manufacturer Part Number

IDC13x2 01rdquo header Berg 54102-T08-13

Mating Connector

IDC 13x2 01rdquo plug Samtec SSW-113-01-T-D

Blackfin FPGA EZ-Extender Manual 2-19

Connectors

IDC Connectors (P5 and P7) The P5 and P7 connectors are standard 01rdquo IDC headers The connectors are in a 14 x 2 configuration and designed for signal probing bread boarding and other signal accesses

High-Speed Connector (P4) The high-speed connector P4 facilitates development of applications where use of the standard IDC connectors is complicated due to signal integrity issues

For the P4 connector and cable assembly availability and pricing contact Samtec

Part Description Manufacturer Part Number

IDC14x2 01rdquo header FCI 68737-428HLF

IDC14x2 01rdquo header Sullins GEC14DAAN

Mating Connector

IDC 14x2 01rdquo plug Samtec SSW-114-01-T-D

Part Description Manufacturer Part Number

QTS 25x2 high-speed connector Samtec QTS-025-01-F-D-A

Mating Connector

QSS 25x2 high-speed connector Samtec QSS-025-01-F-D-A

2-20 Blackfin FPGA EZ-Extender Manual

A BILL OF MATERIALS

The bill of materials corresponds to the board schematics on page B-1

Please check the latest schematics on the Analog Devices website httpwwwanalogcomProcessorsProcessorsDevelopmentToolstec

hnicalLibrarymanualsDevToolsIndexhtmlEvalua-

tion20Kit20Manuals

Blackfin FPGA EZ-Extender Manual A-1

Connectors

ConnectorsBefore using the Blackfin FPGA EZ-Extender follow the steps in ldquoFPGA EZ-Extender Setuprdquo on page 1-1

This section describes the connector functionality and provides informa-tion about the mating connectors The connector locations are shown in Figure 2-5

Figure 2-5 Connector Locations

2-18 Blackfin FPGA EZ-Extender Manual

FPGA EZ-Extender Hardware Reference

Expansion Interface (P1ndash3 and J1ndash3) Connectors P1ndash3 of the expansion interface are used to plug in the EZ-Extender to the ADSP-BF533 ADSP-BF537 or ADSP-BF561 EZ-KIT Lite

Connectors J1ndash3 of the expansion interface are used to plug in another extender board such as the Blackfin USB-LAN EZ-Extender Your own custom board can be plugged into J1ndash3 as well

Plugging in another EZ-Extender or a customer board to the expansion interface can de-grade the overall system performance The extra overall load can cause the user to add wait states or slow down the system bus to get all of the boards to work properly

For the J1ndash3 and P1ndash3 connector availability and pricing contact Samtec

IDC Connectors (P8 P14 P16 and P17) The P8 P14 P16 and P17 connectors are standard 01rdquo IDC headers The connectors are in a 13 x 2 configuration and designed for signal probing bread boarding and other signal accesses

Part Description Manufacturer Part Number

90-position 005rdquo spacing SMT(J1 J2 J3)

Samtec SFC-145-T2-F-D-A

90-position 005rdquo spacing (P1 P2 P3)

Samtec TFC-145-32-F-D

Part Description Manufacturer Part Number

IDC13x2 01rdquo header Berg 54102-T08-13

Mating Connector

IDC 13x2 01rdquo plug Samtec SSW-113-01-T-D

Blackfin FPGA EZ-Extender Manual 2-19

Connectors

IDC Connectors (P5 and P7) The P5 and P7 connectors are standard 01rdquo IDC headers The connectors are in a 14 x 2 configuration and designed for signal probing bread boarding and other signal accesses

High-Speed Connector (P4) The high-speed connector P4 facilitates development of applications where use of the standard IDC connectors is complicated due to signal integrity issues

For the P4 connector and cable assembly availability and pricing contact Samtec

Part Description Manufacturer Part Number

IDC14x2 01rdquo header FCI 68737-428HLF

IDC14x2 01rdquo header Sullins GEC14DAAN

Mating Connector

IDC 14x2 01rdquo plug Samtec SSW-114-01-T-D

Part Description Manufacturer Part Number

QTS 25x2 high-speed connector Samtec QTS-025-01-F-D-A

Mating Connector

QSS 25x2 high-speed connector Samtec QSS-025-01-F-D-A

2-20 Blackfin FPGA EZ-Extender Manual

A BILL OF MATERIALS

The bill of materials corresponds to the board schematics on page B-1

Please check the latest schematics on the Analog Devices website httpwwwanalogcomProcessorsProcessorsDevelopmentToolstec

hnicalLibrarymanualsDevToolsIndexhtmlEvalua-

tion20Kit20Manuals

Blackfin FPGA EZ-Extender Manual A-1

FPGA EZ-Extender Hardware Reference

Expansion Interface (P1ndash3 and J1ndash3) Connectors P1ndash3 of the expansion interface are used to plug in the EZ-Extender to the ADSP-BF533 ADSP-BF537 or ADSP-BF561 EZ-KIT Lite

Connectors J1ndash3 of the expansion interface are used to plug in another extender board such as the Blackfin USB-LAN EZ-Extender Your own custom board can be plugged into J1ndash3 as well

Plugging in another EZ-Extender or a customer board to the expansion interface can de-grade the overall system performance The extra overall load can cause the user to add wait states or slow down the system bus to get all of the boards to work properly

For the J1ndash3 and P1ndash3 connector availability and pricing contact Samtec

IDC Connectors (P8 P14 P16 and P17) The P8 P14 P16 and P17 connectors are standard 01rdquo IDC headers The connectors are in a 13 x 2 configuration and designed for signal probing bread boarding and other signal accesses

Part Description Manufacturer Part Number

90-position 005rdquo spacing SMT(J1 J2 J3)

Samtec SFC-145-T2-F-D-A

90-position 005rdquo spacing (P1 P2 P3)

Samtec TFC-145-32-F-D

Part Description Manufacturer Part Number

IDC13x2 01rdquo header Berg 54102-T08-13

Mating Connector

IDC 13x2 01rdquo plug Samtec SSW-113-01-T-D

Blackfin FPGA EZ-Extender Manual 2-19

Connectors

IDC Connectors (P5 and P7) The P5 and P7 connectors are standard 01rdquo IDC headers The connectors are in a 14 x 2 configuration and designed for signal probing bread boarding and other signal accesses

High-Speed Connector (P4) The high-speed connector P4 facilitates development of applications where use of the standard IDC connectors is complicated due to signal integrity issues

For the P4 connector and cable assembly availability and pricing contact Samtec

Part Description Manufacturer Part Number

IDC14x2 01rdquo header FCI 68737-428HLF

IDC14x2 01rdquo header Sullins GEC14DAAN

Mating Connector

IDC 14x2 01rdquo plug Samtec SSW-114-01-T-D

Part Description Manufacturer Part Number

QTS 25x2 high-speed connector Samtec QTS-025-01-F-D-A

Mating Connector

QSS 25x2 high-speed connector Samtec QSS-025-01-F-D-A

2-20 Blackfin FPGA EZ-Extender Manual

A BILL OF MATERIALS

The bill of materials corresponds to the board schematics on page B-1

Please check the latest schematics on the Analog Devices website httpwwwanalogcomProcessorsProcessorsDevelopmentToolstec

hnicalLibrarymanualsDevToolsIndexhtmlEvalua-

tion20Kit20Manuals

Blackfin FPGA EZ-Extender Manual A-1

Connectors

IDC Connectors (P5 and P7) The P5 and P7 connectors are standard 01rdquo IDC headers The connectors are in a 14 x 2 configuration and designed for signal probing bread boarding and other signal accesses

High-Speed Connector (P4) The high-speed connector P4 facilitates development of applications where use of the standard IDC connectors is complicated due to signal integrity issues

For the P4 connector and cable assembly availability and pricing contact Samtec

Part Description Manufacturer Part Number

IDC14x2 01rdquo header FCI 68737-428HLF

IDC14x2 01rdquo header Sullins GEC14DAAN

Mating Connector

IDC 14x2 01rdquo plug Samtec SSW-114-01-T-D

Part Description Manufacturer Part Number

QTS 25x2 high-speed connector Samtec QTS-025-01-F-D-A

Mating Connector

QSS 25x2 high-speed connector Samtec QSS-025-01-F-D-A

2-20 Blackfin FPGA EZ-Extender Manual

A BILL OF MATERIALS

The bill of materials corresponds to the board schematics on page B-1

Please check the latest schematics on the Analog Devices website httpwwwanalogcomProcessorsProcessorsDevelopmentToolstec

hnicalLibrarymanualsDevToolsIndexhtmlEvalua-

tion20Kit20Manuals

Blackfin FPGA EZ-Extender Manual A-1

A BILL OF MATERIALS

The bill of materials corresponds to the board schematics on page B-1

Please check the latest schematics on the Analog Devices website httpwwwanalogcomProcessorsProcessorsDevelopmentToolstec

hnicalLibrarymanualsDevToolsIndexhtmlEvalua-

tion20Kit20Manuals

Blackfin FPGA EZ-Extender Manual A-1

Ref

Des

crip

tion

Ref

eren

ce D

esig

nato

r M

anuf

actu

rer

Part

Num

ber

11

SN74

LVC

1G12

5 SO

T23

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TI

SN74

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5DB

VR

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SC00

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AR

TA

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FGG

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3475

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ON

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RV

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3475

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U4

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216

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PIN

U7

MIL

L-M

AX

614-

93-3

08-3

1-00

7

A-2 Blackfin FPGA EZ-Extender Manual

Bill Of Materials

113

SPST

-MO

ME

NT

AR

Y

SWT

013

6M

M

SW1

SW3-

4PA

NA

SON

ICE

VQ

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D04

M

123

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2 C

ON

018

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AD

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P

1-3

SAM

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133

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SFC

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F-D

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142

IDC

14X

2 ID

C14

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HE

AD

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P5

P7

FCI

6873

7-42

8HL

F

152

IDC

6X

1 ID

C6X

1H

EA

DE

R

P6

P15

FCI

9072

6-40

6HL

F

161

QT

S 25

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P4

SAM

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025-

01-F

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179

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BE

R-S

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1G

UL

L-W

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D1-

8L

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SON

ICL

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61C

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181

10uF

16V

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AN

TC

4A

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JC10

6K02

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193

3A H

SM35

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SC

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T_R

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TD

1-3

MIC

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350J

201

600

100M

HZ

200

MA

060

30

50 B

EA

DFE

R2

MU

RA

TA

BL

M11

A60

1SP

T

Ref

Des

crip

tion

Ref

eren

ce D

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nato

r M

anuf

actu

rer

Part

Num

ber

Blackfin FPGA EZ-Extender Manual A-3

211

2A S

2A_R

EC

T D

O-2

14A

A

SIL

ICO

N R

EC

TIF

IER

D5

VIS

HA

YS2

A

221

39N

F 50

V 5

8

05C

6PA

NA

SON

ICE

CH

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392J

B5

231

190

100M

HZ

5A

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R00

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R1

MU

RA

TA

DLW

5BSN

191S

Q2

247

10U

F 6

3V 1

0 8

05X

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C14

-16

C35

C55

C83

C

86AV

X08

0560

106K

AT

2A

254

1000

PF

10V

20

805

C

1-2

C10

C74

YA

GE

O12

06C

G22

9C9B

200

263

100U

F 10

V 1

0 C

TA

NT

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W-E

SRC

T1-

3A

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TP

SC10

7K01

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75

275

01U

F 16

V 1

0 0

603

X7R

C3

C38

C56

C84

-85

AVX

0603

YC

104K

AT

2A

2856

001

UF

16V

10

060

3

X7R

C11

-13

C17

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C36

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C39

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C57

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C80

-82

AVX

0603

YC

103K

AT

2A

291

1UF

16V

10

060

3C

5PA

NA

SON

ICE

CJ-

1VB

1C10

5K

303

10U

H 1

7 20

I

ND

005

L1-

3C

OIL

CR

AFT

MSS

1278

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MX

B

318

10K

11

0W 5

0

603

R1

R6

R21

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R28

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R46

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PAN

ASO

NIC

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J-3G

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V

3210

330

110

W 5

0

603

R10

R24

R34

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VIS

HA

YC

RC

W06

0333

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T1

Ref

Des

crip

tion

Ref

eren

ce D

esig

nato

r M

anuf

actu

rer

Part

Num

ber

A-4 Blackfin FPGA EZ-Extender Manual

Bill Of Materials

339

0 1

10W

5

060

3R

3-4

R9

R12

R15

-16

R27

R58

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PAN

ASO

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J-3G

EY

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341

10 1

10W

5

060

3 R

42PA

NA

SON

ICE

RJ-

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YJ1

00V

351

200K

11

6W 1

0

603

R20

VIS

HA

YC

RC

W06

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T1

362

10K

11

0W 1

0

603

R14

R19

PAN

ASO

NIC

P10

0K

HT

R-N

D

372

33 1

10W

1

060

3 R

2R

26Y

AG

EO

9C06

031A

33R

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HFT

385

100

116

W 5

4

02R

5R

7-8

R23

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PAN

ASO

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J-2G

EJ1

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391

390P

F 25

V 5

0

603

NP

OC

7A

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0603

3A39

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T2A

401

499

K 1

16W

1

060

3R

13ST

AC

KP

OL

ER

MC

11

6 4

99K

1

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411

316

K 1

16W

1

060

3 R

17PA

NA

SON

ICE

RJ-

3EK

F316

2V

421

105

K 1

16W

1

060

3 R

11PA

NA

SON

ICE

RJ-

3EK

F105

1V

431

215

K 1

16W

1

060

3R

18PA

NA

SON

ICE

RJ-

3EK

F215

1V

441

GR

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N-S

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LE

D00

1G

UL

L-W

ING

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D9

PAN

ASO

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LN

1361

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453

IDC

2X

1 ID

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1G

OL

DJP

1-3

Ref

Des

crip

tion

Ref

eren

ce D

esig

nato

r M

anuf

actu

rer

Part

Num

ber

Blackfin FPGA EZ-Extender Manual A-5

465

IDC

3X

1 ID

C3X

1P

9-13

BE

RG

5410

1-T

08-0

3

471

IDC

3X

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C3X

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G54

102-

T08

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481

IDC

4X

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C4X

2JP

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INS

S201

2-04

494

IDC

13X

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C13

X2

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8P

14P

16-1

7B

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G54

102-

T08

-13

501

25A

RE

SET

AB

LE

FU

S001

F1R

AY

CH

EM

CO

RP

SMD

250-

2

513

10U

F 10

V 1

0 8

05C

8 C

9 C

71PA

NA

SON

ICE

CJ-

2FB

1A10

6K

Ref

Des

crip

tion

Ref

eren

ce D

esig

nato

r M

anuf

actu

rer

Part

Num

ber

A-6 Blackfin FPGA EZ-Extender Manual

4

3

2

1

A B C D

20 Cotton Road

Nashua NH 03063

A B C D

4

3

2

1

PH 1-800-ANALOGD

C

Title

Size Board No

Date Sheet of

DEVICESANALOG

DNP = Do Not Populate

Rev

BLACKFIN FPGA EZ-EXTENDER

A0199-2005 10

SchematicBLACKFIN FPGA EZ-EXTENDER

1219-9-2005_1040

TITLE

33V

4

3

2

1

A B C D

20 Cotton Road

Nashua NH 03063

A B C D

4

3

2

1

PH 1-800-ANALOGD

C

Title

Size Board No

Date Sheet of

DEVICESANALOG

DNP = Do Not Populate

Rev

BLACKFIN FPGA EZ-EXTENDER

A0199-2005 10

33V

1A

1B

1Y

2A

2B

2Y

3A

3B

3Y

4A

4B

4Y

~AB

EN

25V

33V

33V

33V

33V

33V

25V

33V

OENC OUTOE OUT

CLK

D0

TMS

TCK

TDI

TDO

VCCINT

VCCO

VCCJ

NC1

NC2

NC3

NC4

NC5

NC6

GND

CE

CF

OE~RESET

CEO

VCCAUX_A6

VCCAUX_A17

VCCAUX_F1

VCCAUX_F22

VCCAUX_U1

VCCAUX_U22

VCCAUX_AB6

VCCAUX_AB17

VCCINT_G7

VCCINT_G8

VCCINT_G15

VCCINT_G16

VCCINT_H7

VCCINT_H16

VCCINT_R7

VCCINT_R16

VCCINT_T7

VCCINT_T8

VCCINT_T15

VCCINT_T16

TCK

TDI

TDO

TMS

M0

M1

M2

CCLK

PROG_B

DONE

HSWAP_EN

GND_A1

GND_A22

GND_B2

GND_B21

GND_C9

GND_C14

GND_J3

GND_J9

GND_J10

GND_J11

GND_J12

GND_J13

GND_J14

GND_J20

GND_K9

GND_K10

GND_K11

GND_K12

GND_K13

GND_K14

GND_L9

GND_L10

GND_L11

GND_L12

GND_L13

GND_L14

GND_M9

GND_M10

GND_M11

GND_M12

GND_M13

GND_M14

GND_N9

GND_N10

GND_N11

GND_N12

GND_N13

GND_N14

GND_P3

GND_P9

GND_P10

GND_P11

GND_P12

GND_P13

GND_P14

GND_P20

GND_Y9

GND_Y14

GND_AA2

GND_AA21

GND_AB1

GND_AB22

FPGAFPGA

EXTRA CLOCK SOCKET25MHZ SYSTEM CLOCK

FPGA JTAG HEADER

FLASH JTAG HEADER

BOOTMODE JUMPER

FPGA BOOT FLASH(2Mbit)

MUXFLASHSKTOSC

9-27-2005_1144 2 12

A6

A17

F1

F22

U1

U22

AB6

AB17

G7

G8

G15

G16

H7

H16

R7

R16

T7

T8

T15

T16

A21

B1

B22

A20

AB2

AA1

AB3

AA22

A2

AB21

B3

A1

A22

B2

B21

C9

C14

J3

J9

J10

J11

J12

J13

J14

J20

K9

K10

K11

K12

K13

K14

L9

L10

L11

L12

L13

L14

M9

M10

M11

M12

M13

M14

N9

N10

N11

N12

N13

N14

P3

P9

P10

P11

P12

P13

P14

P20

Y9

Y14

AA2

AA21

AB1

AB22

U1

FG456XC3S1000

CONFIG_PROG_B

6

5

4

3

2

1P6

IDC6X16X1

1

2

3

4

5

6

P15

IDC6X16X1

3

1

8

10

7

13

5

6

4

17

18

19

20

2

9

12

14

15

16

11

U4

TSSOP20XCF04S

2

4

5 6

3

1JP4

IDC3X23X2

402100R5

R400603

402100R44

R8100402

R7100402

1 3

U6

25MHZOSC003

80510UFC14

R29

060310K

R22

060310K

R21

060310K

R1

060310K

1 5

U7

DIPDIP8SOC

R263306030603

33R2

R25

DNP

10K0603

12V

1 2JP1

IDC2X12X1

CONFIG_DONER3

06030

CONFIG_CLK_TSCLK1

FPGA_TMS

FPGA_TDO

FPGA_TCK

FPGA_TDI

FPGA_TCK

FPGA_TDO

FPGA_TDI

FPGA_TMS

FLASH_TMS

FLASH_TDI

FLASH_TDO

FLASH_TCK

M1

M2

M0

12V

SPST-MOMENTARYSWT013SW1

2

3

4

5

6

7

11

10

9

14

13

12

1

15

U2

TSSOP1674LVC157

CONFIG_DONE

FLASH_TMS

FLASH_TCK

FLASH_TDI

FLASH_TDO

M2

M0

M1

FPGA CONFIG

CONFIG_INIT_B_TFS1

FLASH_DOUT

CONFIG_CLK_TSCLK1

FLASH_DONE

001UF0603

C18

IO_L32_0_GCLK6_A11B4_L32N_GCKL1_AA12

C19

0603001UF 001UF

0603

C20 C21

0603001UF 001UF

0603

C25C24

0603001UF001UF

0603

C23C22

0603001UF 001UF

0603

C31 C30

0603001UF 001UF

0603

C29 C28

0603001UF001UF

0603

C27C26

0603001UF

001UF0603

C32 C11

0603001UF 001UF

0603

C12 C13

0603001UF

80510UFC15 C16

10UF805

C17

0603001UF

0603330R24

LED10

LED001AMBER-SMT

CONFIG_DIN_DT1PRI

FLASH_DONE

FLASH_DOUT

DT1PRI

R6

060310K10K

0603

R28

33V 33V

4

3

2

1

A B C D

20 Cotton Road

Nashua NH 03063

A B C D

4

3

2

1

PH 1-800-ANALOGD

C

Title

Size Board No

Date Sheet of

DEVICESANALOG

DNP = Do Not Populate

Rev

BLACKFIN FPGA EZ-EXTENDER

A0199-2005 10

33V

33V

A18

A1

A10

A11

A12

A13

A14

A16

A2

A3

A4

A5

A6

A7

A8

A9

D0

D1

D10

D11

D2

D3

D4

D5

D6

D7

D8

D9

BHE

BLE

CE

OE

WE

A17

D15

D14

D13

D12

A0

A15

A18

A1

A10

A11

A12

A13

A14

A16

A2

A3

A4

A5

A6

A7

A8

A9

D0

D1

D10

D11

D2

D3

D4

D5

D6

D7

D8

D9

BHE

BLE

CE

OE

WE

A17

D15

D14

D13

D12

A0

A15

VCCO_6_M7

VCCO_6_N7

VCCO_6_P7

VCCO_6_R3

VCCO_6_R6

IO_Y1

IO_L16N_6_W4

IO_L16P_6_W3

IO_L17N_6_W2

IO_L17P_6_VREF_6_W1

IO_L19N_6_V5

IO_L19P_6_U5

IO_L20N_6_V4

IO_L20P_6_V3

IO_L21N_6_V2

IO_L21P_6_V1

IO_L22N_6_T6

IO_L22P_6_T5

IO_L23N_6_U4

IO_L23P_6_T4

IO_L24N_6_VREF_6_U3

IO_L24P_6_U2

IO_L26N_6_T3

IO_L26P_6_R4

IO_L27N_6_T2

IO_L27P_6_T1

IO_L28N_6_R5

IO_L28P_6_P6

IO_L29N_6_R2

IO_L29P_6_R1

IO_L31N_6_P5

IO_L31P_6_P4

IO_L32N_6_P2

IO_L32P_6_P1

IO_L33N_6_N6

IO_L33P_6_N5

IO_L34N_6_VREF_6_N4

IO_L34P_6_N3

IO_L35N_6_N2

IO_L35P_6_N1

IO_L38N_6_M6

IO_L38P_6_M5

IO_L39N_6_M4

IO_L39P_6_M3

IO_L40N_6_M2

IO_L40P_6_VREF_6_M1

IO_L01N_6_VRP_6_Y3

IO_L01P_6_VRN_6_Y2

VCCO_7_H3

VCCO_7_H6

VCCO_7_J7

VCCO_7_K7

VCCO_7_L7

IO_C2

IO_L16N_7_D1

IO_L16P_7_VREF_7_C1

IO_L17N_7_E4

IO_L17P_7_D4

IO_L19N_7_VREF_7_D3

IO_L19P_7_D2

IO_L20N_7_F4

IO_L20P_7_E3

IO_L21N_7_E1

IO_L21P_7_E2

IO_L22N_7_G6

IO_L22P_7_F5

IO_L23N_7_F2

IO_L23P_7_F3

IO_L24N_7_H5

IO_L24P_7_G5

IO_L26N_7_G3

IO_L26P_7_G4

IO_L27N_7_G1

IO_L27P_7_VREF_7_G2

IO_L28N_7_H1

IO_L28P_7_H2

IO_L29N_7_J4

IO_L29P_7_H4

IO_L31N_7_J5

IO_L31P_7_J6

IO_L32N_7_J1

IO_L32P_7_J2

IO_L33N_7_K5

IO_L33P_7_K6

IO_L34N_7_K3

IO_L34P_7_K4

IO_L35N_7_K1

IO_L35P_7_K2

IO_L38N_7_L5

IO_L38P_7_L6

IO_L39N_7_L3

IO_L39P_7_L4

IO_L40N_7_VREF_7_L1

IO_L40P_7_L2

IO_L01N_7_VRP_7_C3

IO_L01P_7_VRN_7_C4

(512k x 16bits x 2chips)2MBYTES FPGA SRAM

FPGASRAM SRAM

SRAM_A9

9-27-2005_1144 3 12

FLASH_TDO

FLASH_TMS

FLASH_TDI

FLASH_TCK

M7

N7

P7

R3

R6

Y1

W4

W3

W2

W1

V5

U5

V4

V3

V2

V1

T6

T5

U4

T4

U3

U2

T3

R4

T2

T1

R5

P6

R2

R1

P5

P4

P2

P1

N6

N5

N4

N3

N2

N1

M6

M5

M4

M3

M2

M1

Y3

Y2

H3

H6

J7

K7

L7

C2

D1

C1

E4

D4

D3

D2

F4

E3

E1

E2

G6

F5

F2

F3

H5

G5

G3

G4

G1

G2

H1

H2

J4

H4

J5

J6

J1

J2

K5

K6

K3

K4

K1

K2

L5

L6

L3

L4

L1

L2

C3

C4

U1

FG456XC3S1000

28

2

23

24

25

26

27

43

3

4

5

18

19

20

21

22

7

8

31

32

9

10

13

14

15

16

29

30

40

39

6

41

17

44

38

37

36

35

1

42

U3

TSOP44IS61LV51216

42

1

35

36

37

38

44

17

41

6

39

40

30

29

16

15

14

13

10

9

32

31

8

7

22

21

20

19

18

5

4

3

43

27

26

25

24

23

2

28

U5

TSOP44IS61LV51216

SRAM_D7

SRAM_D6

SRAM_D3

SRAM_D2

SRAM_D0

SRAM_D8

SRAM_D9

SRAM_D5

SRAM_D4

SRAM_D13

SRAM_D1

SRAM_D10

SRAM_D11

SRAM_D12

SRAM_D14

SRAM_D15

SRAM_CE

SRAM_A7

SRAM_A0

SRAM_A5

SRAM_A3

SRAM_A1

SRAM_WE

SRAM_A8

SRAM_A6

SRAM_A4

SRAM_A2

SRAM_A17

SRAM_OE

SRAM_A12

SRAM_A13

SRAM_A15

SRAM_A16

SRAM_A14

SRAM_A18

SRAM_A11

SRAM_A10

SRAM_D22

SRAM_D20

SRAM_D18

SRAM_D17

SRAM_D16

SRAM_D26

SRAM_D21

SRAM_D24

SRAM_D19

SRAM_D31

SRAM_D25

SRAM_D27

SRAM_D28

SRAM_D30

SRAM_D29

PB2

A11

A5

D1

A15

A3

A9

D13

D7

A13

A19

A7

A1

A18

A6

A2

A12

D6

A8

A14

D2

D0

A10

A4

D3

A16

SRAM FPGA BANKS 7 + 8

SRAM_CE

SRAM_WE

SRAM_OE

SRAM_A18

SRAM_A0 SRAM_D0

SRAM_D1

SRAM_D2

SRAM_D3

SRAM_D4

SRAM_D5

SRAM_D6

SRAM_D7

SRAM_D8

SRAM_D9

SRAM_D10

SRAM_D11

SRAM_D12

SRAM_D13

SRAM_D14

SRAM_D15

SRAM_D16

SRAM_D17

SRAM_D18

SRAM_D19

SRAM_D20

SRAM_D21

SRAM_D22

SRAM_D23

SRAM_D24

SRAM_D25

SRAM_D26

SRAM_D27

SRAM_D28

SRAM_D29

SRAM_D30

SRAM_D31

SRAM_A1

SRAM_A2

SRAM_A3

SRAM_A4

SRAM_A5

SRAM_A6

SRAM_A7

SRAM_A8

SRAM_A9

SRAM_A10

SRAM_A11

SRAM_A12

SRAM_A13

SRAM_A14

SRAM_A15

SRAM_A16

SRAM_A17

SRAM_A1

SRAM_A2

SRAM_A3

SRAM_A4

SRAM_A5

SRAM_A6

SRAM_A7

SRAM_A8

SRAM_A9

SRAM_A10

SRAM_A11

SRAM_A12

SRAM_A13

SRAM_A14

SRAM_A15

SRAM_A16

SRAM_A17

SRAM_A18

SRAM_A0

SRAM_OE

SRAM_WE

SRAM_CE

C33

0603001UF

C34

0603001UF001UF

0603

C37001UF0603

C36

C42

0603001UF 001UF

0603

C41 C40

0603001UF001UF

0603

C39001UF0603

C46 C45

0603001UF 001UF

0603

C44C43

0603001UF

B6_L01P_Y2

B6_L01N_Y3

SRAM_D23

4

3

2

1

A B C D

20 Cotton Road

Nashua NH 03063

A B C D

4

3

2

1

PH 1-800-ANALOGD

C

Title

Size Board No

Date Sheet of

DEVICESANALOG

DNP = Do Not Populate

Rev

BLACKFIN FPGA EZ-EXTENDER

A0199-2005 10

EXPANSION INTERFACE TYPE B

P1Expanison Connector

Top Of BoardBottom Of Board

Expansion Connector 1

10-18-2005_1616 4 12

EXPANSION INTERFACE CONNECTOR 1

C3510UF805

01UF0603

C38

5V_EI

5V_EI

1

10

11 12

13 14

15 16

17 18

19

2

20

21 22

23 24

25 26

27 28

29

3

30

31 32

33 34

35 36

37 38

39

4

40

41 42

43 44

45 46

47 48

49

5

50

51 52

53 54

55 56

57 58

59

6

60

61 62

63 64

65 66

67 68

69

7

70

71 72

73 74

75 76

77 78

79

8

80

81 82

83 84

85 86

87 88

89

9

90

P1

CON01845X2

1

10

1112

1314

1516

1718

19

2

20

2122

2324

2526

2728

29

3

30

3132

3334

3536

3738

39

4

40

4142

4344

4546

4748

49

5

50

5152

5354

5556

5758

59

6

60

6162

6364

6566

6768

69

7

70

7172

7374

7576

7778

79

8

80

8182

8384

8586

8788

89

9

90

J1

CON01945X2

PP1

EXPANSION_PPI_CLK

PP3

UDEF2

UDEF4

UDEF6

UDEF8

UDEF10

D9

D7

D15

D13

D11

D5

D1

D3

D15

D9

D5

D1

D3

D0

D2

D4

D6

D8

D10

D14

D12

P1_5

P1_25

P1_27

P1_29

P1_31

P1_33

P1_55

P1_57

P1_59

P1_61

P1_63

P1_65

P1_67

P1_69

P1_35

P1_26

P1_28

P1_30

P1_32

P1_34

P1_56

P1_58

P1_60

P1_62

P1_64

P1_66

P1_68

P1_70

P1_36

P1_26

P1_28

P1_30

P1_32

P1_34

P1_36

P1_56

P1_58

P1_60

P1_62

P1_64

P1_66

P1_68

P1_70

P1_5

P1_25

P1_27

P1_29

P1_31

P1_33

P1_35

P1_55

P1_57

P1_59

P1_61

P1_63

P1_65

P1_67

P1_69

P1_[586]

A5

A6A7

A8A9

A10A11

A12A13

A14A15

A16A17

A18A19

D0

D2

D4

D6D7

D8

D10D11

D12D13

D14

A1

A2

B1_L24N_D15_J1_71B1_L24P_E15_J1_72

B1_L22N_A16_J1_73B1_L22P_B16_J1_74

B1_L19N_C16_J1_75B1_L19P_D16_J1_76

B1_L16N_B17_J1_77B1_L16P_C17_J1_78

B1_L15N_D17_J1_79

A3

B1_L15P_E17_J1_80

B1_L10N_A18_J1_81B1_L10P_B18_J1_82

B1_L09N_C18_J1_83B1_L09P_D18_J1_84

B1_L06N_A19_J1_85B1_L06P_B19_J1_86

A4A5

A6 A7

A8 A9

A10 A11

A12 A13

A14 A15

A16 A17

A18 A19

A1

A2

PP0

PP2

UDEF1

UDEF3

A3

UDEF5

UDEF7

UDEF9

UDEF11

A4

33V

25V 33V

33V

33V

33V

4

3

2

1

A B C D

20 Cotton Road

Nashua NH 03063

A B C D

4

3

2

1

PH 1-800-ANALOGD

C

Title

Size Board No

Date Sheet of

DEVICESANALOG

DNP = Do Not Populate

Rev

BLACKFIN FPGA EZ-EXTENDER

A0199-2005 10

VCCO_0_C8

VCCO_0_F8

VCCO_0_G9

VCCO_0_G10

VCCO_0_G11

IO_A10

IO_D9

IO_D10

IO_F6

IO_VREF_0_A3

IO_VREF_0_C7

IO_VREF_0_E5

IO_VREF_0_F7

IO_L06N_0_D5

IO_L06P_0_C5

IO_L09N_0_B5

IO_L09P_0_A5

IO_L10N_0_E6

IO_L10P_0_D6

IO_L15N_0_C6

IO_L15P_0_B6

IO_L16N_0_E7

IO_L16P_0_D7

IO_L19N_0_B7

IO_L19P_0_A7

IO_L22N_0_E8

IO_L22P_0_D8

IO_L24N_0_B8

IO_L24P_0_A8

IO_L25N_0_F9

IO_L25P_0_E9

IO_L27N_0_B9

IO_L27P_0_A9

IO_L28N_0_F10

IO_L28P_0_E10

IO_L29N_0_C10

IO_L29P_0_B10

IO_L30N_0_F11

IO_L30P_0_E11

IO_L31N_0_D11

IO_L31P_0_VREF_0_C11

IO_L01N_0_VRP_0_B4

IO_L01P_0_VRN_0_A4

IO_L32N_0_GCLK7_B11

IO_L32P_0_GCLK6_A11

VCCO_1_C15

VCCO_1_F15

VCCO_1_G12

VCCO_1_G13

VCCO_1_G14

IO_A12

IO_E16

IO_F12

IO_F13

IO_F16

IO_F17

IO_VREF_1_E13

IO_VREF_1_F14

IO_L06N_1_VREF_1_A19

IO_L06P_1_B19

IO_L09N_1_C18

IO_L09P_1_D18

IO_L10N_1_VREF_1_A18

IO_L10P_1_B18

IO_L15N_1_D17

IO_L15P_1_E17

IO_L16N_1_B17

IO_L16P_1_C17

IO_L19N_1_C16

IO_L19P_1_D16

IO_L22N_1_A16

IO_L22P_1_B16

IO_L24N_1_D15

IO_L24P_1_E15

IO_L25N_1_B15

IO_L25P_1_A15

IO_L27N_1_D14

IO_L27P_1_E14

IO_L28N_1_A14

IO_L28P_1_B14

IO_L29N_1_C13

IO_L29P_1_D13

IO_L30N_1_A13

IO_L30P_1_B13

IO_L31N_1_VREF_1_D12

IO_L31P_1_E12

IO_L01N_1_VRP_1_C19

IO_L01P_1_VRN_1_B20

IO_L32N_1_GCLK5_B12

IO_L32P_1_GCLK4_C12

FPGAFPGA

LAYOUT NOTE PLACE NEAR FPGA

5 129-27-2005_1144

C8

F8

G9

G10

G11

A10

D9

D10

F6

A3

C7

E5

F7

D5

C5

B5

A5

E6

D6

C6

B6

E7

D7

B7

A7

E8

D8

B8

A8

F9

E9

B9

A9

F10

E10

C10

B10

F11

E11

D11

C11

B4

A4

B11

A11

C15

F15

G12

G13

G14

A12

E16

F12

F13

F16

F17

E13

F14

A19

B19

C18

D18

A18

B18

D17

E17

B17

C17

C16

D16

A16

B16

D15

E15

B15

A15

D14

E14

A14

B14

C13

D13

A13

B13

D12

E12

C19

B20

B12

C12

U1

FG456XC3S1000

1

10

11 12

13 14

15 16

17 18

19

2

20

21 22

23 24

25 26

27 28

29

3

30

31 32

33 34

35 36

37 38

4

5 6

7 8

9

39 40

41

43

45

47

49

42

44

46

48

50

25X2CON041

P4

5

1

18

20

22

26

24

16

14

12

25

23

21

19

17

15

13

11

9

3

6

10

8

4

2

7

P8

IDC13X213X2

5

1

18

20

22

26

24

16

14

12

25

23

21

19

17

15

13

11

9

3

6

10

8

4

2

7

P14

IDC13X213X2

FPGA BANKS 0 + 1

001UF0603

C50

DNP0603

R52

B1_L10N_A18_J1_81

B1_L15P_E17_J1_80

R53

0603DNP

B1_L16P_C17_J1_78

R27

06030

B1_L10P_B18_J1_82B1_L10N_A18_J1_81

B1_L15N_D17_J1_79

B1_L16N_B17_J1_77

B1_L24N_D15_J1_71

B1_L22N_A16_J1_73

B1_L19N_C16_J1_75

R51

0603DNPDNP

0603

R50DNP0603

R48

R31

0603DNP

B1_L19N_C16_J1_75

B1_L22N_A16_J1_73

B1_L24N_D15_J1_71

B1_L15N_D17_J1_79

B1_L15P_E17_J1_80

B1_L16N_B17_J1_77

B1_L16P_C17_J1_78

DNP0603

R30

VCCO_1

VCCO_1

C47

0603001UF

VCCO_1

B1_L27N_D14

PB1

AOE

B1_L01P_VRN_B20

B1_L01N_VRP_C19

IO_L32_0_GCLK6_A11

IO_L32_0_GCLK7_B11

IO_L32_0_GCLK7_B11

B1_L32N_GCLK5_B12

B1_L32P_GCLK4_C12 B1_L06P_B19_J1_86

B1_L09P_D18_J1_84

B1_L15P_E17_J1_80

B1_L16P_C17_J1_78

B1_L19P_D16_J1_76

B1_L16N_B17_J1_77

B1_L15N_D17_J1_79

B1_L09N_C18_J1_83

B1_L06N_A19_J1_85

B1_L31P_E12

B1_L31N_D12

B1_L06N_A19_J1_85

B1_L09N_C18_J1_83

B1_L09P_D18_J1_84

B1_L06P_B19_J1_86

B1_F17

B1_F16

B1_E16

B1_F13

B1_E13

B1_F12

B1_A12

B1_F14

B1_L01N_VRP_C19

B1_L01P_VRN_B20

B1_L32P_GCLK4_C12

B1_L32N_GCLK5_B12

AMS3

D5

D4

AMS0

UDEF1

ARE

ARDY

AMS1

AMS2

UDEF11

UDEF9

UDEF7

UDEF5

UDEF3

PP2

PP0

D15

D11

D9

A17

B1_L16P_C17_J1_78

B1_L19P_D16_J1_76

B1_L19N_C16_J1_75

B1_L22P_B16_J1_74

B1_L24N_D15_J1_71

B1_L22N_A16_J1_73

B1_L24P_E15_J1_72

B1_L16N_B17_J1_77

B1_L10P_B18_J1_82

B1_L15P_E17_J1_80

B1_L15N_D17_J1_79

B1_L10N_A18_J1_81

B1_L09P_D18_J1_84

B1_L09N_C18_J1_83

B1_L06P_B19_J1_86

B1_L06N_A19_J1_85

B1_L31N_D12

B1_L30N_A13

B1_L29N_C13

B1_L28N_A14

B1_L27N_D14

B1_L25N_B15

B1_F16

B1_F14

B1_F13

B1_F12

B1_L31P_E12

B1_L30P_B13

B1_L29P_D13

B1_L28P_B14

B1_L27P_E14

B1_L25P_A15

B1_F17

B1_E13

B1_E16

B1_A12

UDEF10

ABE3

ABE1

ABE0

ABE2

AWE

UDEF6

UDEF8

PP3

UDEF4

UDEF2

PP1

D14

D8

D10

D12

B1_L25P_A15B1_L25N_B15

B1_L22N_A16_J1_73

B1_L24N_D15_J1_71

B1_L19N_C16_J1_75

B1_L24P_E15_J1_72

B1_L22P_B16_J1_74

B1_L27P_E14

B1_L19P_D16_J1_76

B1_L22P_B16_J1_74

B1_L24P_E15_J1_72

B1_L25N_B15

B1_L25P_A15

B1_L27N_D14

B1_L27P_E14

B1_L28N_A14

B1_L28P_B14

B1_L29N_C13

B1_L29P_D13

B1_L30N_A13

B1_L30P_B13

B1_L10N_A18_J1_81

B1_L10P_B18_J1_82

3

2

1

3X1IDC3X1

P9

EXPANSION_PPI_CLK

B1_F16 B1_F17

B1_L28P_B14

B1_L29P_D13

B1_L30P_B13

B1_L31P_E12

B1_L28N_A14

B1_L29N_C13

B1_L30N_A13

B1_L31N_D12

B1_E16

B1_E13

B1_A12

B1_L01P_VRN_B20

B1_L32P_GCLK4_C12

B1_F14

B1_L01N_VRP_C19

B1_L32N_GCLK5_B12

B1_F13

B1_F12

B1_L01P_VRN_B20

B1_L01N_VRP_C19

001UF0603

C48 C49

0603001UF

C51

0603001UF 001UF

0603

C52 C53

0603001UF001UF

0603

C54

VCCO_1

R49

0603DNP

B1_L10P_B18_J1_82

DNP0603

R54

4

3

2

1

A B C D

20 Cotton Road

Nashua NH 03063

A B C D

4

3

2

1

PH 1-800-ANALOGD

C

Title

Size Board No

Date Sheet of

DEVICESANALOG

DNP = Do Not Populate

Rev

BLACKFIN FPGA EZ-EXTENDER

A0199-2005 10Expanison ConnectorP2

Bottom Of Board Top Of Board

Expansion Connector 2

33V_EI

6 129-14-2005_1203

EXPANSION INTERFACE CONNECTOR 2

SCK

NMI

TMR1

PF1

PF3

PF5

PF7

PF9

PF11

PF13

PF15

1

10

11 12

13 14

15 16

17 18

19 20

21 22

23 24

25 26

27 28

29

3

30

31 32

33 34

35 36

37 38

39

4

40

41 42

43 44

45 46

47 48

49

5

50

51 52

53 54

55 56

57 58

59

6

60

61 62

63 64

65 66

67 68

69

7

70

71 72

73 74

75 76

77 78

79

8

80

81 82

83 84

85 86

87 88

89

9

90

2P2

CON01845X2

1

10

1112

1314

1516

1718

19

2

20

2122

2324

2526

2728

29

3

30

3132

3334

3536

3738

39

4

40

4142

4344

4546

4748

49

5

50

5152

5354

5556

5758

59

6

60

6162

6364

6566

6768

69

7

70

7172

7374

7576

7778

79

8

80

8182

8384

8586

8788

89

9

90

J2

CON01945X2

ARE

ARDY

AMS0

AMS1

P2_21

P2_19

P2_7

P2_21

P2_71

P2_73

P2_77

P2_79

P2_83

P2_85

P2_81

P2_19

P2_15

P2_5 P2_6

P2_8

P2_22

P2_86

P2_84

P2_82

P2_80

P2_78

P2_74

P2_72

P2_20

P2_18

P2_22

P2_74

P2_78

P2_82

P2_84

P2_86

P2_80

P2_72

P2_20

P2_18

P2_8

P2_6

P2_[586]

P2_5

P2_7

P2_15

P2_85

P2_83

P2_81

P2_79

P2_77

P2_73

P2_71AWE

AOE

ABE0

ABE1

ABE2

ABE3

TSCLK0

TFS0

DT0PRI

DT0SEC

CONFIG_CLK_TSCLK1

CONFIG_INIT_B_TFS1

DT1PRI

DT1SEC

TMR0

TMR2

PF14

PF12

PF10

PF8

PF4

PF6

PF2

PF0

B2_L40N_L21_J2_9

B2_L39N_L19_J2_11

B2_C22_J2_17

B2_L38N_L17_J2_23

B2_L35N_K21_J2_25

B2_L34N_K19_J2_27

B2_L33N_K17_J2_29

B2_L32N_J21_J2_31

B2_L31N_J18_J2_33

B2_L29N_H21_J2_35

B2_L28N_H18_J2_37

B2_L27N_G21_J2_39

B2_L26N_G20_J2_41

B2_L22N_G17_J2_43

B2_L24N_F20_J2_45

B2_L23N_F19_J2_47

B2_L21N_E21_J2_49

B2_L20N_E19_J2_51

B2_L19N_E18_J2_53

B2_L17N_D21_J2_55

B2_L16N_D20_J2_57B2_L16P_D19_J2_58

B2_L17P_D22_J2_56

B2_L19P_F18_J2_54

B2_L20P_E20_J2_52

B2_L21P_E22_J2_50

B2_L23P_G19_J2_48

B2_L24P_F21_J2_46

B2_L22P_G18_J2_44

B2_L26P_H19_J2_42

B2_L27P_G22_J2_40

B2_L28P_J17_J2_38

B2_L29P_H22_J2_36

B2_L31P_J19_J2_34

B2_L32P_J22_J2_32

B2_L33P_K18_J2_30

B2_L34P_K20_J2_28

B2_L35P_K22_J2_26

B2_L38P_L18_J2_24

IO_L01P_2_VRN_2_C21_J2_16

B2_L40P_L22_J2_10

B2_L39P_L20_J2_12

MOSI

MISO

UDEF12

AMS3

AMS2

AMS0

ARDY

AMS1

AREAWE

AOE

ABE0

ABE1

ABE2

ABE3

RSCLK1

RSCLK0

RFS1

DR1PRI

DR1SEC

AMS2

AMS3

DR0SEC

DR0PRI

RFS0

TMR3

SPIDS0

C56

060301UF

80510UFC55

33V_EI

33V

4

3

2

1

A B C D

20 Cotton Road

Nashua NH 03063

A B C D

4

3

2

1

PH 1-800-ANALOGD

C

Title

Size Board No

Date Sheet of

DEVICESANALOG

DNP = Do Not Populate

Rev

BLACKFIN FPGA EZ-EXTENDER

A0199-2005 10

33V

25V33V

33V

33V

VCCO_2_H17

VCCO_2_H20

VCCO_2_J16

VCCO_2_K16

VCCO_2_L16

IO_C22

IO_L16N_2_D20

IO_L16P_2_D19

IO_L17N_2_D21

IO_L17P_2_VREF_2_D22

IO_L19N_2_E18

IO_L19P_2_F18

IO_L20N_2_E19

IO_L20P_2_E20

IO_L21N_2_E21

IO_L21P_2_E22

IO_L22N_2_G17

IO_L22P_2_G18

IO_L23N_2_VREF_2_F19

IO_L23P_2_G19

IO_L24N_2_F20

IO_L24P_2_F21

IO_L26N_2_G20

IO_L26P_2_H19

IO_L27N_2_G21

IO_L27P_2_G22

IO_L28N_2_H18

IO_L28P_2_J17

IO_L29N_2_H21

IO_L29P_2_H22

IO_L31N_2_J18

IO_L31P_2_J19

IO_L32N_2_J21

IO_L32P_2_J22

IO_L33N_2_K17

IO_L33P_2_K18

IO_L34N_2_VREF_2_K19

IO_L34P_2_K20

IO_L35N_2_K21

IO_L35P_2_K22

IO_L38N_2_L17

IO_L38P_2_L18

IO_L39N_2_L19

IO_L39P_2_L20

IO_L40N_2_L21

IO_L40P_2_VREF_2_L22

IO_L01N_2_VRP_2_C20

IO_L01P_2_VRN_2_C21

VCCO_3_M16

VCCO_3_N16

VCCO_3_P16

VCCO_3_R17

VCCO_3_R20

IO_L16N_3_W22

IO_L16P_3_Y22

IO_L17N_3_V19

IO_L17P_3_VREF_3_W19

IO_L19N_3_W21

IO_L19P_3_W20

IO_L20N_3_U19

IO_L20P_3_V20

IO_L21N_3_V22

IO_L21P_3_V21

IO_L22N_3_T17

IO_L22P_3_U18

IO_L23N_3_U21

IO_L23P_3_VREF_3_U20

IO_L24N_3_R18

IO_L24P_3_T18

IO_L26N_3_T20

IO_L26P_3_T19

IO_L27N_3_T22

IO_L27P_3_T21

IO_L28N_3_R22

IO_L28P_3_R21

IO_L29N_3_P19

IO_L29P_3_R19

IO_L31N_3_P18

IO_L31P_3_P17

IO_L32N_3_P22

IO_L32P_3_P21

IO_L33N_3_N18

IO_L33P_3_N17

IO_L34N_3_N20

IO_L34P_3_VREF_3_N19

IO_L35N_3_N22

IO_L35P_3_N21

IO_L38N_3_M18

IO_L38P_3_M17

IO_L39N_3_M20

IO_L39P_3_M19

IO_L40N_3_VREF_3_M22

IO_L40P_3_M21

IO_L01N_3_VRP_3_Y20

IO_L01P_3_VRN_3_Y19

IO_Y21

FPGAFPGA

LAYOUT NOTE PLACE NEAR FPGA

9-27-2005_1144 7 12

H17

H20

J16

K16

L16

C22

D20

D19

D21

D22

E18

F18

E19

E20

E21

E22

G17

G18

F19

G19

F20

F21

G20

H19

G21

G22

H18

J17

H21

H22

J18

J19

J21

J22

K17

K18

K19

K20

K21

K22

L17

L18

L19

L20

L21

L22

C20

C21

M16

N16

P16

R17

R20

W22

Y22

V19

W19

W21

W20

U19

V20

V22

V21

T17

U18

U21

U20

R18

T18

T20

T19

T22

T21

R22

R21

P19

R19

P18

P17

P22

P21

N18

N17

N20

N19

N22

N21

M18

M17

M20

M19

M22

M21

Y20

Y19

Y21

U1

FG456XC3S1000

2

4

8

10

6

12

14

16

24

22

20

18

26

28

3

5

7

9

11

13

15

17

19

21

23

25

27

1P5

IDC14X214X2

1

27

25

23

21

19

17

15

13

11

9

7

5

3

28

26

18

20

22

24

16

14

12

6

10

8

4

2P7

IDC14X214X2

VCCO_2

B2_L26P_H19_J2_42

DNP0603

R55B2_L24P_F21_J2_46

R56

0603DNP

B2_L23P_G19_J2_48

B2_L26N_G20_J2_41

B2_L24N_F20_J2_45

B2_L23N_F19_J2_47 B2_L23P_G19_J2_48

B2_L24P_F21_J2_46

B2_L26P_H19_J2_42

R32

0603DNP

TMR0

VCCO_2

PF221

2X1IDC2X1

JP3

CONFIG_PROG_B

1 2JP2

IDC2X12X1

PF3

CONFIG_INIT_B_TFS1

CONFIG_CLK_TSCLK1

RSCLK1

RFS1

IO_L01N_2_VRP_2_C20

IO_L01P_2_VRN_2_C21_J2_16

B2_L22N_G17_J2_43

B2_L22P_G18_J2_44

B2_L32N_J21_J2_31

SPIDS0

PF0

SCK

NMI

TMR1

DR1SEC

TMR3

DR0PRI

DR1PRI

RFS0

DR0SEC

PF15

PF13

RSCLK0

PF7

PF9

PF6

PF11

PF1

PF3

PF5

MOSI

MISO

UDEF12

TMR2

DT1SEC

DT1PRI

DT0SEC

TSCLK0

PF14

PF12

PF10

PF8

PF4

PF2

FPGA BANKS 2 + 3

DT0PRI

TFS0

B2_L40P_L22_J2_10

B2_L40N_L21_J2_9

B2_L39P_L20_J2_12

B2_L39N_L19_J2_11

B2_L38P_L18_J2_24

B2_L38N_L17_J2_23

B2_L35P_K22_J2_26

B2_L35N_K21_J2_25

B2_L34P_K20_J2_28

B2_L34N_K19_J2_27

B2_L33P_K18_J2_30

B2_L33N_K17_J2_29

B2_L32P_J22_J2_32

B2_L31P_J19_J2_34

B2_L31N_J18_J2_33

B2_L29P_H22_J2_36

B2_L29N_H21_J2_35

B2_L28P_J17_J2_38

B2_L28N_H18_J2_37

B2_L27P_G22_J2_40

B2_L27N_G21_J2_39

B2_L26P_H19_J2_42

B2_L26N_G20_J2_41

B2_L24P_F21_J2_46

B2_L24N_F20_J2_45

B2_L23P_G19_J2_48

B2_L23N_F19_J2_47

B2_L21P_E22_J2_50

B2_L21N_E21_J2_49

B2_L20P_E20_J2_52

B2_L20N_E19_J2_51

B2_L19P_F18_J2_54

B2_L19N_E18_J2_53

B2_L17P_D22_J2_56

B2_L17N_D21_J2_55

B2_L16P_D19_J2_58

B2_L16N_D20_J2_57

B2_C22_J2_17

3

2

1

3X1IDC3X1

P10

IO_L01P_2_VRN_2_C21_J2_16

IO_L01N_2_VRP_2_C20

VCCO_2

CONFIG_DONE

B2_L22N_G17_J2_43

B2_L17N_D21_J2_55

B2_L19N_E18_J2_53

B2_L20N_E19_J2_51

B2_L21N_E21_J2_49

B2_L16N_D20_J2_57

IO_L01N_2_VRP_2_C20

B2_L16P_D19_J2_58

B2_L20P_E20_J2_52

B2_L19P_F18_J2_54

B2_L17P_D22_J2_56

B2_L22P_G18_J2_44

B2_L21P_E22_J2_50

B2_C22_J2_17

IO_L01P_2_VRN_2_C21_J2_16

B2_L40N_L21_J2_9

B2_L39N_L19_J2_11

B2_L38N_L17_J2_23

B2_L35N_K21_J2_25

B2_L34N_K19_J2_27

B2_L33N_K17_J2_29

B2_L32N_J21_J2_31

B2_L31N_J18_J2_33

B2_L29N_H21_J2_35

B2_L28N_H18_J2_37

B2_L27N_G21_J2_39

B2_L40P_L22_J2_10

B2_L34P_K20_J2_28

B2_L35P_K22_J2_26

B2_L38P_L18_J2_24

B2_L39P_L20_J2_12

B2_L33P_K18_J2_30

B2_L32P_J22_J2_32

B2_L28P_J17_J2_38

B2_L31P_J19_J2_34

B2_L29P_H22_J2_36

B2_L27P_G22_J2_40

DNP0603

R33

B2_L23N_F19_J2_47

B2_L24N_F20_J2_45

B2_L26N_G20_J2_41

DNP0603

R57

001UF0603

C60 C59

0603001UF 001UF

0603

C58 C57

0603001UF

C82

0603001UF 001UF

0603

C81 C62

0603001UF001UF

0603

C61

VCCO_2

4

3

2

1

A B C D

20 Cotton Road

Nashua NH 03063

A B C D

4

3

2

1

PH 1-800-ANALOGD

C

Title

Size Board No

Date Sheet of

DEVICESANALOG

DNP = Do Not Populate

Rev

BLACKFIN FPGA EZ-EXTENDER

A0199-2005 10

Expanison ConnectorExpanison Connector

Bottom Of Board Top Of BoardExpansion Connector 3

EXPANSION INTERFACE (TYPE B)

P3P3

9-9-2005_1029 128

EXPANSION INTERFACE CONNECTOR 1

33V_EI5V_EI

1

10

11 12

13 14

15 16

17 18

19

2

20

21 22

23 24

25 26

27 28

29

3

30

31 32

33 34

35 36

37 38

39

4

40

41 42

43 44

45 46

47 48

49

5

50

51 52

53 54

55 56

57 58

59

6

60

61 62

63 64

65 66

67 68

69

7

70

71 72

73 74

75 76

77 78

79

8

80

81 82

83 84

85 86

87 88

89

9

90

P3

CON01845X2

1

10

1112

1314

1516

1718

19

2

20

2122

2324

2526

2728

29

3

30

3132

3334

3536

3738

39

4

40

4142

4344

4546

4748

49

5

50

5152

5354

5556

5758

59

6

60

6162

6364

6566

6768

69

7

70

7172

7374

7576

7778

79

8

80

8182

8384

8586

8788

89

9

90

J3

CON01945X2

TX0

TX1

UDEF17

UDEF19

UDEF21

UDEF23

UDEF25

UDEF29

UDEF27

RESET

UDEF32

UDEF34

UDEF36

UDEF38

UDEF40

B5_L01N_RDWR_B_Y4_J3_1

P3_42

P3_[190]

P3_86

P3_84

P3_82

P3_80

P3_78

P3_76

P3_74

P3_72

P3_70

P3_68

P3_64

P3_62

P3_60

P3_58

P3_56

P3_54

P3_52

P3_50

P3_48

P3_46

P3_42

P3_79

P3_89

P3_77

P3_75

P3_73

P3_71

P3_69

P3_67

P3_63

P3_61

P3_59

P3_57

P3_55

P3_53

P3_51

P3_49

P3_47

P3_45

P3_51

P3_79

P3_89

P3_77

P3_75

P3_73

P3_71

P3_69

P3_67

P3_63

P3_61

P3_59

P3_57

P3_55

P3_53

P3_49

P3_47

P3_45

P3_86

P3_84

P3_82

P3_80

P3_78

P3_76

P3_74

P3_72

P3_70

P3_68

P3_64

P3_62

P3_60

P3_58

P3_56

P3_54

P3_52

P3_50

P3_48

P3_46

B5_L27N_W9_J3_31

B5_L28N_D6_AB9_J3_33

B5_L29N_Y10_J3_35

B5_L30N_AB10_J3_37

B5_L31N_D4_W11_J3_39

B5_L10N_VRP_AB5_J3_9

B5_L25N_AB8_J3_21

B5_L24N_W8_J3_19

B5_L22N_AB7_J3_17

B5_L19N_Y7_J3_15

B5_L16N_AA6_J3_13

B5_L15N_W6_J3_11

B5_L09N_Y5_J3_7

B5_L06N_AB4_J3_5

B5_U6_J3_23

B5_V7_J3_29

B5_U9_J3_41

B5_L31P_D5_V11_J3_40

B5_L30P_AA10_J3_38

B5_L29P_W10_J3_36

B5_L28P_D7_AA9_J3_34

B5_L27P_V9_J3_32

B5_L32N_GCLK3_AA11_J3_30

B5_U7_J3_28

B5_L25P_AA8_J3_22

B5_L24P_V8_J3_20

B5_L22P_AA7_J3_18

B5_L19P_W7_J3_16

B5_L16P_Y6_J3_14

B5_L15P_V6_J3_12

B5_L10P_VRN_AA5_J3_10

B5_L09P_W5_J3_8

B5_L06P_AA4_J3_6

B5_L01P_CS_B_AA3_J3_2

B5_AB11_J3_90

B5_U11_J3_83

B5_V10_J3_85

B5_U10_J3_81

UDEF43

BGH

BG

BR

UDEF30

UDEF28

UDEF26

UDEF24

UDEF22

UDEF20

UDEF18

UDEF16

RX1

RX0

UDEF14 UDEF15

CLK_OUT_EXP1

UDEF31

UDEF33

UDEF35

UDEF37

UDEF39

UDEF41

33V_EI

C84

060301UF

80510UFC83

C8610UF805

01UF0603

C85

5V_EI

33V

33V

25V 33V

33V

33V

33V

4

3

2

1

A B C D

20 Cotton Road

Nashua NH 03063

A B C D

4

3

2

1

PH 1-800-ANALOGD

C

Title

Size Board No

Date Sheet of

DEVICESANALOG

DNP = Do Not Populate

Rev

BLACKFIN FPGA EZ-EXTENDER

A0199-2005 10

VCCO_4_T12

VCCO_4_T13

VCCO_4_T14

VCCO_4_U15

VCCO_4_Y15

IO_U16

IO_U17

IO_W13

IO_W14

IO_VREF_4_V18

IO_VREF_4_Y16

IO_VREF_4_AB13

IO_L05N_4_AA19

IO_L05P_4_AB19

IO_L06N_4_VREF_4_W18

IO_L06P_4_Y18

IO_L09N_4_AA18

IO_L09P_4_AB18

IO_L10N_4_V17

IO_L10P_4_W17

IO_L15N_4_Y17

IO_L15P_4_AA17

IO_L16N_4_V16

IO_L16P_4_W16

IO_L19N_4_AA16

IO_L19P_4_AB16

IO_L22N_4_VREF_4_V15

IO_L22P_4_W15

IO_L24N_4_AA15

IO_L24P_4_AB15

IO_L25N_4_U14

IO_L25P_4_V14

IO_L27N_4_DIN_D0_AA14

IO_L27P_4_D1_AB14

IO_L28N_4_U13

IO_L28P_4_V13

IO_L29N_4_Y13

IO_L29P_4_AA13

IO_L30N_4_D2_U12

IO_L30P_4_D3_V12

IO_L31N_4_INIT_B_W12

IO_L31P_4_DOUT_BUSY_Y12

IO_L01N_4_VRP_4_AA20

IO_L01P_4_VRN_4_AB20

IO_L32N_4_GCLK1_AA12

IO_L32P_4_GCLK0_AB12

VCCO_5_T9

VCCO_5_T10

VCCO_5_T11

VCCO_5_U8

VCCO_5_Y8

IO_U7

IO_U9

IO_U10

IO_U11

IO_V7

IO_V10

IO_VREF_5_U6

IO_VREF_5_AB11

IO_L01N_5_RDWR_B_Y4

IO_L01P_5_CS_B_AA3

IO_L06N_5_AB4

IO_L06P_5_AA4

IO_L09N_5_Y5

IO_L09P_5_W5

IO_L15N_5_W6

IO_L15P_5_V6

IO_L16N_5_AA6

IO_L16P_5_Y6

IO_L19N_5_Y7

IO_L19P_5_VREF_5_W7

IO_L22N_5_AB7

IO_L22P_5_AA7

IO_L24N_5_W8

IO_L24P_5_V8

IO_L25N_5_AB8

IO_L25P_5_AA8

IO_L27N_5_VREF_5_W9

IO_L27P_5_V9

IO_L28N_5_D6_AB9

IO_L28P_5_D7_AA9

IO_L29N_5_Y10

IO_L29P_5_VREF_5_W10

IO_L30N_5_AB10

IO_L30P_5_AA10

IO_L31N_5_D4_W11

IO_L31P_5_D5_V11

IO_L32N_5_GCLK3_AA11

IO_L32P_5_GCLK2_Y11

IO_L10N_5_VRP_5_AB5

IO_L10P_5_VRN_5_AA5

FPGAFPGA

1299-27-2005_1144

T12

T13

T14

U15

Y15

U16

U17

W13

W14

V18

Y16

AB13

AA19

AB19

W18

Y18

AA18

AB18

V17

W17

Y17

AA17

V16

W16

AA16

AB16

V15

W15

AA15

AB15

U14

V14

AA14

AB14

U13

V13

Y13

AA13

U12

V12

W12

Y12

AA20

AB20

AA12

AB12

T9

T10

T11

U8

Y8

U7

U9

U10

U11

V7

V10

U6

AB11

Y4

AA3

AB4

AA4

Y5

W5

W6

V6

AA6

Y6

Y7

W7

AB7

AA7

W8

V8

AB8

AA8

W9

V9

AB9

AA9

Y10

W10

AB10

AA10

W11

V11

AA11

Y11

AB5

AA5

U1

FG456XC3S1000

7

2

4

8

10

6

3

9

11

13

15

17

19

21

23

25

12

14

16

24

26

22

20

18

1

5

P16

IDC13X213X2

5

1

18

20

22

26

24

16

14

12

25

23

21

19

17

15

13

11

9

3

6

10

8

4

2

7

P17

IDC13X213X2

R46

060310K

R43

0603DNP

FPGA BANKS 4 + 5

VCCO_5

CONFIG_INIT_B_TFS1

CLK_OUT_EXP1

B4_L32N_GCKL1_AA12

R9

06030

B5_L10N_VRP_AB5_J3_9

B5_L10N_VRP_AB5_J3_9

B5_L10P_VRN_AA5_J3_10

VCCO_5

B5_L32P_GCLK2_Y1

B5_L32N_GCLK3_AA11_J3_30

CONFIG_DIN_DT1PRI

UDEF16

UDEF38

UDEF14

RX0

TX0

RX1

TX1

UDEF20

UDEF21

UDEF23

UDEF17

UDEF25

UDEF24

UDEF22

RESET

UDEF30

UDEF29

UDEF27

UDEF26

UDEF35

UDEF34

UDEF33

UDEF32

UDEF31

UDEF15

UDEF28

UDEF41

UDEF40

UDEF39

UDEF37

UDEF36

BR

UDEF43

BG

BGH

UDEF19

B5_L31P_D5_V11_J3_40

B5_L31N_D4_W11_J3_39

B5_L30P_AA10_J3_38

B5_L30N_AB10_J3_37

B5_L29P_W10_J3_36

B5_L29N_Y10_J3_35

B5_L28P_D7_AA9_J3_34

B5_L28N_D6_AB9_J3_33

B5_L27P_V9_J3_32

B5_L27N_W9_J3_31

B5_L25P_AA8_J3_22

B5_L25N_AB8_J3_21

B5_L24P_V8_J3_20

B5_L24N_W8_J3_19

B5_L22P_AA7_J3_18

B5_L22N_AB7_J3_17

B5_L19P_W7_J3_16

B5_L19N_Y7_J3_15

B5_L16P_Y6_J3_14

B5_L16N_AA6_J3_13

B5_L15P_V6_J3_12

B5_L15N_W6_J3_11

B5_L09P_W5_J3_8

B5_L09N_Y5_J3_7

B5_L06P_AA4_J3_6

B5_L06N_AB4_J3_5

B5_L01P_CS_B_AA3_J3_2

B5_L01N_RDWR_B_Y4_J3_1

B5_AB11_J3_90

B5_U6_J3_23

B5_V10_J3_85

B5_V7_J3_29

B5_U11_J3_83

B5_U10_J3_81

B5_U9_J3_41

B5_U7_J3_28

UDEF18

3

2

1

3X1IDC3X1

P11

B5_L29N_Y10_J3_35

B5_L30N_AB10_J3_37

B5_L31N_D4_W11_J3_39

B5_U11_J3_83

B5_V10_J3_85B5_AB11_J3_90

B5_U10_J3_81

B5_L31P_D5_V11_J3_40

B5_L30P_AA10_J3_38

B5_L29P_W10_J3_36

B5_L28P_D7_AA9_J3_34

B5_L27P_V9_J3_32

B5_L28N_D6_AB9_J3_33

B5_L27N_W9_J3_31

B5_L25N_AB8_J3_21B5_L25P_AA8_J3_22

B5_L24N_W8_J3_19B5_L24P_V8_J3_20

B5_U9_J3_41B5_U6_J3_23

VCCO_5

B5_L10P_VRN_AA5_J3_10

C70

0603001UF 001UF

0603

C69 C68

0603001UF001UF

0603

C67001UF0603

C66 C65

0603001UF 001UF

0603

C64C63

0603001UF

B5_L09N_Y5_J3_7

B5_U7_J3_28 B5_V7_J3_29

B5_L10P_VRN_AA5_J3_10 B5_L10N_VRP_AB5_J3_9

B5_L15P_V6_J3_12 B5_L15N_W6_J3_11

B5_L16P_Y6_J3_14 B5_L16N_AA6_J3_13

B5_L19P_W7_J3_16 B5_L19N_Y7_J3_15

B5_L22P_AA7_J3_18 B5_L22N_AB7_J3_17

B5_L32N_GCLK3_AA11_J3_30 B5_L32P_GCLK2_Y1

B5_L01P_CS_B_AA3_J3_2 B5_L01N_RDWR_B_Y4_J3_1

B5_L06P_AA4_J3_6 B5_L06N_AB4_J3_5

B5_L09P_W5_J3_8

VCCO_5

DNP0603

R45

25V

33V

33V

4

3

2

1

A B C D

20 Cotton Road

Nashua NH 03063

A B C D

4

3

2

1

PH 1-800-ANALOGD

C

Title

Size Board No

Date Sheet of

DEVICESANALOG

DNP = Do Not Populate

Rev

BLACKFIN FPGA EZ-EXTENDER

A0199-2005 10

SN74LVC1G125

12109-27-2005_1144

2 4

1

SOT23-5SN74LVC1G125

U8

USER IO

C80

0603001UF

SW4SWT013SPST-MOMENTARY

SPST-MOMENTARYSWT013SW3

060310R42

C5

06031UF

R413300603

LED001AMBER-SMTLED8

0603330R40

LED7AMBER-SMTLED001

R393300603

R1033006030603

330R34R35

33006030603

330R36

0603330R37 R38

3300603

LED001AMBER-SMTLED2

AMBER-SMTLED001

LED3AMBER-SMTLED001

LED4AMBER-SMTLED001

LED5

LED001AMBER-SMTLED6

LED9GREEN-SMTLED001

402100R23

1 2

3 4

5 6

7 8

JP5

IDC4X24X2

AMBER-SMTLED001

LED1

B6_L01N_Y3

B6_L01P_Y2

B5_U10_J3_81

B5_AB11_J3_90

PB2

B5_V10_J3_85

B5_U11_J3_83

B5_L31N_D4_W11_J3_39

B5_L30N_AB10_J3_37

B5_L29N_Y10_J3_35

B5_L28N_D6_AB9_J3_33

B5_L27N_W9_J3_31

PB1

B5_L25N_AB8_J3_21

R47

060310K

CHOKE_COIL

4

3

2

1

A B C D

20 Cotton Road

Nashua NH 03063

A B C D

4

3

2

1

PH 1-800-ANALOGD

C

Title

Size Board No

Date Sheet of

DEVICESANALOG

DNP = Do Not Populate

Rev

BLACKFIN FPGA EZ-EXTENDER

A0199-2005 10

25V

33V

VIN

EN

SW

GND

FB

VIN

EN

SW

GND

FB

VIN

EN

SW

GND

FB

4

3

5

2

1

VR3

SOT23-5LM3475MF

1

2

5

3

4

VR2

SOT23-5LM3475MF

4

3

5

2

1

VR1

SOT23-5LM3475MF

12119-27-2005_1124

1

32

Q2

SI2

343D

SS

OT

23D

1

32

Q3

SI2

343D

SS

OT

23D

2 3

1S

I234

3DS

Q1

SO

T23

D

316KR17

0603

215KR18

0603

0603

R11105K

DNPC73

0603

0603

C72DNP

805

C741000PF

0R58

0603

1000PFC10

805

0603

R1910K

C100UFCT2

CT3100UFC

IND005

L110UH

10UHL3

IND005

10UHL2

IND005

1

2 D3

DO214ABSCHOT_RECT

3A

0603

R20200K

805

C639NF

390PFC7

0603

2

1 3A

SCHOT_RECTDO214AB

D2

499KR13

0603

1

2 D1

DO214ABSCHOT_RECT

3A

33V_EI

3

1

2

3X1IDC3X1

P13

UNREG_IN

12V

CT1100UFC

80510UFC71

R1200603

5V_EI

8051000PFC2

FER2

0603

060301UFC3

POWER

FUS00125AF1

4

1

3

2

FER1

DO-214AA

S2A_RECT

2AD5

8051000PFC1 C4

10UFC

3

1

2

3X1IDC3X1

P12

UNREG_IN

1

2

3

CON00525MM_JACK

POWER

J4

2

1P42

IDC2X12X1DNP

1

2

DNP2X1IDC2X1

P43

06030R15

C810UF805

80510UFC9

R1600603

UNREG_IN

0603

R1410K

0603

R590

4

3

2

1

A B C D

20 Cotton Road

Nashua NH 03063

A B C D

4

3

2

1

PH 1-800-ANALOGD

C

Title

Size Board No

Date Sheet of

DEVICESANALOG

DNP = Do Not Populate

Rev

BLACKFIN FPGA EZ-EXTENDER

A0199-2005 1012129-14-2005_1204

5

2

4

8

10

6

1

3

9

11

13

15

17

19

12

14

16

20

18

7

P20

SOIC20

PROTO AREA

1

3

2

SOT23D

P39

2

3

1

SOT23D

P38

2

4

5 6

3

1

SOT23-6

P411

3

65

4

2

SOT23-6

P40

PRT_NUM=DNE

11

13

15 16

14

12

2

4

6

8

109

7

5

3

1

SOIC16

P191

3

5

7

9 10

8

6

4

2

12

14

1615

13

11

SOIC16

P18

21P37

805

1 2

805

P36

21P35

805

1 2

805

P34

1 2

805

P33

21P32

805

1 2

805

P31

21P30

805

1 2

805

P29

21P28

805

1 2

805

P27

21P26

805

21P25

805

1 2

805

P24

21P23

805

1 2

805

P22

TP86

TP85

TP84

TP83

TP82

TP81

TP80

TP79 TP77

TP76

TP75

TP74

TP73

TP72

TP71

TP70

TP68

TP67

TP66

TP65

TP64

TP62

TP61

TP60

TP59

TP58

TP57

TP56

TP55

TP54

TP53

TP51

TP50

TP49

TP48

TP47

TP46

TP45

TP44

TP43

TP41

TP40

TP39

TP38

TP37

TP36

TP35

TP34

TP33

TP32

TP30

TP29

TP28

TP27

TP26

TP25

TP24

TP23

TP22

TP21

TP19

TP18

TP17

TP16

TP15

TP14

TP13

TP12

TP11

TP9

TP8

TP7

TP6

TP5

TP4

TP125

TP124

TP123

TP122

TP121

TP120

TP119

TP118

TP117

TP116

TP114

TP113

TP112

TP111

TP110

TP109

TP108

TP107TP106

TP105TP103

TP102TP101 TP100TP99

TP98 TP97

TP96 TP95

TP94TP93

TP92TP91

TP90 TP89

TP88 TP87

TP78TP69

TP63 TP52

TP42 TP31

TP20 TP10

TP115TP104

7

18

20

16

14

12

19

17

15

13

11

9

3

1

6

10

8

4

2

5

SOIC20

P21

I INDEX

Numerics connectors

25V header (P42) 2-17

AADSP-BF5333761 EZ-KIT Lite interface 2-1ADSP-BF5333761 processors boot mode

settings 2-14architecture of this EZ-Extender 2-2asynchronous static random access memory

(SRAM) xauxiliary oscillator x

Bbill of materials A-1block diagram of this EZ-Extender 2-2boot jumper See JP4

Cconfiguration jumpers See JP2 JP3

map of locations 2-18J1-3 (expansion) 2-19P1-3 (expansion) 2-19P14 (IDC) 2-19P15 (JTAG header) 2-4P16-17 (IDC) 2-19P4 (high-speed) 2-20P5 (IDC) 2-20P6 (JTAG) 2-7P7 (IDC) 2-20P8 (IDC) 2-19

customer support xiii

Ddone LED (LED10) 2-17

Eexpansion interface

connectors (P1-3 J1-3) 2-19of ADSP-BF5333761 EZ-KIT Lites ix

1-3external power supply 1-3 2-8

FField-Programmable Gate Array See FPGA

Blackfin FPGA EZ-Extender Manual I-1

INDEX

FPGAdocumentation 1-2input jumpers (JP5) 2-14softwarefirmware 1-2Xilinx Spartan package x 1-3

FPGA pinsAB10 (LED3) 2-17AB11 (JP58) 2-15AB8 (LED7) 2-17AB9 (LED5) 2-17C11 (PB1SW3) 2-15H5 (PB2SW3) 2-16M2-0 (JP4) 2-14U10 (JP56) 2-15U11 (LED1) 2-17V10 (LED8) 2-17W11 (LED2) 2-17W9 (LED6) 2-17Y10 (LED4) 2-17Y3-2 (JP52-54) 2-15

FPGA programmingblock diagram 2-3via ADSP-BF533376 processors 2-6via JTAG header 2-4via serial ROM 2-5

GGCLK1 (global clock 1) pin 1-4GCLK6 (global clock 6) pin 1-4general-purpose input push buttons 2-15 2-16

Hhigh-speed connector (P4) 2-20

IIDC connectors x 2-19 2-20installation of this EZ-Extender 1-1

JJTAG

cable 1-4 2-7header (P6) 1-5 2-4 2-7 2-14

jumpersmap of locations 2-11JP1 (boot jumper) 2-5 2-12JP2 (confug done) 2-12JP3 (config program) 2-13JP41-46 (boot mode select) 2-5 2-6 2-14JP52-56 (FPGA input) 2-14

LLEDs

map of locations 2-15LED10 (FPGA done pin) 2-4 2-5 2-17LED1-8 (status) 2-17LED9 (power) 2-17

MM2-0 (JP4) pins 2-5master serial boot mode 2-6MCS-86 Hexadecimal Object (mcs) file

format 2-6

Nnotation conventions xvi

Ooscillator x 1-4

PP12 (power in) header 2-9P13 (33V header) 2-9P42 (25V header) 2-10P43 (12V header) 2-10PB1 push button (SW3) 2-15

I-2 Blackfin FPGA EZ-Extender Manual

INDEX

PB2 push button (SW4) 2-16PF14 flag pin (ADSP-BF537 EZ-KIT Lite)

2-12PF3 flag pin (ADSP-BF53361 EZ-KIT Lite)

2-12power

12V header (P43) 2-1025V header (P42) 2-1033V header (P13) 2-9in header (P12) 2-9LED (LED9) 2-17limitations 2-8supplies 1-3 2-8

printed circuit board (PCB) 1-2product overview ixprogram push button (SW1) 2-4 2-15push buttons

See also SWx map of locations 2-15

Sserial ROM 1-5

boot jumper (JP1) 2-12 2-14programming via JTAG Header 2-7

setup of this EZ-Extender 1-1slave serial mode 2-6

SRAM memory banks 1-4status reporting 1-4 2-17SW1 (program) push button 2-4 2-15SW3 (PB1) push button 2-15SW4 (PB2) push button 2-16switching regulators 2-8

TTCK signal 2-7TDI signal 2-7TDO signal 2-7TMS signal 2-7

VVisualDSP++

flash programming utility 1-4 2-6FPGA documentation 2-6

VR1-3 regulators 2-8

XXilinx

JTAG cablesoftware 1-4 2-4 2-7JTAG header 2-12serial ROM 1-5

Blackfin FPGA EZ-Extender Manual I-3

INDEX

I-4 Blackfin FPGA EZ-Extender Manual

• Blackfin FPGA EZ-Extender Manual
• Contents
• Preface
• • Product Overview
  • Purpose of This Manual
  • Intended Audience
  • Manual Contents
  • Whatrsquos New in This Manual
  • Technical or Customer Support
  • Supported Products
  • Product Information
  • • Related Documents
    • • Table 1 Related Processor Publications
      • Table 2 Related VisualDSP++ Publications
      • • Notation Conventions
        • • 1 FPGA EZ-Extender Interfaces
          • • FPGA EZ-Extender Setup
            • • Figure 1-1 FPGA EZ-Extender Setup
              • • FPGA Software and Firmware
                • FPGA EZ-Extender Overview
                • • 2 FPGA EZ-Extender Hardware Reference
                  • • System Architecture
                    • • Figure 2-1 Block Diagram
                      • • Programming the FPGA
                        • • Figure 2-2 FPGA Programming Block Diagram
                          • FPGA Programming via JTAG
                          • • Table 2-1 P15 Connections for PFGA Programming via JTAG
                            • Table 2-2 JP1 Settings for FPGA Programming via JTAG
                            • Table 2-3 JP4 Settings for FPGA Programming via JTAG
                            • • FPGA Programming via Serial ROM
                              • • Table 2-4 JP1 Settings for FPGA Programming via Serial ROM
                                • Table 2-5 JP4 Settings for FPGA Programming in Master Serial Mode
                                • • FPGA Programming via Blackfin Application
                                  • • Table 2-6 JP1 Settings for FPGA Programming via Blackfin Processor
                                    • Table 2-7 JP4 Settings for FPGA Programming via Blackfin Processor
                                    • • Programming the Serial ROM
                                      • • Serial ROM via JTAG Header
                                        • • Table 2-8 P6 Connections for Serial ROM
                                          • • Power
                                            • • Table 2-9 Power Limitations
                                              • Power In Header (P12)
                                              • 33V Header (P13)
                                              • 25V Header (P42)
                                              • 12V Header (P43)
                                              • • Jumpers
                                                • • Figure 2-3 Jumper Locations
                                                  • Serial ROM Boot Jumper (JP1)
                                                  • • Table 2-10 JP1 Settings
                                                    • • Config Done Jumper (JP2)
                                                      • • Table 2-11 JP2 Settings
                                                        • • Config Program Jumper (JP3)
                                                          • • Table 2-12 JP3 Settings
                                                            • • Boot Jumper (JP4)
                                                              • • Table 2-13 JP4 Settings
                                                                • • FPGA Input Jumpers (JP5)
                                                                  • • Table 2-14 JP5 Settings
                                                                    • • Push Buttons and LEDs
                                                                      • • Figure 2-4 Push Button and LED Locations
                                                                        • Program Push Button (SW1)
                                                                        • PB1 Push Button (SW3)
                                                                        • PB2 Push Button (SW4)
                                                                        • Status LEDs (LED1-8)
                                                                        • • Table 2-15 Status LED (LED1-8) Settings
                                                                          • • Power LED (LED9)
                                                                            • Done LED (LED10)
                                                                            • • Connectors
                                                                              • • Figure 2-5 Connector Locations
                                                                                • Expansion Interface (P1-3 and J1-3)
                                                                                • IDC Connectors (P8 P14 P16 and P17)
                                                                                • IDC Connectors (P5 and P7)
                                                                                • High-Speed Connector (P4)
                                                                                • • A Bill Of Materials
                                                                                  • B Schematics
                                                                                  • • Title
                                                                                    • FPGA Config
                                                                                    • SRAM FPGA Banks 7 and 8
                                                                                    • Expansion Interface Connector 1
                                                                                    • FPGA Banks 0 and 1
                                                                                    • Expansion Interface Connectors 2
                                                                                    • FPGA Banks 2 and 3
                                                                                    • Expansion Interface Connector 1
                                                                                    • FPGA Banks 4 and 5
                                                                                    • User IO
                                                                                    • Power
                                                                                    • Proto Area
                                                                                    • • I Index
                                                                                      • • Numerics
                                                                                        • A
                                                                                        • B
                                                                                        • C
                                                                                        • D
                                                                                        • E
                                                                                        • F
                                                                                        • G
                                                                                        • H
                                                                                        • I
                                                                                        • J
                                                                                        • L
                                                                                        • M
                                                                                        • N
                                                                                        • O
                                                                                        • P
                                                                                        • S
                                                                                        • T
                                                                                        • V
                                                                                        • X

Bill Of Materials

113

SPST

-MO

ME

NT

AR

Y

SWT

013

6M

M

SW1

SW3-

4PA

NA

SON

ICE

VQ

-PA

D04

M

123

005

45x

2 C

ON

018

HE

AD

ER

P

1-3

SAM

TE

CT

FC-1

45-3

2-F-

D

133

005

45X

2 C

ON

019

SM

T S

OC

KE

TJ1

-3SA

MT

EC

SFC

-145

-T2-

F-D

-A

142

IDC

14X

2 ID

C14

X2

HE

AD

ER

P5

P7

FCI

6873

7-42

8HL

F

152

IDC

6X

1 ID

C6X

1H

EA

DE

R

P6

P15

FCI

9072

6-40

6HL

F

161

QT

S 25

X2

CO

N04

1SM

T

P4

SAM

TE

CQ

TS-

025-

01-F

-D-A

179

AM

BE

R-S

MT

LE

D00

1G

UL

L-W

ING

LE

D1-

8L

ED

10PA

NA

SON

ICL

N14

61C

-TR

181

10uF

16V

10

CT

AN

TC

4A

VX

TA

JC10

6K02

5R

193

3A H

SM35

0J D

O21

4AB

SC

HO

T_R

EC

TD

1-3

MIC

RO

-SE

MI

HSM

350J

201

600

100M

HZ

200

MA

060

30

50 B

EA

DFE

R2

MU

RA

TA

BL

M11

A60

1SP

T

Ref

Des

crip

tion

Ref

eren

ce D

esig

nato

r M

anuf

actu

rer

Part

Num

ber

Blackfin FPGA EZ-Extender Manual A-3

211

2A S

2A_R

EC

T D

O-2

14A

A

SIL

ICO

N R

EC

TIF

IER

D5

VIS

HA

YS2

A

221

39N

F 50

V 5

8

05C

6PA

NA

SON

ICE

CH

-U1C

392J

B5

231

190

100M

HZ

5A

FE

R00

2 FE

R1

MU

RA

TA

DLW

5BSN

191S

Q2

247

10U

F 6

3V 1

0 8

05X

7R

C14

-16

C35

C55

C83

C

86AV

X08

0560

106K

AT

2A

254

1000

PF

10V

20

805

C

1-2

C10

C74

YA

GE

O12

06C

G22

9C9B

200

263

100U

F 10

V 1

0 C

TA

NT

-LO

W-E

SRC

T1-

3A

VX

TP

SC10

7K01

0R00

75

275

01U

F 16

V 1

0 0

603

X7R

C3

C38

C56

C84

-85

AVX

0603

YC

104K

AT

2A

2856

001

UF

16V

10

060

3

X7R

C11

-13

C17

-34

C36

-37

C39

-54

C57

-70

C80

-82

AVX

0603

YC

103K

AT

2A

291

1UF

16V

10

060

3C

5PA

NA

SON

ICE

CJ-

1VB

1C10

5K

303

10U

H 1

7 20

I

ND

005

L1-

3C

OIL

CR

AFT

MSS

1278

-103

MX

B

318

10K

11

0W 5

0

603

R1

R6

R21

-22

R28

-29

R46

-47

PAN

ASO

NIC

ER

J-3G

EY

J103

V

3210

330

110

W 5

0

603

R10

R24

R34

-41

VIS

HA

YC

RC

W06

0333

1JR

T1

Ref

Des

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tion

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Part

Num

ber

A-4 Blackfin FPGA EZ-Extender Manual

Bill Of Materials

339

0 1

10W

5

060

3R

3-4

R9

R12

R15

-16

R27

R58

-59

PAN

ASO

NIC

ER

J-3G

EY

0R00

V

341

10 1

10W

5

060

3 R

42PA

NA

SON

ICE

RJ-

3GE

YJ1

00V

351

200K

11

6W 1

0

603

R20

VIS

HA

YC

RC

W06

0320

03FR

T1

362

10K

11

0W 1

0

603

R14

R19

PAN

ASO

NIC

P10

0K

HT

R-N

D

372

33 1

10W

1

060

3 R

2R

26Y

AG

EO

9C06

031A

33R

0FK

HFT

385

100

116

W 5

4

02R

5R

7-8

R23

R44

PAN

ASO

NIC

ER

J-2G

EJ1

01X

391

390P

F 25

V 5

0

603

NP

OC

7A

VX

0603

3A39

1FA

T2A

401

499

K 1

16W

1

060

3R

13ST

AC

KP

OL

ER

MC

11

6 4

99K

1

R

411

316

K 1

16W

1

060

3 R

17PA

NA

SON

ICE

RJ-

3EK

F316

2V

421

105

K 1

16W

1

060

3 R

11PA

NA

SON

ICE

RJ-

3EK

F105

1V

431

215

K 1

16W

1

060

3R

18PA

NA

SON

ICE

RJ-

3EK

F215

1V

441

GR

EE

N-S

MT

LE

D00

1G

UL

L-W

ING

LE

D9

PAN

ASO

NIC

LN

1361

C

453

IDC

2X

1 ID

C2X

1G

OL

DJP

1-3

Ref

Des

crip

tion

Ref

eren

ce D

esig

nato

r M

anuf

actu

rer

Part

Num

ber

Blackfin FPGA EZ-Extender Manual A-5

465

IDC

3X

1 ID

C3X

1P

9-13

BE

RG

5410

1-T

08-0

3

471

IDC

3X

2 ID

C3X

2JP

4B

ER

G54

102-

T08

-03

481

IDC

4X

2 ID

C4X

2JP

5SU

LL

INS

S201

2-04

494

IDC

13X

2 ID

C13

X2

P

8P

14P

16-1

7B

ER

G54

102-

T08

-13

501

25A

RE

SET

AB

LE

FU

S001

F1R

AY

CH

EM

CO

RP

SMD

250-

2

513

10U

F 10

V 1

0 8

05C

8 C

9 C

71PA

NA

SON

ICE

CJ-

2FB

1A10

6K

Ref

Des

crip

tion

Ref

eren

ce D

esig

nato

r M

anuf

actu

rer

Part

Num

ber

A-6 Blackfin FPGA EZ-Extender Manual

4

3

2

1

A B C D

20 Cotton Road

Nashua NH 03063

A B C D

4

3

2

1

PH 1-800-ANALOGD

C

Title

Size Board No

Date Sheet of

DEVICESANALOG

DNP = Do Not Populate

Rev

BLACKFIN FPGA EZ-EXTENDER

A0199-2005 10

SchematicBLACKFIN FPGA EZ-EXTENDER

1219-9-2005_1040

TITLE

33V

4

3

2

1

A B C D

20 Cotton Road

Nashua NH 03063

A B C D

4

3

2

1

PH 1-800-ANALOGD

C

Title

Size Board No

Date Sheet of

DEVICESANALOG

DNP = Do Not Populate

Rev

BLACKFIN FPGA EZ-EXTENDER

A0199-2005 10

33V

1A

1B

1Y

2A

2B

2Y

3A

3B

3Y

4A

4B

4Y

~AB

EN

25V

33V

33V

33V

33V

33V

25V

33V

OENC OUTOE OUT

CLK

D0

TMS

TCK

TDI

TDO

VCCINT

VCCO

VCCJ

NC1

NC2

NC3

NC4

NC5

NC6

GND

CE

CF

OE~RESET

CEO

VCCAUX_A6

VCCAUX_A17

VCCAUX_F1

VCCAUX_F22

VCCAUX_U1

VCCAUX_U22

VCCAUX_AB6

VCCAUX_AB17

VCCINT_G7

VCCINT_G8

VCCINT_G15

VCCINT_G16

VCCINT_H7

VCCINT_H16

VCCINT_R7

VCCINT_R16

VCCINT_T7

VCCINT_T8

VCCINT_T15

VCCINT_T16

TCK

TDI

TDO

TMS

M0

M1

M2

CCLK

PROG_B

DONE

HSWAP_EN

GND_A1

GND_A22

GND_B2

GND_B21

GND_C9

GND_C14

GND_J3

GND_J9

GND_J10

GND_J11

GND_J12

GND_J13

GND_J14

GND_J20

GND_K9

GND_K10

GND_K11

GND_K12

GND_K13

GND_K14

GND_L9

GND_L10

GND_L11

GND_L12

GND_L13

GND_L14

GND_M9

GND_M10

GND_M11

GND_M12

GND_M13

GND_M14

GND_N9

GND_N10

GND_N11

GND_N12

GND_N13

GND_N14

GND_P3

GND_P9

GND_P10

GND_P11

GND_P12

GND_P13

GND_P14

GND_P20

GND_Y9

GND_Y14

GND_AA2

GND_AA21

GND_AB1

GND_AB22

FPGAFPGA

EXTRA CLOCK SOCKET25MHZ SYSTEM CLOCK

FPGA JTAG HEADER

FLASH JTAG HEADER

BOOTMODE JUMPER

FPGA BOOT FLASH(2Mbit)

MUXFLASHSKTOSC

9-27-2005_1144 2 12

A6

A17

F1

F22

U1

U22

AB6

AB17

G7

G8

G15

G16

H7

H16

R7

R16

T7

T8

T15

T16

A21

B1

B22

A20

AB2

AA1

AB3

AA22

A2

AB21

B3

A1

A22

B2

B21

C9

C14

J3

J9

J10

J11

J12

J13

J14

J20

K9

K10

K11

K12

K13

K14

L9

L10

L11

L12

L13

L14

M9

M10

M11

M12

M13

M14

N9

N10

N11

N12

N13

N14

P3

P9

P10

P11

P12

P13

P14

P20

Y9

Y14

AA2

AA21

AB1

AB22

U1

FG456XC3S1000

CONFIG_PROG_B

6

5

4

3

2

1P6

IDC6X16X1

1

2

3

4

5

6

P15

IDC6X16X1

3

1

8

10

7

13

5

6

4

17

18

19

20

2

9

12

14

15

16

11

U4

TSSOP20XCF04S

2

4

5 6

3

1JP4

IDC3X23X2

402100R5

R400603

402100R44

R8100402

R7100402

1 3

U6

25MHZOSC003

80510UFC14

R29

060310K

R22

060310K

R21

060310K

R1

060310K

1 5

U7

DIPDIP8SOC

R263306030603

33R2

R25

DNP

10K0603

12V

1 2JP1

IDC2X12X1

CONFIG_DONER3

06030

CONFIG_CLK_TSCLK1

FPGA_TMS

FPGA_TDO

FPGA_TCK

FPGA_TDI

FPGA_TCK

FPGA_TDO

FPGA_TDI

FPGA_TMS

FLASH_TMS

FLASH_TDI

FLASH_TDO

FLASH_TCK

M1

M2

M0

12V

SPST-MOMENTARYSWT013SW1

2

3

4

5

6

7

11

10

9

14

13

12

1

15

U2

TSSOP1674LVC157

CONFIG_DONE

FLASH_TMS

FLASH_TCK

FLASH_TDI

FLASH_TDO

M2

M0

M1

FPGA CONFIG

CONFIG_INIT_B_TFS1

FLASH_DOUT

CONFIG_CLK_TSCLK1

FLASH_DONE

001UF0603

C18

IO_L32_0_GCLK6_A11B4_L32N_GCKL1_AA12

C19

0603001UF 001UF

0603

C20 C21

0603001UF 001UF

0603

C25C24

0603001UF001UF

0603

C23C22

0603001UF 001UF

0603

C31 C30

0603001UF 001UF

0603

C29 C28

0603001UF001UF

0603

C27C26

0603001UF

001UF0603

C32 C11

0603001UF 001UF

0603

C12 C13

0603001UF

80510UFC15 C16

10UF805

C17

0603001UF

0603330R24

LED10

LED001AMBER-SMT

CONFIG_DIN_DT1PRI

FLASH_DONE

FLASH_DOUT

DT1PRI

R6

060310K10K

0603

R28

33V 33V

4

3

2

1

A B C D

20 Cotton Road

Nashua NH 03063

A B C D

4

3

2

1

PH 1-800-ANALOGD

C

Title

Size Board No

Date Sheet of

DEVICESANALOG

DNP = Do Not Populate

Rev

BLACKFIN FPGA EZ-EXTENDER

A0199-2005 10

33V

33V

A18

A1

A10

A11

A12

A13

A14

A16

A2

A3

A4

A5

A6

A7

A8

A9

D0

D1

D10

D11

D2

D3

D4

D5

D6

D7

D8

D9

BHE

BLE

CE

OE

WE

A17

D15

D14

D13

D12

A0

A15

A18

A1

A10

A11

A12

A13

A14

A16

A2

A3

A4

A5

A6

A7

A8

A9

D0

D1

D10

D11

D2

D3

D4

D5

D6

D7

D8

D9

BHE

BLE

CE

OE

WE

A17

D15

D14

D13

D12

A0

A15

VCCO_6_M7

VCCO_6_N7

VCCO_6_P7

VCCO_6_R3

VCCO_6_R6

IO_Y1

IO_L16N_6_W4

IO_L16P_6_W3

IO_L17N_6_W2

IO_L17P_6_VREF_6_W1

IO_L19N_6_V5

IO_L19P_6_U5

IO_L20N_6_V4

IO_L20P_6_V3

IO_L21N_6_V2

IO_L21P_6_V1

IO_L22N_6_T6

IO_L22P_6_T5

IO_L23N_6_U4

IO_L23P_6_T4

IO_L24N_6_VREF_6_U3

IO_L24P_6_U2

IO_L26N_6_T3

IO_L26P_6_R4

IO_L27N_6_T2

IO_L27P_6_T1

IO_L28N_6_R5

IO_L28P_6_P6

IO_L29N_6_R2

IO_L29P_6_R1

IO_L31N_6_P5

IO_L31P_6_P4

IO_L32N_6_P2

IO_L32P_6_P1

IO_L33N_6_N6

IO_L33P_6_N5

IO_L34N_6_VREF_6_N4

IO_L34P_6_N3

IO_L35N_6_N2

IO_L35P_6_N1

IO_L38N_6_M6

IO_L38P_6_M5

IO_L39N_6_M4

IO_L39P_6_M3

IO_L40N_6_M2

IO_L40P_6_VREF_6_M1

IO_L01N_6_VRP_6_Y3

IO_L01P_6_VRN_6_Y2

VCCO_7_H3

VCCO_7_H6

VCCO_7_J7

VCCO_7_K7

VCCO_7_L7

IO_C2

IO_L16N_7_D1

IO_L16P_7_VREF_7_C1

IO_L17N_7_E4

IO_L17P_7_D4

IO_L19N_7_VREF_7_D3

IO_L19P_7_D2

IO_L20N_7_F4

IO_L20P_7_E3

IO_L21N_7_E1

IO_L21P_7_E2

IO_L22N_7_G6

IO_L22P_7_F5

IO_L23N_7_F2

IO_L23P_7_F3

IO_L24N_7_H5

IO_L24P_7_G5

IO_L26N_7_G3

IO_L26P_7_G4

IO_L27N_7_G1

IO_L27P_7_VREF_7_G2

IO_L28N_7_H1

IO_L28P_7_H2

IO_L29N_7_J4

IO_L29P_7_H4

IO_L31N_7_J5

IO_L31P_7_J6

IO_L32N_7_J1

IO_L32P_7_J2

IO_L33N_7_K5

IO_L33P_7_K6

IO_L34N_7_K3

IO_L34P_7_K4

IO_L35N_7_K1

IO_L35P_7_K2

IO_L38N_7_L5

IO_L38P_7_L6

IO_L39N_7_L3

IO_L39P_7_L4

IO_L40N_7_VREF_7_L1

IO_L40P_7_L2

IO_L01N_7_VRP_7_C3

IO_L01P_7_VRN_7_C4

(512k x 16bits x 2chips)2MBYTES FPGA SRAM

FPGASRAM SRAM

SRAM_A9

9-27-2005_1144 3 12

FLASH_TDO

FLASH_TMS

FLASH_TDI

FLASH_TCK

M7

N7

P7

R3

R6

Y1

W4

W3

W2

W1

V5

U5

V4

V3

V2

V1

T6

T5

U4

T4

U3

U2

T3

R4

T2

T1

R5

P6

R2

R1

P5

P4

P2

P1

N6

N5

N4

N3

N2

N1

M6

M5

M4

M3

M2

M1

Y3

Y2

H3

H6

J7

K7

L7

C2

D1

C1

E4

D4

D3

D2

F4

E3

E1

E2

G6

F5

F2

F3

H5

G5

G3

G4

G1

G2

H1

H2

J4

H4

J5

J6

J1

J2

K5

K6

K3

K4

K1

K2

L5

L6

L3

L4

L1

L2

C3

C4

U1

FG456XC3S1000

28

2

23

24

25

26

27

43

3

4

5

18

19

20

21

22

7

8

31

32

9

10

13

14

15

16

29

30

40

39

6

41

17

44

38

37

36

35

1

42

U3

TSOP44IS61LV51216

42

1

35

36

37

38

44

17

41

6

39

40

30

29

16

15

14

13

10

9

32

31

8

7

22

21

20

19

18

5

4

3

43

27

26

25

24

23

2

28

U5

TSOP44IS61LV51216

SRAM_D7

SRAM_D6

SRAM_D3

SRAM_D2

SRAM_D0

SRAM_D8

SRAM_D9

SRAM_D5

SRAM_D4

SRAM_D13

SRAM_D1

SRAM_D10

SRAM_D11

SRAM_D12

SRAM_D14

SRAM_D15

SRAM_CE

SRAM_A7

SRAM_A0

SRAM_A5

SRAM_A3

SRAM_A1

SRAM_WE

SRAM_A8

SRAM_A6

SRAM_A4

SRAM_A2

SRAM_A17

SRAM_OE

SRAM_A12

SRAM_A13

SRAM_A15

SRAM_A16

SRAM_A14

SRAM_A18

SRAM_A11

SRAM_A10

SRAM_D22

SRAM_D20

SRAM_D18

SRAM_D17

SRAM_D16

SRAM_D26

SRAM_D21

SRAM_D24

SRAM_D19

SRAM_D31

SRAM_D25

SRAM_D27

SRAM_D28

SRAM_D30

SRAM_D29

PB2

A11

A5

D1

A15

A3

A9

D13

D7

A13

A19

A7

A1

A18

A6

A2

A12

D6

A8

A14

D2

D0

A10

A4

D3

A16

SRAM FPGA BANKS 7 + 8

SRAM_CE

SRAM_WE

SRAM_OE

SRAM_A18

SRAM_A0 SRAM_D0

SRAM_D1

SRAM_D2

SRAM_D3

SRAM_D4

SRAM_D5

SRAM_D6

SRAM_D7

SRAM_D8

SRAM_D9

SRAM_D10

SRAM_D11

SRAM_D12

SRAM_D13

SRAM_D14

SRAM_D15

SRAM_D16

SRAM_D17

SRAM_D18

SRAM_D19

SRAM_D20

SRAM_D21

SRAM_D22

SRAM_D23

SRAM_D24

SRAM_D25

SRAM_D26

SRAM_D27

SRAM_D28

SRAM_D29

SRAM_D30

SRAM_D31

SRAM_A1

SRAM_A2

SRAM_A3

SRAM_A4

SRAM_A5

SRAM_A6

SRAM_A7

SRAM_A8

SRAM_A9

SRAM_A10

SRAM_A11

SRAM_A12

SRAM_A13

SRAM_A14

SRAM_A15

SRAM_A16

SRAM_A17

SRAM_A1

SRAM_A2

SRAM_A3

SRAM_A4

SRAM_A5

SRAM_A6

SRAM_A7

SRAM_A8

SRAM_A9

SRAM_A10

SRAM_A11

SRAM_A12

SRAM_A13

SRAM_A14

SRAM_A15

SRAM_A16

SRAM_A17

SRAM_A18

SRAM_A0

SRAM_OE

SRAM_WE

SRAM_CE

C33

0603001UF

C34

0603001UF001UF

0603

C37001UF0603

C36

C42

0603001UF 001UF

0603

C41 C40

0603001UF001UF

0603

C39001UF0603

C46 C45

0603001UF 001UF

0603

C44C43

0603001UF

B6_L01P_Y2

B6_L01N_Y3

SRAM_D23

4

3

2

1

A B C D

20 Cotton Road

Nashua NH 03063

A B C D

4

3

2

1

PH 1-800-ANALOGD

C

Title

Size Board No

Date Sheet of

DEVICESANALOG

DNP = Do Not Populate

Rev

BLACKFIN FPGA EZ-EXTENDER

A0199-2005 10

EXPANSION INTERFACE TYPE B

P1Expanison Connector

Top Of BoardBottom Of Board

Expansion Connector 1

10-18-2005_1616 4 12

EXPANSION INTERFACE CONNECTOR 1

C3510UF805

01UF0603

C38

5V_EI

5V_EI

1

10

11 12

13 14

15 16

17 18

19

2

20

21 22

23 24

25 26

27 28

29

3

30

31 32

33 34

35 36

37 38

39

4

40

41 42

43 44

45 46

47 48

49

5

50

51 52

53 54

55 56

57 58

59

6

60

61 62

63 64

65 66

67 68

69

7

70

71 72

73 74

75 76

77 78

79

8

80

81 82

83 84

85 86

87 88

89

9

90

P1

CON01845X2

1

10

1112

1314

1516

1718

19

2

20

2122

2324

2526

2728

29

3

30

3132

3334

3536

3738

39

4

40

4142

4344

4546

4748

49

5

50

5152

5354

5556

5758

59

6

60

6162

6364

6566

6768

69

7

70

7172

7374

7576

7778

79

8

80

8182

8384

8586

8788

89

9

90

J1

CON01945X2

PP1

EXPANSION_PPI_CLK

PP3

UDEF2

UDEF4

UDEF6

UDEF8

UDEF10

D9

D7

D15

D13

D11

D5

D1

D3

D15

D9

D5

D1

D3

D0

D2

D4

D6

D8

D10

D14

D12

P1_5

P1_25

P1_27

P1_29

P1_31

P1_33

P1_55

P1_57

P1_59

P1_61

P1_63

P1_65

P1_67

P1_69

P1_35

P1_26

P1_28

P1_30

P1_32

P1_34

P1_56

P1_58

P1_60

P1_62

P1_64

P1_66

P1_68

P1_70

P1_36

P1_26

P1_28

P1_30

P1_32

P1_34

P1_36

P1_56

P1_58

P1_60

P1_62

P1_64

P1_66

P1_68

P1_70

P1_5

P1_25

P1_27

P1_29

P1_31

P1_33

P1_35

P1_55

P1_57

P1_59

P1_61

P1_63

P1_65

P1_67

P1_69

P1_[586]

A5

A6A7

A8A9

A10A11

A12A13

A14A15

A16A17

A18A19

D0

D2

D4

D6D7

D8

D10D11

D12D13

D14

A1

A2

B1_L24N_D15_J1_71B1_L24P_E15_J1_72

B1_L22N_A16_J1_73B1_L22P_B16_J1_74

B1_L19N_C16_J1_75B1_L19P_D16_J1_76

B1_L16N_B17_J1_77B1_L16P_C17_J1_78

B1_L15N_D17_J1_79

A3

B1_L15P_E17_J1_80

B1_L10N_A18_J1_81B1_L10P_B18_J1_82

B1_L09N_C18_J1_83B1_L09P_D18_J1_84

B1_L06N_A19_J1_85B1_L06P_B19_J1_86

A4A5

A6 A7

A8 A9

A10 A11

A12 A13

A14 A15

A16 A17

A18 A19

A1

A2

PP0

PP2

UDEF1

UDEF3

A3

UDEF5

UDEF7

UDEF9

UDEF11

A4

33V

25V 33V

33V

33V

33V

4

3

2

1

A B C D

20 Cotton Road

Nashua NH 03063

A B C D

4

3

2

1

PH 1-800-ANALOGD

C

Title

Size Board No

Date Sheet of

DEVICESANALOG

DNP = Do Not Populate

Rev

BLACKFIN FPGA EZ-EXTENDER

A0199-2005 10

VCCO_0_C8

VCCO_0_F8

VCCO_0_G9

VCCO_0_G10

VCCO_0_G11

IO_A10

IO_D9

IO_D10

IO_F6

IO_VREF_0_A3

IO_VREF_0_C7

IO_VREF_0_E5

IO_VREF_0_F7

IO_L06N_0_D5

IO_L06P_0_C5

IO_L09N_0_B5

IO_L09P_0_A5

IO_L10N_0_E6

IO_L10P_0_D6

IO_L15N_0_C6

IO_L15P_0_B6

IO_L16N_0_E7

IO_L16P_0_D7

IO_L19N_0_B7

IO_L19P_0_A7

IO_L22N_0_E8

IO_L22P_0_D8

IO_L24N_0_B8

IO_L24P_0_A8

IO_L25N_0_F9

IO_L25P_0_E9

IO_L27N_0_B9

IO_L27P_0_A9

IO_L28N_0_F10

IO_L28P_0_E10

IO_L29N_0_C10

IO_L29P_0_B10

IO_L30N_0_F11

IO_L30P_0_E11

IO_L31N_0_D11

IO_L31P_0_VREF_0_C11

IO_L01N_0_VRP_0_B4

IO_L01P_0_VRN_0_A4

IO_L32N_0_GCLK7_B11

IO_L32P_0_GCLK6_A11

VCCO_1_C15

VCCO_1_F15

VCCO_1_G12

VCCO_1_G13

VCCO_1_G14

IO_A12

IO_E16

IO_F12

IO_F13

IO_F16

IO_F17

IO_VREF_1_E13

IO_VREF_1_F14

IO_L06N_1_VREF_1_A19

IO_L06P_1_B19

IO_L09N_1_C18

IO_L09P_1_D18

IO_L10N_1_VREF_1_A18

IO_L10P_1_B18

IO_L15N_1_D17

IO_L15P_1_E17

IO_L16N_1_B17

IO_L16P_1_C17

IO_L19N_1_C16

IO_L19P_1_D16

IO_L22N_1_A16

IO_L22P_1_B16

IO_L24N_1_D15

IO_L24P_1_E15

IO_L25N_1_B15

IO_L25P_1_A15

IO_L27N_1_D14

IO_L27P_1_E14

IO_L28N_1_A14

IO_L28P_1_B14

IO_L29N_1_C13

IO_L29P_1_D13

IO_L30N_1_A13

IO_L30P_1_B13

IO_L31N_1_VREF_1_D12

IO_L31P_1_E12

IO_L01N_1_VRP_1_C19

IO_L01P_1_VRN_1_B20

IO_L32N_1_GCLK5_B12

IO_L32P_1_GCLK4_C12

FPGAFPGA

LAYOUT NOTE PLACE NEAR FPGA

5 129-27-2005_1144

C8

F8

G9

G10

G11

A10

D9

D10

F6

A3

C7

E5

F7

D5

C5

B5

A5

E6

D6

C6

B6

E7

D7

B7

A7

E8

D8

B8

A8

F9

E9

B9

A9

F10

E10

C10

B10

F11

E11

D11

C11

B4

A4

B11

A11

C15

F15

G12

G13

G14

A12

E16

F12

F13

F16

F17

E13

F14

A19

B19

C18

D18

A18

B18

D17

E17

B17

C17

C16

D16

A16

B16

D15

E15

B15

A15

D14

E14

A14

B14

C13

D13

A13

B13

D12

E12

C19

B20

B12

C12

U1

FG456XC3S1000

1

10

11 12

13 14

15 16

17 18

19

2

20

21 22

23 24

25 26

27 28

29

3

30

31 32

33 34

35 36

37 38

4

5 6

7 8

9

39 40

41

43

45

47

49

42

44

46

48

50

25X2CON041

P4

5

1

18

20

22

26

24

16

14

12

25

23

21

19

17

15

13

11

9

3

6

10

8

4

2

7

P8

IDC13X213X2

5

1

18

20

22

26

24

16

14

12

25

23

21

19

17

15

13

11

9

3

6

10

8

4

2

7

P14

IDC13X213X2

FPGA BANKS 0 + 1

001UF0603

C50

DNP0603

R52

B1_L10N_A18_J1_81

B1_L15P_E17_J1_80

R53

0603DNP

B1_L16P_C17_J1_78

R27

06030

B1_L10P_B18_J1_82B1_L10N_A18_J1_81

B1_L15N_D17_J1_79

B1_L16N_B17_J1_77

B1_L24N_D15_J1_71

B1_L22N_A16_J1_73

B1_L19N_C16_J1_75

R51

0603DNPDNP

0603

R50DNP0603

R48

R31

0603DNP

B1_L19N_C16_J1_75

B1_L22N_A16_J1_73

B1_L24N_D15_J1_71

B1_L15N_D17_J1_79

B1_L15P_E17_J1_80

B1_L16N_B17_J1_77

B1_L16P_C17_J1_78

DNP0603

R30

VCCO_1

VCCO_1

C47

0603001UF

VCCO_1

B1_L27N_D14

PB1

AOE

B1_L01P_VRN_B20

B1_L01N_VRP_C19

IO_L32_0_GCLK6_A11

IO_L32_0_GCLK7_B11

IO_L32_0_GCLK7_B11

B1_L32N_GCLK5_B12

B1_L32P_GCLK4_C12 B1_L06P_B19_J1_86

B1_L09P_D18_J1_84

B1_L15P_E17_J1_80

B1_L16P_C17_J1_78

B1_L19P_D16_J1_76

B1_L16N_B17_J1_77

B1_L15N_D17_J1_79

B1_L09N_C18_J1_83

B1_L06N_A19_J1_85

B1_L31P_E12

B1_L31N_D12

B1_L06N_A19_J1_85

B1_L09N_C18_J1_83

B1_L09P_D18_J1_84

B1_L06P_B19_J1_86

B1_F17

B1_F16

B1_E16

B1_F13

B1_E13

B1_F12

B1_A12

B1_F14

B1_L01N_VRP_C19

B1_L01P_VRN_B20

B1_L32P_GCLK4_C12

B1_L32N_GCLK5_B12

AMS3

D5

D4

AMS0

UDEF1

ARE

ARDY

AMS1

AMS2

UDEF11

UDEF9

UDEF7

UDEF5

UDEF3

PP2

PP0

D15

D11

D9

A17

B1_L16P_C17_J1_78

B1_L19P_D16_J1_76

B1_L19N_C16_J1_75

B1_L22P_B16_J1_74

B1_L24N_D15_J1_71

B1_L22N_A16_J1_73

B1_L24P_E15_J1_72

B1_L16N_B17_J1_77

B1_L10P_B18_J1_82

B1_L15P_E17_J1_80

B1_L15N_D17_J1_79

B1_L10N_A18_J1_81

B1_L09P_D18_J1_84

B1_L09N_C18_J1_83

B1_L06P_B19_J1_86

B1_L06N_A19_J1_85

B1_L31N_D12

B1_L30N_A13

B1_L29N_C13

B1_L28N_A14

B1_L27N_D14

B1_L25N_B15

B1_F16

B1_F14

B1_F13

B1_F12

B1_L31P_E12

B1_L30P_B13

B1_L29P_D13

B1_L28P_B14

B1_L27P_E14

B1_L25P_A15

B1_F17

B1_E13

B1_E16

B1_A12

UDEF10

ABE3

ABE1

ABE0

ABE2

AWE

UDEF6

UDEF8

PP3

UDEF4

UDEF2

PP1

D14

D8

D10

D12

B1_L25P_A15B1_L25N_B15

B1_L22N_A16_J1_73

B1_L24N_D15_J1_71

B1_L19N_C16_J1_75

B1_L24P_E15_J1_72

B1_L22P_B16_J1_74

B1_L27P_E14

B1_L19P_D16_J1_76

B1_L22P_B16_J1_74

B1_L24P_E15_J1_72

B1_L25N_B15

B1_L25P_A15

B1_L27N_D14

B1_L27P_E14

B1_L28N_A14

B1_L28P_B14

B1_L29N_C13

B1_L29P_D13

B1_L30N_A13

B1_L30P_B13

B1_L10N_A18_J1_81

B1_L10P_B18_J1_82

3

2

1

3X1IDC3X1

P9

EXPANSION_PPI_CLK

B1_F16 B1_F17

B1_L28P_B14

B1_L29P_D13

B1_L30P_B13

B1_L31P_E12

B1_L28N_A14

B1_L29N_C13

B1_L30N_A13

B1_L31N_D12

B1_E16

B1_E13

B1_A12

B1_L01P_VRN_B20

B1_L32P_GCLK4_C12

B1_F14

B1_L01N_VRP_C19

B1_L32N_GCLK5_B12

B1_F13

B1_F12

B1_L01P_VRN_B20

B1_L01N_VRP_C19

001UF0603

C48 C49

0603001UF

C51

0603001UF 001UF

0603

C52 C53

0603001UF001UF

0603

C54

VCCO_1

R49

0603DNP

B1_L10P_B18_J1_82

DNP0603

R54

4

3

2

1

A B C D

20 Cotton Road

Nashua NH 03063

A B C D

4

3

2

1

PH 1-800-ANALOGD

C

Title

Size Board No

Date Sheet of

DEVICESANALOG

DNP = Do Not Populate

Rev

BLACKFIN FPGA EZ-EXTENDER

A0199-2005 10Expanison ConnectorP2

Bottom Of Board Top Of Board

Expansion Connector 2

33V_EI

6 129-14-2005_1203

EXPANSION INTERFACE CONNECTOR 2

SCK

NMI

TMR1

PF1

PF3

PF5

PF7

PF9

PF11

PF13

PF15

1

10

11 12

13 14

15 16

17 18

19 20

21 22

23 24

25 26

27 28

29

3

30

31 32

33 34

35 36

37 38

39

4

40

41 42

43 44

45 46

47 48

49

5

50

51 52

53 54

55 56

57 58

59

6

60

61 62

63 64

65 66

67 68

69

7

70

71 72

73 74

75 76

77 78

79

8

80

81 82

83 84

85 86

87 88

89

9

90

2P2

CON01845X2

1

10

1112

1314

1516

1718

19

2

20

2122

2324

2526

2728

29

3

30

3132

3334

3536

3738

39

4

40

4142

4344

4546

4748

49

5

50

5152

5354

5556

5758

59

6

60

6162

6364

6566

6768

69

7

70

7172

7374

7576

7778

79

8

80

8182

8384

8586

8788

89

9

90

J2

CON01945X2

ARE

ARDY

AMS0

AMS1

P2_21

P2_19

P2_7

P2_21

P2_71

P2_73

P2_77

P2_79

P2_83

P2_85

P2_81

P2_19

P2_15

P2_5 P2_6

P2_8

P2_22

P2_86

P2_84

P2_82

P2_80

P2_78

P2_74

P2_72

P2_20

P2_18

P2_22

P2_74

P2_78

P2_82

P2_84

P2_86

P2_80

P2_72

P2_20

P2_18

P2_8

P2_6

P2_[586]

P2_5

P2_7

P2_15

P2_85

P2_83

P2_81

P2_79

P2_77

P2_73

P2_71AWE

AOE

ABE0

ABE1

ABE2

ABE3

TSCLK0

TFS0

DT0PRI

DT0SEC

CONFIG_CLK_TSCLK1

CONFIG_INIT_B_TFS1

DT1PRI

DT1SEC

TMR0

TMR2

PF14

PF12

PF10

PF8

PF4

PF6

PF2

PF0

B2_L40N_L21_J2_9

B2_L39N_L19_J2_11

B2_C22_J2_17

B2_L38N_L17_J2_23

B2_L35N_K21_J2_25

B2_L34N_K19_J2_27

B2_L33N_K17_J2_29

B2_L32N_J21_J2_31

B2_L31N_J18_J2_33

B2_L29N_H21_J2_35

B2_L28N_H18_J2_37

B2_L27N_G21_J2_39

B2_L26N_G20_J2_41

B2_L22N_G17_J2_43

B2_L24N_F20_J2_45

B2_L23N_F19_J2_47

B2_L21N_E21_J2_49

B2_L20N_E19_J2_51

B2_L19N_E18_J2_53

B2_L17N_D21_J2_55

B2_L16N_D20_J2_57B2_L16P_D19_J2_58

B2_L17P_D22_J2_56

B2_L19P_F18_J2_54

B2_L20P_E20_J2_52

B2_L21P_E22_J2_50

B2_L23P_G19_J2_48

B2_L24P_F21_J2_46

B2_L22P_G18_J2_44

B2_L26P_H19_J2_42

B2_L27P_G22_J2_40

B2_L28P_J17_J2_38

B2_L29P_H22_J2_36

B2_L31P_J19_J2_34

B2_L32P_J22_J2_32

B2_L33P_K18_J2_30

B2_L34P_K20_J2_28

B2_L35P_K22_J2_26

B2_L38P_L18_J2_24

IO_L01P_2_VRN_2_C21_J2_16

B2_L40P_L22_J2_10

B2_L39P_L20_J2_12

MOSI

MISO

UDEF12

AMS3

AMS2

AMS0

ARDY

AMS1

AREAWE

AOE

ABE0

ABE1

ABE2

ABE3

RSCLK1

RSCLK0

RFS1

DR1PRI

DR1SEC

AMS2

AMS3

DR0SEC

DR0PRI

RFS0

TMR3

SPIDS0

C56

060301UF

80510UFC55

33V_EI

33V

4

3

2

1

A B C D

20 Cotton Road

Nashua NH 03063

A B C D

4

3

2

1

PH 1-800-ANALOGD

C

Title

Size Board No

Date Sheet of

DEVICESANALOG

DNP = Do Not Populate

Rev

BLACKFIN FPGA EZ-EXTENDER

A0199-2005 10

33V

25V33V

33V

33V

VCCO_2_H17

VCCO_2_H20

VCCO_2_J16

VCCO_2_K16

VCCO_2_L16

IO_C22

IO_L16N_2_D20

IO_L16P_2_D19

IO_L17N_2_D21

IO_L17P_2_VREF_2_D22

IO_L19N_2_E18

IO_L19P_2_F18

IO_L20N_2_E19

IO_L20P_2_E20

IO_L21N_2_E21

IO_L21P_2_E22

IO_L22N_2_G17

IO_L22P_2_G18

IO_L23N_2_VREF_2_F19

IO_L23P_2_G19

IO_L24N_2_F20

IO_L24P_2_F21

IO_L26N_2_G20

IO_L26P_2_H19

IO_L27N_2_G21

IO_L27P_2_G22

IO_L28N_2_H18

IO_L28P_2_J17

IO_L29N_2_H21

IO_L29P_2_H22

IO_L31N_2_J18

IO_L31P_2_J19

IO_L32N_2_J21

IO_L32P_2_J22

IO_L33N_2_K17

IO_L33P_2_K18

IO_L34N_2_VREF_2_K19

IO_L34P_2_K20

IO_L35N_2_K21

IO_L35P_2_K22

IO_L38N_2_L17

IO_L38P_2_L18

IO_L39N_2_L19

IO_L39P_2_L20

IO_L40N_2_L21

IO_L40P_2_VREF_2_L22

IO_L01N_2_VRP_2_C20

IO_L01P_2_VRN_2_C21

VCCO_3_M16

VCCO_3_N16

VCCO_3_P16

VCCO_3_R17

VCCO_3_R20

IO_L16N_3_W22

IO_L16P_3_Y22

IO_L17N_3_V19

IO_L17P_3_VREF_3_W19

IO_L19N_3_W21

IO_L19P_3_W20

IO_L20N_3_U19

IO_L20P_3_V20

IO_L21N_3_V22

IO_L21P_3_V21

IO_L22N_3_T17

IO_L22P_3_U18

IO_L23N_3_U21

IO_L23P_3_VREF_3_U20

IO_L24N_3_R18

IO_L24P_3_T18

IO_L26N_3_T20

IO_L26P_3_T19

IO_L27N_3_T22

IO_L27P_3_T21

IO_L28N_3_R22

IO_L28P_3_R21

IO_L29N_3_P19

IO_L29P_3_R19

IO_L31N_3_P18

IO_L31P_3_P17

IO_L32N_3_P22

IO_L32P_3_P21

IO_L33N_3_N18

IO_L33P_3_N17

IO_L34N_3_N20

IO_L34P_3_VREF_3_N19

IO_L35N_3_N22

IO_L35P_3_N21

IO_L38N_3_M18

IO_L38P_3_M17

IO_L39N_3_M20

IO_L39P_3_M19

IO_L40N_3_VREF_3_M22

IO_L40P_3_M21

IO_L01N_3_VRP_3_Y20

IO_L01P_3_VRN_3_Y19

IO_Y21

FPGAFPGA

LAYOUT NOTE PLACE NEAR FPGA

9-27-2005_1144 7 12

H17

H20

J16

K16

L16

C22

D20

D19

D21

D22

E18

F18

E19

E20

E21

E22

G17

G18

F19

G19

F20

F21

G20

H19

G21

G22

H18

J17

H21

H22

J18

J19

J21

J22

K17

K18

K19

K20

K21

K22

L17

L18

L19

L20

L21

L22

C20

C21

M16

N16

P16

R17

R20

W22

Y22

V19

W19

W21

W20

U19

V20

V22

V21

T17

U18

U21

U20

R18

T18

T20

T19

T22

T21

R22

R21

P19

R19

P18

P17

P22

P21

N18

N17

N20

N19

N22

N21

M18

M17

M20

M19

M22

M21

Y20

Y19

Y21

U1

FG456XC3S1000

2

4

8

10

6

12

14

16

24

22

20

18

26

28

3

5

7

9

11

13

15

17

19

21

23

25

27

1P5

IDC14X214X2

1

27

25

23

21

19

17

15

13

11

9

7

5

3

28

26

18

20

22

24

16

14

12

6

10

8

4

2P7

IDC14X214X2

VCCO_2

B2_L26P_H19_J2_42

DNP0603

R55B2_L24P_F21_J2_46

R56

0603DNP

B2_L23P_G19_J2_48

B2_L26N_G20_J2_41

B2_L24N_F20_J2_45

B2_L23N_F19_J2_47 B2_L23P_G19_J2_48

B2_L24P_F21_J2_46

B2_L26P_H19_J2_42

R32

0603DNP

TMR0

VCCO_2

PF221

2X1IDC2X1

JP3

CONFIG_PROG_B

1 2JP2

IDC2X12X1

PF3

CONFIG_INIT_B_TFS1

CONFIG_CLK_TSCLK1

RSCLK1

RFS1

IO_L01N_2_VRP_2_C20

IO_L01P_2_VRN_2_C21_J2_16

B2_L22N_G17_J2_43

B2_L22P_G18_J2_44

B2_L32N_J21_J2_31

SPIDS0

PF0

SCK

NMI

TMR1

DR1SEC

TMR3

DR0PRI

DR1PRI

RFS0

DR0SEC

PF15

PF13

RSCLK0

PF7

PF9

PF6

PF11

PF1

PF3

PF5

MOSI

MISO

UDEF12

TMR2

DT1SEC

DT1PRI

DT0SEC

TSCLK0

PF14

PF12

PF10

PF8

PF4

PF2

FPGA BANKS 2 + 3

DT0PRI

TFS0

B2_L40P_L22_J2_10

B2_L40N_L21_J2_9

B2_L39P_L20_J2_12

B2_L39N_L19_J2_11

B2_L38P_L18_J2_24

B2_L38N_L17_J2_23

B2_L35P_K22_J2_26

B2_L35N_K21_J2_25

B2_L34P_K20_J2_28

B2_L34N_K19_J2_27

B2_L33P_K18_J2_30

B2_L33N_K17_J2_29

B2_L32P_J22_J2_32

B2_L31P_J19_J2_34

B2_L31N_J18_J2_33

B2_L29P_H22_J2_36

B2_L29N_H21_J2_35

B2_L28P_J17_J2_38

B2_L28N_H18_J2_37

B2_L27P_G22_J2_40

B2_L27N_G21_J2_39

B2_L26P_H19_J2_42

B2_L26N_G20_J2_41

B2_L24P_F21_J2_46

B2_L24N_F20_J2_45

B2_L23P_G19_J2_48

B2_L23N_F19_J2_47

B2_L21P_E22_J2_50

B2_L21N_E21_J2_49

B2_L20P_E20_J2_52

B2_L20N_E19_J2_51

B2_L19P_F18_J2_54

B2_L19N_E18_J2_53

B2_L17P_D22_J2_56

B2_L17N_D21_J2_55

B2_L16P_D19_J2_58

B2_L16N_D20_J2_57

B2_C22_J2_17

3

2

1

3X1IDC3X1

P10

IO_L01P_2_VRN_2_C21_J2_16

IO_L01N_2_VRP_2_C20

VCCO_2

CONFIG_DONE

B2_L22N_G17_J2_43

B2_L17N_D21_J2_55

B2_L19N_E18_J2_53

B2_L20N_E19_J2_51

B2_L21N_E21_J2_49

B2_L16N_D20_J2_57

IO_L01N_2_VRP_2_C20

B2_L16P_D19_J2_58

B2_L20P_E20_J2_52

B2_L19P_F18_J2_54

B2_L17P_D22_J2_56

B2_L22P_G18_J2_44

B2_L21P_E22_J2_50

B2_C22_J2_17

IO_L01P_2_VRN_2_C21_J2_16

B2_L40N_L21_J2_9

B2_L39N_L19_J2_11

B2_L38N_L17_J2_23

B2_L35N_K21_J2_25

B2_L34N_K19_J2_27

B2_L33N_K17_J2_29

B2_L32N_J21_J2_31

B2_L31N_J18_J2_33

B2_L29N_H21_J2_35

B2_L28N_H18_J2_37

B2_L27N_G21_J2_39

B2_L40P_L22_J2_10

B2_L34P_K20_J2_28

B2_L35P_K22_J2_26

B2_L38P_L18_J2_24

B2_L39P_L20_J2_12

B2_L33P_K18_J2_30

B2_L32P_J22_J2_32

B2_L28P_J17_J2_38

B2_L31P_J19_J2_34

B2_L29P_H22_J2_36

B2_L27P_G22_J2_40

DNP0603

R33

B2_L23N_F19_J2_47

B2_L24N_F20_J2_45

B2_L26N_G20_J2_41

DNP0603

R57

001UF0603

C60 C59

0603001UF 001UF

0603

C58 C57

0603001UF

C82

0603001UF 001UF

0603

C81 C62

0603001UF001UF

0603

C61

VCCO_2

4

3

2

1

A B C D

20 Cotton Road

Nashua NH 03063

A B C D

4

3

2

1

PH 1-800-ANALOGD

C

Title

Size Board No

Date Sheet of

DEVICESANALOG

DNP = Do Not Populate

Rev

BLACKFIN FPGA EZ-EXTENDER

A0199-2005 10

Expanison ConnectorExpanison Connector

Bottom Of Board Top Of BoardExpansion Connector 3

EXPANSION INTERFACE (TYPE B)

P3P3

9-9-2005_1029 128

EXPANSION INTERFACE CONNECTOR 1

33V_EI5V_EI

1

10

11 12

13 14

15 16

17 18

19

2

20

21 22

23 24

25 26

27 28

29

3

30

31 32

33 34

35 36

37 38

39

4

40

41 42

43 44

45 46

47 48

49

5

50

51 52

53 54

55 56

57 58

59

6

60

61 62

63 64

65 66

67 68

69

7

70

71 72

73 74

75 76

77 78

79

8

80

81 82

83 84

85 86

87 88

89

9

90

P3

CON01845X2

1

10

1112

1314

1516

1718

19

2

20

2122

2324

2526

2728

29

3

30

3132

3334

3536

3738

39

4

40

4142

4344

4546

4748

49

5

50

5152

5354

5556

5758

59

6

60

6162

6364

6566

6768

69

7

70

7172

7374

7576

7778

79

8

80

8182

8384

8586

8788

89

9

90

J3

CON01945X2

TX0

TX1

UDEF17

UDEF19

UDEF21

UDEF23

UDEF25

UDEF29

UDEF27

RESET

UDEF32

UDEF34

UDEF36

UDEF38

UDEF40

B5_L01N_RDWR_B_Y4_J3_1

P3_42

P3_[190]

P3_86

P3_84

P3_82

P3_80

P3_78

P3_76

P3_74

P3_72

P3_70

P3_68

P3_64

P3_62

P3_60

P3_58

P3_56

P3_54

P3_52

P3_50

P3_48

P3_46

P3_42

P3_79

P3_89

P3_77

P3_75

P3_73

P3_71

P3_69

P3_67

P3_63

P3_61

P3_59

P3_57

P3_55

P3_53

P3_51

P3_49

P3_47

P3_45

P3_51

P3_79

P3_89

P3_77

P3_75

P3_73

P3_71

P3_69

P3_67

P3_63

P3_61

P3_59

P3_57

P3_55

P3_53

P3_49

P3_47

P3_45

P3_86

P3_84

P3_82

P3_80

P3_78

P3_76

P3_74

P3_72

P3_70

P3_68

P3_64

P3_62

P3_60

P3_58

P3_56

P3_54

P3_52

P3_50

P3_48

P3_46

B5_L27N_W9_J3_31

B5_L28N_D6_AB9_J3_33

B5_L29N_Y10_J3_35

B5_L30N_AB10_J3_37

B5_L31N_D4_W11_J3_39

B5_L10N_VRP_AB5_J3_9

B5_L25N_AB8_J3_21

B5_L24N_W8_J3_19

B5_L22N_AB7_J3_17

B5_L19N_Y7_J3_15

B5_L16N_AA6_J3_13

B5_L15N_W6_J3_11

B5_L09N_Y5_J3_7

B5_L06N_AB4_J3_5

B5_U6_J3_23

B5_V7_J3_29

B5_U9_J3_41

B5_L31P_D5_V11_J3_40

B5_L30P_AA10_J3_38

B5_L29P_W10_J3_36

B5_L28P_D7_AA9_J3_34

B5_L27P_V9_J3_32

B5_L32N_GCLK3_AA11_J3_30

B5_U7_J3_28

B5_L25P_AA8_J3_22

B5_L24P_V8_J3_20

B5_L22P_AA7_J3_18

B5_L19P_W7_J3_16

B5_L16P_Y6_J3_14

B5_L15P_V6_J3_12

B5_L10P_VRN_AA5_J3_10

B5_L09P_W5_J3_8

B5_L06P_AA4_J3_6

B5_L01P_CS_B_AA3_J3_2

B5_AB11_J3_90

B5_U11_J3_83

B5_V10_J3_85

B5_U10_J3_81

UDEF43

BGH

BG

BR

UDEF30

UDEF28

UDEF26

UDEF24

UDEF22

UDEF20

UDEF18

UDEF16

RX1

RX0

UDEF14 UDEF15

CLK_OUT_EXP1

UDEF31

UDEF33

UDEF35

UDEF37

UDEF39

UDEF41

33V_EI

C84

060301UF

80510UFC83

C8610UF805

01UF0603

C85

5V_EI

33V

33V

25V 33V

33V

33V

33V

4

3

2

1

A B C D

20 Cotton Road

Nashua NH 03063

A B C D

4

3

2

1

PH 1-800-ANALOGD

C

Title

Size Board No

Date Sheet of

DEVICESANALOG

DNP = Do Not Populate

Rev

BLACKFIN FPGA EZ-EXTENDER

A0199-2005 10

VCCO_4_T12

VCCO_4_T13

VCCO_4_T14

VCCO_4_U15

VCCO_4_Y15

IO_U16

IO_U17

IO_W13

IO_W14

IO_VREF_4_V18

IO_VREF_4_Y16

IO_VREF_4_AB13

IO_L05N_4_AA19

IO_L05P_4_AB19

IO_L06N_4_VREF_4_W18

IO_L06P_4_Y18

IO_L09N_4_AA18

IO_L09P_4_AB18

IO_L10N_4_V17

IO_L10P_4_W17

IO_L15N_4_Y17

IO_L15P_4_AA17

IO_L16N_4_V16

IO_L16P_4_W16

IO_L19N_4_AA16

IO_L19P_4_AB16

IO_L22N_4_VREF_4_V15

IO_L22P_4_W15

IO_L24N_4_AA15

IO_L24P_4_AB15

IO_L25N_4_U14

IO_L25P_4_V14

IO_L27N_4_DIN_D0_AA14

IO_L27P_4_D1_AB14

IO_L28N_4_U13

IO_L28P_4_V13

IO_L29N_4_Y13

IO_L29P_4_AA13

IO_L30N_4_D2_U12

IO_L30P_4_D3_V12

IO_L31N_4_INIT_B_W12

IO_L31P_4_DOUT_BUSY_Y12

IO_L01N_4_VRP_4_AA20

IO_L01P_4_VRN_4_AB20

IO_L32N_4_GCLK1_AA12

IO_L32P_4_GCLK0_AB12

VCCO_5_T9

VCCO_5_T10

VCCO_5_T11

VCCO_5_U8

VCCO_5_Y8

IO_U7

IO_U9

IO_U10

IO_U11

IO_V7

IO_V10

IO_VREF_5_U6

IO_VREF_5_AB11

IO_L01N_5_RDWR_B_Y4

IO_L01P_5_CS_B_AA3

IO_L06N_5_AB4

IO_L06P_5_AA4

IO_L09N_5_Y5

IO_L09P_5_W5

IO_L15N_5_W6

IO_L15P_5_V6

IO_L16N_5_AA6

IO_L16P_5_Y6

IO_L19N_5_Y7

IO_L19P_5_VREF_5_W7

IO_L22N_5_AB7

IO_L22P_5_AA7

IO_L24N_5_W8

IO_L24P_5_V8

IO_L25N_5_AB8

IO_L25P_5_AA8

IO_L27N_5_VREF_5_W9

IO_L27P_5_V9

IO_L28N_5_D6_AB9

IO_L28P_5_D7_AA9

IO_L29N_5_Y10

IO_L29P_5_VREF_5_W10

IO_L30N_5_AB10

IO_L30P_5_AA10

IO_L31N_5_D4_W11

IO_L31P_5_D5_V11

IO_L32N_5_GCLK3_AA11

IO_L32P_5_GCLK2_Y11

IO_L10N_5_VRP_5_AB5

IO_L10P_5_VRN_5_AA5

FPGAFPGA

1299-27-2005_1144

T12

T13

T14

U15

Y15

U16

U17

W13

W14

V18

Y16

AB13

AA19

AB19

W18

Y18

AA18

AB18

V17

W17

Y17

AA17

V16

W16

AA16

AB16

V15

W15

AA15

AB15

U14

V14

AA14

AB14

U13

V13

Y13

AA13

U12

V12

W12

Y12

AA20

AB20

AA12

AB12

T9

T10

T11

U8

Y8

U7

U9

U10

U11

V7

V10

U6

AB11

Y4

AA3

AB4

AA4

Y5

W5

W6

V6

AA6

Y6

Y7

W7

AB7

AA7

W8

V8

AB8

AA8

W9

V9

AB9

AA9

Y10

W10

AB10

AA10

W11

V11

AA11

Y11

AB5

AA5

U1

FG456XC3S1000

7

2

4

8

10

6

3

9

11

13

15

17

19

21

23

25

12

14

16

24

26

22

20

18

1

5

P16

IDC13X213X2

5

1

18

20

22

26

24

16

14

12

25

23

21

19

17

15

13

11

9

3

6

10

8

4

2

7

P17

IDC13X213X2

R46

060310K

R43

0603DNP

FPGA BANKS 4 + 5

VCCO_5

CONFIG_INIT_B_TFS1

CLK_OUT_EXP1

B4_L32N_GCKL1_AA12

R9

06030

B5_L10N_VRP_AB5_J3_9

B5_L10N_VRP_AB5_J3_9

B5_L10P_VRN_AA5_J3_10

VCCO_5

B5_L32P_GCLK2_Y1

B5_L32N_GCLK3_AA11_J3_30

CONFIG_DIN_DT1PRI

UDEF16

UDEF38

UDEF14

RX0

TX0

RX1

TX1

UDEF20

UDEF21

UDEF23

UDEF17

UDEF25

UDEF24

UDEF22

RESET

UDEF30

UDEF29

UDEF27

UDEF26

UDEF35

UDEF34

UDEF33

UDEF32

UDEF31

UDEF15

UDEF28

UDEF41

UDEF40

UDEF39

UDEF37

UDEF36

BR

UDEF43

BG

BGH

UDEF19

B5_L31P_D5_V11_J3_40

B5_L31N_D4_W11_J3_39

B5_L30P_AA10_J3_38

B5_L30N_AB10_J3_37

B5_L29P_W10_J3_36

B5_L29N_Y10_J3_35

B5_L28P_D7_AA9_J3_34

B5_L28N_D6_AB9_J3_33

B5_L27P_V9_J3_32

B5_L27N_W9_J3_31

B5_L25P_AA8_J3_22

B5_L25N_AB8_J3_21

B5_L24P_V8_J3_20

B5_L24N_W8_J3_19

B5_L22P_AA7_J3_18

B5_L22N_AB7_J3_17

B5_L19P_W7_J3_16

B5_L19N_Y7_J3_15

B5_L16P_Y6_J3_14

B5_L16N_AA6_J3_13

B5_L15P_V6_J3_12

B5_L15N_W6_J3_11

B5_L09P_W5_J3_8

B5_L09N_Y5_J3_7

B5_L06P_AA4_J3_6

B5_L06N_AB4_J3_5

B5_L01P_CS_B_AA3_J3_2

B5_L01N_RDWR_B_Y4_J3_1

B5_AB11_J3_90

B5_U6_J3_23

B5_V10_J3_85

B5_V7_J3_29

B5_U11_J3_83

B5_U10_J3_81

B5_U9_J3_41

B5_U7_J3_28

UDEF18

3

2

1

3X1IDC3X1

P11

B5_L29N_Y10_J3_35

B5_L30N_AB10_J3_37

B5_L31N_D4_W11_J3_39

B5_U11_J3_83

B5_V10_J3_85B5_AB11_J3_90

B5_U10_J3_81

B5_L31P_D5_V11_J3_40

B5_L30P_AA10_J3_38

B5_L29P_W10_J3_36

B5_L28P_D7_AA9_J3_34

B5_L27P_V9_J3_32

B5_L28N_D6_AB9_J3_33

B5_L27N_W9_J3_31

B5_L25N_AB8_J3_21B5_L25P_AA8_J3_22

B5_L24N_W8_J3_19B5_L24P_V8_J3_20

B5_U9_J3_41B5_U6_J3_23

VCCO_5

B5_L10P_VRN_AA5_J3_10

C70

0603001UF 001UF

0603

C69 C68

0603001UF001UF

0603

C67001UF0603

C66 C65

0603001UF 001UF

0603

C64C63

0603001UF

B5_L09N_Y5_J3_7

B5_U7_J3_28 B5_V7_J3_29

B5_L10P_VRN_AA5_J3_10 B5_L10N_VRP_AB5_J3_9

B5_L15P_V6_J3_12 B5_L15N_W6_J3_11

B5_L16P_Y6_J3_14 B5_L16N_AA6_J3_13

B5_L19P_W7_J3_16 B5_L19N_Y7_J3_15

B5_L22P_AA7_J3_18 B5_L22N_AB7_J3_17

B5_L32N_GCLK3_AA11_J3_30 B5_L32P_GCLK2_Y1

B5_L01P_CS_B_AA3_J3_2 B5_L01N_RDWR_B_Y4_J3_1

B5_L06P_AA4_J3_6 B5_L06N_AB4_J3_5

B5_L09P_W5_J3_8

VCCO_5

DNP0603

R45

25V

33V

33V

4

3

2

1

A B C D

20 Cotton Road

Nashua NH 03063

A B C D

4

3

2

1

PH 1-800-ANALOGD

C

Title

Size Board No

Date Sheet of

DEVICESANALOG

DNP = Do Not Populate

Rev

BLACKFIN FPGA EZ-EXTENDER

A0199-2005 10

SN74LVC1G125

12109-27-2005_1144

2 4

1

SOT23-5SN74LVC1G125

U8

USER IO

C80

0603001UF

SW4SWT013SPST-MOMENTARY

SPST-MOMENTARYSWT013SW3

060310R42

C5

06031UF

R413300603

LED001AMBER-SMTLED8

0603330R40

LED7AMBER-SMTLED001

R393300603

R1033006030603

330R34R35

33006030603

330R36

0603330R37 R38

3300603

LED001AMBER-SMTLED2

AMBER-SMTLED001

LED3AMBER-SMTLED001

LED4AMBER-SMTLED001

LED5

LED001AMBER-SMTLED6

LED9GREEN-SMTLED001

402100R23

1 2

3 4

5 6

7 8

JP5

IDC4X24X2

AMBER-SMTLED001

LED1

B6_L01N_Y3

B6_L01P_Y2

B5_U10_J3_81

B5_AB11_J3_90

PB2

B5_V10_J3_85

B5_U11_J3_83

B5_L31N_D4_W11_J3_39

B5_L30N_AB10_J3_37

B5_L29N_Y10_J3_35

B5_L28N_D6_AB9_J3_33

B5_L27N_W9_J3_31

PB1

B5_L25N_AB8_J3_21

R47

060310K

CHOKE_COIL

4

3

2

1

A B C D

20 Cotton Road

Nashua NH 03063

A B C D

4

3

2

1

PH 1-800-ANALOGD

C

Title

Size Board No

Date Sheet of

DEVICESANALOG

DNP = Do Not Populate

Rev

BLACKFIN FPGA EZ-EXTENDER

A0199-2005 10

25V

33V

VIN

EN

SW

GND

FB

VIN

EN

SW

GND

FB

VIN

EN

SW

GND

FB

4

3

5

2

1

VR3

SOT23-5LM3475MF

1

2

5

3

4

VR2

SOT23-5LM3475MF

4

3

5

2

1

VR1

SOT23-5LM3475MF

12119-27-2005_1124

1

32

Q2

SI2

343D

SS

OT

23D

1

32

Q3

SI2

343D

SS

OT

23D

2 3

1S

I234

3DS

Q1

SO

T23

D

316KR17

0603

215KR18

0603

0603

R11105K

DNPC73

0603

0603

C72DNP

805

C741000PF

0R58

0603

1000PFC10

805

0603

R1910K

C100UFCT2

CT3100UFC

IND005

L110UH

10UHL3

IND005

10UHL2

IND005

1

2 D3

DO214ABSCHOT_RECT

3A

0603

R20200K

805

C639NF

390PFC7

0603

2

1 3A

SCHOT_RECTDO214AB

D2

499KR13

0603

1

2 D1

DO214ABSCHOT_RECT

3A

33V_EI

3

1

2

3X1IDC3X1

P13

UNREG_IN

12V

CT1100UFC

80510UFC71

R1200603

5V_EI

8051000PFC2

FER2

0603

060301UFC3

POWER

FUS00125AF1

4

1

3

2

FER1

DO-214AA

S2A_RECT

2AD5

8051000PFC1 C4

10UFC

3

1

2

3X1IDC3X1

P12

UNREG_IN

1

2

3

CON00525MM_JACK

POWER

J4

2

1P42

IDC2X12X1DNP

1

2

DNP2X1IDC2X1

P43

06030R15

C810UF805

80510UFC9

R1600603

UNREG_IN

0603

R1410K

0603

R590

4

3

2

1

A B C D

20 Cotton Road

Nashua NH 03063

A B C D

4

3

2

1

PH 1-800-ANALOGD

C

Title

Size Board No

Date Sheet of

DEVICESANALOG

DNP = Do Not Populate

Rev

BLACKFIN FPGA EZ-EXTENDER

A0199-2005 1012129-14-2005_1204

5

2

4

8

10

6

1

3

9

11

13

15

17

19

12

14

16

20

18

7

P20

SOIC20

PROTO AREA

1

3

2

SOT23D

P39

2

3

1

SOT23D

P38

2

4

5 6

3

1

SOT23-6

P411

3

65

4

2

SOT23-6

P40

PRT_NUM=DNE

11

13

15 16

14

12

2

4

6

8

109

7

5

3

1

SOIC16

P191

3

5

7

9 10

8

6

4

2

12

14

1615

13

11

SOIC16

P18

21P37

805

1 2

805

P36

21P35

805

1 2

805

P34

1 2

805

P33

21P32

805

1 2

805

P31

21P30

805

1 2

805

P29

21P28

805

1 2

805

P27

21P26

805

21P25

805

1 2

805

P24

21P23

805

1 2

805

P22

TP86

TP85

TP84

TP83

TP82

TP81

TP80

TP79 TP77

TP76

TP75

TP74

TP73

TP72

TP71

TP70

TP68

TP67

TP66

TP65

TP64

TP62

TP61

TP60

TP59

TP58

TP57

TP56

TP55

TP54

TP53

TP51

TP50

TP49

TP48

TP47

TP46

TP45

TP44

TP43

TP41

TP40

TP39

TP38

TP37

TP36

TP35

TP34

TP33

TP32

TP30

TP29

TP28

TP27

TP26

TP25

TP24

TP23

TP22

TP21

TP19

TP18

TP17

TP16

TP15

TP14

TP13

TP12

TP11

TP9

TP8

TP7

TP6

TP5

TP4

TP125

TP124

TP123

TP122

TP121

TP120

TP119

TP118

TP117

TP116

TP114

TP113

TP112

TP111

TP110

TP109

TP108

TP107TP106

TP105TP103

TP102TP101 TP100TP99

TP98 TP97

TP96 TP95

TP94TP93

TP92TP91

TP90 TP89

TP88 TP87

TP78TP69

TP63 TP52

TP42 TP31

TP20 TP10

TP115TP104

7

18

20

16

14

12

19

17

15

13

11

9

3

1

6

10

8

4

2

5

SOIC20

P21

I INDEX

Numerics connectors

25V header (P42) 2-17

AADSP-BF5333761 EZ-KIT Lite interface 2-1ADSP-BF5333761 processors boot mode

settings 2-14architecture of this EZ-Extender 2-2asynchronous static random access memory

(SRAM) xauxiliary oscillator x

Bbill of materials A-1block diagram of this EZ-Extender 2-2boot jumper See JP4

Cconfiguration jumpers See JP2 JP3

map of locations 2-18J1-3 (expansion) 2-19P1-3 (expansion) 2-19P14 (IDC) 2-19P15 (JTAG header) 2-4P16-17 (IDC) 2-19P4 (high-speed) 2-20P5 (IDC) 2-20P6 (JTAG) 2-7P7 (IDC) 2-20P8 (IDC) 2-19

customer support xiii

Ddone LED (LED10) 2-17

Eexpansion interface

connectors (P1-3 J1-3) 2-19of ADSP-BF5333761 EZ-KIT Lites ix

1-3external power supply 1-3 2-8

FField-Programmable Gate Array See FPGA

Blackfin FPGA EZ-Extender Manual I-1

INDEX

FPGAdocumentation 1-2input jumpers (JP5) 2-14softwarefirmware 1-2Xilinx Spartan package x 1-3

FPGA pinsAB10 (LED3) 2-17AB11 (JP58) 2-15AB8 (LED7) 2-17AB9 (LED5) 2-17C11 (PB1SW3) 2-15H5 (PB2SW3) 2-16M2-0 (JP4) 2-14U10 (JP56) 2-15U11 (LED1) 2-17V10 (LED8) 2-17W11 (LED2) 2-17W9 (LED6) 2-17Y10 (LED4) 2-17Y3-2 (JP52-54) 2-15

FPGA programmingblock diagram 2-3via ADSP-BF533376 processors 2-6via JTAG header 2-4via serial ROM 2-5

GGCLK1 (global clock 1) pin 1-4GCLK6 (global clock 6) pin 1-4general-purpose input push buttons 2-15 2-16

Hhigh-speed connector (P4) 2-20

IIDC connectors x 2-19 2-20installation of this EZ-Extender 1-1

JJTAG

cable 1-4 2-7header (P6) 1-5 2-4 2-7 2-14

jumpersmap of locations 2-11JP1 (boot jumper) 2-5 2-12JP2 (confug done) 2-12JP3 (config program) 2-13JP41-46 (boot mode select) 2-5 2-6 2-14JP52-56 (FPGA input) 2-14

LLEDs

map of locations 2-15LED10 (FPGA done pin) 2-4 2-5 2-17LED1-8 (status) 2-17LED9 (power) 2-17

MM2-0 (JP4) pins 2-5master serial boot mode 2-6MCS-86 Hexadecimal Object (mcs) file

format 2-6

Nnotation conventions xvi

Ooscillator x 1-4

PP12 (power in) header 2-9P13 (33V header) 2-9P42 (25V header) 2-10P43 (12V header) 2-10PB1 push button (SW3) 2-15

I-2 Blackfin FPGA EZ-Extender Manual

INDEX

PB2 push button (SW4) 2-16PF14 flag pin (ADSP-BF537 EZ-KIT Lite)

2-12PF3 flag pin (ADSP-BF53361 EZ-KIT Lite)

2-12power

12V header (P43) 2-1025V header (P42) 2-1033V header (P13) 2-9in header (P12) 2-9LED (LED9) 2-17limitations 2-8supplies 1-3 2-8

printed circuit board (PCB) 1-2product overview ixprogram push button (SW1) 2-4 2-15push buttons

See also SWx map of locations 2-15

Sserial ROM 1-5

boot jumper (JP1) 2-12 2-14programming via JTAG Header 2-7

setup of this EZ-Extender 1-1slave serial mode 2-6

SRAM memory banks 1-4status reporting 1-4 2-17SW1 (program) push button 2-4 2-15SW3 (PB1) push button 2-15SW4 (PB2) push button 2-16switching regulators 2-8

TTCK signal 2-7TDI signal 2-7TDO signal 2-7TMS signal 2-7

VVisualDSP++

flash programming utility 1-4 2-6FPGA documentation 2-6

VR1-3 regulators 2-8

XXilinx

JTAG cablesoftware 1-4 2-4 2-7JTAG header 2-12serial ROM 1-5

Blackfin FPGA EZ-Extender Manual I-3

INDEX

I-4 Blackfin FPGA EZ-Extender Manual

• Blackfin FPGA EZ-Extender Manual
• Contents
• Preface
• • Product Overview
  • Purpose of This Manual
  • Intended Audience
  • Manual Contents
  • Whatrsquos New in This Manual
  • Technical or Customer Support
  • Supported Products
  • Product Information
  • • Related Documents
    • • Table 1 Related Processor Publications
      • Table 2 Related VisualDSP++ Publications
      • • Notation Conventions
        • • 1 FPGA EZ-Extender Interfaces
          • • FPGA EZ-Extender Setup
            • • Figure 1-1 FPGA EZ-Extender Setup
              • • FPGA Software and Firmware
                • FPGA EZ-Extender Overview
                • • 2 FPGA EZ-Extender Hardware Reference
                  • • System Architecture
                    • • Figure 2-1 Block Diagram
                      • • Programming the FPGA
                        • • Figure 2-2 FPGA Programming Block Diagram
                          • FPGA Programming via JTAG
                          • • Table 2-1 P15 Connections for PFGA Programming via JTAG
                            • Table 2-2 JP1 Settings for FPGA Programming via JTAG
                            • Table 2-3 JP4 Settings for FPGA Programming via JTAG
                            • • FPGA Programming via Serial ROM
                              • • Table 2-4 JP1 Settings for FPGA Programming via Serial ROM
                                • Table 2-5 JP4 Settings for FPGA Programming in Master Serial Mode
                                • • FPGA Programming via Blackfin Application
                                  • • Table 2-6 JP1 Settings for FPGA Programming via Blackfin Processor
                                    • Table 2-7 JP4 Settings for FPGA Programming via Blackfin Processor
                                    • • Programming the Serial ROM
                                      • • Serial ROM via JTAG Header
                                        • • Table 2-8 P6 Connections for Serial ROM
                                          • • Power
                                            • • Table 2-9 Power Limitations
                                              • Power In Header (P12)
                                              • 33V Header (P13)
                                              • 25V Header (P42)
                                              • 12V Header (P43)
                                              • • Jumpers
                                                • • Figure 2-3 Jumper Locations
                                                  • Serial ROM Boot Jumper (JP1)
                                                  • • Table 2-10 JP1 Settings
                                                    • • Config Done Jumper (JP2)
                                                      • • Table 2-11 JP2 Settings
                                                        • • Config Program Jumper (JP3)
                                                          • • Table 2-12 JP3 Settings
                                                            • • Boot Jumper (JP4)
                                                              • • Table 2-13 JP4 Settings
                                                                • • FPGA Input Jumpers (JP5)
                                                                  • • Table 2-14 JP5 Settings
                                                                    • • Push Buttons and LEDs
                                                                      • • Figure 2-4 Push Button and LED Locations
                                                                        • Program Push Button (SW1)
                                                                        • PB1 Push Button (SW3)
                                                                        • PB2 Push Button (SW4)
                                                                        • Status LEDs (LED1-8)
                                                                        • • Table 2-15 Status LED (LED1-8) Settings
                                                                          • • Power LED (LED9)
                                                                            • Done LED (LED10)
                                                                            • • Connectors
                                                                              • • Figure 2-5 Connector Locations
                                                                                • Expansion Interface (P1-3 and J1-3)
                                                                                • IDC Connectors (P8 P14 P16 and P17)
                                                                                • IDC Connectors (P5 and P7)
                                                                                • High-Speed Connector (P4)
                                                                                • • A Bill Of Materials
                                                                                  • B Schematics
                                                                                  • • Title
                                                                                    • FPGA Config
                                                                                    • SRAM FPGA Banks 7 and 8
                                                                                    • Expansion Interface Connector 1
                                                                                    • FPGA Banks 0 and 1
                                                                                    • Expansion Interface Connectors 2
                                                                                    • FPGA Banks 2 and 3
                                                                                    • Expansion Interface Connector 1
                                                                                    • FPGA Banks 4 and 5
                                                                                    • User IO
                                                                                    • Power
                                                                                    • Proto Area
                                                                                    • • I Index
                                                                                      • • Numerics
                                                                                        • A
                                                                                        • B
                                                                                        • C
                                                                                        • D
                                                                                        • E
                                                                                        • F
                                                                                        • G
                                                                                        • H
                                                                                        • I
                                                                                        • J
                                                                                        • L
                                                                                        • M
                                                                                        • N
                                                                                        • O
                                                                                        • P
                                                                                        • S
                                                                                        • T
                                                                                        • V
                                                                                        • X

211

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2A_R

EC

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A

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ICO

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TIF

IER

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VIS

HA

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A

221

39N

F 50

V 5

8

05C

6PA

NA

SON

ICE

CH

-U1C

392J

B5

231

190

100M

HZ

5A

FE

R00

2 FE

R1

MU

RA

TA

DLW

5BSN

191S

Q2

247

10U

F 6

3V 1

0 8

05X

7R

C14

-16

C35

C55

C83

C

86AV

X08

0560

106K

AT

2A

254

1000

PF

10V

20

805

C

1-2

C10

C74

YA

GE

O12

06C

G22

9C9B

200

263

100U

F 10

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0 C

TA

NT

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SRC

T1-

3A

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TP

SC10

7K01

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75

275

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F 16

V 1

0 0

603

X7R

C3

C38

C56

C84

-85

AVX

0603

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104K

AT

2A

2856

001

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16V

10

060

3

X7R

C11

-13

C17

-34

C36

-37

C39

-54

C57

-70

C80

-82

AVX

0603

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103K

AT

2A

291

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16V

10

060

3C

5PA

NA

SON

ICE

CJ-

1VB

1C10

5K

303

10U

H 1

7 20

I

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005

L1-

3C

OIL

CR

AFT

MSS

1278

-103

MX

B

318

10K

11

0W 5

0

603

R1

R6

R21

-22

R28

-29

R46

-47

PAN

ASO

NIC

ER

J-3G

EY

J103

V

3210

330

110

W 5

0

603

R10

R24

R34

-41

VIS

HA

YC

RC

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Part

Num

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A-4 Blackfin FPGA EZ-Extender Manual

Bill Of Materials

339

0 1

10W

5

060

3R

3-4

R9

R12

R15

-16

R27

R58

-59

PAN

ASO

NIC

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J-3G

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341

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5

060

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42PA

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ICE

RJ-

3GE

YJ1

00V

351

200K

11

6W 1

0

603

R20

VIS

HA

YC

RC

W06

0320

03FR

T1

362

10K

11

0W 1

0

603

R14

R19

PAN

ASO

NIC

P10

0K

HT

R-N

D

372

33 1

10W

1

060

3 R

2R

26Y

AG

EO

9C06

031A

33R

0FK

HFT

385

100

116

W 5

4

02R

5R

7-8

R23

R44

PAN

ASO

NIC

ER

J-2G

EJ1

01X

391

390P

F 25

V 5

0

603

NP

OC

7A

VX

0603

3A39

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401

499

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3R

13ST

AC

KP

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MC

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411

316

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060

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17PA

NA

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RJ-

3EK

F316

2V

421

105

K 1

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1

060

3 R

11PA

NA

SON

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RJ-

3EK

F105

1V

431

215

K 1

16W

1

060

3R

18PA

NA

SON

ICE

RJ-

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F215

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441

GR

EE

N-S

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UL

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D9

PAN

ASO

NIC

LN

1361

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453

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Blackfin FPGA EZ-Extender Manual A-5

465

IDC

3X

1 ID

C3X

1P

9-13

BE

RG

5410

1-T

08-0

3

471

IDC

3X

2 ID

C3X

2JP

4B

ER

G54

102-

T08

-03

481

IDC

4X

2 ID

C4X

2JP

5SU

LL

INS

S201

2-04

494

IDC

13X

2 ID

C13

X2

P

8P

14P

16-1

7B

ER

G54

102-

T08

-13

501

25A

RE

SET

AB

LE

FU

S001

F1R

AY

CH

EM

CO

RP

SMD

250-

2

513

10U

F 10

V 1

0 8

05C

8 C

9 C

71PA

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CJ-

2FB

1A10

6K

Ref

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Part

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A-6 Blackfin FPGA EZ-Extender Manual

4

3

2

1

A B C D

20 Cotton Road

Nashua NH 03063

A B C D

4

3

2

1

PH 1-800-ANALOGD

C

Title

Size Board No

Date Sheet of

DEVICESANALOG

DNP = Do Not Populate

Rev

BLACKFIN FPGA EZ-EXTENDER

A0199-2005 10

SchematicBLACKFIN FPGA EZ-EXTENDER

1219-9-2005_1040

TITLE

33V

4

3

2

1

A B C D

20 Cotton Road

Nashua NH 03063

A B C D

4

3

2

1

PH 1-800-ANALOGD

C

Title

Size Board No

Date Sheet of

DEVICESANALOG

DNP = Do Not Populate

Rev

BLACKFIN FPGA EZ-EXTENDER

A0199-2005 10

33V

1A

1B

1Y

2A

2B

2Y

3A

3B

3Y

4A

4B

4Y

~AB

EN

25V

33V

33V

33V

33V

33V

25V

33V

OENC OUTOE OUT

CLK

D0

TMS

TCK

TDI

TDO

VCCINT

VCCO

VCCJ

NC1

NC2

NC3

NC4

NC5

NC6

GND

CE

CF

OE~RESET

CEO

VCCAUX_A6

VCCAUX_A17

VCCAUX_F1

VCCAUX_F22

VCCAUX_U1

VCCAUX_U22

VCCAUX_AB6

VCCAUX_AB17

VCCINT_G7

VCCINT_G8

VCCINT_G15

VCCINT_G16

VCCINT_H7

VCCINT_H16

VCCINT_R7

VCCINT_R16

VCCINT_T7

VCCINT_T8

VCCINT_T15

VCCINT_T16

TCK

TDI

TDO

TMS

M0

M1

M2

CCLK

PROG_B

DONE

HSWAP_EN

GND_A1

GND_A22

GND_B2

GND_B21

GND_C9

GND_C14

GND_J3

GND_J9

GND_J10

GND_J11

GND_J12

GND_J13

GND_J14

GND_J20

GND_K9

GND_K10

GND_K11

GND_K12

GND_K13

GND_K14

GND_L9

GND_L10

GND_L11

GND_L12

GND_L13

GND_L14

GND_M9

GND_M10

GND_M11

GND_M12

GND_M13

GND_M14

GND_N9

GND_N10

GND_N11

GND_N12

GND_N13

GND_N14

GND_P3

GND_P9

GND_P10

GND_P11

GND_P12

GND_P13

GND_P14

GND_P20

GND_Y9

GND_Y14

GND_AA2

GND_AA21

GND_AB1

GND_AB22

FPGAFPGA

EXTRA CLOCK SOCKET25MHZ SYSTEM CLOCK

FPGA JTAG HEADER

FLASH JTAG HEADER

BOOTMODE JUMPER

FPGA BOOT FLASH(2Mbit)

MUXFLASHSKTOSC

9-27-2005_1144 2 12

A6

A17

F1

F22

U1

U22

AB6

AB17

G7

G8

G15

G16

H7

H16

R7

R16

T7

T8

T15

T16

A21

B1

B22

A20

AB2

AA1

AB3

AA22

A2

AB21

B3

A1

A22

B2

B21

C9

C14

J3

J9

J10

J11

J12

J13

J14

J20

K9

K10

K11

K12

K13

K14

L9

L10

L11

L12

L13

L14

M9

M10

M11

M12

M13

M14

N9

N10

N11

N12

N13

N14

P3

P9

P10

P11

P12

P13

P14

P20

Y9

Y14

AA2

AA21

AB1

AB22

U1

FG456XC3S1000

CONFIG_PROG_B

6

5

4

3

2

1P6

IDC6X16X1

1

2

3

4

5

6

P15

IDC6X16X1

3

1

8

10

7

13

5

6

4

17

18

19

20

2

9

12

14

15

16

11

U4

TSSOP20XCF04S

2

4

5 6

3

1JP4

IDC3X23X2

402100R5

R400603

402100R44

R8100402

R7100402

1 3

U6

25MHZOSC003

80510UFC14

R29

060310K

R22

060310K

R21

060310K

R1

060310K

1 5

U7

DIPDIP8SOC

R263306030603

33R2

R25

DNP

10K0603

12V

1 2JP1

IDC2X12X1

CONFIG_DONER3

06030

CONFIG_CLK_TSCLK1

FPGA_TMS

FPGA_TDO

FPGA_TCK

FPGA_TDI

FPGA_TCK

FPGA_TDO

FPGA_TDI

FPGA_TMS

FLASH_TMS

FLASH_TDI

FLASH_TDO

FLASH_TCK

M1

M2

M0

12V

SPST-MOMENTARYSWT013SW1

2

3

4

5

6

7

11

10

9

14

13

12

1

15

U2

TSSOP1674LVC157

CONFIG_DONE

FLASH_TMS

FLASH_TCK

FLASH_TDI

FLASH_TDO

M2

M0

M1

FPGA CONFIG

CONFIG_INIT_B_TFS1

FLASH_DOUT

CONFIG_CLK_TSCLK1

FLASH_DONE

001UF0603

C18

IO_L32_0_GCLK6_A11B4_L32N_GCKL1_AA12

C19

0603001UF 001UF

0603

C20 C21

0603001UF 001UF

0603

C25C24

0603001UF001UF

0603

C23C22

0603001UF 001UF

0603

C31 C30

0603001UF 001UF

0603

C29 C28

0603001UF001UF

0603

C27C26

0603001UF

001UF0603

C32 C11

0603001UF 001UF

0603

C12 C13

0603001UF

80510UFC15 C16

10UF805

C17

0603001UF

0603330R24

LED10

LED001AMBER-SMT

CONFIG_DIN_DT1PRI

FLASH_DONE

FLASH_DOUT

DT1PRI

R6

060310K10K

0603

R28

33V 33V

4

3

2

1

A B C D

20 Cotton Road

Nashua NH 03063

A B C D

4

3

2

1

PH 1-800-ANALOGD

C

Title

Size Board No

Date Sheet of

DEVICESANALOG

DNP = Do Not Populate

Rev

BLACKFIN FPGA EZ-EXTENDER

A0199-2005 10

33V

33V

A18

A1

A10

A11

A12

A13

A14

A16

A2

A3

A4

A5

A6

A7

A8

A9

D0

D1

D10

D11

D2

D3

D4

D5

D6

D7

D8

D9

BHE

BLE

CE

OE

WE

A17

D15

D14

D13

D12

A0

A15

A18

A1

A10

A11

A12

A13

A14

A16

A2

A3

A4

A5

A6

A7

A8

A9

D0

D1

D10

D11

D2

D3

D4

D5

D6

D7

D8

D9

BHE

BLE

CE

OE

WE

A17

D15

D14

D13

D12

A0

A15

VCCO_6_M7

VCCO_6_N7

VCCO_6_P7

VCCO_6_R3

VCCO_6_R6

IO_Y1

IO_L16N_6_W4

IO_L16P_6_W3

IO_L17N_6_W2

IO_L17P_6_VREF_6_W1

IO_L19N_6_V5

IO_L19P_6_U5

IO_L20N_6_V4

IO_L20P_6_V3

IO_L21N_6_V2

IO_L21P_6_V1

IO_L22N_6_T6

IO_L22P_6_T5

IO_L23N_6_U4

IO_L23P_6_T4

IO_L24N_6_VREF_6_U3

IO_L24P_6_U2

IO_L26N_6_T3

IO_L26P_6_R4

IO_L27N_6_T2

IO_L27P_6_T1

IO_L28N_6_R5

IO_L28P_6_P6

IO_L29N_6_R2

IO_L29P_6_R1

IO_L31N_6_P5

IO_L31P_6_P4

IO_L32N_6_P2

IO_L32P_6_P1

IO_L33N_6_N6

IO_L33P_6_N5

IO_L34N_6_VREF_6_N4

IO_L34P_6_N3

IO_L35N_6_N2

IO_L35P_6_N1

IO_L38N_6_M6

IO_L38P_6_M5

IO_L39N_6_M4

IO_L39P_6_M3

IO_L40N_6_M2

IO_L40P_6_VREF_6_M1

IO_L01N_6_VRP_6_Y3

IO_L01P_6_VRN_6_Y2

VCCO_7_H3

VCCO_7_H6

VCCO_7_J7

VCCO_7_K7

VCCO_7_L7

IO_C2

IO_L16N_7_D1

IO_L16P_7_VREF_7_C1

IO_L17N_7_E4

IO_L17P_7_D4

IO_L19N_7_VREF_7_D3

IO_L19P_7_D2

IO_L20N_7_F4

IO_L20P_7_E3

IO_L21N_7_E1

IO_L21P_7_E2

IO_L22N_7_G6

IO_L22P_7_F5

IO_L23N_7_F2

IO_L23P_7_F3

IO_L24N_7_H5

IO_L24P_7_G5

IO_L26N_7_G3

IO_L26P_7_G4

IO_L27N_7_G1

IO_L27P_7_VREF_7_G2

IO_L28N_7_H1

IO_L28P_7_H2

IO_L29N_7_J4

IO_L29P_7_H4

IO_L31N_7_J5

IO_L31P_7_J6

IO_L32N_7_J1

IO_L32P_7_J2

IO_L33N_7_K5

IO_L33P_7_K6

IO_L34N_7_K3

IO_L34P_7_K4

IO_L35N_7_K1

IO_L35P_7_K2

IO_L38N_7_L5

IO_L38P_7_L6

IO_L39N_7_L3

IO_L39P_7_L4

IO_L40N_7_VREF_7_L1

IO_L40P_7_L2

IO_L01N_7_VRP_7_C3

IO_L01P_7_VRN_7_C4

(512k x 16bits x 2chips)2MBYTES FPGA SRAM

FPGASRAM SRAM

SRAM_A9

9-27-2005_1144 3 12

FLASH_TDO

FLASH_TMS

FLASH_TDI

FLASH_TCK

M7

N7

P7

R3

R6

Y1

W4

W3

W2

W1

V5

U5

V4

V3

V2

V1

T6

T5

U4

T4

U3

U2

T3

R4

T2

T1

R5

P6

R2

R1

P5

P4

P2

P1

N6

N5

N4

N3

N2

N1

M6

M5

M4

M3

M2

M1

Y3

Y2

H3

H6

J7

K7

L7

C2

D1

C1

E4

D4

D3

D2

F4

E3

E1

E2

G6

F5

F2

F3

H5

G5

G3

G4

G1

G2

H1

H2

J4

H4

J5

J6

J1

J2

K5

K6

K3

K4

K1

K2

L5

L6

L3

L4

L1

L2

C3

C4

U1

FG456XC3S1000

28

2

23

24

25

26

27

43

3

4

5

18

19

20

21

22

7

8

31

32

9

10

13

14

15

16

29

30

40

39

6

41

17

44

38

37

36

35

1

42

U3

TSOP44IS61LV51216

42

1

35

36

37

38

44

17

41

6

39

40

30

29

16

15

14

13

10

9

32

31

8

7

22

21

20

19

18

5

4

3

43

27

26

25

24

23

2

28

U5

TSOP44IS61LV51216

SRAM_D7

SRAM_D6

SRAM_D3

SRAM_D2

SRAM_D0

SRAM_D8

SRAM_D9

SRAM_D5

SRAM_D4

SRAM_D13

SRAM_D1

SRAM_D10

SRAM_D11

SRAM_D12

SRAM_D14

SRAM_D15

SRAM_CE

SRAM_A7

SRAM_A0

SRAM_A5

SRAM_A3

SRAM_A1

SRAM_WE

SRAM_A8

SRAM_A6

SRAM_A4

SRAM_A2

SRAM_A17

SRAM_OE

SRAM_A12

SRAM_A13

SRAM_A15

SRAM_A16

SRAM_A14

SRAM_A18

SRAM_A11

SRAM_A10

SRAM_D22

SRAM_D20

SRAM_D18

SRAM_D17

SRAM_D16

SRAM_D26

SRAM_D21

SRAM_D24

SRAM_D19

SRAM_D31

SRAM_D25

SRAM_D27

SRAM_D28

SRAM_D30

SRAM_D29

PB2

A11

A5

D1

A15

A3

A9

D13

D7

A13

A19

A7

A1

A18

A6

A2

A12

D6

A8

A14

D2

D0

A10

A4

D3

A16

SRAM FPGA BANKS 7 + 8

SRAM_CE

SRAM_WE

SRAM_OE

SRAM_A18

SRAM_A0 SRAM_D0

SRAM_D1

SRAM_D2

SRAM_D3

SRAM_D4

SRAM_D5

SRAM_D6

SRAM_D7

SRAM_D8

SRAM_D9

SRAM_D10

SRAM_D11

SRAM_D12

SRAM_D13

SRAM_D14

SRAM_D15

SRAM_D16

SRAM_D17

SRAM_D18

SRAM_D19

SRAM_D20

SRAM_D21

SRAM_D22

SRAM_D23

SRAM_D24

SRAM_D25

SRAM_D26

SRAM_D27

SRAM_D28

SRAM_D29

SRAM_D30

SRAM_D31

SRAM_A1

SRAM_A2

SRAM_A3

SRAM_A4

SRAM_A5

SRAM_A6

SRAM_A7

SRAM_A8

SRAM_A9

SRAM_A10

SRAM_A11

SRAM_A12

SRAM_A13

SRAM_A14

SRAM_A15

SRAM_A16

SRAM_A17

SRAM_A1

SRAM_A2

SRAM_A3

SRAM_A4

SRAM_A5

SRAM_A6

SRAM_A7

SRAM_A8

SRAM_A9

SRAM_A10

SRAM_A11

SRAM_A12

SRAM_A13

SRAM_A14

SRAM_A15

SRAM_A16

SRAM_A17

SRAM_A18

SRAM_A0

SRAM_OE

SRAM_WE

SRAM_CE

C33

0603001UF

C34

0603001UF001UF

0603

C37001UF0603

C36

C42

0603001UF 001UF

0603

C41 C40

0603001UF001UF

0603

C39001UF0603

C46 C45

0603001UF 001UF

0603

C44C43

0603001UF

B6_L01P_Y2

B6_L01N_Y3

SRAM_D23

4

3

2

1

A B C D

20 Cotton Road

Nashua NH 03063

A B C D

4

3

2

1

PH 1-800-ANALOGD

C

Title

Size Board No

Date Sheet of

DEVICESANALOG

DNP = Do Not Populate

Rev

BLACKFIN FPGA EZ-EXTENDER

A0199-2005 10

EXPANSION INTERFACE TYPE B

P1Expanison Connector

Top Of BoardBottom Of Board

Expansion Connector 1

10-18-2005_1616 4 12

EXPANSION INTERFACE CONNECTOR 1

C3510UF805

01UF0603

C38

5V_EI

5V_EI

1

10

11 12

13 14

15 16

17 18

19

2

20

21 22

23 24

25 26

27 28

29

3

30

31 32

33 34

35 36

37 38

39

4

40

41 42

43 44

45 46

47 48

49

5

50

51 52

53 54

55 56

57 58

59

6

60

61 62

63 64

65 66

67 68

69

7

70

71 72

73 74

75 76

77 78

79

8

80

81 82

83 84

85 86

87 88

89

9

90

P1

CON01845X2

1

10

1112

1314

1516

1718

19

2

20

2122

2324

2526

2728

29

3

30

3132

3334

3536

3738

39

4

40

4142

4344

4546

4748

49

5

50

5152

5354

5556

5758

59

6

60

6162

6364

6566

6768

69

7

70

7172

7374

7576

7778

79

8

80

8182

8384

8586

8788

89

9

90

J1

CON01945X2

PP1

EXPANSION_PPI_CLK

PP3

UDEF2

UDEF4

UDEF6

UDEF8

UDEF10

D9

D7

D15

D13

D11

D5

D1

D3

D15

D9

D5

D1

D3

D0

D2

D4

D6

D8

D10

D14

D12

P1_5

P1_25

P1_27

P1_29

P1_31

P1_33

P1_55

P1_57

P1_59

P1_61

P1_63

P1_65

P1_67

P1_69

P1_35

P1_26

P1_28

P1_30

P1_32

P1_34

P1_56

P1_58

P1_60

P1_62

P1_64

P1_66

P1_68

P1_70

P1_36

P1_26

P1_28

P1_30

P1_32

P1_34

P1_36

P1_56

P1_58

P1_60

P1_62

P1_64

P1_66

P1_68

P1_70

P1_5

P1_25

P1_27

P1_29

P1_31

P1_33

P1_35

P1_55

P1_57

P1_59

P1_61

P1_63

P1_65

P1_67

P1_69

P1_[586]

A5

A6A7

A8A9

A10A11

A12A13

A14A15

A16A17

A18A19

D0

D2

D4

D6D7

D8

D10D11

D12D13

D14

A1

A2

B1_L24N_D15_J1_71B1_L24P_E15_J1_72

B1_L22N_A16_J1_73B1_L22P_B16_J1_74

B1_L19N_C16_J1_75B1_L19P_D16_J1_76

B1_L16N_B17_J1_77B1_L16P_C17_J1_78

B1_L15N_D17_J1_79

A3

B1_L15P_E17_J1_80

B1_L10N_A18_J1_81B1_L10P_B18_J1_82

B1_L09N_C18_J1_83B1_L09P_D18_J1_84

B1_L06N_A19_J1_85B1_L06P_B19_J1_86

A4A5

A6 A7

A8 A9

A10 A11

A12 A13

A14 A15

A16 A17

A18 A19

A1

A2

PP0

PP2

UDEF1

UDEF3

A3

UDEF5

UDEF7

UDEF9

UDEF11

A4

33V

25V 33V

33V

33V

33V

4

3

2

1

A B C D

20 Cotton Road

Nashua NH 03063

A B C D

4

3

2

1

PH 1-800-ANALOGD

C

Title

Size Board No

Date Sheet of

DEVICESANALOG

DNP = Do Not Populate

Rev

BLACKFIN FPGA EZ-EXTENDER

A0199-2005 10

VCCO_0_C8

VCCO_0_F8

VCCO_0_G9

VCCO_0_G10

VCCO_0_G11

IO_A10

IO_D9

IO_D10

IO_F6

IO_VREF_0_A3

IO_VREF_0_C7

IO_VREF_0_E5

IO_VREF_0_F7

IO_L06N_0_D5

IO_L06P_0_C5

IO_L09N_0_B5

IO_L09P_0_A5

IO_L10N_0_E6

IO_L10P_0_D6

IO_L15N_0_C6

IO_L15P_0_B6

IO_L16N_0_E7

IO_L16P_0_D7

IO_L19N_0_B7

IO_L19P_0_A7

IO_L22N_0_E8

IO_L22P_0_D8

IO_L24N_0_B8

IO_L24P_0_A8

IO_L25N_0_F9

IO_L25P_0_E9

IO_L27N_0_B9

IO_L27P_0_A9

IO_L28N_0_F10

IO_L28P_0_E10

IO_L29N_0_C10

IO_L29P_0_B10

IO_L30N_0_F11

IO_L30P_0_E11

IO_L31N_0_D11

IO_L31P_0_VREF_0_C11

IO_L01N_0_VRP_0_B4

IO_L01P_0_VRN_0_A4

IO_L32N_0_GCLK7_B11

IO_L32P_0_GCLK6_A11

VCCO_1_C15

VCCO_1_F15

VCCO_1_G12

VCCO_1_G13

VCCO_1_G14

IO_A12

IO_E16

IO_F12

IO_F13

IO_F16

IO_F17

IO_VREF_1_E13

IO_VREF_1_F14

IO_L06N_1_VREF_1_A19

IO_L06P_1_B19

IO_L09N_1_C18

IO_L09P_1_D18

IO_L10N_1_VREF_1_A18

IO_L10P_1_B18

IO_L15N_1_D17

IO_L15P_1_E17

IO_L16N_1_B17

IO_L16P_1_C17

IO_L19N_1_C16

IO_L19P_1_D16

IO_L22N_1_A16

IO_L22P_1_B16

IO_L24N_1_D15

IO_L24P_1_E15

IO_L25N_1_B15

IO_L25P_1_A15

IO_L27N_1_D14

IO_L27P_1_E14

IO_L28N_1_A14

IO_L28P_1_B14

IO_L29N_1_C13

IO_L29P_1_D13

IO_L30N_1_A13

IO_L30P_1_B13

IO_L31N_1_VREF_1_D12

IO_L31P_1_E12

IO_L01N_1_VRP_1_C19

IO_L01P_1_VRN_1_B20

IO_L32N_1_GCLK5_B12

IO_L32P_1_GCLK4_C12

FPGAFPGA

LAYOUT NOTE PLACE NEAR FPGA

5 129-27-2005_1144

C8

F8

G9

G10

G11

A10

D9

D10

F6

A3

C7

E5

F7

D5

C5

B5

A5

E6

D6

C6

B6

E7

D7

B7

A7

E8

D8

B8

A8

F9

E9

B9

A9

F10

E10

C10

B10

F11

E11

D11

C11

B4

A4

B11

A11

C15

F15

G12

G13

G14

A12

E16

F12

F13

F16

F17

E13

F14

A19

B19

C18

D18

A18

B18

D17

E17

B17

C17

C16

D16

A16

B16

D15

E15

B15

A15

D14

E14

A14

B14

C13

D13

A13

B13

D12

E12

C19

B20

B12

C12

U1

FG456XC3S1000

1

10

11 12

13 14

15 16

17 18

19

2

20

21 22

23 24

25 26

27 28

29

3

30

31 32

33 34

35 36

37 38

4

5 6

7 8

9

39 40

41

43

45

47

49

42

44

46

48

50

25X2CON041

P4

5

1

18

20

22

26

24

16

14

12

25

23

21

19

17

15

13

11

9

3

6

10

8

4

2

7

P8

IDC13X213X2

5

1

18

20

22

26

24

16

14

12

25

23

21

19

17

15

13

11

9

3

6

10

8

4

2

7

P14

IDC13X213X2

FPGA BANKS 0 + 1

001UF0603

C50

DNP0603

R52

B1_L10N_A18_J1_81

B1_L15P_E17_J1_80

R53

0603DNP

B1_L16P_C17_J1_78

R27

06030

B1_L10P_B18_J1_82B1_L10N_A18_J1_81

B1_L15N_D17_J1_79

B1_L16N_B17_J1_77

B1_L24N_D15_J1_71

B1_L22N_A16_J1_73

B1_L19N_C16_J1_75

R51

0603DNPDNP

0603

R50DNP0603

R48

R31

0603DNP

B1_L19N_C16_J1_75

B1_L22N_A16_J1_73

B1_L24N_D15_J1_71

B1_L15N_D17_J1_79

B1_L15P_E17_J1_80

B1_L16N_B17_J1_77

B1_L16P_C17_J1_78

DNP0603

R30

VCCO_1

VCCO_1

C47

0603001UF

VCCO_1

B1_L27N_D14

PB1

AOE

B1_L01P_VRN_B20

B1_L01N_VRP_C19

IO_L32_0_GCLK6_A11

IO_L32_0_GCLK7_B11

IO_L32_0_GCLK7_B11

B1_L32N_GCLK5_B12

B1_L32P_GCLK4_C12 B1_L06P_B19_J1_86

B1_L09P_D18_J1_84

B1_L15P_E17_J1_80

B1_L16P_C17_J1_78

B1_L19P_D16_J1_76

B1_L16N_B17_J1_77

B1_L15N_D17_J1_79

B1_L09N_C18_J1_83

B1_L06N_A19_J1_85

B1_L31P_E12

B1_L31N_D12

B1_L06N_A19_J1_85

B1_L09N_C18_J1_83

B1_L09P_D18_J1_84

B1_L06P_B19_J1_86

B1_F17

B1_F16

B1_E16

B1_F13

B1_E13

B1_F12

B1_A12

B1_F14

B1_L01N_VRP_C19

B1_L01P_VRN_B20

B1_L32P_GCLK4_C12

B1_L32N_GCLK5_B12

AMS3

D5

D4

AMS0

UDEF1

ARE

ARDY

AMS1

AMS2

UDEF11

UDEF9

UDEF7

UDEF5

UDEF3

PP2

PP0

D15

D11

D9

A17

B1_L16P_C17_J1_78

B1_L19P_D16_J1_76

B1_L19N_C16_J1_75

B1_L22P_B16_J1_74

B1_L24N_D15_J1_71

B1_L22N_A16_J1_73

B1_L24P_E15_J1_72

B1_L16N_B17_J1_77

B1_L10P_B18_J1_82

B1_L15P_E17_J1_80

B1_L15N_D17_J1_79

B1_L10N_A18_J1_81

B1_L09P_D18_J1_84

B1_L09N_C18_J1_83

B1_L06P_B19_J1_86

B1_L06N_A19_J1_85

B1_L31N_D12

B1_L30N_A13

B1_L29N_C13

B1_L28N_A14

B1_L27N_D14

B1_L25N_B15

B1_F16

B1_F14

B1_F13

B1_F12

B1_L31P_E12

B1_L30P_B13

B1_L29P_D13

B1_L28P_B14

B1_L27P_E14

B1_L25P_A15

B1_F17

B1_E13

B1_E16

B1_A12

UDEF10

ABE3

ABE1

ABE0

ABE2

AWE

UDEF6

UDEF8

PP3

UDEF4

UDEF2

PP1

D14

D8

D10

D12

B1_L25P_A15B1_L25N_B15

B1_L22N_A16_J1_73

B1_L24N_D15_J1_71

B1_L19N_C16_J1_75

B1_L24P_E15_J1_72

B1_L22P_B16_J1_74

B1_L27P_E14

B1_L19P_D16_J1_76

B1_L22P_B16_J1_74

B1_L24P_E15_J1_72

B1_L25N_B15

B1_L25P_A15

B1_L27N_D14

B1_L27P_E14

B1_L28N_A14

B1_L28P_B14

B1_L29N_C13

B1_L29P_D13

B1_L30N_A13

B1_L30P_B13

B1_L10N_A18_J1_81

B1_L10P_B18_J1_82

3

2

1

3X1IDC3X1

P9

EXPANSION_PPI_CLK

B1_F16 B1_F17

B1_L28P_B14

B1_L29P_D13

B1_L30P_B13

B1_L31P_E12

B1_L28N_A14

B1_L29N_C13

B1_L30N_A13

B1_L31N_D12

B1_E16

B1_E13

B1_A12

B1_L01P_VRN_B20

B1_L32P_GCLK4_C12

B1_F14

B1_L01N_VRP_C19

B1_L32N_GCLK5_B12

B1_F13

B1_F12

B1_L01P_VRN_B20

B1_L01N_VRP_C19

001UF0603

C48 C49

0603001UF

C51

0603001UF 001UF

0603

C52 C53

0603001UF001UF

0603

C54

VCCO_1

R49

0603DNP

B1_L10P_B18_J1_82

DNP0603

R54

4

3

2

1

A B C D

20 Cotton Road

Nashua NH 03063

A B C D

4

3

2

1

PH 1-800-ANALOGD

C

Title

Size Board No

Date Sheet of

DEVICESANALOG

DNP = Do Not Populate

Rev

BLACKFIN FPGA EZ-EXTENDER

A0199-2005 10Expanison ConnectorP2

Bottom Of Board Top Of Board

Expansion Connector 2

33V_EI

6 129-14-2005_1203

EXPANSION INTERFACE CONNECTOR 2

SCK

NMI

TMR1

PF1

PF3

PF5

PF7

PF9

PF11

PF13

PF15

1

10

11 12

13 14

15 16

17 18

19 20

21 22

23 24

25 26

27 28

29

3

30

31 32

33 34

35 36

37 38

39

4

40

41 42

43 44

45 46

47 48

49

5

50

51 52

53 54

55 56

57 58

59

6

60

61 62

63 64

65 66

67 68

69

7

70

71 72

73 74

75 76

77 78

79

8

80

81 82

83 84

85 86

87 88

89

9

90

2P2

CON01845X2

1

10

1112

1314

1516

1718

19

2

20

2122

2324

2526

2728

29

3

30

3132

3334

3536

3738

39

4

40

4142

4344

4546

4748

49

5

50

5152

5354

5556

5758

59

6

60

6162

6364

6566

6768

69

7

70

7172

7374

7576

7778

79

8

80

8182

8384

8586

8788

89

9

90

J2

CON01945X2

ARE

ARDY

AMS0

AMS1

P2_21

P2_19

P2_7

P2_21

P2_71

P2_73

P2_77

P2_79

P2_83

P2_85

P2_81

P2_19

P2_15

P2_5 P2_6

P2_8

P2_22

P2_86

P2_84

P2_82

P2_80

P2_78

P2_74

P2_72

P2_20

P2_18

P2_22

P2_74

P2_78

P2_82

P2_84

P2_86

P2_80

P2_72

P2_20

P2_18

P2_8

P2_6

P2_[586]

P2_5

P2_7

P2_15

P2_85

P2_83

P2_81

P2_79

P2_77

P2_73

P2_71AWE

AOE

ABE0

ABE1

ABE2

ABE3

TSCLK0

TFS0

DT0PRI

DT0SEC

CONFIG_CLK_TSCLK1

CONFIG_INIT_B_TFS1

DT1PRI

DT1SEC

TMR0

TMR2

PF14

PF12

PF10

PF8

PF4

PF6

PF2

PF0

B2_L40N_L21_J2_9

B2_L39N_L19_J2_11

B2_C22_J2_17

B2_L38N_L17_J2_23

B2_L35N_K21_J2_25

B2_L34N_K19_J2_27

B2_L33N_K17_J2_29

B2_L32N_J21_J2_31

B2_L31N_J18_J2_33

B2_L29N_H21_J2_35

B2_L28N_H18_J2_37

B2_L27N_G21_J2_39

B2_L26N_G20_J2_41

B2_L22N_G17_J2_43

B2_L24N_F20_J2_45

B2_L23N_F19_J2_47

B2_L21N_E21_J2_49

B2_L20N_E19_J2_51

B2_L19N_E18_J2_53

B2_L17N_D21_J2_55

B2_L16N_D20_J2_57B2_L16P_D19_J2_58

B2_L17P_D22_J2_56

B2_L19P_F18_J2_54

B2_L20P_E20_J2_52

B2_L21P_E22_J2_50

B2_L23P_G19_J2_48

B2_L24P_F21_J2_46

B2_L22P_G18_J2_44

B2_L26P_H19_J2_42

B2_L27P_G22_J2_40

B2_L28P_J17_J2_38

B2_L29P_H22_J2_36

B2_L31P_J19_J2_34

B2_L32P_J22_J2_32

B2_L33P_K18_J2_30

B2_L34P_K20_J2_28

B2_L35P_K22_J2_26

B2_L38P_L18_J2_24

IO_L01P_2_VRN_2_C21_J2_16

B2_L40P_L22_J2_10

B2_L39P_L20_J2_12

MOSI

MISO

UDEF12

AMS3

AMS2

AMS0

ARDY

AMS1

AREAWE

AOE

ABE0

ABE1

ABE2

ABE3

RSCLK1

RSCLK0

RFS1

DR1PRI

DR1SEC

AMS2

AMS3

DR0SEC

DR0PRI

RFS0

TMR3

SPIDS0

C56

060301UF

80510UFC55

33V_EI

33V

4

3

2

1

A B C D

20 Cotton Road

Nashua NH 03063

A B C D

4

3

2

1

PH 1-800-ANALOGD

C

Title

Size Board No

Date Sheet of

DEVICESANALOG

DNP = Do Not Populate

Rev

BLACKFIN FPGA EZ-EXTENDER

A0199-2005 10

33V

25V33V

33V

33V

VCCO_2_H17

VCCO_2_H20

VCCO_2_J16

VCCO_2_K16

VCCO_2_L16

IO_C22

IO_L16N_2_D20

IO_L16P_2_D19

IO_L17N_2_D21

IO_L17P_2_VREF_2_D22

IO_L19N_2_E18

IO_L19P_2_F18

IO_L20N_2_E19

IO_L20P_2_E20

IO_L21N_2_E21

IO_L21P_2_E22

IO_L22N_2_G17

IO_L22P_2_G18

IO_L23N_2_VREF_2_F19

IO_L23P_2_G19

IO_L24N_2_F20

IO_L24P_2_F21

IO_L26N_2_G20

IO_L26P_2_H19

IO_L27N_2_G21

IO_L27P_2_G22

IO_L28N_2_H18

IO_L28P_2_J17

IO_L29N_2_H21

IO_L29P_2_H22

IO_L31N_2_J18

IO_L31P_2_J19

IO_L32N_2_J21

IO_L32P_2_J22

IO_L33N_2_K17

IO_L33P_2_K18

IO_L34N_2_VREF_2_K19

IO_L34P_2_K20

IO_L35N_2_K21

IO_L35P_2_K22

IO_L38N_2_L17

IO_L38P_2_L18

IO_L39N_2_L19

IO_L39P_2_L20

IO_L40N_2_L21

IO_L40P_2_VREF_2_L22

IO_L01N_2_VRP_2_C20

IO_L01P_2_VRN_2_C21

VCCO_3_M16

VCCO_3_N16

VCCO_3_P16

VCCO_3_R17

VCCO_3_R20

IO_L16N_3_W22

IO_L16P_3_Y22

IO_L17N_3_V19

IO_L17P_3_VREF_3_W19

IO_L19N_3_W21

IO_L19P_3_W20

IO_L20N_3_U19

IO_L20P_3_V20

IO_L21N_3_V22

IO_L21P_3_V21

IO_L22N_3_T17

IO_L22P_3_U18

IO_L23N_3_U21

IO_L23P_3_VREF_3_U20

IO_L24N_3_R18

IO_L24P_3_T18

IO_L26N_3_T20

IO_L26P_3_T19

IO_L27N_3_T22

IO_L27P_3_T21

IO_L28N_3_R22

IO_L28P_3_R21

IO_L29N_3_P19

IO_L29P_3_R19

IO_L31N_3_P18

IO_L31P_3_P17

IO_L32N_3_P22

IO_L32P_3_P21

IO_L33N_3_N18

IO_L33P_3_N17

IO_L34N_3_N20

IO_L34P_3_VREF_3_N19

IO_L35N_3_N22

IO_L35P_3_N21

IO_L38N_3_M18

IO_L38P_3_M17

IO_L39N_3_M20

IO_L39P_3_M19

IO_L40N_3_VREF_3_M22

IO_L40P_3_M21

IO_L01N_3_VRP_3_Y20

IO_L01P_3_VRN_3_Y19

IO_Y21

FPGAFPGA

LAYOUT NOTE PLACE NEAR FPGA

9-27-2005_1144 7 12

H17

H20

J16

K16

L16

C22

D20

D19

D21

D22

E18

F18

E19

E20

E21

E22

G17

G18

F19

G19

F20

F21

G20

H19

G21

G22

H18

J17

H21

H22

J18

J19

J21

J22

K17

K18

K19

K20

K21

K22

L17

L18

L19

L20

L21

L22

C20

C21

M16

N16

P16

R17

R20

W22

Y22

V19

W19

W21

W20

U19

V20

V22

V21

T17

U18

U21

U20

R18

T18

T20

T19

T22

T21

R22

R21

P19

R19

P18

P17

P22

P21

N18

N17

N20

N19

N22

N21

M18

M17

M20

M19

M22

M21

Y20

Y19

Y21

U1

FG456XC3S1000

2

4

8

10

6

12

14

16

24

22

20

18

26

28

3

5

7

9

11

13

15

17

19

21

23

25

27

1P5

IDC14X214X2

1

27

25

23

21

19

17

15

13

11

9

7

5

3

28

26

18

20

22

24

16

14

12

6

10

8

4

2P7

IDC14X214X2

VCCO_2

B2_L26P_H19_J2_42

DNP0603

R55B2_L24P_F21_J2_46

R56

0603DNP

B2_L23P_G19_J2_48

B2_L26N_G20_J2_41

B2_L24N_F20_J2_45

B2_L23N_F19_J2_47 B2_L23P_G19_J2_48

B2_L24P_F21_J2_46

B2_L26P_H19_J2_42

R32

0603DNP

TMR0

VCCO_2

PF221

2X1IDC2X1

JP3

CONFIG_PROG_B

1 2JP2

IDC2X12X1

PF3

CONFIG_INIT_B_TFS1

CONFIG_CLK_TSCLK1

RSCLK1

RFS1

IO_L01N_2_VRP_2_C20

IO_L01P_2_VRN_2_C21_J2_16

B2_L22N_G17_J2_43

B2_L22P_G18_J2_44

B2_L32N_J21_J2_31

SPIDS0

PF0

SCK

NMI

TMR1

DR1SEC

TMR3

DR0PRI

DR1PRI

RFS0

DR0SEC

PF15

PF13

RSCLK0

PF7

PF9

PF6

PF11

PF1

PF3

PF5

MOSI

MISO

UDEF12

TMR2

DT1SEC

DT1PRI

DT0SEC

TSCLK0

PF14

PF12

PF10

PF8

PF4

PF2

FPGA BANKS 2 + 3

DT0PRI

TFS0

B2_L40P_L22_J2_10

B2_L40N_L21_J2_9

B2_L39P_L20_J2_12

B2_L39N_L19_J2_11

B2_L38P_L18_J2_24

B2_L38N_L17_J2_23

B2_L35P_K22_J2_26

B2_L35N_K21_J2_25

B2_L34P_K20_J2_28

B2_L34N_K19_J2_27

B2_L33P_K18_J2_30

B2_L33N_K17_J2_29

B2_L32P_J22_J2_32

B2_L31P_J19_J2_34

B2_L31N_J18_J2_33

B2_L29P_H22_J2_36

B2_L29N_H21_J2_35

B2_L28P_J17_J2_38

B2_L28N_H18_J2_37

B2_L27P_G22_J2_40

B2_L27N_G21_J2_39

B2_L26P_H19_J2_42

B2_L26N_G20_J2_41

B2_L24P_F21_J2_46

B2_L24N_F20_J2_45

B2_L23P_G19_J2_48

B2_L23N_F19_J2_47

B2_L21P_E22_J2_50

B2_L21N_E21_J2_49

B2_L20P_E20_J2_52

B2_L20N_E19_J2_51

B2_L19P_F18_J2_54

B2_L19N_E18_J2_53

B2_L17P_D22_J2_56

B2_L17N_D21_J2_55

B2_L16P_D19_J2_58

B2_L16N_D20_J2_57

B2_C22_J2_17

3

2

1

3X1IDC3X1

P10

IO_L01P_2_VRN_2_C21_J2_16

IO_L01N_2_VRP_2_C20

VCCO_2

CONFIG_DONE

B2_L22N_G17_J2_43

B2_L17N_D21_J2_55

B2_L19N_E18_J2_53

B2_L20N_E19_J2_51

B2_L21N_E21_J2_49

B2_L16N_D20_J2_57

IO_L01N_2_VRP_2_C20

B2_L16P_D19_J2_58

B2_L20P_E20_J2_52

B2_L19P_F18_J2_54

B2_L17P_D22_J2_56

B2_L22P_G18_J2_44

B2_L21P_E22_J2_50

B2_C22_J2_17

IO_L01P_2_VRN_2_C21_J2_16

B2_L40N_L21_J2_9

B2_L39N_L19_J2_11

B2_L38N_L17_J2_23

B2_L35N_K21_J2_25

B2_L34N_K19_J2_27

B2_L33N_K17_J2_29

B2_L32N_J21_J2_31

B2_L31N_J18_J2_33

B2_L29N_H21_J2_35

B2_L28N_H18_J2_37

B2_L27N_G21_J2_39

B2_L40P_L22_J2_10

B2_L34P_K20_J2_28

B2_L35P_K22_J2_26

B2_L38P_L18_J2_24

B2_L39P_L20_J2_12

B2_L33P_K18_J2_30

B2_L32P_J22_J2_32

B2_L28P_J17_J2_38

B2_L31P_J19_J2_34

B2_L29P_H22_J2_36

B2_L27P_G22_J2_40

DNP0603

R33

B2_L23N_F19_J2_47

B2_L24N_F20_J2_45

B2_L26N_G20_J2_41

DNP0603

R57

001UF0603

C60 C59

0603001UF 001UF

0603

C58 C57

0603001UF

C82

0603001UF 001UF

0603

C81 C62

0603001UF001UF

0603

C61

VCCO_2

4

3

2

1

A B C D

20 Cotton Road

Nashua NH 03063

A B C D

4

3

2

1

PH 1-800-ANALOGD

C

Title

Size Board No

Date Sheet of

DEVICESANALOG

DNP = Do Not Populate

Rev

BLACKFIN FPGA EZ-EXTENDER

A0199-2005 10

Expanison ConnectorExpanison Connector

Bottom Of Board Top Of BoardExpansion Connector 3

EXPANSION INTERFACE (TYPE B)

P3P3

9-9-2005_1029 128

EXPANSION INTERFACE CONNECTOR 1

33V_EI5V_EI

1

10

11 12

13 14

15 16

17 18

19

2

20

21 22

23 24

25 26

27 28

29

3

30

31 32

33 34

35 36

37 38

39

4

40

41 42

43 44

45 46

47 48

49

5

50

51 52

53 54

55 56

57 58

59

6

60

61 62

63 64

65 66

67 68

69

7

70

71 72

73 74

75 76

77 78

79

8

80

81 82

83 84

85 86

87 88

89

9

90

P3

CON01845X2

1

10

1112

1314

1516

1718

19

2

20

2122

2324

2526

2728

29

3

30

3132

3334

3536

3738

39

4

40

4142

4344

4546

4748

49

5

50

5152

5354

5556

5758

59

6

60

6162

6364

6566

6768

69

7

70

7172

7374

7576

7778

79

8

80

8182

8384

8586

8788

89

9

90

J3

CON01945X2

TX0

TX1

UDEF17

UDEF19

UDEF21

UDEF23

UDEF25

UDEF29

UDEF27

RESET

UDEF32

UDEF34

UDEF36

UDEF38

UDEF40

B5_L01N_RDWR_B_Y4_J3_1

P3_42

P3_[190]

P3_86

P3_84

P3_82

P3_80

P3_78

P3_76

P3_74

P3_72

P3_70

P3_68

P3_64

P3_62

P3_60

P3_58

P3_56

P3_54

P3_52

P3_50

P3_48

P3_46

P3_42

P3_79

P3_89

P3_77

P3_75

P3_73

P3_71

P3_69

P3_67

P3_63

P3_61

P3_59

P3_57

P3_55

P3_53

P3_51

P3_49

P3_47

P3_45

P3_51

P3_79

P3_89

P3_77

P3_75

P3_73

P3_71

P3_69

P3_67

P3_63

P3_61

P3_59

P3_57

P3_55

P3_53

P3_49

P3_47

P3_45

P3_86

P3_84

P3_82

P3_80

P3_78

P3_76

P3_74

P3_72

P3_70

P3_68

P3_64

P3_62

P3_60

P3_58

P3_56

P3_54

P3_52

P3_50

P3_48

P3_46

B5_L27N_W9_J3_31

B5_L28N_D6_AB9_J3_33

B5_L29N_Y10_J3_35

B5_L30N_AB10_J3_37

B5_L31N_D4_W11_J3_39

B5_L10N_VRP_AB5_J3_9

B5_L25N_AB8_J3_21

B5_L24N_W8_J3_19

B5_L22N_AB7_J3_17

B5_L19N_Y7_J3_15

B5_L16N_AA6_J3_13

B5_L15N_W6_J3_11

B5_L09N_Y5_J3_7

B5_L06N_AB4_J3_5

B5_U6_J3_23

B5_V7_J3_29

B5_U9_J3_41

B5_L31P_D5_V11_J3_40

B5_L30P_AA10_J3_38

B5_L29P_W10_J3_36

B5_L28P_D7_AA9_J3_34

B5_L27P_V9_J3_32

B5_L32N_GCLK3_AA11_J3_30

B5_U7_J3_28

B5_L25P_AA8_J3_22

B5_L24P_V8_J3_20

B5_L22P_AA7_J3_18

B5_L19P_W7_J3_16

B5_L16P_Y6_J3_14

B5_L15P_V6_J3_12

B5_L10P_VRN_AA5_J3_10

B5_L09P_W5_J3_8

B5_L06P_AA4_J3_6

B5_L01P_CS_B_AA3_J3_2

B5_AB11_J3_90

B5_U11_J3_83

B5_V10_J3_85

B5_U10_J3_81

UDEF43

BGH

BG

BR

UDEF30

UDEF28

UDEF26

UDEF24

UDEF22

UDEF20

UDEF18

UDEF16

RX1

RX0

UDEF14 UDEF15

CLK_OUT_EXP1

UDEF31

UDEF33

UDEF35

UDEF37

UDEF39

UDEF41

33V_EI

C84

060301UF

80510UFC83

C8610UF805

01UF0603

C85

5V_EI

33V

33V

25V 33V

33V

33V

33V

4

3

2

1

A B C D

20 Cotton Road

Nashua NH 03063

A B C D

4

3

2

1

PH 1-800-ANALOGD

C

Title

Size Board No

Date Sheet of

DEVICESANALOG

DNP = Do Not Populate

Rev

BLACKFIN FPGA EZ-EXTENDER

A0199-2005 10

VCCO_4_T12

VCCO_4_T13

VCCO_4_T14

VCCO_4_U15

VCCO_4_Y15

IO_U16

IO_U17

IO_W13

IO_W14

IO_VREF_4_V18

IO_VREF_4_Y16

IO_VREF_4_AB13

IO_L05N_4_AA19

IO_L05P_4_AB19

IO_L06N_4_VREF_4_W18

IO_L06P_4_Y18

IO_L09N_4_AA18

IO_L09P_4_AB18

IO_L10N_4_V17

IO_L10P_4_W17

IO_L15N_4_Y17

IO_L15P_4_AA17

IO_L16N_4_V16

IO_L16P_4_W16

IO_L19N_4_AA16

IO_L19P_4_AB16

IO_L22N_4_VREF_4_V15

IO_L22P_4_W15

IO_L24N_4_AA15

IO_L24P_4_AB15

IO_L25N_4_U14

IO_L25P_4_V14

IO_L27N_4_DIN_D0_AA14

IO_L27P_4_D1_AB14

IO_L28N_4_U13

IO_L28P_4_V13

IO_L29N_4_Y13

IO_L29P_4_AA13

IO_L30N_4_D2_U12

IO_L30P_4_D3_V12

IO_L31N_4_INIT_B_W12

IO_L31P_4_DOUT_BUSY_Y12

IO_L01N_4_VRP_4_AA20

IO_L01P_4_VRN_4_AB20

IO_L32N_4_GCLK1_AA12

IO_L32P_4_GCLK0_AB12

VCCO_5_T9

VCCO_5_T10

VCCO_5_T11

VCCO_5_U8

VCCO_5_Y8

IO_U7

IO_U9

IO_U10

IO_U11

IO_V7

IO_V10

IO_VREF_5_U6

IO_VREF_5_AB11

IO_L01N_5_RDWR_B_Y4

IO_L01P_5_CS_B_AA3

IO_L06N_5_AB4

IO_L06P_5_AA4

IO_L09N_5_Y5

IO_L09P_5_W5

IO_L15N_5_W6

IO_L15P_5_V6

IO_L16N_5_AA6

IO_L16P_5_Y6

IO_L19N_5_Y7

IO_L19P_5_VREF_5_W7

IO_L22N_5_AB7

IO_L22P_5_AA7

IO_L24N_5_W8

IO_L24P_5_V8

IO_L25N_5_AB8

IO_L25P_5_AA8

IO_L27N_5_VREF_5_W9

IO_L27P_5_V9

IO_L28N_5_D6_AB9

IO_L28P_5_D7_AA9

IO_L29N_5_Y10

IO_L29P_5_VREF_5_W10

IO_L30N_5_AB10

IO_L30P_5_AA10

IO_L31N_5_D4_W11

IO_L31P_5_D5_V11

IO_L32N_5_GCLK3_AA11

IO_L32P_5_GCLK2_Y11

IO_L10N_5_VRP_5_AB5

IO_L10P_5_VRN_5_AA5

FPGAFPGA

1299-27-2005_1144

T12

T13

T14

U15

Y15

U16

U17

W13

W14

V18

Y16

AB13

AA19

AB19

W18

Y18

AA18

AB18

V17

W17

Y17

AA17

V16

W16

AA16

AB16

V15

W15

AA15

AB15

U14

V14

AA14

AB14

U13

V13

Y13

AA13

U12

V12

W12

Y12

AA20

AB20

AA12

AB12

T9

T10

T11

U8

Y8

U7

U9

U10

U11

V7

V10

U6

AB11

Y4

AA3

AB4

AA4

Y5

W5

W6

V6

AA6

Y6

Y7

W7

AB7

AA7

W8

V8

AB8

AA8

W9

V9

AB9

AA9

Y10

W10

AB10

AA10

W11

V11

AA11

Y11

AB5

AA5

U1

FG456XC3S1000

7

2

4

8

10

6

3

9

11

13

15

17

19

21

23

25

12

14

16

24

26

22

20

18

1

5

P16

IDC13X213X2

5

1

18

20

22

26

24

16

14

12

25

23

21

19

17

15

13

11

9

3

6

10

8

4

2

7

P17

IDC13X213X2

R46

060310K

R43

0603DNP

FPGA BANKS 4 + 5

VCCO_5

CONFIG_INIT_B_TFS1

CLK_OUT_EXP1

B4_L32N_GCKL1_AA12

R9

06030

B5_L10N_VRP_AB5_J3_9

B5_L10N_VRP_AB5_J3_9

B5_L10P_VRN_AA5_J3_10

VCCO_5

B5_L32P_GCLK2_Y1

B5_L32N_GCLK3_AA11_J3_30

CONFIG_DIN_DT1PRI

UDEF16

UDEF38

UDEF14

RX0

TX0

RX1

TX1

UDEF20

UDEF21

UDEF23

UDEF17

UDEF25

UDEF24

UDEF22

RESET

UDEF30

UDEF29

UDEF27

UDEF26

UDEF35

UDEF34

UDEF33

UDEF32

UDEF31

UDEF15

UDEF28

UDEF41

UDEF40

UDEF39

UDEF37

UDEF36

BR

UDEF43

BG

BGH

UDEF19

B5_L31P_D5_V11_J3_40

B5_L31N_D4_W11_J3_39

B5_L30P_AA10_J3_38

B5_L30N_AB10_J3_37

B5_L29P_W10_J3_36

B5_L29N_Y10_J3_35

B5_L28P_D7_AA9_J3_34

B5_L28N_D6_AB9_J3_33

B5_L27P_V9_J3_32

B5_L27N_W9_J3_31

B5_L25P_AA8_J3_22

B5_L25N_AB8_J3_21

B5_L24P_V8_J3_20

B5_L24N_W8_J3_19

B5_L22P_AA7_J3_18

B5_L22N_AB7_J3_17

B5_L19P_W7_J3_16

B5_L19N_Y7_J3_15

B5_L16P_Y6_J3_14

B5_L16N_AA6_J3_13

B5_L15P_V6_J3_12

B5_L15N_W6_J3_11

B5_L09P_W5_J3_8

B5_L09N_Y5_J3_7

B5_L06P_AA4_J3_6

B5_L06N_AB4_J3_5

B5_L01P_CS_B_AA3_J3_2

B5_L01N_RDWR_B_Y4_J3_1

B5_AB11_J3_90

B5_U6_J3_23

B5_V10_J3_85

B5_V7_J3_29

B5_U11_J3_83

B5_U10_J3_81

B5_U9_J3_41

B5_U7_J3_28

UDEF18

3

2

1

3X1IDC3X1

P11

B5_L29N_Y10_J3_35

B5_L30N_AB10_J3_37

B5_L31N_D4_W11_J3_39

B5_U11_J3_83

B5_V10_J3_85B5_AB11_J3_90

B5_U10_J3_81

B5_L31P_D5_V11_J3_40

B5_L30P_AA10_J3_38

B5_L29P_W10_J3_36

B5_L28P_D7_AA9_J3_34

B5_L27P_V9_J3_32

B5_L28N_D6_AB9_J3_33

B5_L27N_W9_J3_31

B5_L25N_AB8_J3_21B5_L25P_AA8_J3_22

B5_L24N_W8_J3_19B5_L24P_V8_J3_20

B5_U9_J3_41B5_U6_J3_23

VCCO_5

B5_L10P_VRN_AA5_J3_10

C70

0603001UF 001UF

0603

C69 C68

0603001UF001UF

0603

C67001UF0603

C66 C65

0603001UF 001UF

0603

C64C63

0603001UF

B5_L09N_Y5_J3_7

B5_U7_J3_28 B5_V7_J3_29

B5_L10P_VRN_AA5_J3_10 B5_L10N_VRP_AB5_J3_9

B5_L15P_V6_J3_12 B5_L15N_W6_J3_11

B5_L16P_Y6_J3_14 B5_L16N_AA6_J3_13

B5_L19P_W7_J3_16 B5_L19N_Y7_J3_15

B5_L22P_AA7_J3_18 B5_L22N_AB7_J3_17

B5_L32N_GCLK3_AA11_J3_30 B5_L32P_GCLK2_Y1

B5_L01P_CS_B_AA3_J3_2 B5_L01N_RDWR_B_Y4_J3_1

B5_L06P_AA4_J3_6 B5_L06N_AB4_J3_5

B5_L09P_W5_J3_8

VCCO_5

DNP0603

R45

25V

33V

33V

4

3

2

1

A B C D

20 Cotton Road

Nashua NH 03063

A B C D

4

3

2

1

PH 1-800-ANALOGD

C

Title

Size Board No

Date Sheet of

DEVICESANALOG

DNP = Do Not Populate

Rev

BLACKFIN FPGA EZ-EXTENDER

A0199-2005 10

SN74LVC1G125

12109-27-2005_1144

2 4

1

SOT23-5SN74LVC1G125

U8

USER IO

C80

0603001UF

SW4SWT013SPST-MOMENTARY

SPST-MOMENTARYSWT013SW3

060310R42

C5

06031UF

R413300603

LED001AMBER-SMTLED8

0603330R40

LED7AMBER-SMTLED001

R393300603

R1033006030603

330R34R35

33006030603

330R36

0603330R37 R38

3300603

LED001AMBER-SMTLED2

AMBER-SMTLED001

LED3AMBER-SMTLED001

LED4AMBER-SMTLED001

LED5

LED001AMBER-SMTLED6

LED9GREEN-SMTLED001

402100R23

1 2

3 4

5 6

7 8

JP5

IDC4X24X2

AMBER-SMTLED001

LED1

B6_L01N_Y3

B6_L01P_Y2

B5_U10_J3_81

B5_AB11_J3_90

PB2

B5_V10_J3_85

B5_U11_J3_83

B5_L31N_D4_W11_J3_39

B5_L30N_AB10_J3_37

B5_L29N_Y10_J3_35

B5_L28N_D6_AB9_J3_33

B5_L27N_W9_J3_31

PB1

B5_L25N_AB8_J3_21

R47

060310K

CHOKE_COIL

4

3

2

1

A B C D

20 Cotton Road

Nashua NH 03063

A B C D

4

3

2

1

PH 1-800-ANALOGD

C

Title

Size Board No

Date Sheet of

DEVICESANALOG

DNP = Do Not Populate

Rev

BLACKFIN FPGA EZ-EXTENDER

A0199-2005 10

25V

33V

VIN

EN

SW

GND

FB

VIN

EN

SW

GND

FB

VIN

EN

SW

GND

FB

4

3

5

2

1

VR3

SOT23-5LM3475MF

1

2

5

3

4

VR2

SOT23-5LM3475MF

4

3

5

2

1

VR1

SOT23-5LM3475MF

12119-27-2005_1124

1

32

Q2

SI2

343D

SS

OT

23D

1

32

Q3

SI2

343D

SS

OT

23D

2 3

1S

I234

3DS

Q1

SO

T23

D

316KR17

0603

215KR18

0603

0603

R11105K

DNPC73

0603

0603

C72DNP

805

C741000PF

0R58

0603

1000PFC10

805

0603

R1910K

C100UFCT2

CT3100UFC

IND005

L110UH

10UHL3

IND005

10UHL2

IND005

1

2 D3

DO214ABSCHOT_RECT

3A

0603

R20200K

805

C639NF

390PFC7

0603

2

1 3A

SCHOT_RECTDO214AB

D2

499KR13

0603

1

2 D1

DO214ABSCHOT_RECT

3A

33V_EI

3

1

2

3X1IDC3X1

P13

UNREG_IN

12V

CT1100UFC

80510UFC71

R1200603

5V_EI

8051000PFC2

FER2

0603

060301UFC3

POWER

FUS00125AF1

4

1

3

2

FER1

DO-214AA

S2A_RECT

2AD5

8051000PFC1 C4

10UFC

3

1

2

3X1IDC3X1

P12

UNREG_IN

1

2

3

CON00525MM_JACK

POWER

J4

2

1P42

IDC2X12X1DNP

1

2

DNP2X1IDC2X1

P43

06030R15

C810UF805

80510UFC9

R1600603

UNREG_IN

0603

R1410K

0603

R590

4

3

2

1

A B C D

20 Cotton Road

Nashua NH 03063

A B C D

4

3

2

1

PH 1-800-ANALOGD

C

Title

Size Board No

Date Sheet of

DEVICESANALOG

DNP = Do Not Populate

Rev

BLACKFIN FPGA EZ-EXTENDER

A0199-2005 1012129-14-2005_1204

5

2

4

8

10

6

1

3

9

11

13

15

17

19

12

14

16

20

18

7

P20

SOIC20

PROTO AREA

1

3

2

SOT23D

P39

2

3

1

SOT23D

P38

2

4

5 6

3

1

SOT23-6

P411

3

65

4

2

SOT23-6

P40

PRT_NUM=DNE

11

13

15 16

14

12

2

4

6

8

109

7

5

3

1

SOIC16

P191

3

5

7

9 10

8

6

4

2

12

14

1615

13

11

SOIC16

P18

21P37

805

1 2

805

P36

21P35

805

1 2

805

P34

1 2

805

P33

21P32

805

1 2

805

P31

21P30

805

1 2

805

P29

21P28

805

1 2

805

P27

21P26

805

21P25

805

1 2

805

P24

21P23

805

1 2

805

P22

TP86

TP85

TP84

TP83

TP82

TP81

TP80

TP79 TP77

TP76

TP75

TP74

TP73

TP72

TP71

TP70

TP68

TP67

TP66

TP65

TP64

TP62

TP61

TP60

TP59

TP58

TP57

TP56

TP55

TP54

TP53

TP51

TP50

TP49

TP48

TP47

TP46

TP45

TP44

TP43

TP41

TP40

TP39

TP38

TP37

TP36

TP35

TP34

TP33

TP32

TP30

TP29

TP28

TP27

TP26

TP25

TP24

TP23

TP22

TP21

TP19

TP18

TP17

TP16

TP15

TP14

TP13

TP12

TP11

TP9

TP8

TP7

TP6

TP5

TP4

TP125

TP124

TP123

TP122

TP121

TP120

TP119

TP118

TP117

TP116

TP114

TP113

TP112

TP111

TP110

TP109

TP108

TP107TP106

TP105TP103

TP102TP101 TP100TP99

TP98 TP97

TP96 TP95

TP94TP93

TP92TP91

TP90 TP89

TP88 TP87

TP78TP69

TP63 TP52

TP42 TP31

TP20 TP10

TP115TP104

7

18

20

16

14

12

19

17

15

13

11

9

3

1

6

10

8

4

2

5

SOIC20

P21

I INDEX

Numerics connectors

25V header (P42) 2-17

AADSP-BF5333761 EZ-KIT Lite interface 2-1ADSP-BF5333761 processors boot mode

settings 2-14architecture of this EZ-Extender 2-2asynchronous static random access memory

(SRAM) xauxiliary oscillator x

Bbill of materials A-1block diagram of this EZ-Extender 2-2boot jumper See JP4

Cconfiguration jumpers See JP2 JP3

map of locations 2-18J1-3 (expansion) 2-19P1-3 (expansion) 2-19P14 (IDC) 2-19P15 (JTAG header) 2-4P16-17 (IDC) 2-19P4 (high-speed) 2-20P5 (IDC) 2-20P6 (JTAG) 2-7P7 (IDC) 2-20P8 (IDC) 2-19

customer support xiii

Ddone LED (LED10) 2-17

Eexpansion interface

connectors (P1-3 J1-3) 2-19of ADSP-BF5333761 EZ-KIT Lites ix

1-3external power supply 1-3 2-8

FField-Programmable Gate Array See FPGA

Blackfin FPGA EZ-Extender Manual I-1

INDEX

FPGAdocumentation 1-2input jumpers (JP5) 2-14softwarefirmware 1-2Xilinx Spartan package x 1-3

FPGA pinsAB10 (LED3) 2-17AB11 (JP58) 2-15AB8 (LED7) 2-17AB9 (LED5) 2-17C11 (PB1SW3) 2-15H5 (PB2SW3) 2-16M2-0 (JP4) 2-14U10 (JP56) 2-15U11 (LED1) 2-17V10 (LED8) 2-17W11 (LED2) 2-17W9 (LED6) 2-17Y10 (LED4) 2-17Y3-2 (JP52-54) 2-15

FPGA programmingblock diagram 2-3via ADSP-BF533376 processors 2-6via JTAG header 2-4via serial ROM 2-5

GGCLK1 (global clock 1) pin 1-4GCLK6 (global clock 6) pin 1-4general-purpose input push buttons 2-15 2-16

Hhigh-speed connector (P4) 2-20

IIDC connectors x 2-19 2-20installation of this EZ-Extender 1-1

JJTAG

cable 1-4 2-7header (P6) 1-5 2-4 2-7 2-14

jumpersmap of locations 2-11JP1 (boot jumper) 2-5 2-12JP2 (confug done) 2-12JP3 (config program) 2-13JP41-46 (boot mode select) 2-5 2-6 2-14JP52-56 (FPGA input) 2-14

LLEDs

map of locations 2-15LED10 (FPGA done pin) 2-4 2-5 2-17LED1-8 (status) 2-17LED9 (power) 2-17

MM2-0 (JP4) pins 2-5master serial boot mode 2-6MCS-86 Hexadecimal Object (mcs) file

format 2-6

Nnotation conventions xvi

Ooscillator x 1-4

PP12 (power in) header 2-9P13 (33V header) 2-9P42 (25V header) 2-10P43 (12V header) 2-10PB1 push button (SW3) 2-15

I-2 Blackfin FPGA EZ-Extender Manual

INDEX

PB2 push button (SW4) 2-16PF14 flag pin (ADSP-BF537 EZ-KIT Lite)

2-12PF3 flag pin (ADSP-BF53361 EZ-KIT Lite)

2-12power

12V header (P43) 2-1025V header (P42) 2-1033V header (P13) 2-9in header (P12) 2-9LED (LED9) 2-17limitations 2-8supplies 1-3 2-8

printed circuit board (PCB) 1-2product overview ixprogram push button (SW1) 2-4 2-15push buttons

See also SWx map of locations 2-15

Sserial ROM 1-5

boot jumper (JP1) 2-12 2-14programming via JTAG Header 2-7

setup of this EZ-Extender 1-1slave serial mode 2-6

SRAM memory banks 1-4status reporting 1-4 2-17SW1 (program) push button 2-4 2-15SW3 (PB1) push button 2-15SW4 (PB2) push button 2-16switching regulators 2-8

TTCK signal 2-7TDI signal 2-7TDO signal 2-7TMS signal 2-7

VVisualDSP++

flash programming utility 1-4 2-6FPGA documentation 2-6

VR1-3 regulators 2-8

XXilinx

JTAG cablesoftware 1-4 2-4 2-7JTAG header 2-12serial ROM 1-5

Blackfin FPGA EZ-Extender Manual I-3

INDEX

I-4 Blackfin FPGA EZ-Extender Manual

• Blackfin FPGA EZ-Extender Manual
• Contents
• Preface
• • Product Overview
  • Purpose of This Manual
  • Intended Audience
  • Manual Contents
  • Whatrsquos New in This Manual
  • Technical or Customer Support
  • Supported Products
  • Product Information
  • • Related Documents
    • • Table 1 Related Processor Publications
      • Table 2 Related VisualDSP++ Publications
      • • Notation Conventions
        • • 1 FPGA EZ-Extender Interfaces
          • • FPGA EZ-Extender Setup
            • • Figure 1-1 FPGA EZ-Extender Setup
              • • FPGA Software and Firmware
                • FPGA EZ-Extender Overview
                • • 2 FPGA EZ-Extender Hardware Reference
                  • • System Architecture
                    • • Figure 2-1 Block Diagram
                      • • Programming the FPGA
                        • • Figure 2-2 FPGA Programming Block Diagram
                          • FPGA Programming via JTAG
                          • • Table 2-1 P15 Connections for PFGA Programming via JTAG
                            • Table 2-2 JP1 Settings for FPGA Programming via JTAG
                            • Table 2-3 JP4 Settings for FPGA Programming via JTAG
                            • • FPGA Programming via Serial ROM
                              • • Table 2-4 JP1 Settings for FPGA Programming via Serial ROM
                                • Table 2-5 JP4 Settings for FPGA Programming in Master Serial Mode
                                • • FPGA Programming via Blackfin Application
                                  • • Table 2-6 JP1 Settings for FPGA Programming via Blackfin Processor
                                    • Table 2-7 JP4 Settings for FPGA Programming via Blackfin Processor
                                    • • Programming the Serial ROM
                                      • • Serial ROM via JTAG Header
                                        • • Table 2-8 P6 Connections for Serial ROM
                                          • • Power
                                            • • Table 2-9 Power Limitations
                                              • Power In Header (P12)
                                              • 33V Header (P13)
                                              • 25V Header (P42)
                                              • 12V Header (P43)
                                              • • Jumpers
                                                • • Figure 2-3 Jumper Locations
                                                  • Serial ROM Boot Jumper (JP1)
                                                  • • Table 2-10 JP1 Settings
                                                    • • Config Done Jumper (JP2)
                                                      • • Table 2-11 JP2 Settings
                                                        • • Config Program Jumper (JP3)
                                                          • • Table 2-12 JP3 Settings
                                                            • • Boot Jumper (JP4)
                                                              • • Table 2-13 JP4 Settings
                                                                • • FPGA Input Jumpers (JP5)
                                                                  • • Table 2-14 JP5 Settings
                                                                    • • Push Buttons and LEDs
                                                                      • • Figure 2-4 Push Button and LED Locations
                                                                        • Program Push Button (SW1)
                                                                        • PB1 Push Button (SW3)
                                                                        • PB2 Push Button (SW4)
                                                                        • Status LEDs (LED1-8)
                                                                        • • Table 2-15 Status LED (LED1-8) Settings
                                                                          • • Power LED (LED9)
                                                                            • Done LED (LED10)
                                                                            • • Connectors
                                                                              • • Figure 2-5 Connector Locations
                                                                                • Expansion Interface (P1-3 and J1-3)
                                                                                • IDC Connectors (P8 P14 P16 and P17)
                                                                                • IDC Connectors (P5 and P7)
                                                                                • High-Speed Connector (P4)
                                                                                • • A Bill Of Materials
                                                                                  • B Schematics
                                                                                  • • Title
                                                                                    • FPGA Config
                                                                                    • SRAM FPGA Banks 7 and 8
                                                                                    • Expansion Interface Connector 1
                                                                                    • FPGA Banks 0 and 1
                                                                                    • Expansion Interface Connectors 2
                                                                                    • FPGA Banks 2 and 3
                                                                                    • Expansion Interface Connector 1
                                                                                    • FPGA Banks 4 and 5
                                                                                    • User IO
                                                                                    • Power
                                                                                    • Proto Area
                                                                                    • • I Index
                                                                                      • • Numerics
                                                                                        • A
                                                                                        • B
                                                                                        • C
                                                                                        • D
                                                                                        • E
                                                                                        • F
                                                                                        • G
                                                                                        • H
                                                                                        • I
                                                                                        • J
                                                                                        • L
                                                                                        • M
                                                                                        • N
                                                                                        • O
                                                                                        • P
                                                                                        • S
                                                                                        • T
                                                                                        • V
                                                                                        • X

Bill Of Materials

339

0 1

10W

5

060

3R

3-4

R9

R12

R15

-16

R27

R58

-59

PAN

ASO

NIC

ER

J-3G

EY

0R00

V

341

10 1

10W

5

060

3 R

42PA

NA

SON

ICE

RJ-

3GE

YJ1

00V

351

200K

11

6W 1

0

603

R20

VIS

HA

YC

RC

W06

0320

03FR

T1

362

10K

11

0W 1

0

603

R14

R19

PAN

ASO

NIC

P10

0K

HT

R-N

D

372

33 1

10W

1

060

3 R

2R

26Y

AG

EO

9C06

031A

33R

0FK

HFT

385

100

116

W 5

4

02R

5R

7-8

R23

R44

PAN

ASO

NIC

ER

J-2G

EJ1

01X

391

390P

F 25

V 5

0

603

NP

OC

7A

VX

0603

3A39

1FA

T2A

401

499

K 1

16W

1

060

3R

13ST

AC

KP

OL

ER

MC

11

6 4

99K

1

R

411

316

K 1

16W

1

060

3 R

17PA

NA

SON

ICE

RJ-

3EK

F316

2V

421

105

K 1

16W

1

060

3 R

11PA

NA

SON

ICE

RJ-

3EK

F105

1V

431

215

K 1

16W

1

060

3R

18PA

NA

SON

ICE

RJ-

3EK

F215

1V

441

GR

EE

N-S

MT

LE

D00

1G

UL

L-W

ING

LE

D9

PAN

ASO

NIC

LN

1361

C

453

IDC

2X

1 ID

C2X

1G

OL

DJP

1-3

Ref

Des

crip

tion

Ref

eren

ce D

esig

nato

r M

anuf

actu

rer

Part

Num

ber

Blackfin FPGA EZ-Extender Manual A-5

465

IDC

3X

1 ID

C3X

1P

9-13

BE

RG

5410

1-T

08-0

3

471

IDC

3X

2 ID

C3X

2JP

4B

ER

G54

102-

T08

-03

481

IDC

4X

2 ID

C4X

2JP

5SU

LL

INS

S201

2-04

494

IDC

13X

2 ID

C13

X2

P

8P

14P

16-1

7B

ER

G54

102-

T08

-13

501

25A

RE

SET

AB

LE

FU

S001

F1R

AY

CH

EM

CO

RP

SMD

250-

2

513

10U

F 10

V 1

0 8

05C

8 C

9 C

71PA

NA

SON

ICE

CJ-

2FB

1A10

6K

Ref

Des

crip

tion

Ref

eren

ce D

esig

nato

r M

anuf

actu

rer

Part

Num

ber

A-6 Blackfin FPGA EZ-Extender Manual

4

3

2

1

A B C D

20 Cotton Road

Nashua NH 03063

A B C D

4

3

2

1

PH 1-800-ANALOGD

C

Title

Size Board No

Date Sheet of

DEVICESANALOG

DNP = Do Not Populate

Rev

BLACKFIN FPGA EZ-EXTENDER

A0199-2005 10

SchematicBLACKFIN FPGA EZ-EXTENDER

1219-9-2005_1040

TITLE

33V

4

3

2

1

A B C D

20 Cotton Road

Nashua NH 03063

A B C D

4

3

2

1

PH 1-800-ANALOGD

C

Title

Size Board No

Date Sheet of

DEVICESANALOG

DNP = Do Not Populate

Rev

BLACKFIN FPGA EZ-EXTENDER

A0199-2005 10

33V

1A

1B

1Y

2A

2B

2Y

3A

3B

3Y

4A

4B

4Y

~AB

EN

25V

33V

33V

33V

33V

33V

25V

33V

OENC OUTOE OUT

CLK

D0

TMS

TCK

TDI

TDO

VCCINT

VCCO

VCCJ

NC1

NC2

NC3

NC4

NC5

NC6

GND

CE

CF

OE~RESET

CEO

VCCAUX_A6

VCCAUX_A17

VCCAUX_F1

VCCAUX_F22

VCCAUX_U1

VCCAUX_U22

VCCAUX_AB6

VCCAUX_AB17

VCCINT_G7

VCCINT_G8

VCCINT_G15

VCCINT_G16

VCCINT_H7

VCCINT_H16

VCCINT_R7

VCCINT_R16

VCCINT_T7

VCCINT_T8

VCCINT_T15

VCCINT_T16

TCK

TDI

TDO

TMS

M0

M1

M2

CCLK

PROG_B

DONE

HSWAP_EN

GND_A1

GND_A22

GND_B2

GND_B21

GND_C9

GND_C14

GND_J3

GND_J9

GND_J10

GND_J11

GND_J12

GND_J13

GND_J14

GND_J20

GND_K9

GND_K10

GND_K11

GND_K12

GND_K13

GND_K14

GND_L9

GND_L10

GND_L11

GND_L12

GND_L13

GND_L14

GND_M9

GND_M10

GND_M11

GND_M12

GND_M13

GND_M14

GND_N9

GND_N10

GND_N11

GND_N12

GND_N13

GND_N14

GND_P3

GND_P9

GND_P10

GND_P11

GND_P12

GND_P13

GND_P14

GND_P20

GND_Y9

GND_Y14

GND_AA2

GND_AA21

GND_AB1

GND_AB22

FPGAFPGA

EXTRA CLOCK SOCKET25MHZ SYSTEM CLOCK

FPGA JTAG HEADER

FLASH JTAG HEADER

BOOTMODE JUMPER

FPGA BOOT FLASH(2Mbit)

MUXFLASHSKTOSC

9-27-2005_1144 2 12

A6

A17

F1

F22

U1

U22

AB6

AB17

G7

G8

G15

G16

H7

H16

R7

R16

T7

T8

T15

T16

A21

B1

B22

A20

AB2

AA1

AB3

AA22

A2

AB21

B3

A1

A22

B2

B21

C9

C14

J3

J9

J10

J11

J12

J13

J14

J20

K9

K10

K11

K12

K13

K14

L9

L10

L11

L12

L13

L14

M9

M10

M11

M12

M13

M14

N9

N10

N11

N12

N13

N14

P3

P9

P10

P11

P12

P13

P14

P20

Y9

Y14

AA2

AA21

AB1

AB22

U1

FG456XC3S1000

CONFIG_PROG_B

6

5

4

3

2

1P6

IDC6X16X1

1

2

3

4

5

6

P15

IDC6X16X1

3

1

8

10

7

13

5

6

4

17

18

19

20

2

9

12

14

15

16

11

U4

TSSOP20XCF04S

2

4

5 6

3

1JP4

IDC3X23X2

402100R5

R400603

402100R44

R8100402

R7100402

1 3

U6

25MHZOSC003

80510UFC14

R29

060310K

R22

060310K

R21

060310K

R1

060310K

1 5

U7

DIPDIP8SOC

R263306030603

33R2

R25

DNP

10K0603

12V

1 2JP1

IDC2X12X1

CONFIG_DONER3

06030

CONFIG_CLK_TSCLK1

FPGA_TMS

FPGA_TDO

FPGA_TCK

FPGA_TDI

FPGA_TCK

FPGA_TDO

FPGA_TDI

FPGA_TMS

FLASH_TMS

FLASH_TDI

FLASH_TDO

FLASH_TCK

M1

M2

M0

12V

SPST-MOMENTARYSWT013SW1

2

3

4

5

6

7

11

10

9

14

13

12

1

15

U2

TSSOP1674LVC157

CONFIG_DONE

FLASH_TMS

FLASH_TCK

FLASH_TDI

FLASH_TDO

M2

M0

M1

FPGA CONFIG

CONFIG_INIT_B_TFS1

FLASH_DOUT

CONFIG_CLK_TSCLK1

FLASH_DONE

001UF0603

C18

IO_L32_0_GCLK6_A11B4_L32N_GCKL1_AA12

C19

0603001UF 001UF

0603

C20 C21

0603001UF 001UF

0603

C25C24

0603001UF001UF

0603

C23C22

0603001UF 001UF

0603

C31 C30

0603001UF 001UF

0603

C29 C28

0603001UF001UF

0603

C27C26

0603001UF

001UF0603

C32 C11

0603001UF 001UF

0603

C12 C13

0603001UF

80510UFC15 C16

10UF805

C17

0603001UF

0603330R24

LED10

LED001AMBER-SMT

CONFIG_DIN_DT1PRI

FLASH_DONE

FLASH_DOUT

DT1PRI

R6

060310K10K

0603

R28

33V 33V

4

3

2

1

A B C D

20 Cotton Road

Nashua NH 03063

A B C D

4

3

2

1

PH 1-800-ANALOGD

C

Title

Size Board No

Date Sheet of

DEVICESANALOG

DNP = Do Not Populate

Rev

BLACKFIN FPGA EZ-EXTENDER

A0199-2005 10

33V

33V

A18

A1

A10

A11

A12

A13

A14

A16

A2

A3

A4

A5

A6

A7

A8

A9

D0

D1

D10

D11

D2

D3

D4

D5

D6

D7

D8

D9

BHE

BLE

CE

OE

WE

A17

D15

D14

D13

D12

A0

A15

A18

A1

A10

A11

A12

A13

A14

A16

A2

A3

A4

A5

A6

A7

A8

A9

D0

D1

D10

D11

D2

D3

D4

D5

D6

D7

D8

D9

BHE

BLE

CE

OE

WE

A17

D15

D14

D13

D12

A0

A15

VCCO_6_M7

VCCO_6_N7

VCCO_6_P7

VCCO_6_R3

VCCO_6_R6

IO_Y1

IO_L16N_6_W4

IO_L16P_6_W3

IO_L17N_6_W2

IO_L17P_6_VREF_6_W1

IO_L19N_6_V5

IO_L19P_6_U5

IO_L20N_6_V4

IO_L20P_6_V3

IO_L21N_6_V2

IO_L21P_6_V1

IO_L22N_6_T6

IO_L22P_6_T5

IO_L23N_6_U4

IO_L23P_6_T4

IO_L24N_6_VREF_6_U3

IO_L24P_6_U2

IO_L26N_6_T3

IO_L26P_6_R4

IO_L27N_6_T2

IO_L27P_6_T1

IO_L28N_6_R5

IO_L28P_6_P6

IO_L29N_6_R2

IO_L29P_6_R1

IO_L31N_6_P5

IO_L31P_6_P4

IO_L32N_6_P2

IO_L32P_6_P1

IO_L33N_6_N6

IO_L33P_6_N5

IO_L34N_6_VREF_6_N4

IO_L34P_6_N3

IO_L35N_6_N2

IO_L35P_6_N1

IO_L38N_6_M6

IO_L38P_6_M5

IO_L39N_6_M4

IO_L39P_6_M3

IO_L40N_6_M2

IO_L40P_6_VREF_6_M1

IO_L01N_6_VRP_6_Y3

IO_L01P_6_VRN_6_Y2

VCCO_7_H3

VCCO_7_H6

VCCO_7_J7

VCCO_7_K7

VCCO_7_L7

IO_C2

IO_L16N_7_D1

IO_L16P_7_VREF_7_C1

IO_L17N_7_E4

IO_L17P_7_D4

IO_L19N_7_VREF_7_D3

IO_L19P_7_D2

IO_L20N_7_F4

IO_L20P_7_E3

IO_L21N_7_E1

IO_L21P_7_E2

IO_L22N_7_G6

IO_L22P_7_F5

IO_L23N_7_F2

IO_L23P_7_F3

IO_L24N_7_H5

IO_L24P_7_G5

IO_L26N_7_G3

IO_L26P_7_G4

IO_L27N_7_G1

IO_L27P_7_VREF_7_G2

IO_L28N_7_H1

IO_L28P_7_H2

IO_L29N_7_J4

IO_L29P_7_H4

IO_L31N_7_J5

IO_L31P_7_J6

IO_L32N_7_J1

IO_L32P_7_J2

IO_L33N_7_K5

IO_L33P_7_K6

IO_L34N_7_K3

IO_L34P_7_K4

IO_L35N_7_K1

IO_L35P_7_K2

IO_L38N_7_L5

IO_L38P_7_L6

IO_L39N_7_L3

IO_L39P_7_L4

IO_L40N_7_VREF_7_L1

IO_L40P_7_L2

IO_L01N_7_VRP_7_C3

IO_L01P_7_VRN_7_C4

(512k x 16bits x 2chips)2MBYTES FPGA SRAM

FPGASRAM SRAM

SRAM_A9

9-27-2005_1144 3 12

FLASH_TDO

FLASH_TMS

FLASH_TDI

FLASH_TCK

M7

N7

P7

R3

R6

Y1

W4

W3

W2

W1

V5

U5

V4

V3

V2

V1

T6

T5

U4

T4

U3

U2

T3

R4

T2

T1

R5

P6

R2

R1

P5

P4

P2

P1

N6

N5

N4

N3

N2

N1

M6

M5

M4

M3

M2

M1

Y3

Y2

H3

H6

J7

K7

L7

C2

D1

C1

E4

D4

D3

D2

F4

E3

E1

E2

G6

F5

F2

F3

H5

G5

G3

G4

G1

G2

H1

H2

J4

H4

J5

J6

J1

J2

K5

K6

K3

K4

K1

K2

L5

L6

L3

L4

L1

L2

C3

C4

U1

FG456XC3S1000

28

2

23

24

25

26

27

43

3

4

5

18

19

20

21

22

7

8

31

32

9

10

13

14

15

16

29

30

40

39

6

41

17

44

38

37

36

35

1

42

U3

TSOP44IS61LV51216

42

1

35

36

37

38

44

17

41

6

39

40

30

29

16

15

14

13

10

9

32

31

8

7

22

21

20

19

18

5

4

3

43

27

26

25

24

23

2

28

U5

TSOP44IS61LV51216

SRAM_D7

SRAM_D6

SRAM_D3

SRAM_D2

SRAM_D0

SRAM_D8

SRAM_D9

SRAM_D5

SRAM_D4

SRAM_D13

SRAM_D1

SRAM_D10

SRAM_D11

SRAM_D12

SRAM_D14

SRAM_D15

SRAM_CE

SRAM_A7

SRAM_A0

SRAM_A5

SRAM_A3

SRAM_A1

SRAM_WE

SRAM_A8

SRAM_A6

SRAM_A4

SRAM_A2

SRAM_A17

SRAM_OE

SRAM_A12

SRAM_A13

SRAM_A15

SRAM_A16

SRAM_A14

SRAM_A18

SRAM_A11

SRAM_A10

SRAM_D22

SRAM_D20

SRAM_D18

SRAM_D17

SRAM_D16

SRAM_D26

SRAM_D21

SRAM_D24

SRAM_D19

SRAM_D31

SRAM_D25

SRAM_D27

SRAM_D28

SRAM_D30

SRAM_D29

PB2

A11

A5

D1

A15

A3

A9

D13

D7

A13

A19

A7

A1

A18

A6

A2

A12

D6

A8

A14

D2

D0

A10

A4

D3

A16

SRAM FPGA BANKS 7 + 8

SRAM_CE

SRAM_WE

SRAM_OE

SRAM_A18

SRAM_A0 SRAM_D0

SRAM_D1

SRAM_D2

SRAM_D3

SRAM_D4

SRAM_D5

SRAM_D6

SRAM_D7

SRAM_D8

SRAM_D9

SRAM_D10

SRAM_D11

SRAM_D12

SRAM_D13

SRAM_D14

SRAM_D15

SRAM_D16

SRAM_D17

SRAM_D18

SRAM_D19

SRAM_D20

SRAM_D21

SRAM_D22

SRAM_D23

SRAM_D24

SRAM_D25

SRAM_D26

SRAM_D27

SRAM_D28

SRAM_D29

SRAM_D30

SRAM_D31

SRAM_A1

SRAM_A2

SRAM_A3

SRAM_A4

SRAM_A5

SRAM_A6

SRAM_A7

SRAM_A8

SRAM_A9

SRAM_A10

SRAM_A11

SRAM_A12

SRAM_A13

SRAM_A14

SRAM_A15

SRAM_A16

SRAM_A17

SRAM_A1

SRAM_A2

SRAM_A3

SRAM_A4

SRAM_A5

SRAM_A6

SRAM_A7

SRAM_A8

SRAM_A9

SRAM_A10

SRAM_A11

SRAM_A12

SRAM_A13

SRAM_A14

SRAM_A15

SRAM_A16

SRAM_A17

SRAM_A18

SRAM_A0

SRAM_OE

SRAM_WE

SRAM_CE

C33

0603001UF

C34

0603001UF001UF

0603

C37001UF0603

C36

C42

0603001UF 001UF

0603

C41 C40

0603001UF001UF

0603

C39001UF0603

C46 C45

0603001UF 001UF

0603

C44C43

0603001UF

B6_L01P_Y2

B6_L01N_Y3

SRAM_D23

4

3

2

1

A B C D

20 Cotton Road

Nashua NH 03063

A B C D

4

3

2

1

PH 1-800-ANALOGD

C

Title

Size Board No

Date Sheet of

DEVICESANALOG

DNP = Do Not Populate

Rev

BLACKFIN FPGA EZ-EXTENDER

A0199-2005 10

EXPANSION INTERFACE TYPE B

P1Expanison Connector

Top Of BoardBottom Of Board

Expansion Connector 1

10-18-2005_1616 4 12

EXPANSION INTERFACE CONNECTOR 1

C3510UF805

01UF0603

C38

5V_EI

5V_EI

1

10

11 12

13 14

15 16

17 18

19

2

20

21 22

23 24

25 26

27 28

29

3

30

31 32

33 34

35 36

37 38

39

4

40

41 42

43 44

45 46

47 48

49

5

50

51 52

53 54

55 56

57 58

59

6

60

61 62

63 64

65 66

67 68

69

7

70

71 72

73 74

75 76

77 78

79

8

80

81 82

83 84

85 86

87 88

89

9

90

P1

CON01845X2

1

10

1112

1314

1516

1718

19

2

20

2122

2324

2526

2728

29

3

30

3132

3334

3536

3738

39

4

40

4142

4344

4546

4748

49

5

50

5152

5354

5556

5758

59

6

60

6162

6364

6566

6768

69

7

70

7172

7374

7576

7778

79

8

80

8182

8384

8586

8788

89

9

90

J1

CON01945X2

PP1

EXPANSION_PPI_CLK

PP3

UDEF2

UDEF4

UDEF6

UDEF8

UDEF10

D9

D7

D15

D13

D11

D5

D1

D3

D15

D9

D5

D1

D3

D0

D2

D4

D6

D8

D10

D14

D12

P1_5

P1_25

P1_27

P1_29

P1_31

P1_33

P1_55

P1_57

P1_59

P1_61

P1_63

P1_65

P1_67

P1_69

P1_35

P1_26

P1_28

P1_30

P1_32

P1_34

P1_56

P1_58

P1_60

P1_62

P1_64

P1_66

P1_68

P1_70

P1_36

P1_26

P1_28

P1_30

P1_32

P1_34

P1_36

P1_56

P1_58

P1_60

P1_62

P1_64

P1_66

P1_68

P1_70

P1_5

P1_25

P1_27

P1_29

P1_31

P1_33

P1_35

P1_55

P1_57

P1_59

P1_61

P1_63

P1_65

P1_67

P1_69

P1_[586]

A5

A6A7

A8A9

A10A11

A12A13

A14A15

A16A17

A18A19

D0

D2

D4

D6D7

D8

D10D11

D12D13

D14

A1

A2

B1_L24N_D15_J1_71B1_L24P_E15_J1_72

B1_L22N_A16_J1_73B1_L22P_B16_J1_74

B1_L19N_C16_J1_75B1_L19P_D16_J1_76

B1_L16N_B17_J1_77B1_L16P_C17_J1_78

B1_L15N_D17_J1_79

A3

B1_L15P_E17_J1_80

B1_L10N_A18_J1_81B1_L10P_B18_J1_82

B1_L09N_C18_J1_83B1_L09P_D18_J1_84

B1_L06N_A19_J1_85B1_L06P_B19_J1_86

A4A5

A6 A7

A8 A9

A10 A11

A12 A13

A14 A15

A16 A17

A18 A19

A1

A2

PP0

PP2

UDEF1

UDEF3

A3

UDEF5

UDEF7

UDEF9

UDEF11

A4

33V

25V 33V

33V

33V

33V

4

3

2

1

A B C D

20 Cotton Road

Nashua NH 03063

A B C D

4

3

2

1

PH 1-800-ANALOGD

C

Title

Size Board No

Date Sheet of

DEVICESANALOG

DNP = Do Not Populate

Rev

BLACKFIN FPGA EZ-EXTENDER

A0199-2005 10

VCCO_0_C8

VCCO_0_F8

VCCO_0_G9

VCCO_0_G10

VCCO_0_G11

IO_A10

IO_D9

IO_D10

IO_F6

IO_VREF_0_A3

IO_VREF_0_C7

IO_VREF_0_E5

IO_VREF_0_F7

IO_L06N_0_D5

IO_L06P_0_C5

IO_L09N_0_B5

IO_L09P_0_A5

IO_L10N_0_E6

IO_L10P_0_D6

IO_L15N_0_C6

IO_L15P_0_B6

IO_L16N_0_E7

IO_L16P_0_D7

IO_L19N_0_B7

IO_L19P_0_A7

IO_L22N_0_E8

IO_L22P_0_D8

IO_L24N_0_B8

IO_L24P_0_A8

IO_L25N_0_F9

IO_L25P_0_E9

IO_L27N_0_B9

IO_L27P_0_A9

IO_L28N_0_F10

IO_L28P_0_E10

IO_L29N_0_C10

IO_L29P_0_B10

IO_L30N_0_F11

IO_L30P_0_E11

IO_L31N_0_D11

IO_L31P_0_VREF_0_C11

IO_L01N_0_VRP_0_B4

IO_L01P_0_VRN_0_A4

IO_L32N_0_GCLK7_B11

IO_L32P_0_GCLK6_A11

VCCO_1_C15

VCCO_1_F15

VCCO_1_G12

VCCO_1_G13

VCCO_1_G14

IO_A12

IO_E16

IO_F12

IO_F13

IO_F16

IO_F17

IO_VREF_1_E13

IO_VREF_1_F14

IO_L06N_1_VREF_1_A19

IO_L06P_1_B19

IO_L09N_1_C18

IO_L09P_1_D18

IO_L10N_1_VREF_1_A18

IO_L10P_1_B18

IO_L15N_1_D17

IO_L15P_1_E17

IO_L16N_1_B17

IO_L16P_1_C17

IO_L19N_1_C16

IO_L19P_1_D16

IO_L22N_1_A16

IO_L22P_1_B16

IO_L24N_1_D15

IO_L24P_1_E15

IO_L25N_1_B15

IO_L25P_1_A15

IO_L27N_1_D14

IO_L27P_1_E14

IO_L28N_1_A14

IO_L28P_1_B14

IO_L29N_1_C13

IO_L29P_1_D13

IO_L30N_1_A13

IO_L30P_1_B13

IO_L31N_1_VREF_1_D12

IO_L31P_1_E12

IO_L01N_1_VRP_1_C19

IO_L01P_1_VRN_1_B20

IO_L32N_1_GCLK5_B12

IO_L32P_1_GCLK4_C12

FPGAFPGA

LAYOUT NOTE PLACE NEAR FPGA

5 129-27-2005_1144

C8

F8

G9

G10

G11

A10

D9

D10

F6

A3

C7

E5

F7

D5

C5

B5

A5

E6

D6

C6

B6

E7

D7

B7

A7

E8

D8

B8

A8

F9

E9

B9

A9

F10

E10

C10

B10

F11

E11

D11

C11

B4

A4

B11

A11

C15

F15

G12

G13

G14

A12

E16

F12

F13

F16

F17

E13

F14

A19

B19

C18

D18

A18

B18

D17

E17

B17

C17

C16

D16

A16

B16

D15

E15

B15

A15

D14

E14

A14

B14

C13

D13

A13

B13

D12

E12

C19

B20

B12

C12

U1

FG456XC3S1000

1

10

11 12

13 14

15 16

17 18

19

2

20

21 22

23 24

25 26

27 28

29

3

30

31 32

33 34

35 36

37 38

4

5 6

7 8

9

39 40

41

43

45

47

49

42

44

46

48

50

25X2CON041

P4

5

1

18

20

22

26

24

16

14

12

25

23

21

19

17

15

13

11

9

3

6

10

8

4

2

7

P8

IDC13X213X2

5

1

18

20

22

26

24

16

14

12

25

23

21

19

17

15

13

11

9

3

6

10

8

4

2

7

P14

IDC13X213X2

FPGA BANKS 0 + 1

001UF0603

C50

DNP0603

R52

B1_L10N_A18_J1_81

B1_L15P_E17_J1_80

R53

0603DNP

B1_L16P_C17_J1_78

R27

06030

B1_L10P_B18_J1_82B1_L10N_A18_J1_81

B1_L15N_D17_J1_79

B1_L16N_B17_J1_77

B1_L24N_D15_J1_71

B1_L22N_A16_J1_73

B1_L19N_C16_J1_75

R51

0603DNPDNP

0603

R50DNP0603

R48

R31

0603DNP

B1_L19N_C16_J1_75

B1_L22N_A16_J1_73

B1_L24N_D15_J1_71

B1_L15N_D17_J1_79

B1_L15P_E17_J1_80

B1_L16N_B17_J1_77

B1_L16P_C17_J1_78

DNP0603

R30

VCCO_1

VCCO_1

C47

0603001UF

VCCO_1

B1_L27N_D14

PB1

AOE

B1_L01P_VRN_B20

B1_L01N_VRP_C19

IO_L32_0_GCLK6_A11

IO_L32_0_GCLK7_B11

IO_L32_0_GCLK7_B11

B1_L32N_GCLK5_B12

B1_L32P_GCLK4_C12 B1_L06P_B19_J1_86

B1_L09P_D18_J1_84

B1_L15P_E17_J1_80

B1_L16P_C17_J1_78

B1_L19P_D16_J1_76

B1_L16N_B17_J1_77

B1_L15N_D17_J1_79

B1_L09N_C18_J1_83

B1_L06N_A19_J1_85

B1_L31P_E12

B1_L31N_D12

B1_L06N_A19_J1_85

B1_L09N_C18_J1_83

B1_L09P_D18_J1_84

B1_L06P_B19_J1_86

B1_F17

B1_F16

B1_E16

B1_F13

B1_E13

B1_F12

B1_A12

B1_F14

B1_L01N_VRP_C19

B1_L01P_VRN_B20

B1_L32P_GCLK4_C12

B1_L32N_GCLK5_B12

AMS3

D5

D4

AMS0

UDEF1

ARE

ARDY

AMS1

AMS2

UDEF11

UDEF9

UDEF7

UDEF5

UDEF3

PP2

PP0

D15

D11

D9

A17

B1_L16P_C17_J1_78

B1_L19P_D16_J1_76

B1_L19N_C16_J1_75

B1_L22P_B16_J1_74

B1_L24N_D15_J1_71

B1_L22N_A16_J1_73

B1_L24P_E15_J1_72

B1_L16N_B17_J1_77

B1_L10P_B18_J1_82

B1_L15P_E17_J1_80

B1_L15N_D17_J1_79

B1_L10N_A18_J1_81

B1_L09P_D18_J1_84

B1_L09N_C18_J1_83

B1_L06P_B19_J1_86

B1_L06N_A19_J1_85

B1_L31N_D12

B1_L30N_A13

B1_L29N_C13

B1_L28N_A14

B1_L27N_D14

B1_L25N_B15

B1_F16

B1_F14

B1_F13

B1_F12

B1_L31P_E12

B1_L30P_B13

B1_L29P_D13

B1_L28P_B14

B1_L27P_E14

B1_L25P_A15

B1_F17

B1_E13

B1_E16

B1_A12

UDEF10

ABE3

ABE1

ABE0

ABE2

AWE

UDEF6

UDEF8

PP3

UDEF4

UDEF2

PP1

D14

D8

D10

D12

B1_L25P_A15B1_L25N_B15

B1_L22N_A16_J1_73

B1_L24N_D15_J1_71

B1_L19N_C16_J1_75

B1_L24P_E15_J1_72

B1_L22P_B16_J1_74

B1_L27P_E14

B1_L19P_D16_J1_76

B1_L22P_B16_J1_74

B1_L24P_E15_J1_72

B1_L25N_B15

B1_L25P_A15

B1_L27N_D14

B1_L27P_E14

B1_L28N_A14

B1_L28P_B14

B1_L29N_C13

B1_L29P_D13

B1_L30N_A13

B1_L30P_B13

B1_L10N_A18_J1_81

B1_L10P_B18_J1_82

3

2

1

3X1IDC3X1

P9

EXPANSION_PPI_CLK

B1_F16 B1_F17

B1_L28P_B14

B1_L29P_D13

B1_L30P_B13

B1_L31P_E12

B1_L28N_A14

B1_L29N_C13

B1_L30N_A13

B1_L31N_D12

B1_E16

B1_E13

B1_A12

B1_L01P_VRN_B20

B1_L32P_GCLK4_C12

B1_F14

B1_L01N_VRP_C19

B1_L32N_GCLK5_B12

B1_F13

B1_F12

B1_L01P_VRN_B20

B1_L01N_VRP_C19

001UF0603

C48 C49

0603001UF

C51

0603001UF 001UF

0603

C52 C53

0603001UF001UF

0603

C54

VCCO_1

R49

0603DNP

B1_L10P_B18_J1_82

DNP0603

R54

4

3

2

1

A B C D

20 Cotton Road

Nashua NH 03063

A B C D

4

3

2

1

PH 1-800-ANALOGD

C

Title

Size Board No

Date Sheet of

DEVICESANALOG

DNP = Do Not Populate

Rev

BLACKFIN FPGA EZ-EXTENDER

A0199-2005 10Expanison ConnectorP2

Bottom Of Board Top Of Board

Expansion Connector 2

33V_EI

6 129-14-2005_1203

EXPANSION INTERFACE CONNECTOR 2

SCK

NMI

TMR1

PF1

PF3

PF5

PF7

PF9

PF11

PF13

PF15

1

10

11 12

13 14

15 16

17 18

19 20

21 22

23 24

25 26

27 28

29

3

30

31 32

33 34

35 36

37 38

39

4

40

41 42

43 44

45 46

47 48

49

5

50

51 52

53 54

55 56

57 58

59

6

60

61 62

63 64

65 66

67 68

69

7

70

71 72

73 74

75 76

77 78

79

8

80

81 82

83 84

85 86

87 88

89

9

90

2P2

CON01845X2

1

10

1112

1314

1516

1718

19

2

20

2122

2324

2526

2728

29

3

30

3132

3334

3536

3738

39

4

40

4142

4344

4546

4748

49

5

50

5152

5354

5556

5758

59

6

60

6162

6364

6566

6768

69

7

70

7172

7374

7576

7778

79

8

80

8182

8384

8586

8788

89

9

90

J2

CON01945X2

ARE

ARDY

AMS0

AMS1

P2_21

P2_19

P2_7

P2_21

P2_71

P2_73

P2_77

P2_79

P2_83

P2_85

P2_81

P2_19

P2_15

P2_5 P2_6

P2_8

P2_22

P2_86

P2_84

P2_82

P2_80

P2_78

P2_74

P2_72

P2_20

P2_18

P2_22

P2_74

P2_78

P2_82

P2_84

P2_86

P2_80

P2_72

P2_20

P2_18

P2_8

P2_6

P2_[586]

P2_5

P2_7

P2_15

P2_85

P2_83

P2_81

P2_79

P2_77

P2_73

P2_71AWE

AOE

ABE0

ABE1

ABE2

ABE3

TSCLK0

TFS0

DT0PRI

DT0SEC

CONFIG_CLK_TSCLK1

CONFIG_INIT_B_TFS1

DT1PRI

DT1SEC

TMR0

TMR2

PF14

PF12

PF10

PF8

PF4

PF6

PF2

PF0

B2_L40N_L21_J2_9

B2_L39N_L19_J2_11

B2_C22_J2_17

B2_L38N_L17_J2_23

B2_L35N_K21_J2_25

B2_L34N_K19_J2_27

B2_L33N_K17_J2_29

B2_L32N_J21_J2_31

B2_L31N_J18_J2_33

B2_L29N_H21_J2_35

B2_L28N_H18_J2_37

B2_L27N_G21_J2_39

B2_L26N_G20_J2_41

B2_L22N_G17_J2_43

B2_L24N_F20_J2_45

B2_L23N_F19_J2_47

B2_L21N_E21_J2_49

B2_L20N_E19_J2_51

B2_L19N_E18_J2_53

B2_L17N_D21_J2_55

B2_L16N_D20_J2_57B2_L16P_D19_J2_58

B2_L17P_D22_J2_56

B2_L19P_F18_J2_54

B2_L20P_E20_J2_52

B2_L21P_E22_J2_50

B2_L23P_G19_J2_48

B2_L24P_F21_J2_46

B2_L22P_G18_J2_44

B2_L26P_H19_J2_42

B2_L27P_G22_J2_40

B2_L28P_J17_J2_38

B2_L29P_H22_J2_36

B2_L31P_J19_J2_34

B2_L32P_J22_J2_32

B2_L33P_K18_J2_30

B2_L34P_K20_J2_28

B2_L35P_K22_J2_26

B2_L38P_L18_J2_24

IO_L01P_2_VRN_2_C21_J2_16

B2_L40P_L22_J2_10

B2_L39P_L20_J2_12

MOSI

MISO

UDEF12

AMS3

AMS2

AMS0

ARDY

AMS1

AREAWE

AOE

ABE0

ABE1

ABE2

ABE3

RSCLK1

RSCLK0

RFS1

DR1PRI

DR1SEC

AMS2

AMS3

DR0SEC

DR0PRI

RFS0

TMR3

SPIDS0

C56

060301UF

80510UFC55

33V_EI

33V

4

3

2

1

A B C D

20 Cotton Road

Nashua NH 03063

A B C D

4

3

2

1

PH 1-800-ANALOGD

C

Title

Size Board No

Date Sheet of

DEVICESANALOG

DNP = Do Not Populate

Rev

BLACKFIN FPGA EZ-EXTENDER

A0199-2005 10

33V

25V33V

33V

33V

VCCO_2_H17

VCCO_2_H20

VCCO_2_J16

VCCO_2_K16

VCCO_2_L16

IO_C22

IO_L16N_2_D20

IO_L16P_2_D19

IO_L17N_2_D21

IO_L17P_2_VREF_2_D22

IO_L19N_2_E18

IO_L19P_2_F18

IO_L20N_2_E19

IO_L20P_2_E20

IO_L21N_2_E21

IO_L21P_2_E22

IO_L22N_2_G17

IO_L22P_2_G18

IO_L23N_2_VREF_2_F19

IO_L23P_2_G19

IO_L24N_2_F20

IO_L24P_2_F21

IO_L26N_2_G20

IO_L26P_2_H19

IO_L27N_2_G21

IO_L27P_2_G22

IO_L28N_2_H18

IO_L28P_2_J17

IO_L29N_2_H21

IO_L29P_2_H22

IO_L31N_2_J18

IO_L31P_2_J19

IO_L32N_2_J21

IO_L32P_2_J22

IO_L33N_2_K17

IO_L33P_2_K18

IO_L34N_2_VREF_2_K19

IO_L34P_2_K20

IO_L35N_2_K21

IO_L35P_2_K22

IO_L38N_2_L17

IO_L38P_2_L18

IO_L39N_2_L19

IO_L39P_2_L20

IO_L40N_2_L21

IO_L40P_2_VREF_2_L22

IO_L01N_2_VRP_2_C20

IO_L01P_2_VRN_2_C21

VCCO_3_M16

VCCO_3_N16

VCCO_3_P16

VCCO_3_R17

VCCO_3_R20

IO_L16N_3_W22

IO_L16P_3_Y22

IO_L17N_3_V19

IO_L17P_3_VREF_3_W19

IO_L19N_3_W21

IO_L19P_3_W20

IO_L20N_3_U19

IO_L20P_3_V20

IO_L21N_3_V22

IO_L21P_3_V21

IO_L22N_3_T17

IO_L22P_3_U18

IO_L23N_3_U21

IO_L23P_3_VREF_3_U20

IO_L24N_3_R18

IO_L24P_3_T18

IO_L26N_3_T20

IO_L26P_3_T19

IO_L27N_3_T22

IO_L27P_3_T21

IO_L28N_3_R22

IO_L28P_3_R21

IO_L29N_3_P19

IO_L29P_3_R19

IO_L31N_3_P18

IO_L31P_3_P17

IO_L32N_3_P22

IO_L32P_3_P21

IO_L33N_3_N18

IO_L33P_3_N17

IO_L34N_3_N20

IO_L34P_3_VREF_3_N19

IO_L35N_3_N22

IO_L35P_3_N21

IO_L38N_3_M18

IO_L38P_3_M17

IO_L39N_3_M20

IO_L39P_3_M19

IO_L40N_3_VREF_3_M22

IO_L40P_3_M21

IO_L01N_3_VRP_3_Y20

IO_L01P_3_VRN_3_Y19

IO_Y21

FPGAFPGA

LAYOUT NOTE PLACE NEAR FPGA

9-27-2005_1144 7 12

H17

H20

J16

K16

L16

C22

D20

D19

D21

D22

E18

F18

E19

E20

E21

E22

G17

G18

F19

G19

F20

F21

G20

H19

G21

G22

H18

J17

H21

H22

J18

J19

J21

J22

K17

K18

K19

K20

K21

K22

L17

L18

L19

L20

L21

L22

C20

C21

M16

N16

P16

R17

R20

W22

Y22

V19

W19

W21

W20

U19

V20

V22

V21

T17

U18

U21

U20

R18

T18

T20

T19

T22

T21

R22

R21

P19

R19

P18

P17

P22

P21

N18

N17

N20

N19

N22

N21

M18

M17

M20

M19

M22

M21

Y20

Y19

Y21

U1

FG456XC3S1000

2

4

8

10

6

12

14

16

24

22

20

18

26

28

3

5

7

9

11

13

15

17

19

21

23

25

27

1P5

IDC14X214X2

1

27

25

23

21

19

17

15

13

11

9

7

5

3

28

26

18

20

22

24

16

14

12

6

10

8

4

2P7

IDC14X214X2

VCCO_2

B2_L26P_H19_J2_42

DNP0603

R55B2_L24P_F21_J2_46

R56

0603DNP

B2_L23P_G19_J2_48

B2_L26N_G20_J2_41

B2_L24N_F20_J2_45

B2_L23N_F19_J2_47 B2_L23P_G19_J2_48

B2_L24P_F21_J2_46

B2_L26P_H19_J2_42

R32

0603DNP

TMR0

VCCO_2

PF221

2X1IDC2X1

JP3

CONFIG_PROG_B

1 2JP2

IDC2X12X1

PF3

CONFIG_INIT_B_TFS1

CONFIG_CLK_TSCLK1

RSCLK1

RFS1

IO_L01N_2_VRP_2_C20

IO_L01P_2_VRN_2_C21_J2_16

B2_L22N_G17_J2_43

B2_L22P_G18_J2_44

B2_L32N_J21_J2_31

SPIDS0

PF0

SCK

NMI

TMR1

DR1SEC

TMR3

DR0PRI

DR1PRI

RFS0

DR0SEC

PF15

PF13

RSCLK0

PF7

PF9

PF6

PF11

PF1

PF3

PF5

MOSI

MISO

UDEF12

TMR2

DT1SEC

DT1PRI

DT0SEC

TSCLK0

PF14

PF12

PF10

PF8

PF4

PF2

FPGA BANKS 2 + 3

DT0PRI

TFS0

B2_L40P_L22_J2_10

B2_L40N_L21_J2_9

B2_L39P_L20_J2_12

B2_L39N_L19_J2_11

B2_L38P_L18_J2_24

B2_L38N_L17_J2_23

B2_L35P_K22_J2_26

B2_L35N_K21_J2_25

B2_L34P_K20_J2_28

B2_L34N_K19_J2_27

B2_L33P_K18_J2_30

B2_L33N_K17_J2_29

B2_L32P_J22_J2_32

B2_L31P_J19_J2_34

B2_L31N_J18_J2_33

B2_L29P_H22_J2_36

B2_L29N_H21_J2_35

B2_L28P_J17_J2_38

B2_L28N_H18_J2_37

B2_L27P_G22_J2_40

B2_L27N_G21_J2_39

B2_L26P_H19_J2_42

B2_L26N_G20_J2_41

B2_L24P_F21_J2_46

B2_L24N_F20_J2_45

B2_L23P_G19_J2_48

B2_L23N_F19_J2_47

B2_L21P_E22_J2_50

B2_L21N_E21_J2_49

B2_L20P_E20_J2_52

B2_L20N_E19_J2_51

B2_L19P_F18_J2_54

B2_L19N_E18_J2_53

B2_L17P_D22_J2_56

B2_L17N_D21_J2_55

B2_L16P_D19_J2_58

B2_L16N_D20_J2_57

B2_C22_J2_17

3

2

1

3X1IDC3X1

P10

IO_L01P_2_VRN_2_C21_J2_16

IO_L01N_2_VRP_2_C20

VCCO_2

CONFIG_DONE

B2_L22N_G17_J2_43

B2_L17N_D21_J2_55

B2_L19N_E18_J2_53

B2_L20N_E19_J2_51

B2_L21N_E21_J2_49

B2_L16N_D20_J2_57

IO_L01N_2_VRP_2_C20

B2_L16P_D19_J2_58

B2_L20P_E20_J2_52

B2_L19P_F18_J2_54

B2_L17P_D22_J2_56

B2_L22P_G18_J2_44

B2_L21P_E22_J2_50

B2_C22_J2_17

IO_L01P_2_VRN_2_C21_J2_16

B2_L40N_L21_J2_9

B2_L39N_L19_J2_11

B2_L38N_L17_J2_23

B2_L35N_K21_J2_25

B2_L34N_K19_J2_27

B2_L33N_K17_J2_29

B2_L32N_J21_J2_31

B2_L31N_J18_J2_33

B2_L29N_H21_J2_35

B2_L28N_H18_J2_37

B2_L27N_G21_J2_39

B2_L40P_L22_J2_10

B2_L34P_K20_J2_28

B2_L35P_K22_J2_26

B2_L38P_L18_J2_24

B2_L39P_L20_J2_12

B2_L33P_K18_J2_30

B2_L32P_J22_J2_32

B2_L28P_J17_J2_38

B2_L31P_J19_J2_34

B2_L29P_H22_J2_36

B2_L27P_G22_J2_40

DNP0603

R33

B2_L23N_F19_J2_47

B2_L24N_F20_J2_45

B2_L26N_G20_J2_41

DNP0603

R57

001UF0603

C60 C59

0603001UF 001UF

0603

C58 C57

0603001UF

C82

0603001UF 001UF

0603

C81 C62

0603001UF001UF

0603

C61

VCCO_2

4

3

2

1

A B C D

20 Cotton Road

Nashua NH 03063

A B C D

4

3

2

1

PH 1-800-ANALOGD

C

Title

Size Board No

Date Sheet of

DEVICESANALOG

DNP = Do Not Populate

Rev

BLACKFIN FPGA EZ-EXTENDER

A0199-2005 10

Expanison ConnectorExpanison Connector

Bottom Of Board Top Of BoardExpansion Connector 3

EXPANSION INTERFACE (TYPE B)

P3P3

9-9-2005_1029 128

EXPANSION INTERFACE CONNECTOR 1

33V_EI5V_EI

1

10

11 12

13 14

15 16

17 18

19

2

20

21 22

23 24

25 26

27 28

29

3

30

31 32

33 34

35 36

37 38

39

4

40

41 42

43 44

45 46

47 48

49

5

50

51 52

53 54

55 56

57 58

59

6

60

61 62

63 64

65 66

67 68

69

7

70

71 72

73 74

75 76

77 78

79

8

80

81 82

83 84

85 86

87 88

89

9

90

P3

CON01845X2

1

10

1112

1314

1516

1718

19

2

20

2122

2324

2526

2728

29

3

30

3132

3334

3536

3738

39

4

40

4142

4344

4546

4748

49

5

50

5152

5354

5556

5758

59

6

60

6162

6364

6566

6768

69

7

70

7172

7374

7576

7778

79

8

80

8182

8384

8586

8788

89

9

90

J3

CON01945X2

TX0

TX1

UDEF17

UDEF19

UDEF21

UDEF23

UDEF25

UDEF29

UDEF27

RESET

UDEF32

UDEF34

UDEF36

UDEF38

UDEF40

B5_L01N_RDWR_B_Y4_J3_1

P3_42

P3_[190]

P3_86

P3_84

P3_82

P3_80

P3_78

P3_76

P3_74

P3_72

P3_70

P3_68

P3_64

P3_62

P3_60

P3_58

P3_56

P3_54

P3_52

P3_50

P3_48

P3_46

P3_42

P3_79

P3_89

P3_77

P3_75

P3_73

P3_71

P3_69

P3_67

P3_63

P3_61

P3_59

P3_57

P3_55

P3_53

P3_51

P3_49

P3_47

P3_45

P3_51

P3_79

P3_89

P3_77

P3_75

P3_73

P3_71

P3_69

P3_67

P3_63

P3_61

P3_59

P3_57

P3_55

P3_53

P3_49

P3_47

P3_45

P3_86

P3_84

P3_82

P3_80

P3_78

P3_76

P3_74

P3_72

P3_70

P3_68

P3_64

P3_62

P3_60

P3_58

P3_56

P3_54

P3_52

P3_50

P3_48

P3_46

B5_L27N_W9_J3_31

B5_L28N_D6_AB9_J3_33

B5_L29N_Y10_J3_35

B5_L30N_AB10_J3_37

B5_L31N_D4_W11_J3_39

B5_L10N_VRP_AB5_J3_9

B5_L25N_AB8_J3_21

B5_L24N_W8_J3_19

B5_L22N_AB7_J3_17

B5_L19N_Y7_J3_15

B5_L16N_AA6_J3_13

B5_L15N_W6_J3_11

B5_L09N_Y5_J3_7

B5_L06N_AB4_J3_5

B5_U6_J3_23

B5_V7_J3_29

B5_U9_J3_41

B5_L31P_D5_V11_J3_40

B5_L30P_AA10_J3_38

B5_L29P_W10_J3_36

B5_L28P_D7_AA9_J3_34

B5_L27P_V9_J3_32

B5_L32N_GCLK3_AA11_J3_30

B5_U7_J3_28

B5_L25P_AA8_J3_22

B5_L24P_V8_J3_20

B5_L22P_AA7_J3_18

B5_L19P_W7_J3_16

B5_L16P_Y6_J3_14

B5_L15P_V6_J3_12

B5_L10P_VRN_AA5_J3_10

B5_L09P_W5_J3_8

B5_L06P_AA4_J3_6

B5_L01P_CS_B_AA3_J3_2

B5_AB11_J3_90

B5_U11_J3_83

B5_V10_J3_85

B5_U10_J3_81

UDEF43

BGH

BG

BR

UDEF30

UDEF28

UDEF26

UDEF24

UDEF22

UDEF20

UDEF18

UDEF16

RX1

RX0

UDEF14 UDEF15

CLK_OUT_EXP1

UDEF31

UDEF33

UDEF35

UDEF37

UDEF39

UDEF41

33V_EI

C84

060301UF

80510UFC83

C8610UF805

01UF0603

C85

5V_EI

33V

33V

25V 33V

33V

33V

33V

4

3

2

1

A B C D

20 Cotton Road

Nashua NH 03063

A B C D

4

3

2

1

PH 1-800-ANALOGD

C

Title

Size Board No

Date Sheet of

DEVICESANALOG

DNP = Do Not Populate

Rev

BLACKFIN FPGA EZ-EXTENDER

A0199-2005 10

VCCO_4_T12

VCCO_4_T13

VCCO_4_T14

VCCO_4_U15

VCCO_4_Y15

IO_U16

IO_U17

IO_W13

IO_W14

IO_VREF_4_V18

IO_VREF_4_Y16

IO_VREF_4_AB13

IO_L05N_4_AA19

IO_L05P_4_AB19

IO_L06N_4_VREF_4_W18

IO_L06P_4_Y18

IO_L09N_4_AA18

IO_L09P_4_AB18

IO_L10N_4_V17

IO_L10P_4_W17

IO_L15N_4_Y17

IO_L15P_4_AA17

IO_L16N_4_V16

IO_L16P_4_W16

IO_L19N_4_AA16

IO_L19P_4_AB16

IO_L22N_4_VREF_4_V15

IO_L22P_4_W15

IO_L24N_4_AA15

IO_L24P_4_AB15

IO_L25N_4_U14

IO_L25P_4_V14

IO_L27N_4_DIN_D0_AA14

IO_L27P_4_D1_AB14

IO_L28N_4_U13

IO_L28P_4_V13

IO_L29N_4_Y13

IO_L29P_4_AA13

IO_L30N_4_D2_U12

IO_L30P_4_D3_V12

IO_L31N_4_INIT_B_W12

IO_L31P_4_DOUT_BUSY_Y12

IO_L01N_4_VRP_4_AA20

IO_L01P_4_VRN_4_AB20

IO_L32N_4_GCLK1_AA12

IO_L32P_4_GCLK0_AB12

VCCO_5_T9

VCCO_5_T10

VCCO_5_T11

VCCO_5_U8

VCCO_5_Y8

IO_U7

IO_U9

IO_U10

IO_U11

IO_V7

IO_V10

IO_VREF_5_U6

IO_VREF_5_AB11

IO_L01N_5_RDWR_B_Y4

IO_L01P_5_CS_B_AA3

IO_L06N_5_AB4

IO_L06P_5_AA4

IO_L09N_5_Y5

IO_L09P_5_W5

IO_L15N_5_W6

IO_L15P_5_V6

IO_L16N_5_AA6

IO_L16P_5_Y6

IO_L19N_5_Y7

IO_L19P_5_VREF_5_W7

IO_L22N_5_AB7

IO_L22P_5_AA7

IO_L24N_5_W8

IO_L24P_5_V8

IO_L25N_5_AB8

IO_L25P_5_AA8

IO_L27N_5_VREF_5_W9

IO_L27P_5_V9

IO_L28N_5_D6_AB9

IO_L28P_5_D7_AA9

IO_L29N_5_Y10

IO_L29P_5_VREF_5_W10

IO_L30N_5_AB10

IO_L30P_5_AA10

IO_L31N_5_D4_W11

IO_L31P_5_D5_V11

IO_L32N_5_GCLK3_AA11

IO_L32P_5_GCLK2_Y11

IO_L10N_5_VRP_5_AB5

IO_L10P_5_VRN_5_AA5

FPGAFPGA

1299-27-2005_1144

T12

T13

T14

U15

Y15

U16

U17

W13

W14

V18

Y16

AB13

AA19

AB19

W18

Y18

AA18

AB18

V17

W17

Y17

AA17

V16

W16

AA16

AB16

V15

W15

AA15

AB15

U14

V14

AA14

AB14

U13

V13

Y13

AA13

U12

V12

W12

Y12

AA20

AB20

AA12

AB12

T9

T10

T11

U8

Y8

U7

U9

U10

U11

V7

V10

U6

AB11

Y4

AA3

AB4

AA4

Y5

W5

W6

V6

AA6

Y6

Y7

W7

AB7

AA7

W8

V8

AB8

AA8

W9

V9

AB9

AA9

Y10

W10

AB10

AA10

W11

V11

AA11

Y11

AB5

AA5

U1

FG456XC3S1000

7

2

4

8

10

6

3

9

11

13

15

17

19

21

23

25

12

14

16

24

26

22

20

18

1

5

P16

IDC13X213X2

5

1

18

20

22

26

24

16

14

12

25

23

21

19

17

15

13

11

9

3

6

10

8

4

2

7

P17

IDC13X213X2

R46

060310K

R43

0603DNP

FPGA BANKS 4 + 5

VCCO_5

CONFIG_INIT_B_TFS1

CLK_OUT_EXP1

B4_L32N_GCKL1_AA12

R9

06030

B5_L10N_VRP_AB5_J3_9

B5_L10N_VRP_AB5_J3_9

B5_L10P_VRN_AA5_J3_10

VCCO_5

B5_L32P_GCLK2_Y1

B5_L32N_GCLK3_AA11_J3_30

CONFIG_DIN_DT1PRI

UDEF16

UDEF38

UDEF14

RX0

TX0

RX1

TX1

UDEF20

UDEF21

UDEF23

UDEF17

UDEF25

UDEF24

UDEF22

RESET

UDEF30

UDEF29

UDEF27

UDEF26

UDEF35

UDEF34

UDEF33

UDEF32

UDEF31

UDEF15

UDEF28

UDEF41

UDEF40

UDEF39

UDEF37

UDEF36

BR

UDEF43

BG

BGH

UDEF19

B5_L31P_D5_V11_J3_40

B5_L31N_D4_W11_J3_39

B5_L30P_AA10_J3_38

B5_L30N_AB10_J3_37

B5_L29P_W10_J3_36

B5_L29N_Y10_J3_35

B5_L28P_D7_AA9_J3_34

B5_L28N_D6_AB9_J3_33

B5_L27P_V9_J3_32

B5_L27N_W9_J3_31

B5_L25P_AA8_J3_22

B5_L25N_AB8_J3_21

B5_L24P_V8_J3_20

B5_L24N_W8_J3_19

B5_L22P_AA7_J3_18

B5_L22N_AB7_J3_17

B5_L19P_W7_J3_16

B5_L19N_Y7_J3_15

B5_L16P_Y6_J3_14

B5_L16N_AA6_J3_13

B5_L15P_V6_J3_12

B5_L15N_W6_J3_11

B5_L09P_W5_J3_8

B5_L09N_Y5_J3_7

B5_L06P_AA4_J3_6

B5_L06N_AB4_J3_5

B5_L01P_CS_B_AA3_J3_2

B5_L01N_RDWR_B_Y4_J3_1

B5_AB11_J3_90

B5_U6_J3_23

B5_V10_J3_85

B5_V7_J3_29

B5_U11_J3_83

B5_U10_J3_81

B5_U9_J3_41

B5_U7_J3_28

UDEF18

3

2

1

3X1IDC3X1

P11

B5_L29N_Y10_J3_35

B5_L30N_AB10_J3_37

B5_L31N_D4_W11_J3_39

B5_U11_J3_83

B5_V10_J3_85B5_AB11_J3_90

B5_U10_J3_81

B5_L31P_D5_V11_J3_40

B5_L30P_AA10_J3_38

B5_L29P_W10_J3_36

B5_L28P_D7_AA9_J3_34

B5_L27P_V9_J3_32

B5_L28N_D6_AB9_J3_33

B5_L27N_W9_J3_31

B5_L25N_AB8_J3_21B5_L25P_AA8_J3_22

B5_L24N_W8_J3_19B5_L24P_V8_J3_20

B5_U9_J3_41B5_U6_J3_23

VCCO_5

B5_L10P_VRN_AA5_J3_10

C70

0603001UF 001UF

0603

C69 C68

0603001UF001UF

0603

C67001UF0603

C66 C65

0603001UF 001UF

0603

C64C63

0603001UF

B5_L09N_Y5_J3_7

B5_U7_J3_28 B5_V7_J3_29

B5_L10P_VRN_AA5_J3_10 B5_L10N_VRP_AB5_J3_9

B5_L15P_V6_J3_12 B5_L15N_W6_J3_11

B5_L16P_Y6_J3_14 B5_L16N_AA6_J3_13

B5_L19P_W7_J3_16 B5_L19N_Y7_J3_15

B5_L22P_AA7_J3_18 B5_L22N_AB7_J3_17

B5_L32N_GCLK3_AA11_J3_30 B5_L32P_GCLK2_Y1

B5_L01P_CS_B_AA3_J3_2 B5_L01N_RDWR_B_Y4_J3_1

B5_L06P_AA4_J3_6 B5_L06N_AB4_J3_5

B5_L09P_W5_J3_8

VCCO_5

DNP0603

R45

25V

33V

33V

4

3

2

1

A B C D

20 Cotton Road

Nashua NH 03063

A B C D

4

3

2

1

PH 1-800-ANALOGD

C

Title

Size Board No

Date Sheet of

DEVICESANALOG

DNP = Do Not Populate

Rev

BLACKFIN FPGA EZ-EXTENDER

A0199-2005 10

SN74LVC1G125

12109-27-2005_1144

2 4

1

SOT23-5SN74LVC1G125

U8

USER IO

C80

0603001UF

SW4SWT013SPST-MOMENTARY

SPST-MOMENTARYSWT013SW3

060310R42

C5

06031UF

R413300603

LED001AMBER-SMTLED8

0603330R40

LED7AMBER-SMTLED001

R393300603

R1033006030603

330R34R35

33006030603

330R36

0603330R37 R38

3300603

LED001AMBER-SMTLED2

AMBER-SMTLED001

LED3AMBER-SMTLED001

LED4AMBER-SMTLED001

LED5

LED001AMBER-SMTLED6

LED9GREEN-SMTLED001

402100R23

1 2

3 4

5 6

7 8

JP5

IDC4X24X2

AMBER-SMTLED001

LED1

B6_L01N_Y3

B6_L01P_Y2

B5_U10_J3_81

B5_AB11_J3_90

PB2

B5_V10_J3_85

B5_U11_J3_83

B5_L31N_D4_W11_J3_39

B5_L30N_AB10_J3_37

B5_L29N_Y10_J3_35

B5_L28N_D6_AB9_J3_33

B5_L27N_W9_J3_31

PB1

B5_L25N_AB8_J3_21

R47

060310K

CHOKE_COIL

4

3

2

1

A B C D

20 Cotton Road

Nashua NH 03063

A B C D

4

3

2

1

PH 1-800-ANALOGD

C

Title

Size Board No

Date Sheet of

DEVICESANALOG

DNP = Do Not Populate

Rev

BLACKFIN FPGA EZ-EXTENDER

A0199-2005 10

25V

33V

VIN

EN

SW

GND

FB

VIN

EN

SW

GND

FB

VIN

EN

SW

GND

FB

4

3

5

2

1

VR3

SOT23-5LM3475MF

1

2

5

3

4

VR2

SOT23-5LM3475MF

4

3

5

2

1

VR1

SOT23-5LM3475MF

12119-27-2005_1124

1

32

Q2

SI2

343D

SS

OT

23D

1

32

Q3

SI2

343D

SS

OT

23D

2 3

1S

I234

3DS

Q1

SO

T23

D

316KR17

0603

215KR18

0603

0603

R11105K

DNPC73

0603

0603

C72DNP

805

C741000PF

0R58

0603

1000PFC10

805

0603

R1910K

C100UFCT2

CT3100UFC

IND005

L110UH

10UHL3

IND005

10UHL2

IND005

1

2 D3

DO214ABSCHOT_RECT

3A

0603

R20200K

805

C639NF

390PFC7

0603

2

1 3A

SCHOT_RECTDO214AB

D2

499KR13

0603

1

2 D1

DO214ABSCHOT_RECT

3A

33V_EI

3

1

2

3X1IDC3X1

P13

UNREG_IN

12V

CT1100UFC

80510UFC71

R1200603

5V_EI

8051000PFC2

FER2

0603

060301UFC3

POWER

FUS00125AF1

4

1

3

2

FER1

DO-214AA

S2A_RECT

2AD5

8051000PFC1 C4

10UFC

3

1

2

3X1IDC3X1

P12

UNREG_IN

1

2

3

CON00525MM_JACK

POWER

J4

2

1P42

IDC2X12X1DNP

1

2

DNP2X1IDC2X1

P43

06030R15

C810UF805

80510UFC9

R1600603

UNREG_IN

0603

R1410K

0603

R590

4

3

2

1

A B C D

20 Cotton Road

Nashua NH 03063

A B C D

4

3

2

1

PH 1-800-ANALOGD

C

Title

Size Board No

Date Sheet of

DEVICESANALOG

DNP = Do Not Populate

Rev

BLACKFIN FPGA EZ-EXTENDER

A0199-2005 1012129-14-2005_1204

5

2

4

8

10

6

1

3

9

11

13

15

17

19

12

14

16

20

18

7

P20

SOIC20

PROTO AREA

1

3

2

SOT23D

P39

2

3

1

SOT23D

P38

2

4

5 6

3

1

SOT23-6

P411

3

65

4

2

SOT23-6

P40

PRT_NUM=DNE

11

13

15 16

14

12

2

4

6

8

109

7

5

3

1

SOIC16

P191

3

5

7

9 10

8

6

4

2

12

14

1615

13

11

SOIC16

P18

21P37

805

1 2

805

P36

21P35

805

1 2

805

P34

1 2

805

P33

21P32

805

1 2

805

P31

21P30

805

1 2

805

P29

21P28

805

1 2

805

P27

21P26

805

21P25

805

1 2

805

P24

21P23

805

1 2

805

P22

TP86

TP85

TP84

TP83

TP82

TP81

TP80

TP79 TP77

TP76

TP75

TP74

TP73

TP72

TP71

TP70

TP68

TP67

TP66

TP65

TP64

TP62

TP61

TP60

TP59

TP58

TP57

TP56

TP55

TP54

TP53

TP51

TP50

TP49

TP48

TP47

TP46

TP45

TP44

TP43

TP41

TP40

TP39

TP38

TP37

TP36

TP35

TP34

TP33

TP32

TP30

TP29

TP28

TP27

TP26

TP25

TP24

TP23

TP22

TP21

TP19

TP18

TP17

TP16

TP15

TP14

TP13

TP12

TP11

TP9

TP8

TP7

TP6

TP5

TP4

TP125

TP124

TP123

TP122

TP121

TP120

TP119

TP118

TP117

TP116

TP114

TP113

TP112

TP111

TP110

TP109

TP108

TP107TP106

TP105TP103

TP102TP101 TP100TP99

TP98 TP97

TP96 TP95

TP94TP93

TP92TP91

TP90 TP89

TP88 TP87

TP78TP69

TP63 TP52

TP42 TP31

TP20 TP10

TP115TP104

7

18

20

16

14

12

19

17

15

13

11

9

3

1

6

10

8

4

2

5

SOIC20

P21

I INDEX

Numerics connectors

25V header (P42) 2-17

AADSP-BF5333761 EZ-KIT Lite interface 2-1ADSP-BF5333761 processors boot mode

settings 2-14architecture of this EZ-Extender 2-2asynchronous static random access memory

(SRAM) xauxiliary oscillator x

Bbill of materials A-1block diagram of this EZ-Extender 2-2boot jumper See JP4

Cconfiguration jumpers See JP2 JP3

map of locations 2-18J1-3 (expansion) 2-19P1-3 (expansion) 2-19P14 (IDC) 2-19P15 (JTAG header) 2-4P16-17 (IDC) 2-19P4 (high-speed) 2-20P5 (IDC) 2-20P6 (JTAG) 2-7P7 (IDC) 2-20P8 (IDC) 2-19

customer support xiii

Ddone LED (LED10) 2-17

Eexpansion interface

connectors (P1-3 J1-3) 2-19of ADSP-BF5333761 EZ-KIT Lites ix

1-3external power supply 1-3 2-8

FField-Programmable Gate Array See FPGA

Blackfin FPGA EZ-Extender Manual I-1

INDEX

FPGAdocumentation 1-2input jumpers (JP5) 2-14softwarefirmware 1-2Xilinx Spartan package x 1-3

FPGA pinsAB10 (LED3) 2-17AB11 (JP58) 2-15AB8 (LED7) 2-17AB9 (LED5) 2-17C11 (PB1SW3) 2-15H5 (PB2SW3) 2-16M2-0 (JP4) 2-14U10 (JP56) 2-15U11 (LED1) 2-17V10 (LED8) 2-17W11 (LED2) 2-17W9 (LED6) 2-17Y10 (LED4) 2-17Y3-2 (JP52-54) 2-15

FPGA programmingblock diagram 2-3via ADSP-BF533376 processors 2-6via JTAG header 2-4via serial ROM 2-5

GGCLK1 (global clock 1) pin 1-4GCLK6 (global clock 6) pin 1-4general-purpose input push buttons 2-15 2-16

Hhigh-speed connector (P4) 2-20

IIDC connectors x 2-19 2-20installation of this EZ-Extender 1-1

JJTAG

cable 1-4 2-7header (P6) 1-5 2-4 2-7 2-14

jumpersmap of locations 2-11JP1 (boot jumper) 2-5 2-12JP2 (confug done) 2-12JP3 (config program) 2-13JP41-46 (boot mode select) 2-5 2-6 2-14JP52-56 (FPGA input) 2-14

LLEDs

map of locations 2-15LED10 (FPGA done pin) 2-4 2-5 2-17LED1-8 (status) 2-17LED9 (power) 2-17

MM2-0 (JP4) pins 2-5master serial boot mode 2-6MCS-86 Hexadecimal Object (mcs) file

format 2-6

Nnotation conventions xvi

Ooscillator x 1-4

PP12 (power in) header 2-9P13 (33V header) 2-9P42 (25V header) 2-10P43 (12V header) 2-10PB1 push button (SW3) 2-15

I-2 Blackfin FPGA EZ-Extender Manual

INDEX

PB2 push button (SW4) 2-16PF14 flag pin (ADSP-BF537 EZ-KIT Lite)

2-12PF3 flag pin (ADSP-BF53361 EZ-KIT Lite)

2-12power

12V header (P43) 2-1025V header (P42) 2-1033V header (P13) 2-9in header (P12) 2-9LED (LED9) 2-17limitations 2-8supplies 1-3 2-8

printed circuit board (PCB) 1-2product overview ixprogram push button (SW1) 2-4 2-15push buttons

See also SWx map of locations 2-15

Sserial ROM 1-5

boot jumper (JP1) 2-12 2-14programming via JTAG Header 2-7

setup of this EZ-Extender 1-1slave serial mode 2-6

SRAM memory banks 1-4status reporting 1-4 2-17SW1 (program) push button 2-4 2-15SW3 (PB1) push button 2-15SW4 (PB2) push button 2-16switching regulators 2-8

TTCK signal 2-7TDI signal 2-7TDO signal 2-7TMS signal 2-7

VVisualDSP++

flash programming utility 1-4 2-6FPGA documentation 2-6

VR1-3 regulators 2-8

XXilinx

JTAG cablesoftware 1-4 2-4 2-7JTAG header 2-12serial ROM 1-5

Blackfin FPGA EZ-Extender Manual I-3

INDEX

I-4 Blackfin FPGA EZ-Extender Manual

• Blackfin FPGA EZ-Extender Manual
• Contents
• Preface
• • Product Overview
  • Purpose of This Manual
  • Intended Audience
  • Manual Contents
  • Whatrsquos New in This Manual
  • Technical or Customer Support
  • Supported Products
  • Product Information
  • • Related Documents
    • • Table 1 Related Processor Publications
      • Table 2 Related VisualDSP++ Publications
      • • Notation Conventions
        • • 1 FPGA EZ-Extender Interfaces
          • • FPGA EZ-Extender Setup
            • • Figure 1-1 FPGA EZ-Extender Setup
              • • FPGA Software and Firmware
                • FPGA EZ-Extender Overview
                • • 2 FPGA EZ-Extender Hardware Reference
                  • • System Architecture
                    • • Figure 2-1 Block Diagram
                      • • Programming the FPGA
                        • • Figure 2-2 FPGA Programming Block Diagram
                          • FPGA Programming via JTAG
                          • • Table 2-1 P15 Connections for PFGA Programming via JTAG
                            • Table 2-2 JP1 Settings for FPGA Programming via JTAG
                            • Table 2-3 JP4 Settings for FPGA Programming via JTAG
                            • • FPGA Programming via Serial ROM
                              • • Table 2-4 JP1 Settings for FPGA Programming via Serial ROM
                                • Table 2-5 JP4 Settings for FPGA Programming in Master Serial Mode
                                • • FPGA Programming via Blackfin Application
                                  • • Table 2-6 JP1 Settings for FPGA Programming via Blackfin Processor
                                    • Table 2-7 JP4 Settings for FPGA Programming via Blackfin Processor
                                    • • Programming the Serial ROM
                                      • • Serial ROM via JTAG Header
                                        • • Table 2-8 P6 Connections for Serial ROM
                                          • • Power
                                            • • Table 2-9 Power Limitations
                                              • Power In Header (P12)
                                              • 33V Header (P13)
                                              • 25V Header (P42)
                                              • 12V Header (P43)
                                              • • Jumpers
                                                • • Figure 2-3 Jumper Locations
                                                  • Serial ROM Boot Jumper (JP1)
                                                  • • Table 2-10 JP1 Settings
                                                    • • Config Done Jumper (JP2)
                                                      • • Table 2-11 JP2 Settings
                                                        • • Config Program Jumper (JP3)
                                                          • • Table 2-12 JP3 Settings
                                                            • • Boot Jumper (JP4)
                                                              • • Table 2-13 JP4 Settings
                                                                • • FPGA Input Jumpers (JP5)
                                                                  • • Table 2-14 JP5 Settings
                                                                    • • Push Buttons and LEDs
                                                                      • • Figure 2-4 Push Button and LED Locations
                                                                        • Program Push Button (SW1)
                                                                        • PB1 Push Button (SW3)
                                                                        • PB2 Push Button (SW4)
                                                                        • Status LEDs (LED1-8)
                                                                        • • Table 2-15 Status LED (LED1-8) Settings
                                                                          • • Power LED (LED9)
                                                                            • Done LED (LED10)
                                                                            • • Connectors
                                                                              • • Figure 2-5 Connector Locations
                                                                                • Expansion Interface (P1-3 and J1-3)
                                                                                • IDC Connectors (P8 P14 P16 and P17)
                                                                                • IDC Connectors (P5 and P7)
                                                                                • High-Speed Connector (P4)
                                                                                • • A Bill Of Materials
                                                                                  • B Schematics
                                                                                  • • Title
                                                                                    • FPGA Config
                                                                                    • SRAM FPGA Banks 7 and 8
                                                                                    • Expansion Interface Connector 1
                                                                                    • FPGA Banks 0 and 1
                                                                                    • Expansion Interface Connectors 2
                                                                                    • FPGA Banks 2 and 3
                                                                                    • Expansion Interface Connector 1
                                                                                    • FPGA Banks 4 and 5
                                                                                    • User IO
                                                                                    • Power
                                                                                    • Proto Area
                                                                                    • • I Index
                                                                                      • • Numerics
                                                                                        • A
                                                                                        • B
                                                                                        • C
                                                                                        • D
                                                                                        • E
                                                                                        • F
                                                                                        • G
                                                                                        • H
                                                                                        • I
                                                                                        • J
                                                                                        • L
                                                                                        • M
                                                                                        • N
                                                                                        • O
                                                                                        • P
                                                                                        • S
                                                                                        • T
                                                                                        • V
                                                                                        • X

465

IDC

3X

1 ID

C3X

1P

9-13

BE

RG

5410

1-T

08-0

3

471

IDC

3X

2 ID

C3X

2JP

4B

ER

G54

102-

T08

-03

481

IDC

4X

2 ID

C4X

2JP

5SU

LL

INS

S201

2-04

494

IDC

13X

2 ID

C13

X2

P

8P

14P

16-1

7B

ER

G54

102-

T08

-13

501

25A

RE

SET

AB

LE

FU

S001

F1R

AY

CH

EM

CO

RP

SMD

250-

2

513

10U

F 10

V 1

0 8

05C

8 C

9 C

71PA

NA

SON

ICE

CJ-

2FB

1A10

6K

Ref

Des

crip

tion

Ref

eren

ce D

esig

nato

r M

anuf

actu

rer

Part

Num

ber

A-6 Blackfin FPGA EZ-Extender Manual

4

3

2

1

A B C D

20 Cotton Road

Nashua NH 03063

A B C D

4

3

2

1

PH 1-800-ANALOGD

C

Title

Size Board No

Date Sheet of

DEVICESANALOG

DNP = Do Not Populate

Rev

BLACKFIN FPGA EZ-EXTENDER

A0199-2005 10

SchematicBLACKFIN FPGA EZ-EXTENDER

1219-9-2005_1040

TITLE

33V

4

3

2

1

A B C D

20 Cotton Road

Nashua NH 03063

A B C D

4

3

2

1

PH 1-800-ANALOGD

C

Title

Size Board No

Date Sheet of

DEVICESANALOG

DNP = Do Not Populate

Rev

BLACKFIN FPGA EZ-EXTENDER

A0199-2005 10

33V

1A

1B

1Y

2A

2B

2Y

3A

3B

3Y

4A

4B

4Y

~AB

EN

25V

33V

33V

33V

33V

33V

25V

33V

OENC OUTOE OUT

CLK

D0

TMS

TCK

TDI

TDO

VCCINT

VCCO

VCCJ

NC1

NC2

NC3

NC4

NC5

NC6

GND

CE

CF

OE~RESET

CEO

VCCAUX_A6

VCCAUX_A17

VCCAUX_F1

VCCAUX_F22

VCCAUX_U1

VCCAUX_U22

VCCAUX_AB6

VCCAUX_AB17

VCCINT_G7

VCCINT_G8

VCCINT_G15

VCCINT_G16

VCCINT_H7

VCCINT_H16

VCCINT_R7

VCCINT_R16

VCCINT_T7

VCCINT_T8

VCCINT_T15

VCCINT_T16

TCK

TDI

TDO

TMS

M0

M1

M2

CCLK

PROG_B

DONE

HSWAP_EN

GND_A1

GND_A22

GND_B2

GND_B21

GND_C9

GND_C14

GND_J3

GND_J9

GND_J10

GND_J11

GND_J12

GND_J13

GND_J14

GND_J20

GND_K9

GND_K10

GND_K11

GND_K12

GND_K13

GND_K14

GND_L9

GND_L10

GND_L11

GND_L12

GND_L13

GND_L14

GND_M9

GND_M10

GND_M11

GND_M12

GND_M13

GND_M14

GND_N9

GND_N10

GND_N11

GND_N12

GND_N13

GND_N14

GND_P3

GND_P9

GND_P10

GND_P11

GND_P12

GND_P13

GND_P14

GND_P20

GND_Y9

GND_Y14

GND_AA2

GND_AA21

GND_AB1

GND_AB22

FPGAFPGA

EXTRA CLOCK SOCKET25MHZ SYSTEM CLOCK

FPGA JTAG HEADER

FLASH JTAG HEADER

BOOTMODE JUMPER

FPGA BOOT FLASH(2Mbit)

MUXFLASHSKTOSC

9-27-2005_1144 2 12

A6

A17

F1

F22

U1

U22

AB6

AB17

G7

G8

G15

G16

H7

H16

R7

R16

T7

T8

T15

T16

A21

B1

B22

A20

AB2

AA1

AB3

AA22

A2

AB21

B3

A1

A22

B2

B21

C9

C14

J3

J9

J10

J11

J12

J13

J14

J20

K9

K10

K11

K12

K13

K14

L9

L10

L11

L12

L13

L14

M9

M10

M11

M12

M13

M14

N9

N10

N11

N12

N13

N14

P3

P9

P10

P11

P12

P13

P14

P20

Y9

Y14

AA2

AA21

AB1

AB22

U1

FG456XC3S1000

CONFIG_PROG_B

6

5

4

3

2

1P6

IDC6X16X1

1

2

3

4

5

6

P15

IDC6X16X1

3

1

8

10

7

13

5

6

4

17

18

19

20

2

9

12

14

15

16

11

U4

TSSOP20XCF04S

2

4

5 6

3

1JP4

IDC3X23X2

402100R5

R400603

402100R44

R8100402

R7100402

1 3

U6

25MHZOSC003

80510UFC14

R29

060310K

R22

060310K

R21

060310K

R1

060310K

1 5

U7

DIPDIP8SOC

R263306030603

33R2

R25

DNP

10K0603

12V

1 2JP1

IDC2X12X1

CONFIG_DONER3

06030

CONFIG_CLK_TSCLK1

FPGA_TMS

FPGA_TDO

FPGA_TCK

FPGA_TDI

FPGA_TCK

FPGA_TDO

FPGA_TDI

FPGA_TMS

FLASH_TMS

FLASH_TDI

FLASH_TDO

FLASH_TCK

M1

M2

M0

12V

SPST-MOMENTARYSWT013SW1

2

3

4

5

6

7

11

10

9

14

13

12

1

15

U2

TSSOP1674LVC157

CONFIG_DONE

FLASH_TMS

FLASH_TCK

FLASH_TDI

FLASH_TDO

M2

M0

M1

FPGA CONFIG

CONFIG_INIT_B_TFS1

FLASH_DOUT

CONFIG_CLK_TSCLK1

FLASH_DONE

001UF0603

C18

IO_L32_0_GCLK6_A11B4_L32N_GCKL1_AA12

C19

0603001UF 001UF

0603

C20 C21

0603001UF 001UF

0603

C25C24

0603001UF001UF

0603

C23C22

0603001UF 001UF

0603

C31 C30

0603001UF 001UF

0603

C29 C28

0603001UF001UF

0603

C27C26

0603001UF

001UF0603

C32 C11

0603001UF 001UF

0603

C12 C13

0603001UF

80510UFC15 C16

10UF805

C17

0603001UF

0603330R24

LED10

LED001AMBER-SMT

CONFIG_DIN_DT1PRI

FLASH_DONE

FLASH_DOUT

DT1PRI

R6

060310K10K

0603

R28

33V 33V

4

3

2

1

A B C D

20 Cotton Road

Nashua NH 03063

A B C D

4

3

2

1

PH 1-800-ANALOGD

C

Title

Size Board No

Date Sheet of

DEVICESANALOG

DNP = Do Not Populate

Rev

BLACKFIN FPGA EZ-EXTENDER

A0199-2005 10

33V

33V

A18

A1

A10

A11

A12

A13

A14

A16

A2

A3

A4

A5

A6

A7

A8

A9

D0

D1

D10

D11

D2

D3

D4

D5

D6

D7

D8

D9

BHE

BLE

CE

OE

WE

A17

D15

D14

D13

D12

A0

A15

A18

A1

A10

A11

A12

A13

A14

A16

A2

A3

A4

A5

A6

A7

A8

A9

D0

D1

D10

D11

D2

D3

D4

D5

D6

D7

D8

D9

BHE

BLE

CE

OE

WE

A17

D15

D14

D13

D12

A0

A15

VCCO_6_M7

VCCO_6_N7

VCCO_6_P7

VCCO_6_R3

VCCO_6_R6

IO_Y1

IO_L16N_6_W4

IO_L16P_6_W3

IO_L17N_6_W2

IO_L17P_6_VREF_6_W1

IO_L19N_6_V5

IO_L19P_6_U5

IO_L20N_6_V4

IO_L20P_6_V3

IO_L21N_6_V2

IO_L21P_6_V1

IO_L22N_6_T6

IO_L22P_6_T5

IO_L23N_6_U4

IO_L23P_6_T4

IO_L24N_6_VREF_6_U3

IO_L24P_6_U2

IO_L26N_6_T3

IO_L26P_6_R4

IO_L27N_6_T2

IO_L27P_6_T1

IO_L28N_6_R5

IO_L28P_6_P6

IO_L29N_6_R2

IO_L29P_6_R1

IO_L31N_6_P5

IO_L31P_6_P4

IO_L32N_6_P2

IO_L32P_6_P1

IO_L33N_6_N6

IO_L33P_6_N5

IO_L34N_6_VREF_6_N4

IO_L34P_6_N3

IO_L35N_6_N2

IO_L35P_6_N1

IO_L38N_6_M6

IO_L38P_6_M5

IO_L39N_6_M4

IO_L39P_6_M3

IO_L40N_6_M2

IO_L40P_6_VREF_6_M1

IO_L01N_6_VRP_6_Y3

IO_L01P_6_VRN_6_Y2

VCCO_7_H3

VCCO_7_H6

VCCO_7_J7

VCCO_7_K7

VCCO_7_L7

IO_C2

IO_L16N_7_D1

IO_L16P_7_VREF_7_C1

IO_L17N_7_E4

IO_L17P_7_D4

IO_L19N_7_VREF_7_D3

IO_L19P_7_D2

IO_L20N_7_F4

IO_L20P_7_E3

IO_L21N_7_E1

IO_L21P_7_E2

IO_L22N_7_G6

IO_L22P_7_F5

IO_L23N_7_F2

IO_L23P_7_F3

IO_L24N_7_H5

IO_L24P_7_G5

IO_L26N_7_G3

IO_L26P_7_G4

IO_L27N_7_G1

IO_L27P_7_VREF_7_G2

IO_L28N_7_H1

IO_L28P_7_H2

IO_L29N_7_J4

IO_L29P_7_H4

IO_L31N_7_J5

IO_L31P_7_J6

IO_L32N_7_J1

IO_L32P_7_J2

IO_L33N_7_K5

IO_L33P_7_K6

IO_L34N_7_K3

IO_L34P_7_K4

IO_L35N_7_K1

IO_L35P_7_K2

IO_L38N_7_L5

IO_L38P_7_L6

IO_L39N_7_L3

IO_L39P_7_L4

IO_L40N_7_VREF_7_L1

IO_L40P_7_L2

IO_L01N_7_VRP_7_C3

IO_L01P_7_VRN_7_C4

(512k x 16bits x 2chips)2MBYTES FPGA SRAM

FPGASRAM SRAM

SRAM_A9

9-27-2005_1144 3 12

FLASH_TDO

FLASH_TMS

FLASH_TDI

FLASH_TCK

M7

N7

P7

R3

R6

Y1

W4

W3

W2

W1

V5

U5

V4

V3

V2

V1

T6

T5

U4

T4

U3

U2

T3

R4

T2

T1

R5

P6

R2

R1

P5

P4

P2

P1

N6

N5

N4

N3

N2

N1

M6

M5

M4

M3

M2

M1

Y3

Y2

H3

H6

J7

K7

L7

C2

D1

C1

E4

D4

D3

D2

F4

E3

E1

E2

G6

F5

F2

F3

H5

G5

G3

G4

G1

G2

H1

H2

J4

H4

J5

J6

J1

J2

K5

K6

K3

K4

K1

K2

L5

L6

L3

L4

L1

L2

C3

C4

U1

FG456XC3S1000

28

2

23

24

25

26

27

43

3

4

5

18

19

20

21

22

7

8

31

32

9

10

13

14

15

16

29

30

40

39

6

41

17

44

38

37

36

35

1

42

U3

TSOP44IS61LV51216

42

1

35

36

37

38

44

17

41

6

39

40

30

29

16

15

14

13

10

9

32

31

8

7

22

21

20

19

18

5

4

3

43

27

26

25

24

23

2

28

U5

TSOP44IS61LV51216

SRAM_D7

SRAM_D6

SRAM_D3

SRAM_D2

SRAM_D0

SRAM_D8

SRAM_D9

SRAM_D5

SRAM_D4

SRAM_D13

SRAM_D1

SRAM_D10

SRAM_D11

SRAM_D12

SRAM_D14

SRAM_D15

SRAM_CE

SRAM_A7

SRAM_A0

SRAM_A5

SRAM_A3

SRAM_A1

SRAM_WE

SRAM_A8

SRAM_A6

SRAM_A4

SRAM_A2

SRAM_A17

SRAM_OE

SRAM_A12

SRAM_A13

SRAM_A15

SRAM_A16

SRAM_A14

SRAM_A18

SRAM_A11

SRAM_A10

SRAM_D22

SRAM_D20

SRAM_D18

SRAM_D17

SRAM_D16

SRAM_D26

SRAM_D21

SRAM_D24

SRAM_D19

SRAM_D31

SRAM_D25

SRAM_D27

SRAM_D28

SRAM_D30

SRAM_D29

PB2

A11

A5

D1

A15

A3

A9

D13

D7

A13

A19

A7

A1

A18

A6

A2

A12

D6

A8

A14

D2

D0

A10

A4

D3

A16

SRAM FPGA BANKS 7 + 8

SRAM_CE

SRAM_WE

SRAM_OE

SRAM_A18

SRAM_A0 SRAM_D0

SRAM_D1

SRAM_D2

SRAM_D3

SRAM_D4

SRAM_D5

SRAM_D6

SRAM_D7

SRAM_D8

SRAM_D9

SRAM_D10

SRAM_D11

SRAM_D12

SRAM_D13

SRAM_D14

SRAM_D15

SRAM_D16

SRAM_D17

SRAM_D18

SRAM_D19

SRAM_D20

SRAM_D21

SRAM_D22

SRAM_D23

SRAM_D24

SRAM_D25

SRAM_D26

SRAM_D27

SRAM_D28

SRAM_D29

SRAM_D30

SRAM_D31

SRAM_A1

SRAM_A2

SRAM_A3

SRAM_A4

SRAM_A5

SRAM_A6

SRAM_A7

SRAM_A8

SRAM_A9

SRAM_A10

SRAM_A11

SRAM_A12

SRAM_A13

SRAM_A14

SRAM_A15

SRAM_A16

SRAM_A17

SRAM_A1

SRAM_A2

SRAM_A3

SRAM_A4

SRAM_A5

SRAM_A6

SRAM_A7

SRAM_A8

SRAM_A9

SRAM_A10

SRAM_A11

SRAM_A12

SRAM_A13

SRAM_A14

SRAM_A15

SRAM_A16

SRAM_A17

SRAM_A18

SRAM_A0

SRAM_OE

SRAM_WE

SRAM_CE

C33

0603001UF

C34

0603001UF001UF

0603

C37001UF0603

C36

C42

0603001UF 001UF

0603

C41 C40

0603001UF001UF

0603

C39001UF0603

C46 C45

0603001UF 001UF

0603

C44C43

0603001UF

B6_L01P_Y2

B6_L01N_Y3

SRAM_D23

4

3

2

1

A B C D

20 Cotton Road

Nashua NH 03063

A B C D

4

3

2

1

PH 1-800-ANALOGD

C

Title

Size Board No

Date Sheet of

DEVICESANALOG

DNP = Do Not Populate

Rev

BLACKFIN FPGA EZ-EXTENDER

A0199-2005 10

EXPANSION INTERFACE TYPE B

P1Expanison Connector

Top Of BoardBottom Of Board

Expansion Connector 1

10-18-2005_1616 4 12

EXPANSION INTERFACE CONNECTOR 1

C3510UF805

01UF0603

C38

5V_EI

5V_EI

1

10

11 12

13 14

15 16

17 18

19

2

20

21 22

23 24

25 26

27 28

29

3

30

31 32

33 34

35 36

37 38

39

4

40

41 42

43 44

45 46

47 48

49

5

50

51 52

53 54

55 56

57 58

59

6

60

61 62

63 64

65 66

67 68

69

7

70

71 72

73 74

75 76

77 78

79

8

80

81 82

83 84

85 86

87 88

89

9

90

P1

CON01845X2

1

10

1112

1314

1516

1718

19

2

20

2122

2324

2526

2728

29

3

30

3132

3334

3536

3738

39

4

40

4142

4344

4546

4748

49

5

50

5152

5354

5556

5758

59

6

60

6162

6364

6566

6768

69

7

70

7172

7374

7576

7778

79

8

80

8182

8384

8586

8788

89

9

90

J1

CON01945X2

PP1

EXPANSION_PPI_CLK

PP3

UDEF2

UDEF4

UDEF6

UDEF8

UDEF10

D9

D7

D15

D13

D11

D5

D1

D3

D15

D9

D5

D1

D3

D0

D2

D4

D6

D8

D10

D14

D12

P1_5

P1_25

P1_27

P1_29

P1_31

P1_33

P1_55

P1_57

P1_59

P1_61

P1_63

P1_65

P1_67

P1_69

P1_35

P1_26

P1_28

P1_30

P1_32

P1_34

P1_56

P1_58

P1_60

P1_62

P1_64

P1_66

P1_68

P1_70

P1_36

P1_26

P1_28

P1_30

P1_32

P1_34

P1_36

P1_56

P1_58

P1_60

P1_62

P1_64

P1_66

P1_68

P1_70

P1_5

P1_25

P1_27

P1_29

P1_31

P1_33

P1_35

P1_55

P1_57

P1_59

P1_61

P1_63

P1_65

P1_67

P1_69

P1_[586]

A5

A6A7

A8A9

A10A11

A12A13

A14A15

A16A17

A18A19

D0

D2

D4

D6D7

D8

D10D11

D12D13

D14

A1

A2

B1_L24N_D15_J1_71B1_L24P_E15_J1_72

B1_L22N_A16_J1_73B1_L22P_B16_J1_74

B1_L19N_C16_J1_75B1_L19P_D16_J1_76

B1_L16N_B17_J1_77B1_L16P_C17_J1_78

B1_L15N_D17_J1_79

A3

B1_L15P_E17_J1_80

B1_L10N_A18_J1_81B1_L10P_B18_J1_82

B1_L09N_C18_J1_83B1_L09P_D18_J1_84

B1_L06N_A19_J1_85B1_L06P_B19_J1_86

A4A5

A6 A7

A8 A9

A10 A11

A12 A13

A14 A15

A16 A17

A18 A19

A1

A2

PP0

PP2

UDEF1

UDEF3

A3

UDEF5

UDEF7

UDEF9

UDEF11

A4

33V

25V 33V

33V

33V

33V

4

3

2

1

A B C D

20 Cotton Road

Nashua NH 03063

A B C D

4

3

2

1

PH 1-800-ANALOGD

C

Title

Size Board No

Date Sheet of

DEVICESANALOG

DNP = Do Not Populate

Rev

BLACKFIN FPGA EZ-EXTENDER

A0199-2005 10

VCCO_0_C8

VCCO_0_F8

VCCO_0_G9

VCCO_0_G10

VCCO_0_G11

IO_A10

IO_D9

IO_D10

IO_F6

IO_VREF_0_A3

IO_VREF_0_C7

IO_VREF_0_E5

IO_VREF_0_F7

IO_L06N_0_D5

IO_L06P_0_C5

IO_L09N_0_B5

IO_L09P_0_A5

IO_L10N_0_E6

IO_L10P_0_D6

IO_L15N_0_C6

IO_L15P_0_B6

IO_L16N_0_E7

IO_L16P_0_D7

IO_L19N_0_B7

IO_L19P_0_A7

IO_L22N_0_E8

IO_L22P_0_D8

IO_L24N_0_B8

IO_L24P_0_A8

IO_L25N_0_F9

IO_L25P_0_E9

IO_L27N_0_B9

IO_L27P_0_A9

IO_L28N_0_F10

IO_L28P_0_E10

IO_L29N_0_C10

IO_L29P_0_B10

IO_L30N_0_F11

IO_L30P_0_E11

IO_L31N_0_D11

IO_L31P_0_VREF_0_C11

IO_L01N_0_VRP_0_B4

IO_L01P_0_VRN_0_A4

IO_L32N_0_GCLK7_B11

IO_L32P_0_GCLK6_A11

VCCO_1_C15

VCCO_1_F15

VCCO_1_G12

VCCO_1_G13

VCCO_1_G14

IO_A12

IO_E16

IO_F12

IO_F13

IO_F16

IO_F17

IO_VREF_1_E13

IO_VREF_1_F14

IO_L06N_1_VREF_1_A19

IO_L06P_1_B19

IO_L09N_1_C18

IO_L09P_1_D18

IO_L10N_1_VREF_1_A18

IO_L10P_1_B18

IO_L15N_1_D17

IO_L15P_1_E17

IO_L16N_1_B17

IO_L16P_1_C17

IO_L19N_1_C16

IO_L19P_1_D16

IO_L22N_1_A16

IO_L22P_1_B16

IO_L24N_1_D15

IO_L24P_1_E15

IO_L25N_1_B15

IO_L25P_1_A15

IO_L27N_1_D14

IO_L27P_1_E14

IO_L28N_1_A14

IO_L28P_1_B14

IO_L29N_1_C13

IO_L29P_1_D13

IO_L30N_1_A13

IO_L30P_1_B13

IO_L31N_1_VREF_1_D12

IO_L31P_1_E12

IO_L01N_1_VRP_1_C19

IO_L01P_1_VRN_1_B20

IO_L32N_1_GCLK5_B12

IO_L32P_1_GCLK4_C12

FPGAFPGA

LAYOUT NOTE PLACE NEAR FPGA

5 129-27-2005_1144

C8

F8

G9

G10

G11

A10

D9

D10

F6

A3

C7

E5

F7

D5

C5

B5

A5

E6

D6

C6

B6

E7

D7

B7

A7

E8

D8

B8

A8

F9

E9

B9

A9

F10

E10

C10

B10

F11

E11

D11

C11

B4

A4

B11

A11

C15

F15

G12

G13

G14

A12

E16

F12

F13

F16

F17

E13

F14

A19

B19

C18

D18

A18

B18

D17

E17

B17

C17

C16

D16

A16

B16

D15

E15

B15

A15

D14

E14

A14

B14

C13

D13

A13

B13

D12

E12

C19

B20

B12

C12

U1

FG456XC3S1000

1

10

11 12

13 14

15 16

17 18

19

2

20

21 22

23 24

25 26

27 28

29

3

30

31 32

33 34

35 36

37 38

4

5 6

7 8

9

39 40

41

43

45

47

49

42

44

46

48

50

25X2CON041

P4

5

1

18

20

22

26

24

16

14

12

25

23

21

19

17

15

13

11

9

3

6

10

8

4

2

7

P8

IDC13X213X2

5

1

18

20

22

26

24

16

14

12

25

23

21

19

17

15

13

11

9

3

6

10

8

4

2

7

P14

IDC13X213X2

FPGA BANKS 0 + 1

001UF0603

C50

DNP0603

R52

B1_L10N_A18_J1_81

B1_L15P_E17_J1_80

R53

0603DNP

B1_L16P_C17_J1_78

R27

06030

B1_L10P_B18_J1_82B1_L10N_A18_J1_81

B1_L15N_D17_J1_79

B1_L16N_B17_J1_77

B1_L24N_D15_J1_71

B1_L22N_A16_J1_73

B1_L19N_C16_J1_75

R51

0603DNPDNP

0603

R50DNP0603

R48

R31

0603DNP

B1_L19N_C16_J1_75

B1_L22N_A16_J1_73

B1_L24N_D15_J1_71

B1_L15N_D17_J1_79

B1_L15P_E17_J1_80

B1_L16N_B17_J1_77

B1_L16P_C17_J1_78

DNP0603

R30

VCCO_1

VCCO_1

C47

0603001UF

VCCO_1

B1_L27N_D14

PB1

AOE

B1_L01P_VRN_B20

B1_L01N_VRP_C19

IO_L32_0_GCLK6_A11

IO_L32_0_GCLK7_B11

IO_L32_0_GCLK7_B11

B1_L32N_GCLK5_B12

B1_L32P_GCLK4_C12 B1_L06P_B19_J1_86

B1_L09P_D18_J1_84

B1_L15P_E17_J1_80

B1_L16P_C17_J1_78

B1_L19P_D16_J1_76

B1_L16N_B17_J1_77

B1_L15N_D17_J1_79

B1_L09N_C18_J1_83

B1_L06N_A19_J1_85

B1_L31P_E12

B1_L31N_D12

B1_L06N_A19_J1_85

B1_L09N_C18_J1_83

B1_L09P_D18_J1_84

B1_L06P_B19_J1_86

B1_F17

B1_F16

B1_E16

B1_F13

B1_E13

B1_F12

B1_A12

B1_F14

B1_L01N_VRP_C19

B1_L01P_VRN_B20

B1_L32P_GCLK4_C12

B1_L32N_GCLK5_B12

AMS3

D5

D4

AMS0

UDEF1

ARE

ARDY

AMS1

AMS2

UDEF11

UDEF9

UDEF7

UDEF5

UDEF3

PP2

PP0

D15

D11

D9

A17

B1_L16P_C17_J1_78

B1_L19P_D16_J1_76

B1_L19N_C16_J1_75

B1_L22P_B16_J1_74

B1_L24N_D15_J1_71

B1_L22N_A16_J1_73

B1_L24P_E15_J1_72

B1_L16N_B17_J1_77

B1_L10P_B18_J1_82

B1_L15P_E17_J1_80

B1_L15N_D17_J1_79

B1_L10N_A18_J1_81

B1_L09P_D18_J1_84

B1_L09N_C18_J1_83

B1_L06P_B19_J1_86

B1_L06N_A19_J1_85

B1_L31N_D12

B1_L30N_A13

B1_L29N_C13

B1_L28N_A14

B1_L27N_D14

B1_L25N_B15

B1_F16

B1_F14

B1_F13

B1_F12

B1_L31P_E12

B1_L30P_B13

B1_L29P_D13

B1_L28P_B14

B1_L27P_E14

B1_L25P_A15

B1_F17

B1_E13

B1_E16

B1_A12

UDEF10

ABE3

ABE1

ABE0

ABE2

AWE

UDEF6

UDEF8

PP3

UDEF4

UDEF2

PP1

D14

D8

D10

D12

B1_L25P_A15B1_L25N_B15

B1_L22N_A16_J1_73

B1_L24N_D15_J1_71

B1_L19N_C16_J1_75

B1_L24P_E15_J1_72

B1_L22P_B16_J1_74

B1_L27P_E14

B1_L19P_D16_J1_76

B1_L22P_B16_J1_74

B1_L24P_E15_J1_72

B1_L25N_B15

B1_L25P_A15

B1_L27N_D14

B1_L27P_E14

B1_L28N_A14

B1_L28P_B14

B1_L29N_C13

B1_L29P_D13

B1_L30N_A13

B1_L30P_B13

B1_L10N_A18_J1_81

B1_L10P_B18_J1_82

3

2

1

3X1IDC3X1

P9

EXPANSION_PPI_CLK

B1_F16 B1_F17

B1_L28P_B14

B1_L29P_D13

B1_L30P_B13

B1_L31P_E12

B1_L28N_A14

B1_L29N_C13

B1_L30N_A13

B1_L31N_D12

B1_E16

B1_E13

B1_A12

B1_L01P_VRN_B20

B1_L32P_GCLK4_C12

B1_F14

B1_L01N_VRP_C19

B1_L32N_GCLK5_B12

B1_F13

B1_F12

B1_L01P_VRN_B20

B1_L01N_VRP_C19

001UF0603

C48 C49

0603001UF

C51

0603001UF 001UF

0603

C52 C53

0603001UF001UF

0603

C54

VCCO_1

R49

0603DNP

B1_L10P_B18_J1_82

DNP0603

R54

4

3

2

1

A B C D

20 Cotton Road

Nashua NH 03063

A B C D

4

3

2

1

PH 1-800-ANALOGD

C

Title

Size Board No

Date Sheet of

DEVICESANALOG

DNP = Do Not Populate

Rev

BLACKFIN FPGA EZ-EXTENDER

A0199-2005 10Expanison ConnectorP2

Bottom Of Board Top Of Board

Expansion Connector 2

33V_EI

6 129-14-2005_1203

EXPANSION INTERFACE CONNECTOR 2

SCK

NMI

TMR1

PF1

PF3

PF5

PF7

PF9

PF11

PF13

PF15

1

10

11 12

13 14

15 16

17 18

19 20

21 22

23 24

25 26

27 28

29

3

30

31 32

33 34

35 36

37 38

39

4

40

41 42

43 44

45 46

47 48

49

5

50

51 52

53 54

55 56

57 58

59

6

60

61 62

63 64

65 66

67 68

69

7

70

71 72

73 74

75 76

77 78

79

8

80

81 82

83 84

85 86

87 88

89

9

90

2P2

CON01845X2

1

10

1112

1314

1516

1718

19

2

20

2122

2324

2526

2728

29

3

30

3132

3334

3536

3738

39

4

40

4142

4344

4546

4748

49

5

50

5152

5354

5556

5758

59

6

60

6162

6364

6566

6768

69

7

70

7172

7374

7576

7778

79

8

80

8182

8384

8586

8788

89

9

90

J2

CON01945X2

ARE

ARDY

AMS0

AMS1

P2_21

P2_19

P2_7

P2_21

P2_71

P2_73

P2_77

P2_79

P2_83

P2_85

P2_81

P2_19

P2_15

P2_5 P2_6

P2_8

P2_22

P2_86

P2_84

P2_82

P2_80

P2_78

P2_74

P2_72

P2_20

P2_18

P2_22

P2_74

P2_78

P2_82

P2_84

P2_86

P2_80

P2_72

P2_20

P2_18

P2_8

P2_6

P2_[586]

P2_5

P2_7

P2_15

P2_85

P2_83

P2_81

P2_79

P2_77

P2_73

P2_71AWE

AOE

ABE0

ABE1

ABE2

ABE3

TSCLK0

TFS0

DT0PRI

DT0SEC

CONFIG_CLK_TSCLK1

CONFIG_INIT_B_TFS1

DT1PRI

DT1SEC

TMR0

TMR2

PF14

PF12

PF10

PF8

PF4

PF6

PF2

PF0

B2_L40N_L21_J2_9

B2_L39N_L19_J2_11

B2_C22_J2_17

B2_L38N_L17_J2_23

B2_L35N_K21_J2_25

B2_L34N_K19_J2_27

B2_L33N_K17_J2_29

B2_L32N_J21_J2_31

B2_L31N_J18_J2_33

B2_L29N_H21_J2_35

B2_L28N_H18_J2_37

B2_L27N_G21_J2_39

B2_L26N_G20_J2_41

B2_L22N_G17_J2_43

B2_L24N_F20_J2_45

B2_L23N_F19_J2_47

B2_L21N_E21_J2_49

B2_L20N_E19_J2_51

B2_L19N_E18_J2_53

B2_L17N_D21_J2_55

B2_L16N_D20_J2_57B2_L16P_D19_J2_58

B2_L17P_D22_J2_56

B2_L19P_F18_J2_54

B2_L20P_E20_J2_52

B2_L21P_E22_J2_50

B2_L23P_G19_J2_48

B2_L24P_F21_J2_46

B2_L22P_G18_J2_44

B2_L26P_H19_J2_42

B2_L27P_G22_J2_40

B2_L28P_J17_J2_38

B2_L29P_H22_J2_36

B2_L31P_J19_J2_34

B2_L32P_J22_J2_32

B2_L33P_K18_J2_30

B2_L34P_K20_J2_28

B2_L35P_K22_J2_26

B2_L38P_L18_J2_24

IO_L01P_2_VRN_2_C21_J2_16

B2_L40P_L22_J2_10

B2_L39P_L20_J2_12

MOSI

MISO

UDEF12

AMS3

AMS2

AMS0

ARDY

AMS1

AREAWE

AOE

ABE0

ABE1

ABE2

ABE3

RSCLK1

RSCLK0

RFS1

DR1PRI

DR1SEC

AMS2

AMS3

DR0SEC

DR0PRI

RFS0

TMR3

SPIDS0

C56

060301UF

80510UFC55

33V_EI

33V

4

3

2

1

A B C D

20 Cotton Road

Nashua NH 03063

A B C D

4

3

2

1

PH 1-800-ANALOGD

C

Title

Size Board No

Date Sheet of

DEVICESANALOG

DNP = Do Not Populate

Rev

BLACKFIN FPGA EZ-EXTENDER

A0199-2005 10

33V

25V33V

33V

33V

VCCO_2_H17

VCCO_2_H20

VCCO_2_J16

VCCO_2_K16

VCCO_2_L16

IO_C22

IO_L16N_2_D20

IO_L16P_2_D19

IO_L17N_2_D21

IO_L17P_2_VREF_2_D22

IO_L19N_2_E18

IO_L19P_2_F18

IO_L20N_2_E19

IO_L20P_2_E20

IO_L21N_2_E21

IO_L21P_2_E22

IO_L22N_2_G17

IO_L22P_2_G18

IO_L23N_2_VREF_2_F19

IO_L23P_2_G19

IO_L24N_2_F20

IO_L24P_2_F21

IO_L26N_2_G20

IO_L26P_2_H19

IO_L27N_2_G21

IO_L27P_2_G22

IO_L28N_2_H18

IO_L28P_2_J17

IO_L29N_2_H21

IO_L29P_2_H22

IO_L31N_2_J18

IO_L31P_2_J19

IO_L32N_2_J21

IO_L32P_2_J22

IO_L33N_2_K17

IO_L33P_2_K18

IO_L34N_2_VREF_2_K19

IO_L34P_2_K20

IO_L35N_2_K21

IO_L35P_2_K22

IO_L38N_2_L17

IO_L38P_2_L18

IO_L39N_2_L19

IO_L39P_2_L20

IO_L40N_2_L21

IO_L40P_2_VREF_2_L22

IO_L01N_2_VRP_2_C20

IO_L01P_2_VRN_2_C21

VCCO_3_M16

VCCO_3_N16

VCCO_3_P16

VCCO_3_R17

VCCO_3_R20

IO_L16N_3_W22

IO_L16P_3_Y22

IO_L17N_3_V19

IO_L17P_3_VREF_3_W19

IO_L19N_3_W21

IO_L19P_3_W20

IO_L20N_3_U19

IO_L20P_3_V20

IO_L21N_3_V22

IO_L21P_3_V21

IO_L22N_3_T17

IO_L22P_3_U18

IO_L23N_3_U21

IO_L23P_3_VREF_3_U20

IO_L24N_3_R18

IO_L24P_3_T18

IO_L26N_3_T20

IO_L26P_3_T19

IO_L27N_3_T22

IO_L27P_3_T21

IO_L28N_3_R22

IO_L28P_3_R21

IO_L29N_3_P19

IO_L29P_3_R19

IO_L31N_3_P18

IO_L31P_3_P17

IO_L32N_3_P22

IO_L32P_3_P21

IO_L33N_3_N18

IO_L33P_3_N17

IO_L34N_3_N20

IO_L34P_3_VREF_3_N19

IO_L35N_3_N22

IO_L35P_3_N21

IO_L38N_3_M18

IO_L38P_3_M17

IO_L39N_3_M20

IO_L39P_3_M19

IO_L40N_3_VREF_3_M22

IO_L40P_3_M21

IO_L01N_3_VRP_3_Y20

IO_L01P_3_VRN_3_Y19

IO_Y21

FPGAFPGA

LAYOUT NOTE PLACE NEAR FPGA

9-27-2005_1144 7 12

H17

H20

J16

K16

L16

C22

D20

D19

D21

D22

E18

F18

E19

E20

E21

E22

G17

G18

F19

G19

F20

F21

G20

H19

G21

G22

H18

J17

H21

H22

J18

J19

J21

J22

K17

K18

K19

K20

K21

K22

L17

L18

L19

L20

L21

L22

C20

C21

M16

N16

P16

R17

R20

W22

Y22

V19

W19

W21

W20

U19

V20

V22

V21

T17

U18

U21

U20

R18

T18

T20

T19

T22

T21

R22

R21

P19

R19

P18

P17

P22

P21

N18

N17

N20

N19

N22

N21

M18

M17

M20

M19

M22

M21

Y20

Y19

Y21

U1

FG456XC3S1000

2

4

8

10

6

12

14

16

24

22

20

18

26

28

3

5

7

9

11

13

15

17

19

21

23

25

27

1P5

IDC14X214X2

1

27

25

23

21

19

17

15

13

11

9

7

5

3

28

26

18

20

22

24

16

14

12

6

10

8

4

2P7

IDC14X214X2

VCCO_2

B2_L26P_H19_J2_42

DNP0603

R55B2_L24P_F21_J2_46

R56

0603DNP

B2_L23P_G19_J2_48

B2_L26N_G20_J2_41

B2_L24N_F20_J2_45

B2_L23N_F19_J2_47 B2_L23P_G19_J2_48

B2_L24P_F21_J2_46

B2_L26P_H19_J2_42

R32

0603DNP

TMR0

VCCO_2

PF221

2X1IDC2X1

JP3

CONFIG_PROG_B

1 2JP2

IDC2X12X1

PF3

CONFIG_INIT_B_TFS1

CONFIG_CLK_TSCLK1

RSCLK1

RFS1

IO_L01N_2_VRP_2_C20

IO_L01P_2_VRN_2_C21_J2_16

B2_L22N_G17_J2_43

B2_L22P_G18_J2_44

B2_L32N_J21_J2_31

SPIDS0

PF0

SCK

NMI

TMR1

DR1SEC

TMR3

DR0PRI

DR1PRI

RFS0

DR0SEC

PF15

PF13

RSCLK0

PF7

PF9

PF6

PF11

PF1

PF3

PF5

MOSI

MISO

UDEF12

TMR2

DT1SEC

DT1PRI

DT0SEC

TSCLK0

PF14

PF12

PF10

PF8

PF4

PF2

FPGA BANKS 2 + 3

DT0PRI

TFS0

B2_L40P_L22_J2_10

B2_L40N_L21_J2_9

B2_L39P_L20_J2_12

B2_L39N_L19_J2_11

B2_L38P_L18_J2_24

B2_L38N_L17_J2_23

B2_L35P_K22_J2_26

B2_L35N_K21_J2_25

B2_L34P_K20_J2_28

B2_L34N_K19_J2_27

B2_L33P_K18_J2_30

B2_L33N_K17_J2_29

B2_L32P_J22_J2_32

B2_L31P_J19_J2_34

B2_L31N_J18_J2_33

B2_L29P_H22_J2_36

B2_L29N_H21_J2_35

B2_L28P_J17_J2_38

B2_L28N_H18_J2_37

B2_L27P_G22_J2_40

B2_L27N_G21_J2_39

B2_L26P_H19_J2_42

B2_L26N_G20_J2_41

B2_L24P_F21_J2_46

B2_L24N_F20_J2_45

B2_L23P_G19_J2_48

B2_L23N_F19_J2_47

B2_L21P_E22_J2_50

B2_L21N_E21_J2_49

B2_L20P_E20_J2_52

B2_L20N_E19_J2_51

B2_L19P_F18_J2_54

B2_L19N_E18_J2_53

B2_L17P_D22_J2_56

B2_L17N_D21_J2_55

B2_L16P_D19_J2_58

B2_L16N_D20_J2_57

B2_C22_J2_17

3

2

1

3X1IDC3X1

P10

IO_L01P_2_VRN_2_C21_J2_16

IO_L01N_2_VRP_2_C20

VCCO_2

CONFIG_DONE

B2_L22N_G17_J2_43

B2_L17N_D21_J2_55

B2_L19N_E18_J2_53

B2_L20N_E19_J2_51

B2_L21N_E21_J2_49

B2_L16N_D20_J2_57

IO_L01N_2_VRP_2_C20

B2_L16P_D19_J2_58

B2_L20P_E20_J2_52

B2_L19P_F18_J2_54

B2_L17P_D22_J2_56

B2_L22P_G18_J2_44

B2_L21P_E22_J2_50

B2_C22_J2_17

IO_L01P_2_VRN_2_C21_J2_16

B2_L40N_L21_J2_9

B2_L39N_L19_J2_11

B2_L38N_L17_J2_23

B2_L35N_K21_J2_25

B2_L34N_K19_J2_27

B2_L33N_K17_J2_29

B2_L32N_J21_J2_31

B2_L31N_J18_J2_33

B2_L29N_H21_J2_35

B2_L28N_H18_J2_37

B2_L27N_G21_J2_39

B2_L40P_L22_J2_10

B2_L34P_K20_J2_28

B2_L35P_K22_J2_26

B2_L38P_L18_J2_24

B2_L39P_L20_J2_12

B2_L33P_K18_J2_30

B2_L32P_J22_J2_32

B2_L28P_J17_J2_38

B2_L31P_J19_J2_34

B2_L29P_H22_J2_36

B2_L27P_G22_J2_40

DNP0603

R33

B2_L23N_F19_J2_47

B2_L24N_F20_J2_45

B2_L26N_G20_J2_41

DNP0603

R57

001UF0603

C60 C59

0603001UF 001UF

0603

C58 C57

0603001UF

C82

0603001UF 001UF

0603

C81 C62

0603001UF001UF

0603

C61

VCCO_2

4

3

2

1

A B C D

20 Cotton Road

Nashua NH 03063

A B C D

4

3

2

1

PH 1-800-ANALOGD

C

Title

Size Board No

Date Sheet of

DEVICESANALOG

DNP = Do Not Populate

Rev

BLACKFIN FPGA EZ-EXTENDER

A0199-2005 10

Expanison ConnectorExpanison Connector

Bottom Of Board Top Of BoardExpansion Connector 3

EXPANSION INTERFACE (TYPE B)

P3P3

9-9-2005_1029 128

EXPANSION INTERFACE CONNECTOR 1

33V_EI5V_EI

1

10

11 12

13 14

15 16

17 18

19

2

20

21 22

23 24

25 26

27 28

29

3

30

31 32

33 34

35 36

37 38

39

4

40

41 42

43 44

45 46

47 48

49

5

50

51 52

53 54

55 56

57 58

59

6

60

61 62

63 64

65 66

67 68

69

7

70

71 72

73 74

75 76

77 78

79

8

80

81 82

83 84

85 86

87 88

89

9

90

P3

CON01845X2

1

10

1112

1314

1516

1718

19

2

20

2122

2324

2526

2728

29

3

30

3132

3334

3536

3738

39

4

40

4142

4344

4546

4748

49

5

50

5152

5354

5556

5758

59

6

60

6162

6364

6566

6768

69

7

70

7172

7374

7576

7778

79

8

80

8182

8384

8586

8788

89

9

90

J3

CON01945X2

TX0

TX1

UDEF17

UDEF19

UDEF21

UDEF23

UDEF25

UDEF29

UDEF27

RESET

UDEF32

UDEF34

UDEF36

UDEF38

UDEF40

B5_L01N_RDWR_B_Y4_J3_1

P3_42

P3_[190]

P3_86

P3_84

P3_82

P3_80

P3_78

P3_76

P3_74

P3_72

P3_70

P3_68

P3_64

P3_62

P3_60

P3_58

P3_56

P3_54

P3_52

P3_50

P3_48

P3_46

P3_42

P3_79

P3_89

P3_77

P3_75

P3_73

P3_71

P3_69

P3_67

P3_63

P3_61

P3_59

P3_57

P3_55

P3_53

P3_51

P3_49

P3_47

P3_45

P3_51

P3_79

P3_89

P3_77

P3_75

P3_73

P3_71

P3_69

P3_67

P3_63

P3_61

P3_59

P3_57

P3_55

P3_53

P3_49

P3_47

P3_45

P3_86

P3_84

P3_82

P3_80

P3_78

P3_76

P3_74

P3_72

P3_70

P3_68

P3_64

P3_62

P3_60

P3_58

P3_56

P3_54

P3_52

P3_50

P3_48

P3_46

B5_L27N_W9_J3_31

B5_L28N_D6_AB9_J3_33

B5_L29N_Y10_J3_35

B5_L30N_AB10_J3_37

B5_L31N_D4_W11_J3_39

B5_L10N_VRP_AB5_J3_9

B5_L25N_AB8_J3_21

B5_L24N_W8_J3_19

B5_L22N_AB7_J3_17

B5_L19N_Y7_J3_15

B5_L16N_AA6_J3_13

B5_L15N_W6_J3_11

B5_L09N_Y5_J3_7

B5_L06N_AB4_J3_5

B5_U6_J3_23

B5_V7_J3_29

B5_U9_J3_41

B5_L31P_D5_V11_J3_40

B5_L30P_AA10_J3_38

B5_L29P_W10_J3_36

B5_L28P_D7_AA9_J3_34

B5_L27P_V9_J3_32

B5_L32N_GCLK3_AA11_J3_30

B5_U7_J3_28

B5_L25P_AA8_J3_22

B5_L24P_V8_J3_20

B5_L22P_AA7_J3_18

B5_L19P_W7_J3_16

B5_L16P_Y6_J3_14

B5_L15P_V6_J3_12

B5_L10P_VRN_AA5_J3_10

B5_L09P_W5_J3_8

B5_L06P_AA4_J3_6

B5_L01P_CS_B_AA3_J3_2

B5_AB11_J3_90

B5_U11_J3_83

B5_V10_J3_85

B5_U10_J3_81

UDEF43

BGH

BG

BR

UDEF30

UDEF28

UDEF26

UDEF24

UDEF22

UDEF20

UDEF18

UDEF16

RX1

RX0

UDEF14 UDEF15

CLK_OUT_EXP1

UDEF31

UDEF33

UDEF35

UDEF37

UDEF39

UDEF41

33V_EI

C84

060301UF

80510UFC83

C8610UF805

01UF0603

C85

5V_EI

33V

33V

25V 33V

33V

33V

33V

4

3

2

1

A B C D

20 Cotton Road

Nashua NH 03063

A B C D

4

3

2

1

PH 1-800-ANALOGD

C

Title

Size Board No

Date Sheet of

DEVICESANALOG

DNP = Do Not Populate

Rev

BLACKFIN FPGA EZ-EXTENDER

A0199-2005 10

VCCO_4_T12

VCCO_4_T13

VCCO_4_T14

VCCO_4_U15

VCCO_4_Y15

IO_U16

IO_U17

IO_W13

IO_W14

IO_VREF_4_V18

IO_VREF_4_Y16

IO_VREF_4_AB13

IO_L05N_4_AA19

IO_L05P_4_AB19

IO_L06N_4_VREF_4_W18

IO_L06P_4_Y18

IO_L09N_4_AA18

IO_L09P_4_AB18

IO_L10N_4_V17

IO_L10P_4_W17

IO_L15N_4_Y17

IO_L15P_4_AA17

IO_L16N_4_V16

IO_L16P_4_W16

IO_L19N_4_AA16

IO_L19P_4_AB16

IO_L22N_4_VREF_4_V15

IO_L22P_4_W15

IO_L24N_4_AA15

IO_L24P_4_AB15

IO_L25N_4_U14

IO_L25P_4_V14

IO_L27N_4_DIN_D0_AA14

IO_L27P_4_D1_AB14

IO_L28N_4_U13

IO_L28P_4_V13

IO_L29N_4_Y13

IO_L29P_4_AA13

IO_L30N_4_D2_U12

IO_L30P_4_D3_V12

IO_L31N_4_INIT_B_W12

IO_L31P_4_DOUT_BUSY_Y12

IO_L01N_4_VRP_4_AA20

IO_L01P_4_VRN_4_AB20

IO_L32N_4_GCLK1_AA12

IO_L32P_4_GCLK0_AB12

VCCO_5_T9

VCCO_5_T10

VCCO_5_T11

VCCO_5_U8

VCCO_5_Y8

IO_U7

IO_U9

IO_U10

IO_U11

IO_V7

IO_V10

IO_VREF_5_U6

IO_VREF_5_AB11

IO_L01N_5_RDWR_B_Y4

IO_L01P_5_CS_B_AA3

IO_L06N_5_AB4

IO_L06P_5_AA4

IO_L09N_5_Y5

IO_L09P_5_W5

IO_L15N_5_W6

IO_L15P_5_V6

IO_L16N_5_AA6

IO_L16P_5_Y6

IO_L19N_5_Y7

IO_L19P_5_VREF_5_W7

IO_L22N_5_AB7

IO_L22P_5_AA7

IO_L24N_5_W8

IO_L24P_5_V8

IO_L25N_5_AB8

IO_L25P_5_AA8

IO_L27N_5_VREF_5_W9

IO_L27P_5_V9

IO_L28N_5_D6_AB9

IO_L28P_5_D7_AA9

IO_L29N_5_Y10

IO_L29P_5_VREF_5_W10

IO_L30N_5_AB10

IO_L30P_5_AA10

IO_L31N_5_D4_W11

IO_L31P_5_D5_V11

IO_L32N_5_GCLK3_AA11

IO_L32P_5_GCLK2_Y11

IO_L10N_5_VRP_5_AB5

IO_L10P_5_VRN_5_AA5

FPGAFPGA

1299-27-2005_1144

T12

T13

T14

U15

Y15

U16

U17

W13

W14

V18

Y16

AB13

AA19

AB19

W18

Y18

AA18

AB18

V17

W17

Y17

AA17

V16

W16

AA16

AB16

V15

W15

AA15

AB15

U14

V14

AA14

AB14

U13

V13

Y13

AA13

U12

V12

W12

Y12

AA20

AB20

AA12

AB12

T9

T10

T11

U8

Y8

U7

U9

U10

U11

V7

V10

U6

AB11

Y4

AA3

AB4

AA4

Y5

W5

W6

V6

AA6

Y6

Y7

W7

AB7

AA7

W8

V8

AB8

AA8

W9

V9

AB9

AA9

Y10

W10

AB10

AA10

W11

V11

AA11

Y11

AB5

AA5

U1

FG456XC3S1000

7

2

4

8

10

6

3

9

11

13

15

17

19

21

23

25

12

14

16

24

26

22

20

18

1

5

P16

IDC13X213X2

5

1

18

20

22

26

24

16

14

12

25

23

21

19

17

15

13

11

9

3

6

10

8

4

2

7

P17

IDC13X213X2

R46

060310K

R43

0603DNP

FPGA BANKS 4 + 5

VCCO_5

CONFIG_INIT_B_TFS1

CLK_OUT_EXP1

B4_L32N_GCKL1_AA12

R9

06030

B5_L10N_VRP_AB5_J3_9

B5_L10N_VRP_AB5_J3_9

B5_L10P_VRN_AA5_J3_10

VCCO_5

B5_L32P_GCLK2_Y1

B5_L32N_GCLK3_AA11_J3_30

CONFIG_DIN_DT1PRI

UDEF16

UDEF38

UDEF14

RX0

TX0

RX1

TX1

UDEF20

UDEF21

UDEF23

UDEF17

UDEF25

UDEF24

UDEF22

RESET

UDEF30

UDEF29

UDEF27

UDEF26

UDEF35

UDEF34

UDEF33

UDEF32

UDEF31

UDEF15

UDEF28

UDEF41

UDEF40

UDEF39

UDEF37

UDEF36

BR

UDEF43

BG

BGH

UDEF19

B5_L31P_D5_V11_J3_40

B5_L31N_D4_W11_J3_39

B5_L30P_AA10_J3_38

B5_L30N_AB10_J3_37

B5_L29P_W10_J3_36

B5_L29N_Y10_J3_35

B5_L28P_D7_AA9_J3_34

B5_L28N_D6_AB9_J3_33

B5_L27P_V9_J3_32

B5_L27N_W9_J3_31

B5_L25P_AA8_J3_22

B5_L25N_AB8_J3_21

B5_L24P_V8_J3_20

B5_L24N_W8_J3_19

B5_L22P_AA7_J3_18

B5_L22N_AB7_J3_17

B5_L19P_W7_J3_16

B5_L19N_Y7_J3_15

B5_L16P_Y6_J3_14

B5_L16N_AA6_J3_13

B5_L15P_V6_J3_12

B5_L15N_W6_J3_11

B5_L09P_W5_J3_8

B5_L09N_Y5_J3_7

B5_L06P_AA4_J3_6

B5_L06N_AB4_J3_5

B5_L01P_CS_B_AA3_J3_2

B5_L01N_RDWR_B_Y4_J3_1

B5_AB11_J3_90

B5_U6_J3_23

B5_V10_J3_85

B5_V7_J3_29

B5_U11_J3_83

B5_U10_J3_81

B5_U9_J3_41

B5_U7_J3_28

UDEF18

3

2

1

3X1IDC3X1

P11

B5_L29N_Y10_J3_35

B5_L30N_AB10_J3_37

B5_L31N_D4_W11_J3_39

B5_U11_J3_83

B5_V10_J3_85B5_AB11_J3_90

B5_U10_J3_81

B5_L31P_D5_V11_J3_40

B5_L30P_AA10_J3_38

B5_L29P_W10_J3_36

B5_L28P_D7_AA9_J3_34

B5_L27P_V9_J3_32

B5_L28N_D6_AB9_J3_33

B5_L27N_W9_J3_31

B5_L25N_AB8_J3_21B5_L25P_AA8_J3_22

B5_L24N_W8_J3_19B5_L24P_V8_J3_20

B5_U9_J3_41B5_U6_J3_23

VCCO_5

B5_L10P_VRN_AA5_J3_10

C70

0603001UF 001UF

0603

C69 C68

0603001UF001UF

0603

C67001UF0603

C66 C65

0603001UF 001UF

0603

C64C63

0603001UF

B5_L09N_Y5_J3_7

B5_U7_J3_28 B5_V7_J3_29

B5_L10P_VRN_AA5_J3_10 B5_L10N_VRP_AB5_J3_9

B5_L15P_V6_J3_12 B5_L15N_W6_J3_11

B5_L16P_Y6_J3_14 B5_L16N_AA6_J3_13

B5_L19P_W7_J3_16 B5_L19N_Y7_J3_15

B5_L22P_AA7_J3_18 B5_L22N_AB7_J3_17

B5_L32N_GCLK3_AA11_J3_30 B5_L32P_GCLK2_Y1

B5_L01P_CS_B_AA3_J3_2 B5_L01N_RDWR_B_Y4_J3_1

B5_L06P_AA4_J3_6 B5_L06N_AB4_J3_5

B5_L09P_W5_J3_8

VCCO_5

DNP0603

R45

25V

33V

33V

4

3

2

1

A B C D

20 Cotton Road

Nashua NH 03063

A B C D

4

3

2

1

PH 1-800-ANALOGD

C

Title

Size Board No

Date Sheet of

DEVICESANALOG

DNP = Do Not Populate

Rev

BLACKFIN FPGA EZ-EXTENDER

A0199-2005 10

SN74LVC1G125

12109-27-2005_1144

2 4

1

SOT23-5SN74LVC1G125

U8

USER IO

C80

0603001UF

SW4SWT013SPST-MOMENTARY

SPST-MOMENTARYSWT013SW3

060310R42

C5

06031UF

R413300603

LED001AMBER-SMTLED8

0603330R40

LED7AMBER-SMTLED001

R393300603

R1033006030603

330R34R35

33006030603

330R36

0603330R37 R38

3300603

LED001AMBER-SMTLED2

AMBER-SMTLED001

LED3AMBER-SMTLED001

LED4AMBER-SMTLED001

LED5

LED001AMBER-SMTLED6

LED9GREEN-SMTLED001

402100R23

1 2

3 4

5 6

7 8

JP5

IDC4X24X2

AMBER-SMTLED001

LED1

B6_L01N_Y3

B6_L01P_Y2

B5_U10_J3_81

B5_AB11_J3_90

PB2

B5_V10_J3_85

B5_U11_J3_83

B5_L31N_D4_W11_J3_39

B5_L30N_AB10_J3_37

B5_L29N_Y10_J3_35

B5_L28N_D6_AB9_J3_33

B5_L27N_W9_J3_31

PB1

B5_L25N_AB8_J3_21

R47

060310K

CHOKE_COIL

4

3

2

1

A B C D

20 Cotton Road

Nashua NH 03063

A B C D

4

3

2

1

PH 1-800-ANALOGD

C

Title

Size Board No

Date Sheet of

DEVICESANALOG

DNP = Do Not Populate

Rev

BLACKFIN FPGA EZ-EXTENDER

A0199-2005 10

25V

33V

VIN

EN

SW

GND

FB

VIN

EN

SW

GND

FB

VIN

EN

SW

GND

FB

4

3

5

2

1

VR3

SOT23-5LM3475MF

1

2

5

3

4

VR2

SOT23-5LM3475MF

4

3

5

2

1

VR1

SOT23-5LM3475MF

12119-27-2005_1124

1

32

Q2

SI2

343D

SS

OT

23D

1

32

Q3

SI2

343D

SS

OT

23D

2 3

1S

I234

3DS

Q1

SO

T23

D

316KR17

0603

215KR18

0603

0603

R11105K

DNPC73

0603

0603

C72DNP

805

C741000PF

0R58

0603

1000PFC10

805

0603

R1910K

C100UFCT2

CT3100UFC

IND005

L110UH

10UHL3

IND005

10UHL2

IND005

1

2 D3

DO214ABSCHOT_RECT

3A

0603

R20200K

805

C639NF

390PFC7

0603

2

1 3A

SCHOT_RECTDO214AB

D2

499KR13

0603

1

2 D1

DO214ABSCHOT_RECT

3A

33V_EI

3

1

2

3X1IDC3X1

P13

UNREG_IN

12V

CT1100UFC

80510UFC71

R1200603

5V_EI

8051000PFC2

FER2

0603

060301UFC3

POWER

FUS00125AF1

4

1

3

2

FER1

DO-214AA

S2A_RECT

2AD5

8051000PFC1 C4

10UFC

3

1

2

3X1IDC3X1

P12

UNREG_IN

1

2

3

CON00525MM_JACK

POWER

J4

2

1P42

IDC2X12X1DNP

1

2

DNP2X1IDC2X1

P43

06030R15

C810UF805

80510UFC9

R1600603

UNREG_IN

0603

R1410K

0603

R590

4

3

2

1

A B C D

20 Cotton Road

Nashua NH 03063

A B C D

4

3

2

1

PH 1-800-ANALOGD

C

Title

Size Board No

Date Sheet of

DEVICESANALOG

DNP = Do Not Populate

Rev

BLACKFIN FPGA EZ-EXTENDER

A0199-2005 1012129-14-2005_1204

5

2

4

8

10

6

1

3

9

11

13

15

17

19

12

14

16

20

18

7

P20

SOIC20

PROTO AREA

1

3

2

SOT23D

P39

2

3

1

SOT23D

P38

2

4

5 6

3

1

SOT23-6

P411

3

65

4

2

SOT23-6

P40

PRT_NUM=DNE

11

13

15 16

14

12

2

4

6

8

109

7

5

3

1

SOIC16

P191

3

5

7

9 10

8

6

4

2

12

14

1615

13

11

SOIC16

P18

21P37

805

1 2

805

P36

21P35

805

1 2

805

P34

1 2

805

P33

21P32

805

1 2

805

P31

21P30

805

1 2

805

P29

21P28

805

1 2

805

P27

21P26

805

21P25

805

1 2

805

P24

21P23

805

1 2

805

P22

TP86

TP85

TP84

TP83

TP82

TP81

TP80

TP79 TP77

TP76

TP75

TP74

TP73

TP72

TP71

TP70

TP68

TP67

TP66

TP65

TP64

TP62

TP61

TP60

TP59

TP58

TP57

TP56

TP55

TP54

TP53

TP51

TP50

TP49

TP48

TP47

TP46

TP45

TP44

TP43

TP41

TP40

TP39

TP38

TP37

TP36

TP35

TP34

TP33

TP32

TP30

TP29

TP28

TP27

TP26

TP25

TP24

TP23

TP22

TP21

TP19

TP18

TP17

TP16

TP15

TP14

TP13

TP12

TP11

TP9

TP8

TP7

TP6

TP5

TP4

TP125

TP124

TP123

TP122

TP121

TP120

TP119

TP118

TP117

TP116

TP114

TP113

TP112

TP111

TP110

TP109

TP108

TP107TP106

TP105TP103

TP102TP101 TP100TP99

TP98 TP97

TP96 TP95

TP94TP93

TP92TP91

TP90 TP89

TP88 TP87

TP78TP69

TP63 TP52

TP42 TP31

TP20 TP10

TP115TP104

7

18

20

16

14

12

19

17

15

13

11

9

3

1

6

10

8

4

2

5

SOIC20

P21

I INDEX

Numerics connectors

25V header (P42) 2-17

AADSP-BF5333761 EZ-KIT Lite interface 2-1ADSP-BF5333761 processors boot mode

settings 2-14architecture of this EZ-Extender 2-2asynchronous static random access memory

(SRAM) xauxiliary oscillator x

Bbill of materials A-1block diagram of this EZ-Extender 2-2boot jumper See JP4

Cconfiguration jumpers See JP2 JP3

map of locations 2-18J1-3 (expansion) 2-19P1-3 (expansion) 2-19P14 (IDC) 2-19P15 (JTAG header) 2-4P16-17 (IDC) 2-19P4 (high-speed) 2-20P5 (IDC) 2-20P6 (JTAG) 2-7P7 (IDC) 2-20P8 (IDC) 2-19

customer support xiii

Ddone LED (LED10) 2-17

Eexpansion interface

connectors (P1-3 J1-3) 2-19of ADSP-BF5333761 EZ-KIT Lites ix

1-3external power supply 1-3 2-8

FField-Programmable Gate Array See FPGA

Blackfin FPGA EZ-Extender Manual I-1

INDEX

FPGAdocumentation 1-2input jumpers (JP5) 2-14softwarefirmware 1-2Xilinx Spartan package x 1-3

FPGA pinsAB10 (LED3) 2-17AB11 (JP58) 2-15AB8 (LED7) 2-17AB9 (LED5) 2-17C11 (PB1SW3) 2-15H5 (PB2SW3) 2-16M2-0 (JP4) 2-14U10 (JP56) 2-15U11 (LED1) 2-17V10 (LED8) 2-17W11 (LED2) 2-17W9 (LED6) 2-17Y10 (LED4) 2-17Y3-2 (JP52-54) 2-15

FPGA programmingblock diagram 2-3via ADSP-BF533376 processors 2-6via JTAG header 2-4via serial ROM 2-5

GGCLK1 (global clock 1) pin 1-4GCLK6 (global clock 6) pin 1-4general-purpose input push buttons 2-15 2-16

Hhigh-speed connector (P4) 2-20

IIDC connectors x 2-19 2-20installation of this EZ-Extender 1-1

JJTAG

cable 1-4 2-7header (P6) 1-5 2-4 2-7 2-14

jumpersmap of locations 2-11JP1 (boot jumper) 2-5 2-12JP2 (confug done) 2-12JP3 (config program) 2-13JP41-46 (boot mode select) 2-5 2-6 2-14JP52-56 (FPGA input) 2-14

LLEDs

map of locations 2-15LED10 (FPGA done pin) 2-4 2-5 2-17LED1-8 (status) 2-17LED9 (power) 2-17

MM2-0 (JP4) pins 2-5master serial boot mode 2-6MCS-86 Hexadecimal Object (mcs) file

format 2-6

Nnotation conventions xvi

Ooscillator x 1-4

PP12 (power in) header 2-9P13 (33V header) 2-9P42 (25V header) 2-10P43 (12V header) 2-10PB1 push button (SW3) 2-15

I-2 Blackfin FPGA EZ-Extender Manual

INDEX

PB2 push button (SW4) 2-16PF14 flag pin (ADSP-BF537 EZ-KIT Lite)

2-12PF3 flag pin (ADSP-BF53361 EZ-KIT Lite)

2-12power

12V header (P43) 2-1025V header (P42) 2-1033V header (P13) 2-9in header (P12) 2-9LED (LED9) 2-17limitations 2-8supplies 1-3 2-8

printed circuit board (PCB) 1-2product overview ixprogram push button (SW1) 2-4 2-15push buttons

See also SWx map of locations 2-15

Sserial ROM 1-5

boot jumper (JP1) 2-12 2-14programming via JTAG Header 2-7

setup of this EZ-Extender 1-1slave serial mode 2-6

SRAM memory banks 1-4status reporting 1-4 2-17SW1 (program) push button 2-4 2-15SW3 (PB1) push button 2-15SW4 (PB2) push button 2-16switching regulators 2-8

TTCK signal 2-7TDI signal 2-7TDO signal 2-7TMS signal 2-7

VVisualDSP++

flash programming utility 1-4 2-6FPGA documentation 2-6

VR1-3 regulators 2-8

XXilinx

JTAG cablesoftware 1-4 2-4 2-7JTAG header 2-12serial ROM 1-5

Blackfin FPGA EZ-Extender Manual I-3

INDEX

I-4 Blackfin FPGA EZ-Extender Manual

• Blackfin FPGA EZ-Extender Manual
• Contents
• Preface
• • Product Overview
  • Purpose of This Manual
  • Intended Audience
  • Manual Contents
  • Whatrsquos New in This Manual
  • Technical or Customer Support
  • Supported Products
  • Product Information
  • • Related Documents
    • • Table 1 Related Processor Publications
      • Table 2 Related VisualDSP++ Publications
      • • Notation Conventions
        • • 1 FPGA EZ-Extender Interfaces
          • • FPGA EZ-Extender Setup
            • • Figure 1-1 FPGA EZ-Extender Setup
              • • FPGA Software and Firmware
                • FPGA EZ-Extender Overview
                • • 2 FPGA EZ-Extender Hardware Reference
                  • • System Architecture
                    • • Figure 2-1 Block Diagram
                      • • Programming the FPGA
                        • • Figure 2-2 FPGA Programming Block Diagram
                          • FPGA Programming via JTAG
                          • • Table 2-1 P15 Connections for PFGA Programming via JTAG
                            • Table 2-2 JP1 Settings for FPGA Programming via JTAG
                            • Table 2-3 JP4 Settings for FPGA Programming via JTAG
                            • • FPGA Programming via Serial ROM
                              • • Table 2-4 JP1 Settings for FPGA Programming via Serial ROM
                                • Table 2-5 JP4 Settings for FPGA Programming in Master Serial Mode
                                • • FPGA Programming via Blackfin Application
                                  • • Table 2-6 JP1 Settings for FPGA Programming via Blackfin Processor
                                    • Table 2-7 JP4 Settings for FPGA Programming via Blackfin Processor
                                    • • Programming the Serial ROM
                                      • • Serial ROM via JTAG Header
                                        • • Table 2-8 P6 Connections for Serial ROM
                                          • • Power
                                            • • Table 2-9 Power Limitations
                                              • Power In Header (P12)
                                              • 33V Header (P13)
                                              • 25V Header (P42)
                                              • 12V Header (P43)
                                              • • Jumpers
                                                • • Figure 2-3 Jumper Locations
                                                  • Serial ROM Boot Jumper (JP1)
                                                  • • Table 2-10 JP1 Settings
                                                    • • Config Done Jumper (JP2)
                                                      • • Table 2-11 JP2 Settings
                                                        • • Config Program Jumper (JP3)
                                                          • • Table 2-12 JP3 Settings
                                                            • • Boot Jumper (JP4)
                                                              • • Table 2-13 JP4 Settings
                                                                • • FPGA Input Jumpers (JP5)
                                                                  • • Table 2-14 JP5 Settings
                                                                    • • Push Buttons and LEDs
                                                                      • • Figure 2-4 Push Button and LED Locations
                                                                        • Program Push Button (SW1)
                                                                        • PB1 Push Button (SW3)
                                                                        • PB2 Push Button (SW4)
                                                                        • Status LEDs (LED1-8)
                                                                        • • Table 2-15 Status LED (LED1-8) Settings
                                                                          • • Power LED (LED9)
                                                                            • Done LED (LED10)
                                                                            • • Connectors
                                                                              • • Figure 2-5 Connector Locations
                                                                                • Expansion Interface (P1-3 and J1-3)
                                                                                • IDC Connectors (P8 P14 P16 and P17)
                                                                                • IDC Connectors (P5 and P7)
                                                                                • High-Speed Connector (P4)
                                                                                • • A Bill Of Materials
                                                                                  • B Schematics
                                                                                  • • Title
                                                                                    • FPGA Config
                                                                                    • SRAM FPGA Banks 7 and 8
                                                                                    • Expansion Interface Connector 1
                                                                                    • FPGA Banks 0 and 1
                                                                                    • Expansion Interface Connectors 2
                                                                                    • FPGA Banks 2 and 3
                                                                                    • Expansion Interface Connector 1
                                                                                    • FPGA Banks 4 and 5
                                                                                    • User IO
                                                                                    • Power
                                                                                    • Proto Area
                                                                                    • • I Index
                                                                                      • • Numerics
                                                                                        • A
                                                                                        • B
                                                                                        • C
                                                                                        • D
                                                                                        • E
                                                                                        • F
                                                                                        • G
                                                                                        • H
                                                                                        • I
                                                                                        • J
                                                                                        • L
                                                                                        • M
                                                                                        • N
                                                                                        • O
                                                                                        • P
                                                                                        • S
                                                                                        • T
                                                                                        • V
                                                                                        • X

4

3

2

1

A B C D

20 Cotton Road

Nashua NH 03063

A B C D

4

3

2

1

PH 1-800-ANALOGD

C

Title

Size Board No

Date Sheet of

DEVICESANALOG

DNP = Do Not Populate

Rev

BLACKFIN FPGA EZ-EXTENDER

A0199-2005 10

SchematicBLACKFIN FPGA EZ-EXTENDER

1219-9-2005_1040

TITLE

33V

4

3

2

1

A B C D

20 Cotton Road

Nashua NH 03063

A B C D

4

3

2

1

PH 1-800-ANALOGD

C

Title

Size Board No

Date Sheet of

DEVICESANALOG

DNP = Do Not Populate

Rev

BLACKFIN FPGA EZ-EXTENDER

A0199-2005 10

33V

1A

1B

1Y

2A

2B

2Y

3A

3B

3Y

4A

4B

4Y

~AB

EN

25V

33V

33V

33V

33V

33V

25V

33V

OENC OUTOE OUT

CLK

D0

TMS

TCK

TDI

TDO

VCCINT

VCCO

VCCJ

NC1

NC2

NC3

NC4

NC5

NC6

GND

CE

CF

OE~RESET

CEO

VCCAUX_A6

VCCAUX_A17

VCCAUX_F1

VCCAUX_F22

VCCAUX_U1

VCCAUX_U22

VCCAUX_AB6

VCCAUX_AB17

VCCINT_G7

VCCINT_G8

VCCINT_G15

VCCINT_G16

VCCINT_H7

VCCINT_H16

VCCINT_R7

VCCINT_R16

VCCINT_T7

VCCINT_T8

VCCINT_T15

VCCINT_T16

TCK

TDI

TDO

TMS

M0

M1

M2

CCLK

PROG_B

DONE

HSWAP_EN

GND_A1

GND_A22

GND_B2

GND_B21

GND_C9

GND_C14

GND_J3

GND_J9

GND_J10

GND_J11

GND_J12

GND_J13

GND_J14

GND_J20

GND_K9

GND_K10

GND_K11

GND_K12

GND_K13

GND_K14

GND_L9

GND_L10

GND_L11

GND_L12

GND_L13

GND_L14

GND_M9

GND_M10

GND_M11

GND_M12

GND_M13

GND_M14

GND_N9

GND_N10

GND_N11

GND_N12

GND_N13

GND_N14

GND_P3

GND_P9

GND_P10

GND_P11

GND_P12

GND_P13

GND_P14

GND_P20

GND_Y9

GND_Y14

GND_AA2

GND_AA21

GND_AB1

GND_AB22

FPGAFPGA

EXTRA CLOCK SOCKET25MHZ SYSTEM CLOCK

FPGA JTAG HEADER

FLASH JTAG HEADER

BOOTMODE JUMPER

FPGA BOOT FLASH(2Mbit)

MUXFLASHSKTOSC

9-27-2005_1144 2 12

A6

A17

F1

F22

U1

U22

AB6

AB17

G7

G8

G15

G16

H7

H16

R7

R16

T7

T8

T15

T16

A21

B1

B22

A20

AB2

AA1

AB3

AA22

A2

AB21

B3

A1

A22

B2

B21

C9

C14

J3

J9

J10

J11

J12

J13

J14

J20

K9

K10

K11

K12

K13

K14

L9

L10

L11

L12

L13

L14

M9

M10

M11

M12

M13

M14

N9

N10

N11

N12

N13

N14

P3

P9

P10

P11

P12

P13

P14

P20

Y9

Y14

AA2

AA21

AB1

AB22

U1

FG456XC3S1000

CONFIG_PROG_B

6

5

4

3

2

1P6

IDC6X16X1

1

2

3

4

5

6

P15

IDC6X16X1

3

1

8

10

7

13

5

6

4

17

18

19

20

2

9

12

14

15

16

11

U4

TSSOP20XCF04S

2

4

5 6

3

1JP4

IDC3X23X2

402100R5

R400603

402100R44

R8100402

R7100402

1 3

U6

25MHZOSC003

80510UFC14

R29

060310K

R22

060310K

R21

060310K

R1

060310K

1 5

U7

DIPDIP8SOC

R263306030603

33R2

R25

DNP

10K0603

12V

1 2JP1

IDC2X12X1

CONFIG_DONER3

06030

CONFIG_CLK_TSCLK1

FPGA_TMS

FPGA_TDO

FPGA_TCK

FPGA_TDI

FPGA_TCK

FPGA_TDO

FPGA_TDI

FPGA_TMS

FLASH_TMS

FLASH_TDI

FLASH_TDO

FLASH_TCK

M1

M2

M0

12V

SPST-MOMENTARYSWT013SW1

2

3

4

5

6

7

11

10

9

14

13

12

1

15

U2

TSSOP1674LVC157

CONFIG_DONE

FLASH_TMS

FLASH_TCK

FLASH_TDI

FLASH_TDO

M2

M0

M1

FPGA CONFIG

CONFIG_INIT_B_TFS1

FLASH_DOUT

CONFIG_CLK_TSCLK1

FLASH_DONE

001UF0603

C18

IO_L32_0_GCLK6_A11B4_L32N_GCKL1_AA12

C19

0603001UF 001UF

0603

C20 C21

0603001UF 001UF

0603

C25C24

0603001UF001UF

0603

C23C22

0603001UF 001UF

0603

C31 C30

0603001UF 001UF

0603

C29 C28

0603001UF001UF

0603

C27C26

0603001UF

001UF0603

C32 C11

0603001UF 001UF

0603

C12 C13

0603001UF

80510UFC15 C16

10UF805

C17

0603001UF

0603330R24

LED10

LED001AMBER-SMT

CONFIG_DIN_DT1PRI

FLASH_DONE

FLASH_DOUT

DT1PRI

R6

060310K10K

0603

R28

33V 33V

4

3

2

1

A B C D

20 Cotton Road

Nashua NH 03063

A B C D

4

3

2

1

PH 1-800-ANALOGD

C

Title

Size Board No

Date Sheet of

DEVICESANALOG

DNP = Do Not Populate

Rev

BLACKFIN FPGA EZ-EXTENDER

A0199-2005 10

33V

33V

A18

A1

A10

A11

A12

A13

A14

A16

A2

A3

A4

A5

A6

A7

A8

A9

D0

D1

D10

D11

D2

D3

D4

D5

D6

D7

D8

D9

BHE

BLE

CE

OE

WE

A17

D15

D14

D13

D12

A0

A15

A18

A1

A10

A11

A12

A13

A14

A16

A2

A3

A4

A5

A6

A7

A8

A9

D0

D1

D10

D11

D2

D3

D4

D5

D6

D7

D8

D9

BHE

BLE

CE

OE

WE

A17

D15

D14

D13

D12

A0

A15

VCCO_6_M7

VCCO_6_N7

VCCO_6_P7

VCCO_6_R3

VCCO_6_R6

IO_Y1

IO_L16N_6_W4

IO_L16P_6_W3

IO_L17N_6_W2

IO_L17P_6_VREF_6_W1

IO_L19N_6_V5

IO_L19P_6_U5

IO_L20N_6_V4

IO_L20P_6_V3

IO_L21N_6_V2

IO_L21P_6_V1

IO_L22N_6_T6

IO_L22P_6_T5

IO_L23N_6_U4

IO_L23P_6_T4

IO_L24N_6_VREF_6_U3

IO_L24P_6_U2

IO_L26N_6_T3

IO_L26P_6_R4

IO_L27N_6_T2

IO_L27P_6_T1

IO_L28N_6_R5

IO_L28P_6_P6

IO_L29N_6_R2

IO_L29P_6_R1

IO_L31N_6_P5

IO_L31P_6_P4

IO_L32N_6_P2

IO_L32P_6_P1

IO_L33N_6_N6

IO_L33P_6_N5

IO_L34N_6_VREF_6_N4

IO_L34P_6_N3

IO_L35N_6_N2

IO_L35P_6_N1

IO_L38N_6_M6

IO_L38P_6_M5

IO_L39N_6_M4

IO_L39P_6_M3

IO_L40N_6_M2

IO_L40P_6_VREF_6_M1

IO_L01N_6_VRP_6_Y3

IO_L01P_6_VRN_6_Y2

VCCO_7_H3

VCCO_7_H6

VCCO_7_J7

VCCO_7_K7

VCCO_7_L7

IO_C2

IO_L16N_7_D1

IO_L16P_7_VREF_7_C1

IO_L17N_7_E4

IO_L17P_7_D4

IO_L19N_7_VREF_7_D3

IO_L19P_7_D2

IO_L20N_7_F4

IO_L20P_7_E3

IO_L21N_7_E1

IO_L21P_7_E2

IO_L22N_7_G6

IO_L22P_7_F5

IO_L23N_7_F2

IO_L23P_7_F3

IO_L24N_7_H5

IO_L24P_7_G5

IO_L26N_7_G3

IO_L26P_7_G4

IO_L27N_7_G1

IO_L27P_7_VREF_7_G2

IO_L28N_7_H1

IO_L28P_7_H2

IO_L29N_7_J4

IO_L29P_7_H4

IO_L31N_7_J5

IO_L31P_7_J6

IO_L32N_7_J1

IO_L32P_7_J2

IO_L33N_7_K5

IO_L33P_7_K6

IO_L34N_7_K3

IO_L34P_7_K4

IO_L35N_7_K1

IO_L35P_7_K2

IO_L38N_7_L5

IO_L38P_7_L6

IO_L39N_7_L3

IO_L39P_7_L4

IO_L40N_7_VREF_7_L1

IO_L40P_7_L2

IO_L01N_7_VRP_7_C3

IO_L01P_7_VRN_7_C4

(512k x 16bits x 2chips)2MBYTES FPGA SRAM

FPGASRAM SRAM

SRAM_A9

9-27-2005_1144 3 12

FLASH_TDO

FLASH_TMS

FLASH_TDI

FLASH_TCK

M7

N7

P7

R3

R6

Y1

W4

W3

W2

W1

V5

U5

V4

V3

V2

V1

T6

T5

U4

T4

U3

U2

T3

R4

T2

T1

R5

P6

R2

R1

P5

P4

P2

P1

N6

N5

N4

N3

N2

N1

M6

M5

M4

M3

M2

M1

Y3

Y2

H3

H6

J7

K7

L7

C2

D1

C1

E4

D4

D3

D2

F4

E3

E1

E2

G6

F5

F2

F3

H5

G5

G3

G4

G1

G2

H1

H2

J4

H4

J5

J6

J1

J2

K5

K6

K3

K4

K1

K2

L5

L6

L3

L4

L1

L2

C3

C4

U1

FG456XC3S1000

28

2

23

24

25

26

27

43

3

4

5

18

19

20

21

22

7

8

31

32

9

10

13

14

15

16

29

30

40

39

6

41

17

44

38

37

36

35

1

42

U3

TSOP44IS61LV51216

42

1

35

36

37

38

44

17

41

6

39

40

30

29

16

15

14

13

10

9

32

31

8

7

22

21

20

19

18

5

4

3

43

27

26

25

24

23

2

28

U5

TSOP44IS61LV51216

SRAM_D7

SRAM_D6

SRAM_D3

SRAM_D2

SRAM_D0

SRAM_D8

SRAM_D9

SRAM_D5

SRAM_D4

SRAM_D13

SRAM_D1

SRAM_D10

SRAM_D11

SRAM_D12

SRAM_D14

SRAM_D15

SRAM_CE

SRAM_A7

SRAM_A0

SRAM_A5

SRAM_A3

SRAM_A1

SRAM_WE

SRAM_A8

SRAM_A6

SRAM_A4

SRAM_A2

SRAM_A17

SRAM_OE

SRAM_A12

SRAM_A13

SRAM_A15

SRAM_A16

SRAM_A14

SRAM_A18

SRAM_A11

SRAM_A10

SRAM_D22

SRAM_D20

SRAM_D18

SRAM_D17

SRAM_D16

SRAM_D26

SRAM_D21

SRAM_D24

SRAM_D19

SRAM_D31

SRAM_D25

SRAM_D27

SRAM_D28

SRAM_D30

SRAM_D29

PB2

A11

A5

D1

A15

A3

A9

D13

D7

A13

A19

A7

A1

A18

A6

A2

A12

D6

A8

A14

D2

D0

A10

A4

D3

A16

SRAM FPGA BANKS 7 + 8

SRAM_CE

SRAM_WE

SRAM_OE

SRAM_A18

SRAM_A0 SRAM_D0

SRAM_D1

SRAM_D2

SRAM_D3

SRAM_D4

SRAM_D5

SRAM_D6

SRAM_D7

SRAM_D8

SRAM_D9

SRAM_D10

SRAM_D11

SRAM_D12

SRAM_D13

SRAM_D14

SRAM_D15

SRAM_D16

SRAM_D17

SRAM_D18

SRAM_D19

SRAM_D20

SRAM_D21

SRAM_D22

SRAM_D23

SRAM_D24

SRAM_D25

SRAM_D26

SRAM_D27

SRAM_D28

SRAM_D29

SRAM_D30

SRAM_D31

SRAM_A1

SRAM_A2

SRAM_A3

SRAM_A4

SRAM_A5

SRAM_A6

SRAM_A7

SRAM_A8

SRAM_A9

SRAM_A10

SRAM_A11

SRAM_A12

SRAM_A13

SRAM_A14

SRAM_A15

SRAM_A16

SRAM_A17

SRAM_A1

SRAM_A2

SRAM_A3

SRAM_A4

SRAM_A5

SRAM_A6

SRAM_A7

SRAM_A8

SRAM_A9

SRAM_A10

SRAM_A11

SRAM_A12

SRAM_A13

SRAM_A14

SRAM_A15

SRAM_A16

SRAM_A17

SRAM_A18

SRAM_A0

SRAM_OE

SRAM_WE

SRAM_CE

C33

0603001UF

C34

0603001UF001UF

0603

C37001UF0603

C36

C42

0603001UF 001UF

0603

C41 C40

0603001UF001UF

0603

C39001UF0603

C46 C45

0603001UF 001UF

0603

C44C43

0603001UF

B6_L01P_Y2

B6_L01N_Y3

SRAM_D23

4

3

2

1

A B C D

20 Cotton Road

Nashua NH 03063

A B C D

4

3

2

1

PH 1-800-ANALOGD

C

Title

Size Board No

Date Sheet of

DEVICESANALOG

DNP = Do Not Populate

Rev

BLACKFIN FPGA EZ-EXTENDER

A0199-2005 10

EXPANSION INTERFACE TYPE B

P1Expanison Connector

Top Of BoardBottom Of Board

Expansion Connector 1

10-18-2005_1616 4 12

EXPANSION INTERFACE CONNECTOR 1

C3510UF805

01UF0603

C38

5V_EI

5V_EI

1

10

11 12

13 14

15 16

17 18

19

2

20

21 22

23 24

25 26

27 28

29

3

30

31 32

33 34

35 36

37 38

39

4

40

41 42

43 44

45 46

47 48

49

5

50

51 52

53 54

55 56

57 58

59

6

60

61 62

63 64

65 66

67 68

69

7

70

71 72

73 74

75 76

77 78

79

8

80

81 82

83 84

85 86

87 88

89

9

90

P1

CON01845X2

1

10

1112

1314

1516

1718

19

2

20

2122

2324

2526

2728

29

3

30

3132

3334

3536

3738

39

4

40

4142

4344

4546

4748

49

5

50

5152

5354

5556

5758

59

6

60

6162

6364

6566

6768

69

7

70

7172

7374

7576

7778

79

8

80

8182

8384

8586

8788

89

9

90

J1

CON01945X2

PP1

EXPANSION_PPI_CLK

PP3

UDEF2

UDEF4

UDEF6

UDEF8

UDEF10

D9

D7

D15

D13

D11

D5

D1

D3

D15

D9

D5

D1

D3

D0

D2

D4

D6

D8

D10

D14

D12

P1_5

P1_25

P1_27

P1_29

P1_31

P1_33

P1_55

P1_57

P1_59

P1_61

P1_63

P1_65

P1_67

P1_69

P1_35

P1_26

P1_28

P1_30

P1_32

P1_34

P1_56

P1_58

P1_60

P1_62

P1_64

P1_66

P1_68

P1_70

P1_36

P1_26

P1_28

P1_30

P1_32

P1_34

P1_36

P1_56

P1_58

P1_60

P1_62

P1_64

P1_66

P1_68

P1_70

P1_5

P1_25

P1_27

P1_29

P1_31

P1_33

P1_35

P1_55

P1_57

P1_59

P1_61

P1_63

P1_65

P1_67

P1_69

P1_[586]

A5

A6A7

A8A9

A10A11

A12A13

A14A15

A16A17

A18A19

D0

D2

D4

D6D7

D8

D10D11

D12D13

D14

A1

A2

B1_L24N_D15_J1_71B1_L24P_E15_J1_72

B1_L22N_A16_J1_73B1_L22P_B16_J1_74

B1_L19N_C16_J1_75B1_L19P_D16_J1_76

B1_L16N_B17_J1_77B1_L16P_C17_J1_78

B1_L15N_D17_J1_79

A3

B1_L15P_E17_J1_80

B1_L10N_A18_J1_81B1_L10P_B18_J1_82

B1_L09N_C18_J1_83B1_L09P_D18_J1_84

B1_L06N_A19_J1_85B1_L06P_B19_J1_86

A4A5

A6 A7

A8 A9

A10 A11

A12 A13

A14 A15

A16 A17

A18 A19

A1

A2

PP0

PP2

UDEF1

UDEF3

A3

UDEF5

UDEF7

UDEF9

UDEF11

A4

33V

25V 33V

33V

33V

33V

4

3

2

1

A B C D

20 Cotton Road

Nashua NH 03063

A B C D

4

3

2

1

PH 1-800-ANALOGD

C

Title

Size Board No

Date Sheet of

DEVICESANALOG

DNP = Do Not Populate

Rev

BLACKFIN FPGA EZ-EXTENDER

A0199-2005 10

VCCO_0_C8

VCCO_0_F8

VCCO_0_G9

VCCO_0_G10

VCCO_0_G11

IO_A10

IO_D9

IO_D10

IO_F6

IO_VREF_0_A3

IO_VREF_0_C7

IO_VREF_0_E5

IO_VREF_0_F7

IO_L06N_0_D5

IO_L06P_0_C5

IO_L09N_0_B5

IO_L09P_0_A5

IO_L10N_0_E6

IO_L10P_0_D6

IO_L15N_0_C6

IO_L15P_0_B6

IO_L16N_0_E7

IO_L16P_0_D7

IO_L19N_0_B7

IO_L19P_0_A7

IO_L22N_0_E8

IO_L22P_0_D8

IO_L24N_0_B8

IO_L24P_0_A8

IO_L25N_0_F9

IO_L25P_0_E9

IO_L27N_0_B9

IO_L27P_0_A9

IO_L28N_0_F10

IO_L28P_0_E10

IO_L29N_0_C10

IO_L29P_0_B10

IO_L30N_0_F11

IO_L30P_0_E11

IO_L31N_0_D11

IO_L31P_0_VREF_0_C11

IO_L01N_0_VRP_0_B4

IO_L01P_0_VRN_0_A4

IO_L32N_0_GCLK7_B11

IO_L32P_0_GCLK6_A11

VCCO_1_C15

VCCO_1_F15

VCCO_1_G12

VCCO_1_G13

VCCO_1_G14

IO_A12

IO_E16

IO_F12

IO_F13

IO_F16

IO_F17

IO_VREF_1_E13

IO_VREF_1_F14

IO_L06N_1_VREF_1_A19

IO_L06P_1_B19

IO_L09N_1_C18

IO_L09P_1_D18

IO_L10N_1_VREF_1_A18

IO_L10P_1_B18

IO_L15N_1_D17

IO_L15P_1_E17

IO_L16N_1_B17

IO_L16P_1_C17

IO_L19N_1_C16

IO_L19P_1_D16

IO_L22N_1_A16

IO_L22P_1_B16

IO_L24N_1_D15

IO_L24P_1_E15

IO_L25N_1_B15

IO_L25P_1_A15

IO_L27N_1_D14

IO_L27P_1_E14

IO_L28N_1_A14

IO_L28P_1_B14

IO_L29N_1_C13

IO_L29P_1_D13

IO_L30N_1_A13

IO_L30P_1_B13

IO_L31N_1_VREF_1_D12

IO_L31P_1_E12

IO_L01N_1_VRP_1_C19

IO_L01P_1_VRN_1_B20

IO_L32N_1_GCLK5_B12

IO_L32P_1_GCLK4_C12

FPGAFPGA

LAYOUT NOTE PLACE NEAR FPGA

5 129-27-2005_1144

C8

F8

G9

G10

G11

A10

D9

D10

F6

A3

C7

E5

F7

D5

C5

B5

A5

E6

D6

C6

B6

E7

D7

B7

A7

E8

D8

B8

A8

F9

E9

B9

A9

F10

E10

C10

B10

F11

E11

D11

C11

B4

A4

B11

A11

C15

F15

G12

G13

G14

A12

E16

F12

F13

F16

F17

E13

F14

A19

B19

C18

D18

A18

B18

D17

E17

B17

C17

C16

D16

A16

B16

D15

E15

B15

A15

D14

E14

A14

B14

C13

D13

A13

B13

D12

E12

C19

B20

B12

C12

U1

FG456XC3S1000

1

10

11 12

13 14

15 16

17 18

19

2

20

21 22

23 24

25 26

27 28

29

3

30

31 32

33 34

35 36

37 38

4

5 6

7 8

9

39 40

41

43

45

47

49

42

44

46

48

50

25X2CON041

P4

5

1

18

20

22

26

24

16

14

12

25

23

21

19

17

15

13

11

9

3

6

10

8

4

2

7

P8

IDC13X213X2

5

1

18

20

22

26

24

16

14

12

25

23

21

19

17

15

13

11

9

3

6

10

8

4

2

7

P14

IDC13X213X2

FPGA BANKS 0 + 1

001UF0603

C50

DNP0603

R52

B1_L10N_A18_J1_81

B1_L15P_E17_J1_80

R53

0603DNP

B1_L16P_C17_J1_78

R27

06030

B1_L10P_B18_J1_82B1_L10N_A18_J1_81

B1_L15N_D17_J1_79

B1_L16N_B17_J1_77

B1_L24N_D15_J1_71

B1_L22N_A16_J1_73

B1_L19N_C16_J1_75

R51

0603DNPDNP

0603

R50DNP0603

R48

R31

0603DNP

B1_L19N_C16_J1_75

B1_L22N_A16_J1_73

B1_L24N_D15_J1_71

B1_L15N_D17_J1_79

B1_L15P_E17_J1_80

B1_L16N_B17_J1_77

B1_L16P_C17_J1_78

DNP0603

R30

VCCO_1

VCCO_1

C47

0603001UF

VCCO_1

B1_L27N_D14

PB1

AOE

B1_L01P_VRN_B20

B1_L01N_VRP_C19

IO_L32_0_GCLK6_A11

IO_L32_0_GCLK7_B11

IO_L32_0_GCLK7_B11

B1_L32N_GCLK5_B12

B1_L32P_GCLK4_C12 B1_L06P_B19_J1_86

B1_L09P_D18_J1_84

B1_L15P_E17_J1_80

B1_L16P_C17_J1_78

B1_L19P_D16_J1_76

B1_L16N_B17_J1_77

B1_L15N_D17_J1_79

B1_L09N_C18_J1_83

B1_L06N_A19_J1_85

B1_L31P_E12

B1_L31N_D12

B1_L06N_A19_J1_85

B1_L09N_C18_J1_83

B1_L09P_D18_J1_84

B1_L06P_B19_J1_86

B1_F17

B1_F16

B1_E16

B1_F13

B1_E13

B1_F12

B1_A12

B1_F14

B1_L01N_VRP_C19

B1_L01P_VRN_B20

B1_L32P_GCLK4_C12

B1_L32N_GCLK5_B12

AMS3

D5

D4

AMS0

UDEF1

ARE

ARDY

AMS1

AMS2

UDEF11

UDEF9

UDEF7

UDEF5

UDEF3

PP2

PP0

D15

D11

D9

A17

B1_L16P_C17_J1_78

B1_L19P_D16_J1_76

B1_L19N_C16_J1_75

B1_L22P_B16_J1_74

B1_L24N_D15_J1_71

B1_L22N_A16_J1_73

B1_L24P_E15_J1_72

B1_L16N_B17_J1_77

B1_L10P_B18_J1_82

B1_L15P_E17_J1_80

B1_L15N_D17_J1_79

B1_L10N_A18_J1_81

B1_L09P_D18_J1_84

B1_L09N_C18_J1_83

B1_L06P_B19_J1_86

B1_L06N_A19_J1_85

B1_L31N_D12

B1_L30N_A13

B1_L29N_C13

B1_L28N_A14

B1_L27N_D14

B1_L25N_B15

B1_F16

B1_F14

B1_F13

B1_F12

B1_L31P_E12

B1_L30P_B13

B1_L29P_D13

B1_L28P_B14

B1_L27P_E14

B1_L25P_A15

B1_F17

B1_E13

B1_E16

B1_A12

UDEF10

ABE3

ABE1

ABE0

ABE2

AWE

UDEF6

UDEF8

PP3

UDEF4

UDEF2

PP1

D14

D8

D10

D12

B1_L25P_A15B1_L25N_B15

B1_L22N_A16_J1_73

B1_L24N_D15_J1_71

B1_L19N_C16_J1_75

B1_L24P_E15_J1_72

B1_L22P_B16_J1_74

B1_L27P_E14

B1_L19P_D16_J1_76

B1_L22P_B16_J1_74

B1_L24P_E15_J1_72

B1_L25N_B15

B1_L25P_A15

B1_L27N_D14

B1_L27P_E14

B1_L28N_A14

B1_L28P_B14

B1_L29N_C13

B1_L29P_D13

B1_L30N_A13

B1_L30P_B13

B1_L10N_A18_J1_81

B1_L10P_B18_J1_82

3

2

1

3X1IDC3X1

P9

EXPANSION_PPI_CLK

B1_F16 B1_F17

B1_L28P_B14

B1_L29P_D13

B1_L30P_B13

B1_L31P_E12

B1_L28N_A14

B1_L29N_C13

B1_L30N_A13

B1_L31N_D12

B1_E16

B1_E13

B1_A12

B1_L01P_VRN_B20

B1_L32P_GCLK4_C12

B1_F14

B1_L01N_VRP_C19

B1_L32N_GCLK5_B12

B1_F13

B1_F12

B1_L01P_VRN_B20

B1_L01N_VRP_C19

001UF0603

C48 C49

0603001UF

C51

0603001UF 001UF

0603

C52 C53

0603001UF001UF

0603

C54

VCCO_1

R49

0603DNP

B1_L10P_B18_J1_82

DNP0603

R54

4

3

2

1

A B C D

20 Cotton Road

Nashua NH 03063

A B C D

4

3

2

1

PH 1-800-ANALOGD

C

Title

Size Board No

Date Sheet of

DEVICESANALOG

DNP = Do Not Populate

Rev

BLACKFIN FPGA EZ-EXTENDER

A0199-2005 10Expanison ConnectorP2

Bottom Of Board Top Of Board

Expansion Connector 2

33V_EI

6 129-14-2005_1203

EXPANSION INTERFACE CONNECTOR 2

SCK

NMI

TMR1

PF1

PF3

PF5

PF7

PF9

PF11

PF13

PF15

1

10

11 12

13 14

15 16

17 18

19 20

21 22

23 24

25 26

27 28

29

3

30

31 32

33 34

35 36

37 38

39

4

40

41 42

43 44

45 46

47 48

49

5

50

51 52

53 54

55 56

57 58

59

6

60

61 62

63 64

65 66

67 68

69

7

70

71 72

73 74

75 76

77 78

79

8

80

81 82

83 84

85 86

87 88

89

9

90

2P2

CON01845X2

1

10

1112

1314

1516

1718

19

2

20

2122

2324

2526

2728

29

3

30

3132

3334

3536

3738

39

4

40

4142

4344

4546

4748

49

5

50

5152

5354

5556

5758

59

6

60

6162

6364

6566

6768

69

7

70

7172

7374

7576

7778

79

8

80

8182

8384

8586

8788

89

9

90

J2

CON01945X2

ARE

ARDY

AMS0

AMS1

P2_21

P2_19

P2_7

P2_21

P2_71

P2_73

P2_77

P2_79

P2_83

P2_85

P2_81

P2_19

P2_15

P2_5 P2_6

P2_8

P2_22

P2_86

P2_84

P2_82

P2_80

P2_78

P2_74

P2_72

P2_20

P2_18

P2_22

P2_74

P2_78

P2_82

P2_84

P2_86

P2_80

P2_72

P2_20

P2_18

P2_8

P2_6

P2_[586]

P2_5

P2_7

P2_15

P2_85

P2_83

P2_81

P2_79

P2_77

P2_73

P2_71AWE

AOE

ABE0

ABE1

ABE2

ABE3

TSCLK0

TFS0

DT0PRI

DT0SEC

CONFIG_CLK_TSCLK1

CONFIG_INIT_B_TFS1

DT1PRI

DT1SEC

TMR0

TMR2

PF14

PF12

PF10

PF8

PF4

PF6

PF2

PF0

B2_L40N_L21_J2_9

B2_L39N_L19_J2_11

B2_C22_J2_17

B2_L38N_L17_J2_23

B2_L35N_K21_J2_25

B2_L34N_K19_J2_27

B2_L33N_K17_J2_29

B2_L32N_J21_J2_31

B2_L31N_J18_J2_33

B2_L29N_H21_J2_35

B2_L28N_H18_J2_37

B2_L27N_G21_J2_39

B2_L26N_G20_J2_41

B2_L22N_G17_J2_43

B2_L24N_F20_J2_45

B2_L23N_F19_J2_47

B2_L21N_E21_J2_49

B2_L20N_E19_J2_51

B2_L19N_E18_J2_53

B2_L17N_D21_J2_55

B2_L16N_D20_J2_57B2_L16P_D19_J2_58

B2_L17P_D22_J2_56

B2_L19P_F18_J2_54

B2_L20P_E20_J2_52

B2_L21P_E22_J2_50

B2_L23P_G19_J2_48

B2_L24P_F21_J2_46

B2_L22P_G18_J2_44

B2_L26P_H19_J2_42

B2_L27P_G22_J2_40

B2_L28P_J17_J2_38

B2_L29P_H22_J2_36

B2_L31P_J19_J2_34

B2_L32P_J22_J2_32

B2_L33P_K18_J2_30

B2_L34P_K20_J2_28

B2_L35P_K22_J2_26

B2_L38P_L18_J2_24

IO_L01P_2_VRN_2_C21_J2_16

B2_L40P_L22_J2_10

B2_L39P_L20_J2_12

MOSI

MISO

UDEF12

AMS3

AMS2

AMS0

ARDY

AMS1

AREAWE

AOE

ABE0

ABE1

ABE2

ABE3

RSCLK1

RSCLK0

RFS1

DR1PRI

DR1SEC

AMS2

AMS3

DR0SEC

DR0PRI

RFS0

TMR3

SPIDS0

C56

060301UF

80510UFC55

33V_EI

33V

4

3

2

1

A B C D

20 Cotton Road

Nashua NH 03063

A B C D

4

3

2

1

PH 1-800-ANALOGD

C

Title

Size Board No

Date Sheet of

DEVICESANALOG

DNP = Do Not Populate

Rev

BLACKFIN FPGA EZ-EXTENDER

A0199-2005 10

33V

25V33V

33V

33V

VCCO_2_H17

VCCO_2_H20

VCCO_2_J16

VCCO_2_K16

VCCO_2_L16

IO_C22

IO_L16N_2_D20

IO_L16P_2_D19

IO_L17N_2_D21

IO_L17P_2_VREF_2_D22

IO_L19N_2_E18

IO_L19P_2_F18

IO_L20N_2_E19

IO_L20P_2_E20

IO_L21N_2_E21

IO_L21P_2_E22

IO_L22N_2_G17

IO_L22P_2_G18

IO_L23N_2_VREF_2_F19

IO_L23P_2_G19

IO_L24N_2_F20

IO_L24P_2_F21

IO_L26N_2_G20

IO_L26P_2_H19

IO_L27N_2_G21

IO_L27P_2_G22

IO_L28N_2_H18

IO_L28P_2_J17

IO_L29N_2_H21

IO_L29P_2_H22

IO_L31N_2_J18

IO_L31P_2_J19

IO_L32N_2_J21

IO_L32P_2_J22

IO_L33N_2_K17

IO_L33P_2_K18

IO_L34N_2_VREF_2_K19

IO_L34P_2_K20

IO_L35N_2_K21

IO_L35P_2_K22

IO_L38N_2_L17

IO_L38P_2_L18

IO_L39N_2_L19

IO_L39P_2_L20

IO_L40N_2_L21

IO_L40P_2_VREF_2_L22

IO_L01N_2_VRP_2_C20

IO_L01P_2_VRN_2_C21

VCCO_3_M16

VCCO_3_N16

VCCO_3_P16

VCCO_3_R17

VCCO_3_R20

IO_L16N_3_W22

IO_L16P_3_Y22

IO_L17N_3_V19

IO_L17P_3_VREF_3_W19

IO_L19N_3_W21

IO_L19P_3_W20

IO_L20N_3_U19

IO_L20P_3_V20

IO_L21N_3_V22

IO_L21P_3_V21

IO_L22N_3_T17

IO_L22P_3_U18

IO_L23N_3_U21

IO_L23P_3_VREF_3_U20

IO_L24N_3_R18

IO_L24P_3_T18

IO_L26N_3_T20

IO_L26P_3_T19

IO_L27N_3_T22

IO_L27P_3_T21

IO_L28N_3_R22

IO_L28P_3_R21

IO_L29N_3_P19

IO_L29P_3_R19

IO_L31N_3_P18

IO_L31P_3_P17

IO_L32N_3_P22

IO_L32P_3_P21

IO_L33N_3_N18

IO_L33P_3_N17

IO_L34N_3_N20

IO_L34P_3_VREF_3_N19

IO_L35N_3_N22

IO_L35P_3_N21

IO_L38N_3_M18

IO_L38P_3_M17

IO_L39N_3_M20

IO_L39P_3_M19

IO_L40N_3_VREF_3_M22

IO_L40P_3_M21

IO_L01N_3_VRP_3_Y20

IO_L01P_3_VRN_3_Y19

IO_Y21

FPGAFPGA

LAYOUT NOTE PLACE NEAR FPGA

9-27-2005_1144 7 12

H17

H20

J16

K16

L16

C22

D20

D19

D21

D22

E18

F18

E19

E20

E21

E22

G17

G18

F19

G19

F20

F21

G20

H19

G21

G22

H18

J17

H21

H22

J18

J19

J21

J22

K17

K18

K19

K20

K21

K22

L17

L18

L19

L20

L21

L22

C20

C21

M16

N16

P16

R17

R20

W22

Y22

V19

W19

W21

W20

U19

V20

V22

V21

T17

U18

U21

U20

R18

T18

T20

T19

T22

T21

R22

R21

P19

R19

P18

P17

P22

P21

N18

N17

N20

N19

N22

N21

M18

M17

M20

M19

M22

M21

Y20

Y19

Y21

U1

FG456XC3S1000

2

4

8

10

6

12

14

16

24

22

20

18

26

28

3

5

7

9

11

13

15

17

19

21

23

25

27

1P5

IDC14X214X2

1

27

25

23

21

19

17

15

13

11

9

7

5

3

28

26

18

20

22

24

16

14

12

6

10

8

4

2P7

IDC14X214X2

VCCO_2

B2_L26P_H19_J2_42

DNP0603

R55B2_L24P_F21_J2_46

R56

0603DNP

B2_L23P_G19_J2_48

B2_L26N_G20_J2_41

B2_L24N_F20_J2_45

B2_L23N_F19_J2_47 B2_L23P_G19_J2_48

B2_L24P_F21_J2_46

B2_L26P_H19_J2_42

R32

0603DNP

TMR0

VCCO_2

PF221

2X1IDC2X1

JP3

CONFIG_PROG_B

1 2JP2

IDC2X12X1

PF3

CONFIG_INIT_B_TFS1

CONFIG_CLK_TSCLK1

RSCLK1

RFS1

IO_L01N_2_VRP_2_C20

IO_L01P_2_VRN_2_C21_J2_16

B2_L22N_G17_J2_43

B2_L22P_G18_J2_44

B2_L32N_J21_J2_31

SPIDS0

PF0

SCK

NMI

TMR1

DR1SEC

TMR3

DR0PRI

DR1PRI

RFS0

DR0SEC

PF15

PF13

RSCLK0

PF7

PF9

PF6

PF11

PF1

PF3

PF5

MOSI

MISO

UDEF12

TMR2

DT1SEC

DT1PRI

DT0SEC

TSCLK0

PF14

PF12

PF10

PF8

PF4

PF2

FPGA BANKS 2 + 3

DT0PRI

TFS0

B2_L40P_L22_J2_10

B2_L40N_L21_J2_9

B2_L39P_L20_J2_12

B2_L39N_L19_J2_11

B2_L38P_L18_J2_24

B2_L38N_L17_J2_23

B2_L35P_K22_J2_26

B2_L35N_K21_J2_25

B2_L34P_K20_J2_28

B2_L34N_K19_J2_27

B2_L33P_K18_J2_30

B2_L33N_K17_J2_29

B2_L32P_J22_J2_32

B2_L31P_J19_J2_34

B2_L31N_J18_J2_33

B2_L29P_H22_J2_36

B2_L29N_H21_J2_35

B2_L28P_J17_J2_38

B2_L28N_H18_J2_37

B2_L27P_G22_J2_40

B2_L27N_G21_J2_39

B2_L26P_H19_J2_42

B2_L26N_G20_J2_41

B2_L24P_F21_J2_46

B2_L24N_F20_J2_45

B2_L23P_G19_J2_48

B2_L23N_F19_J2_47

B2_L21P_E22_J2_50

B2_L21N_E21_J2_49

B2_L20P_E20_J2_52

B2_L20N_E19_J2_51

B2_L19P_F18_J2_54

B2_L19N_E18_J2_53

B2_L17P_D22_J2_56

B2_L17N_D21_J2_55

B2_L16P_D19_J2_58

B2_L16N_D20_J2_57

B2_C22_J2_17

3

2

1

3X1IDC3X1

P10

IO_L01P_2_VRN_2_C21_J2_16

IO_L01N_2_VRP_2_C20

VCCO_2

CONFIG_DONE

B2_L22N_G17_J2_43

B2_L17N_D21_J2_55

B2_L19N_E18_J2_53

B2_L20N_E19_J2_51

B2_L21N_E21_J2_49

B2_L16N_D20_J2_57

IO_L01N_2_VRP_2_C20

B2_L16P_D19_J2_58

B2_L20P_E20_J2_52

B2_L19P_F18_J2_54

B2_L17P_D22_J2_56

B2_L22P_G18_J2_44

B2_L21P_E22_J2_50

B2_C22_J2_17

IO_L01P_2_VRN_2_C21_J2_16

B2_L40N_L21_J2_9

B2_L39N_L19_J2_11

B2_L38N_L17_J2_23

B2_L35N_K21_J2_25

B2_L34N_K19_J2_27

B2_L33N_K17_J2_29

B2_L32N_J21_J2_31

B2_L31N_J18_J2_33

B2_L29N_H21_J2_35

B2_L28N_H18_J2_37

B2_L27N_G21_J2_39

B2_L40P_L22_J2_10

B2_L34P_K20_J2_28

B2_L35P_K22_J2_26

B2_L38P_L18_J2_24

B2_L39P_L20_J2_12

B2_L33P_K18_J2_30

B2_L32P_J22_J2_32

B2_L28P_J17_J2_38

B2_L31P_J19_J2_34

B2_L29P_H22_J2_36

B2_L27P_G22_J2_40

DNP0603

R33

B2_L23N_F19_J2_47

B2_L24N_F20_J2_45

B2_L26N_G20_J2_41

DNP0603

R57

001UF0603

C60 C59

0603001UF 001UF

0603

C58 C57

0603001UF

C82

0603001UF 001UF

0603

C81 C62

0603001UF001UF

0603

C61

VCCO_2

4

3

2

1

A B C D

20 Cotton Road

Nashua NH 03063

A B C D

4

3

2

1

PH 1-800-ANALOGD

C

Title

Size Board No

Date Sheet of

DEVICESANALOG

DNP = Do Not Populate

Rev

BLACKFIN FPGA EZ-EXTENDER

A0199-2005 10

Expanison ConnectorExpanison Connector

Bottom Of Board Top Of BoardExpansion Connector 3

EXPANSION INTERFACE (TYPE B)

P3P3

9-9-2005_1029 128

EXPANSION INTERFACE CONNECTOR 1

33V_EI5V_EI

1

10

11 12

13 14

15 16

17 18

19

2

20

21 22

23 24

25 26

27 28

29

3

30

31 32

33 34

35 36

37 38

39

4

40

41 42

43 44

45 46

47 48

49

5

50

51 52

53 54

55 56

57 58

59

6

60

61 62

63 64

65 66

67 68

69

7

70

71 72

73 74

75 76

77 78

79

8

80

81 82

83 84

85 86

87 88

89

9

90

P3

CON01845X2

1

10

1112

1314

1516

1718

19

2

20

2122

2324

2526

2728

29

3

30

3132

3334

3536

3738

39

4

40

4142

4344

4546

4748

49

5

50

5152

5354

5556

5758

59

6

60

6162

6364

6566

6768

69

7

70

7172

7374

7576

7778

79

8

80

8182

8384

8586

8788

89

9

90

J3

CON01945X2

TX0

TX1

UDEF17

UDEF19

UDEF21

UDEF23

UDEF25

UDEF29

UDEF27

RESET

UDEF32

UDEF34

UDEF36

UDEF38

UDEF40

B5_L01N_RDWR_B_Y4_J3_1

P3_42

P3_[190]

P3_86

P3_84

P3_82

P3_80

P3_78

P3_76

P3_74

P3_72

P3_70

P3_68

P3_64

P3_62

P3_60

P3_58

P3_56

P3_54

P3_52

P3_50

P3_48

P3_46

P3_42

P3_79

P3_89

P3_77

P3_75

P3_73

P3_71

P3_69

P3_67

P3_63

P3_61

P3_59

P3_57

P3_55

P3_53

P3_51

P3_49

P3_47

P3_45

P3_51

P3_79

P3_89

P3_77

P3_75

P3_73

P3_71

P3_69

P3_67

P3_63

P3_61

P3_59

P3_57

P3_55

P3_53

P3_49

P3_47

P3_45

P3_86

P3_84

P3_82

P3_80

P3_78

P3_76

P3_74

P3_72

P3_70

P3_68

P3_64

P3_62

P3_60

P3_58

P3_56

P3_54

P3_52

P3_50

P3_48

P3_46

B5_L27N_W9_J3_31

B5_L28N_D6_AB9_J3_33

B5_L29N_Y10_J3_35

B5_L30N_AB10_J3_37

B5_L31N_D4_W11_J3_39

B5_L10N_VRP_AB5_J3_9

B5_L25N_AB8_J3_21

B5_L24N_W8_J3_19

B5_L22N_AB7_J3_17

B5_L19N_Y7_J3_15

B5_L16N_AA6_J3_13

B5_L15N_W6_J3_11

B5_L09N_Y5_J3_7

B5_L06N_AB4_J3_5

B5_U6_J3_23

B5_V7_J3_29

B5_U9_J3_41

B5_L31P_D5_V11_J3_40

B5_L30P_AA10_J3_38

B5_L29P_W10_J3_36

B5_L28P_D7_AA9_J3_34

B5_L27P_V9_J3_32

B5_L32N_GCLK3_AA11_J3_30

B5_U7_J3_28

B5_L25P_AA8_J3_22

B5_L24P_V8_J3_20

B5_L22P_AA7_J3_18

B5_L19P_W7_J3_16

B5_L16P_Y6_J3_14

B5_L15P_V6_J3_12

B5_L10P_VRN_AA5_J3_10

B5_L09P_W5_J3_8

B5_L06P_AA4_J3_6

B5_L01P_CS_B_AA3_J3_2

B5_AB11_J3_90

B5_U11_J3_83

B5_V10_J3_85

B5_U10_J3_81

UDEF43

BGH

BG

BR

UDEF30

UDEF28

UDEF26

UDEF24

UDEF22

UDEF20

UDEF18

UDEF16

RX1

RX0

UDEF14 UDEF15

CLK_OUT_EXP1

UDEF31

UDEF33

UDEF35

UDEF37

UDEF39

UDEF41

33V_EI

C84

060301UF

80510UFC83

C8610UF805

01UF0603

C85

5V_EI

33V

33V

25V 33V

33V

33V

33V

4

3

2

1

A B C D

20 Cotton Road

Nashua NH 03063

A B C D

4

3

2

1

PH 1-800-ANALOGD

C

Title

Size Board No

Date Sheet of

DEVICESANALOG

DNP = Do Not Populate

Rev

BLACKFIN FPGA EZ-EXTENDER

A0199-2005 10

VCCO_4_T12

VCCO_4_T13

VCCO_4_T14

VCCO_4_U15

VCCO_4_Y15

IO_U16

IO_U17

IO_W13

IO_W14

IO_VREF_4_V18

IO_VREF_4_Y16

IO_VREF_4_AB13

IO_L05N_4_AA19

IO_L05P_4_AB19

IO_L06N_4_VREF_4_W18

IO_L06P_4_Y18

IO_L09N_4_AA18

IO_L09P_4_AB18

IO_L10N_4_V17

IO_L10P_4_W17

IO_L15N_4_Y17

IO_L15P_4_AA17

IO_L16N_4_V16

IO_L16P_4_W16

IO_L19N_4_AA16

IO_L19P_4_AB16

IO_L22N_4_VREF_4_V15

IO_L22P_4_W15

IO_L24N_4_AA15

IO_L24P_4_AB15

IO_L25N_4_U14

IO_L25P_4_V14

IO_L27N_4_DIN_D0_AA14

IO_L27P_4_D1_AB14

IO_L28N_4_U13

IO_L28P_4_V13

IO_L29N_4_Y13

IO_L29P_4_AA13

IO_L30N_4_D2_U12

IO_L30P_4_D3_V12

IO_L31N_4_INIT_B_W12

IO_L31P_4_DOUT_BUSY_Y12

IO_L01N_4_VRP_4_AA20

IO_L01P_4_VRN_4_AB20

IO_L32N_4_GCLK1_AA12

IO_L32P_4_GCLK0_AB12

VCCO_5_T9

VCCO_5_T10

VCCO_5_T11

VCCO_5_U8

VCCO_5_Y8

IO_U7

IO_U9

IO_U10

IO_U11

IO_V7

IO_V10

IO_VREF_5_U6

IO_VREF_5_AB11

IO_L01N_5_RDWR_B_Y4

IO_L01P_5_CS_B_AA3

IO_L06N_5_AB4

IO_L06P_5_AA4

IO_L09N_5_Y5

IO_L09P_5_W5

IO_L15N_5_W6

IO_L15P_5_V6

IO_L16N_5_AA6

IO_L16P_5_Y6

IO_L19N_5_Y7

IO_L19P_5_VREF_5_W7

IO_L22N_5_AB7

IO_L22P_5_AA7

IO_L24N_5_W8

IO_L24P_5_V8

IO_L25N_5_AB8

IO_L25P_5_AA8

IO_L27N_5_VREF_5_W9

IO_L27P_5_V9

IO_L28N_5_D6_AB9

IO_L28P_5_D7_AA9

IO_L29N_5_Y10

IO_L29P_5_VREF_5_W10

IO_L30N_5_AB10

IO_L30P_5_AA10

IO_L31N_5_D4_W11

IO_L31P_5_D5_V11

IO_L32N_5_GCLK3_AA11

IO_L32P_5_GCLK2_Y11

IO_L10N_5_VRP_5_AB5

IO_L10P_5_VRN_5_AA5

FPGAFPGA

1299-27-2005_1144

T12

T13

T14

U15

Y15

U16

U17

W13

W14

V18

Y16

AB13

AA19

AB19

W18

Y18

AA18

AB18

V17

W17

Y17

AA17

V16

W16

AA16

AB16

V15

W15

AA15

AB15

U14

V14

AA14

AB14

U13

V13

Y13

AA13

U12

V12

W12

Y12

AA20

AB20

AA12

AB12

T9

T10

T11

U8

Y8

U7

U9

U10

U11

V7

V10

U6

AB11

Y4

AA3

AB4

AA4

Y5

W5

W6

V6

AA6

Y6

Y7

W7

AB7

AA7

W8

V8

AB8

AA8

W9

V9

AB9

AA9

Y10

W10

AB10

AA10

W11

V11

AA11

Y11

AB5

AA5

U1

FG456XC3S1000

7

2

4

8

10

6

3

9

11

13

15

17

19

21

23

25

12

14

16

24

26

22

20

18

1

5

P16

IDC13X213X2

5

1

18

20

22

26

24

16

14

12

25

23

21

19

17

15

13

11

9

3

6

10

8

4

2

7

P17

IDC13X213X2

R46

060310K

R43

0603DNP

FPGA BANKS 4 + 5

VCCO_5

CONFIG_INIT_B_TFS1

CLK_OUT_EXP1

B4_L32N_GCKL1_AA12

R9

06030

B5_L10N_VRP_AB5_J3_9

B5_L10N_VRP_AB5_J3_9

B5_L10P_VRN_AA5_J3_10

VCCO_5

B5_L32P_GCLK2_Y1

B5_L32N_GCLK3_AA11_J3_30

CONFIG_DIN_DT1PRI

UDEF16

UDEF38

UDEF14

RX0

TX0

RX1

TX1

UDEF20

UDEF21

UDEF23

UDEF17

UDEF25

UDEF24

UDEF22

RESET

UDEF30

UDEF29

UDEF27

UDEF26

UDEF35

UDEF34

UDEF33

UDEF32

UDEF31

UDEF15

UDEF28

UDEF41

UDEF40

UDEF39

UDEF37

UDEF36

BR

UDEF43

BG

BGH

UDEF19

B5_L31P_D5_V11_J3_40

B5_L31N_D4_W11_J3_39

B5_L30P_AA10_J3_38

B5_L30N_AB10_J3_37

B5_L29P_W10_J3_36

B5_L29N_Y10_J3_35

B5_L28P_D7_AA9_J3_34

B5_L28N_D6_AB9_J3_33

B5_L27P_V9_J3_32

B5_L27N_W9_J3_31

B5_L25P_AA8_J3_22

B5_L25N_AB8_J3_21

B5_L24P_V8_J3_20

B5_L24N_W8_J3_19

B5_L22P_AA7_J3_18

B5_L22N_AB7_J3_17

B5_L19P_W7_J3_16

B5_L19N_Y7_J3_15

B5_L16P_Y6_J3_14

B5_L16N_AA6_J3_13

B5_L15P_V6_J3_12

B5_L15N_W6_J3_11

B5_L09P_W5_J3_8

B5_L09N_Y5_J3_7

B5_L06P_AA4_J3_6

B5_L06N_AB4_J3_5

B5_L01P_CS_B_AA3_J3_2

B5_L01N_RDWR_B_Y4_J3_1

B5_AB11_J3_90

B5_U6_J3_23

B5_V10_J3_85

B5_V7_J3_29

B5_U11_J3_83

B5_U10_J3_81

B5_U9_J3_41

B5_U7_J3_28

UDEF18

3

2

1

3X1IDC3X1

P11

B5_L29N_Y10_J3_35

B5_L30N_AB10_J3_37

B5_L31N_D4_W11_J3_39

B5_U11_J3_83

B5_V10_J3_85B5_AB11_J3_90

B5_U10_J3_81

B5_L31P_D5_V11_J3_40

B5_L30P_AA10_J3_38

B5_L29P_W10_J3_36

B5_L28P_D7_AA9_J3_34

B5_L27P_V9_J3_32

B5_L28N_D6_AB9_J3_33

B5_L27N_W9_J3_31

B5_L25N_AB8_J3_21B5_L25P_AA8_J3_22

B5_L24N_W8_J3_19B5_L24P_V8_J3_20

B5_U9_J3_41B5_U6_J3_23

VCCO_5

B5_L10P_VRN_AA5_J3_10

C70

0603001UF 001UF

0603

C69 C68

0603001UF001UF

0603

C67001UF0603

C66 C65

0603001UF 001UF

0603

C64C63

0603001UF

B5_L09N_Y5_J3_7

B5_U7_J3_28 B5_V7_J3_29

B5_L10P_VRN_AA5_J3_10 B5_L10N_VRP_AB5_J3_9

B5_L15P_V6_J3_12 B5_L15N_W6_J3_11

B5_L16P_Y6_J3_14 B5_L16N_AA6_J3_13

B5_L19P_W7_J3_16 B5_L19N_Y7_J3_15

B5_L22P_AA7_J3_18 B5_L22N_AB7_J3_17

B5_L32N_GCLK3_AA11_J3_30 B5_L32P_GCLK2_Y1

B5_L01P_CS_B_AA3_J3_2 B5_L01N_RDWR_B_Y4_J3_1

B5_L06P_AA4_J3_6 B5_L06N_AB4_J3_5

B5_L09P_W5_J3_8

VCCO_5

DNP0603

R45

25V

33V

33V

4

3

2

1

A B C D

20 Cotton Road

Nashua NH 03063

A B C D

4

3

2

1

PH 1-800-ANALOGD

C

Title

Size Board No

Date Sheet of

DEVICESANALOG

DNP = Do Not Populate

Rev

BLACKFIN FPGA EZ-EXTENDER

A0199-2005 10

SN74LVC1G125

12109-27-2005_1144

2 4

1

SOT23-5SN74LVC1G125

U8

USER IO

C80

0603001UF

SW4SWT013SPST-MOMENTARY

SPST-MOMENTARYSWT013SW3

060310R42

C5

06031UF

R413300603

LED001AMBER-SMTLED8

0603330R40

LED7AMBER-SMTLED001

R393300603

R1033006030603

330R34R35

33006030603

330R36

0603330R37 R38

3300603

LED001AMBER-SMTLED2

AMBER-SMTLED001

LED3AMBER-SMTLED001

LED4AMBER-SMTLED001

LED5

LED001AMBER-SMTLED6

LED9GREEN-SMTLED001

402100R23

1 2

3 4

5 6

7 8

JP5

IDC4X24X2

AMBER-SMTLED001

LED1

B6_L01N_Y3

B6_L01P_Y2

B5_U10_J3_81

B5_AB11_J3_90

PB2

B5_V10_J3_85

B5_U11_J3_83

B5_L31N_D4_W11_J3_39

B5_L30N_AB10_J3_37

B5_L29N_Y10_J3_35

B5_L28N_D6_AB9_J3_33

B5_L27N_W9_J3_31

PB1

B5_L25N_AB8_J3_21

R47

060310K

CHOKE_COIL

4

3

2

1

A B C D

20 Cotton Road

Nashua NH 03063

A B C D

4

3

2

1

PH 1-800-ANALOGD

C

Title

Size Board No

Date Sheet of

DEVICESANALOG

DNP = Do Not Populate

Rev

BLACKFIN FPGA EZ-EXTENDER

A0199-2005 10

25V

33V

VIN

EN

SW

GND

FB

VIN

EN

SW

GND

FB

VIN

EN

SW

GND

FB

4

3

5

2

1

VR3

SOT23-5LM3475MF

1

2

5

3

4

VR2

SOT23-5LM3475MF

4

3

5

2

1

VR1

SOT23-5LM3475MF

12119-27-2005_1124

1

32

Q2

SI2

343D

SS

OT

23D

1

32

Q3

SI2

343D

SS

OT

23D

2 3

1S

I234

3DS

Q1

SO

T23

D

316KR17

0603

215KR18

0603

0603

R11105K

DNPC73

0603

0603

C72DNP

805

C741000PF

0R58

0603

1000PFC10

805

0603

R1910K

C100UFCT2

CT3100UFC

IND005

L110UH

10UHL3

IND005

10UHL2

IND005

1

2 D3

DO214ABSCHOT_RECT

3A

0603

R20200K

805

C639NF

390PFC7

0603

2

1 3A

SCHOT_RECTDO214AB

D2

499KR13

0603

1

2 D1

DO214ABSCHOT_RECT

3A

33V_EI

3

1

2

3X1IDC3X1

P13

UNREG_IN

12V

CT1100UFC

80510UFC71

R1200603

5V_EI

8051000PFC2

FER2

0603

060301UFC3

POWER

FUS00125AF1

4

1

3

2

FER1

DO-214AA

S2A_RECT

2AD5

8051000PFC1 C4

10UFC

3

1

2

3X1IDC3X1

P12

UNREG_IN

1

2

3

CON00525MM_JACK

POWER

J4

2

1P42

IDC2X12X1DNP

1

2

DNP2X1IDC2X1

P43

06030R15

C810UF805

80510UFC9

R1600603

UNREG_IN

0603

R1410K

0603

R590

4

3

2

1

A B C D

20 Cotton Road

Nashua NH 03063

A B C D

4

3

2

1

PH 1-800-ANALOGD

C

Title

Size Board No

Date Sheet of

DEVICESANALOG

DNP = Do Not Populate

Rev

BLACKFIN FPGA EZ-EXTENDER

A0199-2005 1012129-14-2005_1204

5

2

4

8

10

6

1

3

9

11

13

15

17

19

12

14

16

20

18

7

P20

SOIC20

PROTO AREA

1

3

2

SOT23D

P39

2

3

1

SOT23D

P38

2

4

5 6

3

1

SOT23-6

P411

3

65

4

2

SOT23-6

P40

PRT_NUM=DNE

11

13

15 16

14

12

2

4

6

8

109

7

5

3

1

SOIC16

P191

3

5

7

9 10

8

6

4

2

12

14

1615

13

11

SOIC16

P18

21P37

805

1 2

805

P36

21P35

805

1 2

805

P34

1 2

805

P33

21P32

805

1 2

805

P31

21P30

805

1 2

805

P29

21P28

805

1 2

805

P27

21P26

805

21P25

805

1 2

805

P24

21P23

805

1 2

805

P22

TP86

TP85

TP84

TP83

TP82

TP81

TP80

TP79 TP77

TP76

TP75

TP74

TP73

TP72

TP71

TP70

TP68

TP67

TP66

TP65

TP64

TP62

TP61

TP60

TP59

TP58

TP57

TP56

TP55

TP54

TP53

TP51

TP50

TP49

TP48

TP47

TP46

TP45

TP44

TP43

TP41

TP40

TP39

TP38

TP37

TP36

TP35

TP34

TP33

TP32

TP30

TP29

TP28

TP27

TP26

TP25

TP24

TP23

TP22

TP21

TP19

TP18

TP17

TP16

TP15

TP14

TP13

TP12

TP11

TP9

TP8

TP7

TP6

TP5

TP4

TP125

TP124

TP123

TP122

TP121

TP120

TP119

TP118

TP117

TP116

TP114

TP113

TP112

TP111

TP110

TP109

TP108

TP107TP106

TP105TP103

TP102TP101 TP100TP99

TP98 TP97

TP96 TP95

TP94TP93

TP92TP91

TP90 TP89

TP88 TP87

TP78TP69

TP63 TP52

TP42 TP31

TP20 TP10

TP115TP104

7

18

20

16

14

12

19

17

15

13

11

9

3

1

6

10

8

4

2

5

SOIC20

P21

I INDEX

Numerics connectors

25V header (P42) 2-17

AADSP-BF5333761 EZ-KIT Lite interface 2-1ADSP-BF5333761 processors boot mode

settings 2-14architecture of this EZ-Extender 2-2asynchronous static random access memory

(SRAM) xauxiliary oscillator x

Bbill of materials A-1block diagram of this EZ-Extender 2-2boot jumper See JP4

Cconfiguration jumpers See JP2 JP3

map of locations 2-18J1-3 (expansion) 2-19P1-3 (expansion) 2-19P14 (IDC) 2-19P15 (JTAG header) 2-4P16-17 (IDC) 2-19P4 (high-speed) 2-20P5 (IDC) 2-20P6 (JTAG) 2-7P7 (IDC) 2-20P8 (IDC) 2-19

customer support xiii

Ddone LED (LED10) 2-17

Eexpansion interface

connectors (P1-3 J1-3) 2-19of ADSP-BF5333761 EZ-KIT Lites ix

1-3external power supply 1-3 2-8

FField-Programmable Gate Array See FPGA

Blackfin FPGA EZ-Extender Manual I-1

INDEX

FPGAdocumentation 1-2input jumpers (JP5) 2-14softwarefirmware 1-2Xilinx Spartan package x 1-3

FPGA pinsAB10 (LED3) 2-17AB11 (JP58) 2-15AB8 (LED7) 2-17AB9 (LED5) 2-17C11 (PB1SW3) 2-15H5 (PB2SW3) 2-16M2-0 (JP4) 2-14U10 (JP56) 2-15U11 (LED1) 2-17V10 (LED8) 2-17W11 (LED2) 2-17W9 (LED6) 2-17Y10 (LED4) 2-17Y3-2 (JP52-54) 2-15

FPGA programmingblock diagram 2-3via ADSP-BF533376 processors 2-6via JTAG header 2-4via serial ROM 2-5

GGCLK1 (global clock 1) pin 1-4GCLK6 (global clock 6) pin 1-4general-purpose input push buttons 2-15 2-16

Hhigh-speed connector (P4) 2-20

IIDC connectors x 2-19 2-20installation of this EZ-Extender 1-1

JJTAG

cable 1-4 2-7header (P6) 1-5 2-4 2-7 2-14

jumpersmap of locations 2-11JP1 (boot jumper) 2-5 2-12JP2 (confug done) 2-12JP3 (config program) 2-13JP41-46 (boot mode select) 2-5 2-6 2-14JP52-56 (FPGA input) 2-14

LLEDs

map of locations 2-15LED10 (FPGA done pin) 2-4 2-5 2-17LED1-8 (status) 2-17LED9 (power) 2-17

MM2-0 (JP4) pins 2-5master serial boot mode 2-6MCS-86 Hexadecimal Object (mcs) file

format 2-6

Nnotation conventions xvi

Ooscillator x 1-4

PP12 (power in) header 2-9P13 (33V header) 2-9P42 (25V header) 2-10P43 (12V header) 2-10PB1 push button (SW3) 2-15

I-2 Blackfin FPGA EZ-Extender Manual

INDEX

PB2 push button (SW4) 2-16PF14 flag pin (ADSP-BF537 EZ-KIT Lite)

2-12PF3 flag pin (ADSP-BF53361 EZ-KIT Lite)

2-12power

12V header (P43) 2-1025V header (P42) 2-1033V header (P13) 2-9in header (P12) 2-9LED (LED9) 2-17limitations 2-8supplies 1-3 2-8

printed circuit board (PCB) 1-2product overview ixprogram push button (SW1) 2-4 2-15push buttons

See also SWx map of locations 2-15

Sserial ROM 1-5

boot jumper (JP1) 2-12 2-14programming via JTAG Header 2-7

setup of this EZ-Extender 1-1slave serial mode 2-6

SRAM memory banks 1-4status reporting 1-4 2-17SW1 (program) push button 2-4 2-15SW3 (PB1) push button 2-15SW4 (PB2) push button 2-16switching regulators 2-8

TTCK signal 2-7TDI signal 2-7TDO signal 2-7TMS signal 2-7

VVisualDSP++

flash programming utility 1-4 2-6FPGA documentation 2-6

VR1-3 regulators 2-8

XXilinx

JTAG cablesoftware 1-4 2-4 2-7JTAG header 2-12serial ROM 1-5

Blackfin FPGA EZ-Extender Manual I-3

INDEX

I-4 Blackfin FPGA EZ-Extender Manual

• Blackfin FPGA EZ-Extender Manual
• Contents
• Preface
• • Product Overview
  • Purpose of This Manual
  • Intended Audience
  • Manual Contents
  • Whatrsquos New in This Manual
  • Technical or Customer Support
  • Supported Products
  • Product Information
  • • Related Documents
    • • Table 1 Related Processor Publications
      • Table 2 Related VisualDSP++ Publications
      • • Notation Conventions
        • • 1 FPGA EZ-Extender Interfaces
          • • FPGA EZ-Extender Setup
            • • Figure 1-1 FPGA EZ-Extender Setup
              • • FPGA Software and Firmware
                • FPGA EZ-Extender Overview
                • • 2 FPGA EZ-Extender Hardware Reference
                  • • System Architecture
                    • • Figure 2-1 Block Diagram
                      • • Programming the FPGA
                        • • Figure 2-2 FPGA Programming Block Diagram
                          • FPGA Programming via JTAG
                          • • Table 2-1 P15 Connections for PFGA Programming via JTAG
                            • Table 2-2 JP1 Settings for FPGA Programming via JTAG
                            • Table 2-3 JP4 Settings for FPGA Programming via JTAG
                            • • FPGA Programming via Serial ROM
                              • • Table 2-4 JP1 Settings for FPGA Programming via Serial ROM
                                • Table 2-5 JP4 Settings for FPGA Programming in Master Serial Mode
                                • • FPGA Programming via Blackfin Application
                                  • • Table 2-6 JP1 Settings for FPGA Programming via Blackfin Processor
                                    • Table 2-7 JP4 Settings for FPGA Programming via Blackfin Processor
                                    • • Programming the Serial ROM
                                      • • Serial ROM via JTAG Header
                                        • • Table 2-8 P6 Connections for Serial ROM
                                          • • Power
                                            • • Table 2-9 Power Limitations
                                              • Power In Header (P12)
                                              • 33V Header (P13)
                                              • 25V Header (P42)
                                              • 12V Header (P43)
                                              • • Jumpers
                                                • • Figure 2-3 Jumper Locations
                                                  • Serial ROM Boot Jumper (JP1)
                                                  • • Table 2-10 JP1 Settings
                                                    • • Config Done Jumper (JP2)
                                                      • • Table 2-11 JP2 Settings
                                                        • • Config Program Jumper (JP3)
                                                          • • Table 2-12 JP3 Settings
                                                            • • Boot Jumper (JP4)
                                                              • • Table 2-13 JP4 Settings
                                                                • • FPGA Input Jumpers (JP5)
                                                                  • • Table 2-14 JP5 Settings
                                                                    • • Push Buttons and LEDs
                                                                      • • Figure 2-4 Push Button and LED Locations
                                                                        • Program Push Button (SW1)
                                                                        • PB1 Push Button (SW3)
                                                                        • PB2 Push Button (SW4)
                                                                        • Status LEDs (LED1-8)
                                                                        • • Table 2-15 Status LED (LED1-8) Settings
                                                                          • • Power LED (LED9)
                                                                            • Done LED (LED10)
                                                                            • • Connectors
                                                                              • • Figure 2-5 Connector Locations
                                                                                • Expansion Interface (P1-3 and J1-3)
                                                                                • IDC Connectors (P8 P14 P16 and P17)
                                                                                • IDC Connectors (P5 and P7)
                                                                                • High-Speed Connector (P4)
                                                                                • • A Bill Of Materials
                                                                                  • B Schematics
                                                                                  • • Title
                                                                                    • FPGA Config
                                                                                    • SRAM FPGA Banks 7 and 8
                                                                                    • Expansion Interface Connector 1
                                                                                    • FPGA Banks 0 and 1
                                                                                    • Expansion Interface Connectors 2
                                                                                    • FPGA Banks 2 and 3
                                                                                    • Expansion Interface Connector 1
                                                                                    • FPGA Banks 4 and 5
                                                                                    • User IO
                                                                                    • Power
                                                                                    • Proto Area
                                                                                    • • I Index
                                                                                      • • Numerics
                                                                                        • A
                                                                                        • B
                                                                                        • C
                                                                                        • D
                                                                                        • E
                                                                                        • F
                                                                                        • G
                                                                                        • H
                                                                                        • I
                                                                                        • J
                                                                                        • L
                                                                                        • M
                                                                                        • N
                                                                                        • O
                                                                                        • P
                                                                                        • S
                                                                                        • T
                                                                                        • V
                                                                                        • X

33V

4

3

2

1

A B C D

20 Cotton Road

Nashua NH 03063

A B C D

4

3

2

1

PH 1-800-ANALOGD

C

Title

Size Board No

Date Sheet of

DEVICESANALOG

DNP = Do Not Populate

Rev

BLACKFIN FPGA EZ-EXTENDER

A0199-2005 10

33V

1A

1B

1Y

2A

2B

2Y

3A

3B

3Y

4A

4B

4Y

~AB

EN

25V

33V

33V

33V

33V

33V

25V

33V

OENC OUTOE OUT

CLK

D0

TMS

TCK

TDI

TDO

VCCINT

VCCO

VCCJ

NC1

NC2

NC3

NC4

NC5

NC6

GND

CE

CF

OE~RESET

CEO

VCCAUX_A6

VCCAUX_A17

VCCAUX_F1

VCCAUX_F22

VCCAUX_U1

VCCAUX_U22

VCCAUX_AB6

VCCAUX_AB17

VCCINT_G7

VCCINT_G8

VCCINT_G15

VCCINT_G16

VCCINT_H7

VCCINT_H16

VCCINT_R7

VCCINT_R16

VCCINT_T7

VCCINT_T8

VCCINT_T15

VCCINT_T16

TCK

TDI

TDO

TMS

M0

M1

M2

CCLK

PROG_B

DONE

HSWAP_EN

GND_A1

GND_A22

GND_B2

GND_B21

GND_C9

GND_C14

GND_J3

GND_J9

GND_J10

GND_J11

GND_J12

GND_J13

GND_J14

GND_J20

GND_K9

GND_K10

GND_K11

GND_K12

GND_K13

GND_K14

GND_L9

GND_L10

GND_L11

GND_L12

GND_L13

GND_L14

GND_M9

GND_M10

GND_M11

GND_M12

GND_M13

GND_M14

GND_N9

GND_N10

GND_N11

GND_N12

GND_N13

GND_N14

GND_P3

GND_P9

GND_P10

GND_P11

GND_P12

GND_P13

GND_P14

GND_P20

GND_Y9

GND_Y14

GND_AA2

GND_AA21

GND_AB1

GND_AB22

FPGAFPGA

EXTRA CLOCK SOCKET25MHZ SYSTEM CLOCK

FPGA JTAG HEADER

FLASH JTAG HEADER

BOOTMODE JUMPER

FPGA BOOT FLASH(2Mbit)

MUXFLASHSKTOSC

9-27-2005_1144 2 12

A6

A17

F1

F22

U1

U22

AB6

AB17

G7

G8

G15

G16

H7

H16

R7

R16

T7

T8

T15

T16

A21

B1

B22

A20

AB2

AA1

AB3

AA22

A2

AB21

B3

A1

A22

B2

B21

C9

C14

J3

J9

J10

J11

J12

J13

J14

J20

K9

K10

K11

K12

K13

K14

L9

L10

L11

L12

L13

L14

M9

M10

M11

M12

M13

M14

N9

N10

N11

N12

N13

N14

P3

P9

P10

P11

P12

P13

P14

P20

Y9

Y14

AA2

AA21

AB1

AB22

U1

FG456XC3S1000

CONFIG_PROG_B

6

5

4

3

2

1P6

IDC6X16X1

1

2

3

4

5

6

P15

IDC6X16X1

3

1

8

10

7

13

5

6

4

17

18

19

20

2

9

12

14

15

16

11

U4

TSSOP20XCF04S

2

4

5 6

3

1JP4

IDC3X23X2

402100R5

R400603

402100R44

R8100402

R7100402

1 3

U6

25MHZOSC003

80510UFC14

R29

060310K

R22

060310K

R21

060310K

R1

060310K

1 5

U7

DIPDIP8SOC

R263306030603

33R2

R25

DNP

10K0603

12V

1 2JP1

IDC2X12X1

CONFIG_DONER3

06030

CONFIG_CLK_TSCLK1

FPGA_TMS

FPGA_TDO

FPGA_TCK

FPGA_TDI

FPGA_TCK

FPGA_TDO

FPGA_TDI

FPGA_TMS

FLASH_TMS

FLASH_TDI

FLASH_TDO

FLASH_TCK

M1

M2

M0

12V

SPST-MOMENTARYSWT013SW1

2

3

4

5

6

7

11

10

9

14

13

12

1

15

U2

TSSOP1674LVC157

CONFIG_DONE

FLASH_TMS

FLASH_TCK

FLASH_TDI

FLASH_TDO

M2

M0

M1

FPGA CONFIG

CONFIG_INIT_B_TFS1

FLASH_DOUT

CONFIG_CLK_TSCLK1

FLASH_DONE

001UF0603

C18

IO_L32_0_GCLK6_A11B4_L32N_GCKL1_AA12

C19

0603001UF 001UF

0603

C20 C21

0603001UF 001UF

0603

C25C24

0603001UF001UF

0603

C23C22

0603001UF 001UF

0603

C31 C30

0603001UF 001UF

0603

C29 C28

0603001UF001UF

0603

C27C26

0603001UF

001UF0603

C32 C11

0603001UF 001UF

0603

C12 C13

0603001UF

80510UFC15 C16

10UF805

C17

0603001UF

0603330R24

LED10

LED001AMBER-SMT

CONFIG_DIN_DT1PRI

FLASH_DONE

FLASH_DOUT

DT1PRI

R6

060310K10K

0603

R28

33V 33V

4

3

2

1

A B C D

20 Cotton Road

Nashua NH 03063

A B C D

4

3

2

1

PH 1-800-ANALOGD

C

Title

Size Board No

Date Sheet of

DEVICESANALOG

DNP = Do Not Populate

Rev

BLACKFIN FPGA EZ-EXTENDER

A0199-2005 10

33V

33V

A18

A1

A10

A11

A12

A13

A14

A16

A2

A3

A4

A5

A6

A7

A8

A9

D0

D1

D10

D11

D2

D3

D4

D5

D6

D7

D8

D9

BHE

BLE

CE

OE

WE

A17

D15

D14

D13

D12

A0

A15

A18

A1

A10

A11

A12

A13

A14

A16

A2

A3

A4

A5

A6

A7

A8

A9

D0

D1

D10

D11

D2

D3

D4

D5

D6

D7

D8

D9

BHE

BLE

CE

OE

WE

A17

D15

D14

D13

D12

A0

A15

VCCO_6_M7

VCCO_6_N7

VCCO_6_P7

VCCO_6_R3

VCCO_6_R6

IO_Y1

IO_L16N_6_W4

IO_L16P_6_W3

IO_L17N_6_W2

IO_L17P_6_VREF_6_W1

IO_L19N_6_V5

IO_L19P_6_U5

IO_L20N_6_V4

IO_L20P_6_V3

IO_L21N_6_V2

IO_L21P_6_V1

IO_L22N_6_T6

IO_L22P_6_T5

IO_L23N_6_U4

IO_L23P_6_T4

IO_L24N_6_VREF_6_U3

IO_L24P_6_U2

IO_L26N_6_T3

IO_L26P_6_R4

IO_L27N_6_T2

IO_L27P_6_T1

IO_L28N_6_R5

IO_L28P_6_P6

IO_L29N_6_R2

IO_L29P_6_R1

IO_L31N_6_P5

IO_L31P_6_P4

IO_L32N_6_P2

IO_L32P_6_P1

IO_L33N_6_N6

IO_L33P_6_N5

IO_L34N_6_VREF_6_N4

IO_L34P_6_N3

IO_L35N_6_N2

IO_L35P_6_N1

IO_L38N_6_M6

IO_L38P_6_M5

IO_L39N_6_M4

IO_L39P_6_M3

IO_L40N_6_M2

IO_L40P_6_VREF_6_M1

IO_L01N_6_VRP_6_Y3

IO_L01P_6_VRN_6_Y2

VCCO_7_H3

VCCO_7_H6

VCCO_7_J7

VCCO_7_K7

VCCO_7_L7

IO_C2

IO_L16N_7_D1

IO_L16P_7_VREF_7_C1

IO_L17N_7_E4

IO_L17P_7_D4

IO_L19N_7_VREF_7_D3

IO_L19P_7_D2

IO_L20N_7_F4

IO_L20P_7_E3

IO_L21N_7_E1

IO_L21P_7_E2

IO_L22N_7_G6

IO_L22P_7_F5

IO_L23N_7_F2

IO_L23P_7_F3

IO_L24N_7_H5

IO_L24P_7_G5

IO_L26N_7_G3

IO_L26P_7_G4

IO_L27N_7_G1

IO_L27P_7_VREF_7_G2

IO_L28N_7_H1

IO_L28P_7_H2

IO_L29N_7_J4

IO_L29P_7_H4

IO_L31N_7_J5

IO_L31P_7_J6

IO_L32N_7_J1

IO_L32P_7_J2

IO_L33N_7_K5

IO_L33P_7_K6

IO_L34N_7_K3

IO_L34P_7_K4

IO_L35N_7_K1

IO_L35P_7_K2

IO_L38N_7_L5

IO_L38P_7_L6

IO_L39N_7_L3

IO_L39P_7_L4

IO_L40N_7_VREF_7_L1

IO_L40P_7_L2

IO_L01N_7_VRP_7_C3

IO_L01P_7_VRN_7_C4

(512k x 16bits x 2chips)2MBYTES FPGA SRAM

FPGASRAM SRAM

SRAM_A9

9-27-2005_1144 3 12

FLASH_TDO

FLASH_TMS

FLASH_TDI

FLASH_TCK

M7

N7

P7

R3

R6

Y1

W4

W3

W2

W1

V5

U5

V4

V3

V2

V1

T6

T5

U4

T4

U3

U2

T3

R4

T2

T1

R5

P6

R2

R1

P5

P4

P2

P1

N6

N5

N4

N3

N2

N1

M6

M5

M4

M3

M2

M1

Y3

Y2

H3

H6

J7

K7

L7

C2

D1

C1

E4

D4

D3

D2

F4

E3

E1

E2

G6

F5

F2

F3

H5

G5

G3

G4

G1

G2

H1

H2

J4

H4

J5

J6

J1

J2

K5

K6

K3

K4

K1

K2

L5

L6

L3

L4

L1

L2

C3

C4

U1

FG456XC3S1000

28

2

23

24

25

26

27

43

3

4

5

18

19

20

21

22

7

8

31

32

9

10

13

14

15

16

29

30

40

39

6

41

17

44

38

37

36

35

1

42

U3

TSOP44IS61LV51216

42

1

35

36

37

38

44

17

41

6

39

40

30

29

16

15

14

13

10

9

32

31

8

7

22

21

20

19

18

5

4

3

43

27

26

25

24

23

2

28

U5

TSOP44IS61LV51216

SRAM_D7

SRAM_D6

SRAM_D3

SRAM_D2

SRAM_D0

SRAM_D8

SRAM_D9

SRAM_D5

SRAM_D4

SRAM_D13

SRAM_D1

SRAM_D10

SRAM_D11

SRAM_D12

SRAM_D14

SRAM_D15

SRAM_CE

SRAM_A7

SRAM_A0

SRAM_A5

SRAM_A3

SRAM_A1

SRAM_WE

SRAM_A8

SRAM_A6

SRAM_A4

SRAM_A2

SRAM_A17

SRAM_OE

SRAM_A12

SRAM_A13

SRAM_A15

SRAM_A16

SRAM_A14

SRAM_A18

SRAM_A11

SRAM_A10

SRAM_D22

SRAM_D20

SRAM_D18

SRAM_D17

SRAM_D16

SRAM_D26

SRAM_D21

SRAM_D24

SRAM_D19

SRAM_D31

SRAM_D25

SRAM_D27

SRAM_D28

SRAM_D30

SRAM_D29

PB2

A11

A5

D1

A15

A3

A9

D13

D7

A13

A19

A7

A1

A18

A6

A2

A12

D6

A8

A14

D2

D0

A10

A4

D3

A16

SRAM FPGA BANKS 7 + 8

SRAM_CE

SRAM_WE

SRAM_OE

SRAM_A18

SRAM_A0 SRAM_D0

SRAM_D1

SRAM_D2

SRAM_D3

SRAM_D4

SRAM_D5

SRAM_D6

SRAM_D7

SRAM_D8

SRAM_D9

SRAM_D10

SRAM_D11

SRAM_D12

SRAM_D13

SRAM_D14

SRAM_D15

SRAM_D16

SRAM_D17

SRAM_D18

SRAM_D19

SRAM_D20

SRAM_D21

SRAM_D22

SRAM_D23

SRAM_D24

SRAM_D25

SRAM_D26

SRAM_D27

SRAM_D28

SRAM_D29

SRAM_D30

SRAM_D31

SRAM_A1

SRAM_A2

SRAM_A3

SRAM_A4

SRAM_A5

SRAM_A6

SRAM_A7

SRAM_A8

SRAM_A9

SRAM_A10

SRAM_A11

SRAM_A12

SRAM_A13

SRAM_A14

SRAM_A15

SRAM_A16

SRAM_A17

SRAM_A1

SRAM_A2

SRAM_A3

SRAM_A4

SRAM_A5

SRAM_A6

SRAM_A7

SRAM_A8

SRAM_A9

SRAM_A10

SRAM_A11

SRAM_A12

SRAM_A13

SRAM_A14

SRAM_A15

SRAM_A16

SRAM_A17

SRAM_A18

SRAM_A0

SRAM_OE

SRAM_WE

SRAM_CE

C33

0603001UF

C34

0603001UF001UF

0603

C37001UF0603

C36

C42

0603001UF 001UF

0603

C41 C40

0603001UF001UF

0603

C39001UF0603

C46 C45

0603001UF 001UF

0603

C44C43

0603001UF

B6_L01P_Y2

B6_L01N_Y3

SRAM_D23

4

3

2

1

A B C D

20 Cotton Road

Nashua NH 03063

A B C D

4

3

2

1

PH 1-800-ANALOGD

C

Title

Size Board No

Date Sheet of

DEVICESANALOG

DNP = Do Not Populate

Rev

BLACKFIN FPGA EZ-EXTENDER

A0199-2005 10

EXPANSION INTERFACE TYPE B

P1Expanison Connector

Top Of BoardBottom Of Board

Expansion Connector 1

10-18-2005_1616 4 12

EXPANSION INTERFACE CONNECTOR 1

C3510UF805

01UF0603

C38

5V_EI

5V_EI

1

10

11 12

13 14

15 16

17 18

19

2

20

21 22

23 24

25 26

27 28

29

3

30

31 32

33 34

35 36

37 38

39

4

40

41 42

43 44

45 46

47 48

49

5

50

51 52

53 54

55 56

57 58

59

6

60

61 62

63 64

65 66

67 68

69

7

70

71 72

73 74

75 76

77 78

79

8

80

81 82

83 84

85 86

87 88

89

9

90

P1

CON01845X2

1

10

1112

1314

1516

1718

19

2

20

2122

2324

2526

2728

29

3

30

3132

3334

3536

3738

39

4

40

4142

4344

4546

4748

49

5

50

5152

5354

5556

5758

59

6

60

6162

6364

6566

6768

69

7

70

7172

7374

7576

7778

79

8

80

8182

8384

8586

8788

89

9

90

J1

CON01945X2

PP1

EXPANSION_PPI_CLK

PP3

UDEF2

UDEF4

UDEF6

UDEF8

UDEF10

D9

D7

D15

D13

D11

D5

D1

D3

D15

D9

D5

D1

D3

D0

D2

D4

D6

D8

D10

D14

D12

P1_5

P1_25

P1_27

P1_29

P1_31

P1_33

P1_55

P1_57

P1_59

P1_61

P1_63

P1_65

P1_67

P1_69

P1_35

P1_26

P1_28

P1_30

P1_32

P1_34

P1_56

P1_58

P1_60

P1_62

P1_64

P1_66

P1_68

P1_70

P1_36

P1_26

P1_28

P1_30

P1_32

P1_34

P1_36

P1_56

P1_58

P1_60

P1_62

P1_64

P1_66

P1_68

P1_70

P1_5

P1_25

P1_27

P1_29

P1_31

P1_33

P1_35

P1_55

P1_57

P1_59

P1_61

P1_63

P1_65

P1_67

P1_69

P1_[586]

A5

A6A7

A8A9

A10A11

A12A13

A14A15

A16A17

A18A19

D0

D2

D4

D6D7

D8

D10D11

D12D13

D14

A1

A2

B1_L24N_D15_J1_71B1_L24P_E15_J1_72

B1_L22N_A16_J1_73B1_L22P_B16_J1_74

B1_L19N_C16_J1_75B1_L19P_D16_J1_76

B1_L16N_B17_J1_77B1_L16P_C17_J1_78

B1_L15N_D17_J1_79

A3

B1_L15P_E17_J1_80

B1_L10N_A18_J1_81B1_L10P_B18_J1_82

B1_L09N_C18_J1_83B1_L09P_D18_J1_84

B1_L06N_A19_J1_85B1_L06P_B19_J1_86

A4A5

A6 A7

A8 A9

A10 A11

A12 A13

A14 A15

A16 A17

A18 A19

A1

A2

PP0

PP2

UDEF1

UDEF3

A3

UDEF5

UDEF7

UDEF9

UDEF11

A4

33V

25V 33V

33V

33V

33V

4

3

2

1

A B C D

20 Cotton Road

Nashua NH 03063

A B C D

4

3

2

1

PH 1-800-ANALOGD

C

Title

Size Board No

Date Sheet of

DEVICESANALOG

DNP = Do Not Populate

Rev

BLACKFIN FPGA EZ-EXTENDER

A0199-2005 10

VCCO_0_C8

VCCO_0_F8

VCCO_0_G9

VCCO_0_G10

VCCO_0_G11

IO_A10

IO_D9

IO_D10

IO_F6

IO_VREF_0_A3

IO_VREF_0_C7

IO_VREF_0_E5

IO_VREF_0_F7

IO_L06N_0_D5

IO_L06P_0_C5

IO_L09N_0_B5

IO_L09P_0_A5

IO_L10N_0_E6

IO_L10P_0_D6

IO_L15N_0_C6

IO_L15P_0_B6

IO_L16N_0_E7

IO_L16P_0_D7

IO_L19N_0_B7

IO_L19P_0_A7

IO_L22N_0_E8

IO_L22P_0_D8

IO_L24N_0_B8

IO_L24P_0_A8

IO_L25N_0_F9

IO_L25P_0_E9

IO_L27N_0_B9

IO_L27P_0_A9

IO_L28N_0_F10

IO_L28P_0_E10

IO_L29N_0_C10

IO_L29P_0_B10

IO_L30N_0_F11

IO_L30P_0_E11

IO_L31N_0_D11

IO_L31P_0_VREF_0_C11

IO_L01N_0_VRP_0_B4

IO_L01P_0_VRN_0_A4

IO_L32N_0_GCLK7_B11

IO_L32P_0_GCLK6_A11

VCCO_1_C15

VCCO_1_F15

VCCO_1_G12

VCCO_1_G13

VCCO_1_G14

IO_A12

IO_E16

IO_F12

IO_F13

IO_F16

IO_F17

IO_VREF_1_E13

IO_VREF_1_F14

IO_L06N_1_VREF_1_A19

IO_L06P_1_B19

IO_L09N_1_C18

IO_L09P_1_D18

IO_L10N_1_VREF_1_A18

IO_L10P_1_B18

IO_L15N_1_D17

IO_L15P_1_E17

IO_L16N_1_B17

IO_L16P_1_C17

IO_L19N_1_C16

IO_L19P_1_D16

IO_L22N_1_A16

IO_L22P_1_B16

IO_L24N_1_D15

IO_L24P_1_E15

IO_L25N_1_B15

IO_L25P_1_A15

IO_L27N_1_D14

IO_L27P_1_E14

IO_L28N_1_A14

IO_L28P_1_B14

IO_L29N_1_C13

IO_L29P_1_D13

IO_L30N_1_A13

IO_L30P_1_B13

IO_L31N_1_VREF_1_D12

IO_L31P_1_E12

IO_L01N_1_VRP_1_C19

IO_L01P_1_VRN_1_B20

IO_L32N_1_GCLK5_B12

IO_L32P_1_GCLK4_C12

FPGAFPGA

LAYOUT NOTE PLACE NEAR FPGA

5 129-27-2005_1144

C8

F8

G9

G10

G11

A10

D9

D10

F6

A3

C7

E5

F7

D5

C5

B5

A5

E6

D6

C6

B6

E7

D7

B7

A7

E8

D8

B8

A8

F9

E9

B9

A9

F10

E10

C10

B10

F11

E11

D11

C11

B4

A4

B11

A11

C15

F15

G12

G13

G14

A12

E16

F12

F13

F16

F17

E13

F14

A19

B19

C18

D18

A18

B18

D17

E17

B17

C17

C16

D16

A16

B16

D15

E15

B15

A15

D14

E14

A14

B14

C13

D13

A13

B13

D12

E12

C19

B20

B12

C12

U1

FG456XC3S1000

1

10

11 12

13 14

15 16

17 18

19

2

20

21 22

23 24

25 26

27 28

29

3

30

31 32

33 34

35 36

37 38

4

5 6

7 8

9

39 40

41

43

45

47

49

42

44

46

48

50

25X2CON041

P4

5

1

18

20

22

26

24

16

14

12

25

23

21

19

17

15

13

11

9

3

6

10

8

4

2

7

P8

IDC13X213X2

5

1

18

20

22

26

24

16

14

12

25

23

21

19

17

15

13

11

9

3

6

10

8

4

2

7

P14

IDC13X213X2

FPGA BANKS 0 + 1

001UF0603

C50

DNP0603

R52

B1_L10N_A18_J1_81

B1_L15P_E17_J1_80

R53

0603DNP

B1_L16P_C17_J1_78

R27

06030

B1_L10P_B18_J1_82B1_L10N_A18_J1_81

B1_L15N_D17_J1_79

B1_L16N_B17_J1_77

B1_L24N_D15_J1_71

B1_L22N_A16_J1_73

B1_L19N_C16_J1_75

R51

0603DNPDNP

0603

R50DNP0603

R48

R31

0603DNP

B1_L19N_C16_J1_75

B1_L22N_A16_J1_73

B1_L24N_D15_J1_71

B1_L15N_D17_J1_79

B1_L15P_E17_J1_80

B1_L16N_B17_J1_77

B1_L16P_C17_J1_78

DNP0603

R30

VCCO_1

VCCO_1

C47

0603001UF

VCCO_1

B1_L27N_D14

PB1

AOE

B1_L01P_VRN_B20

B1_L01N_VRP_C19

IO_L32_0_GCLK6_A11

IO_L32_0_GCLK7_B11

IO_L32_0_GCLK7_B11

B1_L32N_GCLK5_B12

B1_L32P_GCLK4_C12 B1_L06P_B19_J1_86

B1_L09P_D18_J1_84

B1_L15P_E17_J1_80

B1_L16P_C17_J1_78

B1_L19P_D16_J1_76

B1_L16N_B17_J1_77

B1_L15N_D17_J1_79

B1_L09N_C18_J1_83

B1_L06N_A19_J1_85

B1_L31P_E12

B1_L31N_D12

B1_L06N_A19_J1_85

B1_L09N_C18_J1_83

B1_L09P_D18_J1_84

B1_L06P_B19_J1_86

B1_F17

B1_F16

B1_E16

B1_F13

B1_E13

B1_F12

B1_A12

B1_F14

B1_L01N_VRP_C19

B1_L01P_VRN_B20

B1_L32P_GCLK4_C12

B1_L32N_GCLK5_B12

AMS3

D5

D4

AMS0

UDEF1

ARE

ARDY

AMS1

AMS2

UDEF11

UDEF9

UDEF7

UDEF5

UDEF3

PP2

PP0

D15

D11

D9

A17

B1_L16P_C17_J1_78

B1_L19P_D16_J1_76

B1_L19N_C16_J1_75

B1_L22P_B16_J1_74

B1_L24N_D15_J1_71

B1_L22N_A16_J1_73

B1_L24P_E15_J1_72

B1_L16N_B17_J1_77

B1_L10P_B18_J1_82

B1_L15P_E17_J1_80

B1_L15N_D17_J1_79

B1_L10N_A18_J1_81

B1_L09P_D18_J1_84

B1_L09N_C18_J1_83

B1_L06P_B19_J1_86

B1_L06N_A19_J1_85

B1_L31N_D12

B1_L30N_A13

B1_L29N_C13

B1_L28N_A14

B1_L27N_D14

B1_L25N_B15

B1_F16

B1_F14

B1_F13

B1_F12

B1_L31P_E12

B1_L30P_B13

B1_L29P_D13

B1_L28P_B14

B1_L27P_E14

B1_L25P_A15

B1_F17

B1_E13

B1_E16

B1_A12

UDEF10

ABE3

ABE1

ABE0

ABE2

AWE

UDEF6

UDEF8

PP3

UDEF4

UDEF2

PP1

D14

D8

D10

D12

B1_L25P_A15B1_L25N_B15

B1_L22N_A16_J1_73

B1_L24N_D15_J1_71

B1_L19N_C16_J1_75

B1_L24P_E15_J1_72

B1_L22P_B16_J1_74

B1_L27P_E14

B1_L19P_D16_J1_76

B1_L22P_B16_J1_74

B1_L24P_E15_J1_72

B1_L25N_B15

B1_L25P_A15

B1_L27N_D14

B1_L27P_E14

B1_L28N_A14

B1_L28P_B14

B1_L29N_C13

B1_L29P_D13

B1_L30N_A13

B1_L30P_B13

B1_L10N_A18_J1_81

B1_L10P_B18_J1_82

3

2

1

3X1IDC3X1

P9

EXPANSION_PPI_CLK

B1_F16 B1_F17

B1_L28P_B14

B1_L29P_D13

B1_L30P_B13

B1_L31P_E12

B1_L28N_A14

B1_L29N_C13

B1_L30N_A13

B1_L31N_D12

B1_E16

B1_E13

B1_A12

B1_L01P_VRN_B20

B1_L32P_GCLK4_C12

B1_F14

B1_L01N_VRP_C19

B1_L32N_GCLK5_B12

B1_F13

B1_F12

B1_L01P_VRN_B20

B1_L01N_VRP_C19

001UF0603

C48 C49

0603001UF

C51

0603001UF 001UF

0603

C52 C53

0603001UF001UF

0603

C54

VCCO_1

R49

0603DNP

B1_L10P_B18_J1_82

DNP0603

R54

4

3

2

1

A B C D

20 Cotton Road

Nashua NH 03063

A B C D

4

3

2

1

PH 1-800-ANALOGD

C

Title

Size Board No

Date Sheet of

DEVICESANALOG

DNP = Do Not Populate

Rev

BLACKFIN FPGA EZ-EXTENDER

A0199-2005 10Expanison ConnectorP2

Bottom Of Board Top Of Board

Expansion Connector 2

33V_EI

6 129-14-2005_1203

EXPANSION INTERFACE CONNECTOR 2

SCK

NMI

TMR1

PF1

PF3

PF5

PF7

PF9

PF11

PF13

PF15

1

10

11 12

13 14

15 16

17 18

19 20

21 22

23 24

25 26

27 28

29

3

30

31 32

33 34

35 36

37 38

39

4

40

41 42

43 44

45 46

47 48

49

5

50

51 52

53 54

55 56

57 58

59

6

60

61 62

63 64

65 66

67 68

69

7

70

71 72

73 74

75 76

77 78

79

8

80

81 82

83 84

85 86

87 88

89

9

90

2P2

CON01845X2

1

10

1112

1314

1516

1718

19

2

20

2122

2324

2526

2728

29

3

30

3132

3334

3536

3738

39

4

40

4142

4344

4546

4748

49

5

50

5152

5354

5556

5758

59

6

60

6162

6364

6566

6768

69

7

70

7172

7374

7576

7778

79

8

80

8182

8384

8586

8788

89

9

90

J2

CON01945X2

ARE

ARDY

AMS0

AMS1

P2_21

P2_19

P2_7

P2_21

P2_71

P2_73

P2_77

P2_79

P2_83

P2_85

P2_81

P2_19

P2_15

P2_5 P2_6

P2_8

P2_22

P2_86

P2_84

P2_82

P2_80

P2_78

P2_74

P2_72

P2_20

P2_18

P2_22

P2_74

P2_78

P2_82

P2_84

P2_86

P2_80

P2_72

P2_20

P2_18

P2_8

P2_6

P2_[586]

P2_5

P2_7

P2_15

P2_85

P2_83

P2_81

P2_79

P2_77

P2_73

P2_71AWE

AOE

ABE0

ABE1

ABE2

ABE3

TSCLK0

TFS0

DT0PRI

DT0SEC

CONFIG_CLK_TSCLK1

CONFIG_INIT_B_TFS1

DT1PRI

DT1SEC

TMR0

TMR2

PF14

PF12

PF10

PF8

PF4

PF6

PF2

PF0

B2_L40N_L21_J2_9

B2_L39N_L19_J2_11

B2_C22_J2_17

B2_L38N_L17_J2_23

B2_L35N_K21_J2_25

B2_L34N_K19_J2_27

B2_L33N_K17_J2_29

B2_L32N_J21_J2_31

B2_L31N_J18_J2_33

B2_L29N_H21_J2_35

B2_L28N_H18_J2_37

B2_L27N_G21_J2_39

B2_L26N_G20_J2_41

B2_L22N_G17_J2_43

B2_L24N_F20_J2_45

B2_L23N_F19_J2_47

B2_L21N_E21_J2_49

B2_L20N_E19_J2_51

B2_L19N_E18_J2_53

B2_L17N_D21_J2_55

B2_L16N_D20_J2_57B2_L16P_D19_J2_58

B2_L17P_D22_J2_56

B2_L19P_F18_J2_54

B2_L20P_E20_J2_52

B2_L21P_E22_J2_50

B2_L23P_G19_J2_48

B2_L24P_F21_J2_46

B2_L22P_G18_J2_44

B2_L26P_H19_J2_42

B2_L27P_G22_J2_40

B2_L28P_J17_J2_38

B2_L29P_H22_J2_36

B2_L31P_J19_J2_34

B2_L32P_J22_J2_32

B2_L33P_K18_J2_30

B2_L34P_K20_J2_28

B2_L35P_K22_J2_26

B2_L38P_L18_J2_24

IO_L01P_2_VRN_2_C21_J2_16

B2_L40P_L22_J2_10

B2_L39P_L20_J2_12

MOSI

MISO

UDEF12

AMS3

AMS2

AMS0

ARDY

AMS1

AREAWE

AOE

ABE0

ABE1

ABE2

ABE3

RSCLK1

RSCLK0

RFS1

DR1PRI

DR1SEC

AMS2

AMS3

DR0SEC

DR0PRI

RFS0

TMR3

SPIDS0

C56

060301UF

80510UFC55

33V_EI

33V

4

3

2

1

A B C D

20 Cotton Road

Nashua NH 03063

A B C D

4

3

2

1

PH 1-800-ANALOGD

C

Title

Size Board No

Date Sheet of

DEVICESANALOG

DNP = Do Not Populate

Rev

BLACKFIN FPGA EZ-EXTENDER

A0199-2005 10

33V

25V33V

33V

33V

VCCO_2_H17

VCCO_2_H20

VCCO_2_J16

VCCO_2_K16

VCCO_2_L16

IO_C22

IO_L16N_2_D20

IO_L16P_2_D19

IO_L17N_2_D21

IO_L17P_2_VREF_2_D22

IO_L19N_2_E18

IO_L19P_2_F18

IO_L20N_2_E19

IO_L20P_2_E20

IO_L21N_2_E21

IO_L21P_2_E22

IO_L22N_2_G17

IO_L22P_2_G18

IO_L23N_2_VREF_2_F19

IO_L23P_2_G19

IO_L24N_2_F20

IO_L24P_2_F21

IO_L26N_2_G20

IO_L26P_2_H19

IO_L27N_2_G21

IO_L27P_2_G22

IO_L28N_2_H18

IO_L28P_2_J17

IO_L29N_2_H21

IO_L29P_2_H22

IO_L31N_2_J18

IO_L31P_2_J19

IO_L32N_2_J21

IO_L32P_2_J22

IO_L33N_2_K17

IO_L33P_2_K18

IO_L34N_2_VREF_2_K19

IO_L34P_2_K20

IO_L35N_2_K21

IO_L35P_2_K22

IO_L38N_2_L17

IO_L38P_2_L18

IO_L39N_2_L19

IO_L39P_2_L20

IO_L40N_2_L21

IO_L40P_2_VREF_2_L22

IO_L01N_2_VRP_2_C20

IO_L01P_2_VRN_2_C21

VCCO_3_M16

VCCO_3_N16

VCCO_3_P16

VCCO_3_R17

VCCO_3_R20

IO_L16N_3_W22

IO_L16P_3_Y22

IO_L17N_3_V19

IO_L17P_3_VREF_3_W19

IO_L19N_3_W21

IO_L19P_3_W20

IO_L20N_3_U19

IO_L20P_3_V20

IO_L21N_3_V22

IO_L21P_3_V21

IO_L22N_3_T17

IO_L22P_3_U18

IO_L23N_3_U21

IO_L23P_3_VREF_3_U20

IO_L24N_3_R18

IO_L24P_3_T18

IO_L26N_3_T20

IO_L26P_3_T19

IO_L27N_3_T22

IO_L27P_3_T21

IO_L28N_3_R22

IO_L28P_3_R21

IO_L29N_3_P19

IO_L29P_3_R19

IO_L31N_3_P18

IO_L31P_3_P17

IO_L32N_3_P22

IO_L32P_3_P21

IO_L33N_3_N18

IO_L33P_3_N17

IO_L34N_3_N20

IO_L34P_3_VREF_3_N19

IO_L35N_3_N22

IO_L35P_3_N21

IO_L38N_3_M18

IO_L38P_3_M17

IO_L39N_3_M20

IO_L39P_3_M19

IO_L40N_3_VREF_3_M22

IO_L40P_3_M21

IO_L01N_3_VRP_3_Y20

IO_L01P_3_VRN_3_Y19

IO_Y21

FPGAFPGA

LAYOUT NOTE PLACE NEAR FPGA

9-27-2005_1144 7 12

H17

H20

J16

K16

L16

C22

D20

D19

D21

D22

E18

F18

E19

E20

E21

E22

G17

G18

F19

G19

F20

F21

G20

H19

G21

G22

H18

J17

H21

H22

J18

J19

J21

J22

K17

K18

K19

K20

K21

K22

L17

L18

L19

L20

L21

L22

C20

C21

M16

N16

P16

R17

R20

W22

Y22

V19

W19

W21

W20

U19

V20

V22

V21

T17

U18

U21

U20

R18

T18

T20

T19

T22

T21

R22

R21

P19

R19

P18

P17

P22

P21

N18

N17

N20

N19

N22

N21

M18

M17

M20

M19

M22

M21

Y20

Y19

Y21

U1

FG456XC3S1000

2

4

8

10

6

12

14

16

24

22

20

18

26

28

3

5

7

9

11

13

15

17

19

21

23

25

27

1P5

IDC14X214X2

1

27

25

23

21

19

17

15

13

11

9

7

5

3

28

26

18

20

22

24

16

14

12

6

10

8

4

2P7

IDC14X214X2

VCCO_2

B2_L26P_H19_J2_42

DNP0603

R55B2_L24P_F21_J2_46

R56

0603DNP

B2_L23P_G19_J2_48

B2_L26N_G20_J2_41

B2_L24N_F20_J2_45

B2_L23N_F19_J2_47 B2_L23P_G19_J2_48

B2_L24P_F21_J2_46

B2_L26P_H19_J2_42

R32

0603DNP

TMR0

VCCO_2

PF221

2X1IDC2X1

JP3

CONFIG_PROG_B

1 2JP2

IDC2X12X1

PF3

CONFIG_INIT_B_TFS1

CONFIG_CLK_TSCLK1

RSCLK1

RFS1

IO_L01N_2_VRP_2_C20

IO_L01P_2_VRN_2_C21_J2_16

B2_L22N_G17_J2_43

B2_L22P_G18_J2_44

B2_L32N_J21_J2_31

SPIDS0

PF0

SCK

NMI

TMR1

DR1SEC

TMR3

DR0PRI

DR1PRI

RFS0

DR0SEC

PF15

PF13

RSCLK0

PF7

PF9

PF6

PF11

PF1

PF3

PF5

MOSI

MISO

UDEF12

TMR2

DT1SEC

DT1PRI

DT0SEC

TSCLK0

PF14

PF12

PF10

PF8

PF4

PF2

FPGA BANKS 2 + 3

DT0PRI

TFS0

B2_L40P_L22_J2_10

B2_L40N_L21_J2_9

B2_L39P_L20_J2_12

B2_L39N_L19_J2_11

B2_L38P_L18_J2_24

B2_L38N_L17_J2_23

B2_L35P_K22_J2_26

B2_L35N_K21_J2_25

B2_L34P_K20_J2_28

B2_L34N_K19_J2_27

B2_L33P_K18_J2_30

B2_L33N_K17_J2_29

B2_L32P_J22_J2_32

B2_L31P_J19_J2_34

B2_L31N_J18_J2_33

B2_L29P_H22_J2_36

B2_L29N_H21_J2_35

B2_L28P_J17_J2_38

B2_L28N_H18_J2_37

B2_L27P_G22_J2_40

B2_L27N_G21_J2_39

B2_L26P_H19_J2_42

B2_L26N_G20_J2_41

B2_L24P_F21_J2_46

B2_L24N_F20_J2_45

B2_L23P_G19_J2_48

B2_L23N_F19_J2_47

B2_L21P_E22_J2_50

B2_L21N_E21_J2_49

B2_L20P_E20_J2_52

B2_L20N_E19_J2_51

B2_L19P_F18_J2_54

B2_L19N_E18_J2_53

B2_L17P_D22_J2_56

B2_L17N_D21_J2_55

B2_L16P_D19_J2_58

B2_L16N_D20_J2_57

B2_C22_J2_17

3

2

1

3X1IDC3X1

P10

IO_L01P_2_VRN_2_C21_J2_16

IO_L01N_2_VRP_2_C20

VCCO_2

CONFIG_DONE

B2_L22N_G17_J2_43

B2_L17N_D21_J2_55

B2_L19N_E18_J2_53

B2_L20N_E19_J2_51

B2_L21N_E21_J2_49

B2_L16N_D20_J2_57

IO_L01N_2_VRP_2_C20

B2_L16P_D19_J2_58

B2_L20P_E20_J2_52

B2_L19P_F18_J2_54

B2_L17P_D22_J2_56

B2_L22P_G18_J2_44

B2_L21P_E22_J2_50

B2_C22_J2_17

IO_L01P_2_VRN_2_C21_J2_16

B2_L40N_L21_J2_9

B2_L39N_L19_J2_11

B2_L38N_L17_J2_23

B2_L35N_K21_J2_25

B2_L34N_K19_J2_27

B2_L33N_K17_J2_29

B2_L32N_J21_J2_31

B2_L31N_J18_J2_33

B2_L29N_H21_J2_35

B2_L28N_H18_J2_37

B2_L27N_G21_J2_39

B2_L40P_L22_J2_10

B2_L34P_K20_J2_28

B2_L35P_K22_J2_26

B2_L38P_L18_J2_24

B2_L39P_L20_J2_12

B2_L33P_K18_J2_30

B2_L32P_J22_J2_32

B2_L28P_J17_J2_38

B2_L31P_J19_J2_34

B2_L29P_H22_J2_36

B2_L27P_G22_J2_40

DNP0603

R33

B2_L23N_F19_J2_47

B2_L24N_F20_J2_45

B2_L26N_G20_J2_41

DNP0603

R57

001UF0603

C60 C59

0603001UF 001UF

0603

C58 C57

0603001UF

C82

0603001UF 001UF

0603

C81 C62

0603001UF001UF

0603

C61

VCCO_2

4

3

2

1

A B C D

20 Cotton Road

Nashua NH 03063

A B C D

4

3

2

1

PH 1-800-ANALOGD

C

Title

Size Board No

Date Sheet of

DEVICESANALOG

DNP = Do Not Populate

Rev

BLACKFIN FPGA EZ-EXTENDER

A0199-2005 10

Expanison ConnectorExpanison Connector

Bottom Of Board Top Of BoardExpansion Connector 3

EXPANSION INTERFACE (TYPE B)

P3P3

9-9-2005_1029 128

EXPANSION INTERFACE CONNECTOR 1

33V_EI5V_EI

1

10

11 12

13 14

15 16

17 18

19

2

20

21 22

23 24

25 26

27 28

29

3

30

31 32

33 34

35 36

37 38

39

4

40

41 42

43 44

45 46

47 48

49

5

50

51 52

53 54

55 56

57 58

59

6

60

61 62

63 64

65 66

67 68

69

7

70

71 72

73 74

75 76

77 78

79

8

80

81 82

83 84

85 86

87 88

89

9

90

P3

CON01845X2

1

10

1112

1314

1516

1718

19

2

20

2122

2324

2526

2728

29

3

30

3132

3334

3536

3738

39

4

40

4142

4344

4546

4748

49

5

50

5152

5354

5556

5758

59

6

60

6162

6364

6566

6768

69

7

70

7172

7374

7576

7778

79

8

80

8182

8384

8586

8788

89

9

90

J3

CON01945X2

TX0

TX1

UDEF17

UDEF19

UDEF21

UDEF23

UDEF25

UDEF29

UDEF27

RESET

UDEF32

UDEF34

UDEF36

UDEF38

UDEF40

B5_L01N_RDWR_B_Y4_J3_1

P3_42

P3_[190]

P3_86

P3_84

P3_82

P3_80

P3_78

P3_76

P3_74

P3_72

P3_70

P3_68

P3_64

P3_62

P3_60

P3_58

P3_56

P3_54

P3_52

P3_50

P3_48

P3_46

P3_42

P3_79

P3_89

P3_77

P3_75

P3_73

P3_71

P3_69

P3_67

P3_63

P3_61

P3_59

P3_57

P3_55

P3_53

P3_51

P3_49

P3_47

P3_45

P3_51

P3_79

P3_89

P3_77

P3_75

P3_73

P3_71

P3_69

P3_67

P3_63

P3_61

P3_59

P3_57

P3_55

P3_53

P3_49

P3_47

P3_45

P3_86

P3_84

P3_82

P3_80

P3_78

P3_76

P3_74

P3_72

P3_70

P3_68

P3_64

P3_62

P3_60

P3_58

P3_56

P3_54

P3_52

P3_50

P3_48

P3_46

B5_L27N_W9_J3_31

B5_L28N_D6_AB9_J3_33

B5_L29N_Y10_J3_35

B5_L30N_AB10_J3_37

B5_L31N_D4_W11_J3_39

B5_L10N_VRP_AB5_J3_9

B5_L25N_AB8_J3_21

B5_L24N_W8_J3_19

B5_L22N_AB7_J3_17

B5_L19N_Y7_J3_15

B5_L16N_AA6_J3_13

B5_L15N_W6_J3_11

B5_L09N_Y5_J3_7

B5_L06N_AB4_J3_5

B5_U6_J3_23

B5_V7_J3_29

B5_U9_J3_41

B5_L31P_D5_V11_J3_40

B5_L30P_AA10_J3_38

B5_L29P_W10_J3_36

B5_L28P_D7_AA9_J3_34

B5_L27P_V9_J3_32

B5_L32N_GCLK3_AA11_J3_30

B5_U7_J3_28

B5_L25P_AA8_J3_22

B5_L24P_V8_J3_20

B5_L22P_AA7_J3_18

B5_L19P_W7_J3_16

B5_L16P_Y6_J3_14

B5_L15P_V6_J3_12

B5_L10P_VRN_AA5_J3_10

B5_L09P_W5_J3_8

B5_L06P_AA4_J3_6

B5_L01P_CS_B_AA3_J3_2

B5_AB11_J3_90

B5_U11_J3_83

B5_V10_J3_85

B5_U10_J3_81

UDEF43

BGH

BG

BR

UDEF30

UDEF28

UDEF26

UDEF24

UDEF22

UDEF20

UDEF18

UDEF16

RX1

RX0

UDEF14 UDEF15

CLK_OUT_EXP1

UDEF31

UDEF33

UDEF35

UDEF37

UDEF39

UDEF41

33V_EI

C84

060301UF

80510UFC83

C8610UF805

01UF0603

C85

5V_EI

33V

33V

25V 33V

33V

33V

33V

4

3

2

1

A B C D

20 Cotton Road

Nashua NH 03063

A B C D

4

3

2

1

PH 1-800-ANALOGD

C

Title

Size Board No

Date Sheet of

DEVICESANALOG

DNP = Do Not Populate

Rev

BLACKFIN FPGA EZ-EXTENDER

A0199-2005 10

VCCO_4_T12

VCCO_4_T13

VCCO_4_T14

VCCO_4_U15

VCCO_4_Y15

IO_U16

IO_U17

IO_W13

IO_W14

IO_VREF_4_V18

IO_VREF_4_Y16

IO_VREF_4_AB13

IO_L05N_4_AA19

IO_L05P_4_AB19

IO_L06N_4_VREF_4_W18

IO_L06P_4_Y18

IO_L09N_4_AA18

IO_L09P_4_AB18

IO_L10N_4_V17

IO_L10P_4_W17

IO_L15N_4_Y17

IO_L15P_4_AA17

IO_L16N_4_V16

IO_L16P_4_W16

IO_L19N_4_AA16

IO_L19P_4_AB16

IO_L22N_4_VREF_4_V15

IO_L22P_4_W15

IO_L24N_4_AA15

IO_L24P_4_AB15

IO_L25N_4_U14

IO_L25P_4_V14

IO_L27N_4_DIN_D0_AA14

IO_L27P_4_D1_AB14

IO_L28N_4_U13

IO_L28P_4_V13

IO_L29N_4_Y13

IO_L29P_4_AA13

IO_L30N_4_D2_U12

IO_L30P_4_D3_V12

IO_L31N_4_INIT_B_W12

IO_L31P_4_DOUT_BUSY_Y12

IO_L01N_4_VRP_4_AA20

IO_L01P_4_VRN_4_AB20

IO_L32N_4_GCLK1_AA12

IO_L32P_4_GCLK0_AB12

VCCO_5_T9

VCCO_5_T10

VCCO_5_T11

VCCO_5_U8

VCCO_5_Y8

IO_U7

IO_U9

IO_U10

IO_U11

IO_V7

IO_V10

IO_VREF_5_U6

IO_VREF_5_AB11

IO_L01N_5_RDWR_B_Y4

IO_L01P_5_CS_B_AA3

IO_L06N_5_AB4

IO_L06P_5_AA4

IO_L09N_5_Y5

IO_L09P_5_W5

IO_L15N_5_W6

IO_L15P_5_V6

IO_L16N_5_AA6

IO_L16P_5_Y6

IO_L19N_5_Y7

IO_L19P_5_VREF_5_W7

IO_L22N_5_AB7

IO_L22P_5_AA7

IO_L24N_5_W8

IO_L24P_5_V8

IO_L25N_5_AB8

IO_L25P_5_AA8

IO_L27N_5_VREF_5_W9

IO_L27P_5_V9

IO_L28N_5_D6_AB9

IO_L28P_5_D7_AA9

IO_L29N_5_Y10

IO_L29P_5_VREF_5_W10

IO_L30N_5_AB10

IO_L30P_5_AA10

IO_L31N_5_D4_W11

IO_L31P_5_D5_V11

IO_L32N_5_GCLK3_AA11

IO_L32P_5_GCLK2_Y11

IO_L10N_5_VRP_5_AB5

IO_L10P_5_VRN_5_AA5

FPGAFPGA

1299-27-2005_1144

T12

T13

T14

U15

Y15

U16

U17

W13

W14

V18

Y16

AB13

AA19

AB19

W18

Y18

AA18

AB18

V17

W17

Y17

AA17

V16

W16

AA16

AB16

V15

W15

AA15

AB15

U14

V14

AA14

AB14

U13

V13

Y13

AA13

U12

V12

W12

Y12

AA20

AB20

AA12

AB12

T9

T10

T11

U8

Y8

U7

U9

U10

U11

V7

V10

U6

AB11

Y4

AA3

AB4

AA4

Y5

W5

W6

V6

AA6

Y6

Y7

W7

AB7

AA7

W8

V8

AB8

AA8

W9

V9

AB9

AA9

Y10

W10

AB10

AA10

W11

V11

AA11

Y11

AB5

AA5

U1

FG456XC3S1000

7

2

4

8

10

6

3

9

11

13

15

17

19

21

23

25

12

14

16

24

26

22

20

18

1

5

P16

IDC13X213X2

5

1

18

20

22

26

24

16

14

12

25

23

21

19

17

15

13

11

9

3

6

10

8

4

2

7

P17

IDC13X213X2

R46

060310K

R43

0603DNP

FPGA BANKS 4 + 5

VCCO_5

CONFIG_INIT_B_TFS1

CLK_OUT_EXP1

B4_L32N_GCKL1_AA12

R9

06030

B5_L10N_VRP_AB5_J3_9

B5_L10N_VRP_AB5_J3_9

B5_L10P_VRN_AA5_J3_10

VCCO_5

B5_L32P_GCLK2_Y1

B5_L32N_GCLK3_AA11_J3_30

CONFIG_DIN_DT1PRI

UDEF16

UDEF38

UDEF14

RX0

TX0

RX1

TX1

UDEF20

UDEF21

UDEF23

UDEF17

UDEF25

UDEF24

UDEF22

RESET

UDEF30

UDEF29

UDEF27

UDEF26

UDEF35

UDEF34

UDEF33

UDEF32

UDEF31

UDEF15

UDEF28

UDEF41

UDEF40

UDEF39

UDEF37

UDEF36

BR

UDEF43

BG

BGH

UDEF19

B5_L31P_D5_V11_J3_40

B5_L31N_D4_W11_J3_39

B5_L30P_AA10_J3_38

B5_L30N_AB10_J3_37

B5_L29P_W10_J3_36

B5_L29N_Y10_J3_35

B5_L28P_D7_AA9_J3_34

B5_L28N_D6_AB9_J3_33

B5_L27P_V9_J3_32

B5_L27N_W9_J3_31

B5_L25P_AA8_J3_22

B5_L25N_AB8_J3_21

B5_L24P_V8_J3_20

B5_L24N_W8_J3_19

B5_L22P_AA7_J3_18

B5_L22N_AB7_J3_17

B5_L19P_W7_J3_16

B5_L19N_Y7_J3_15

B5_L16P_Y6_J3_14

B5_L16N_AA6_J3_13

B5_L15P_V6_J3_12

B5_L15N_W6_J3_11

B5_L09P_W5_J3_8

B5_L09N_Y5_J3_7

B5_L06P_AA4_J3_6

B5_L06N_AB4_J3_5

B5_L01P_CS_B_AA3_J3_2

B5_L01N_RDWR_B_Y4_J3_1

B5_AB11_J3_90

B5_U6_J3_23

B5_V10_J3_85

B5_V7_J3_29

B5_U11_J3_83

B5_U10_J3_81

B5_U9_J3_41

B5_U7_J3_28

UDEF18

3

2

1

3X1IDC3X1

P11

B5_L29N_Y10_J3_35

B5_L30N_AB10_J3_37

B5_L31N_D4_W11_J3_39

B5_U11_J3_83

B5_V10_J3_85B5_AB11_J3_90

B5_U10_J3_81

B5_L31P_D5_V11_J3_40

B5_L30P_AA10_J3_38

B5_L29P_W10_J3_36

B5_L28P_D7_AA9_J3_34

B5_L27P_V9_J3_32

B5_L28N_D6_AB9_J3_33

B5_L27N_W9_J3_31

B5_L25N_AB8_J3_21B5_L25P_AA8_J3_22

B5_L24N_W8_J3_19B5_L24P_V8_J3_20

B5_U9_J3_41B5_U6_J3_23

VCCO_5

B5_L10P_VRN_AA5_J3_10

C70

0603001UF 001UF

0603

C69 C68

0603001UF001UF

0603

C67001UF0603

C66 C65

0603001UF 001UF

0603

C64C63

0603001UF

B5_L09N_Y5_J3_7

B5_U7_J3_28 B5_V7_J3_29

B5_L10P_VRN_AA5_J3_10 B5_L10N_VRP_AB5_J3_9

B5_L15P_V6_J3_12 B5_L15N_W6_J3_11

B5_L16P_Y6_J3_14 B5_L16N_AA6_J3_13

B5_L19P_W7_J3_16 B5_L19N_Y7_J3_15

B5_L22P_AA7_J3_18 B5_L22N_AB7_J3_17

B5_L32N_GCLK3_AA11_J3_30 B5_L32P_GCLK2_Y1

B5_L01P_CS_B_AA3_J3_2 B5_L01N_RDWR_B_Y4_J3_1

B5_L06P_AA4_J3_6 B5_L06N_AB4_J3_5

B5_L09P_W5_J3_8

VCCO_5

DNP0603

R45

25V

33V

33V

4

3

2

1

A B C D

20 Cotton Road

Nashua NH 03063

A B C D

4

3

2

1

PH 1-800-ANALOGD

C

Title

Size Board No

Date Sheet of

DEVICESANALOG

DNP = Do Not Populate

Rev

BLACKFIN FPGA EZ-EXTENDER

A0199-2005 10

SN74LVC1G125

12109-27-2005_1144

2 4

1

SOT23-5SN74LVC1G125

U8

USER IO

C80

0603001UF

SW4SWT013SPST-MOMENTARY

SPST-MOMENTARYSWT013SW3

060310R42

C5

06031UF

R413300603

LED001AMBER-SMTLED8

0603330R40

LED7AMBER-SMTLED001

R393300603

R1033006030603

330R34R35

33006030603

330R36

0603330R37 R38

3300603

LED001AMBER-SMTLED2

AMBER-SMTLED001

LED3AMBER-SMTLED001

LED4AMBER-SMTLED001

LED5

LED001AMBER-SMTLED6

LED9GREEN-SMTLED001

402100R23

1 2

3 4

5 6

7 8

JP5

IDC4X24X2

AMBER-SMTLED001

LED1

B6_L01N_Y3

B6_L01P_Y2

B5_U10_J3_81

B5_AB11_J3_90

PB2

B5_V10_J3_85

B5_U11_J3_83

B5_L31N_D4_W11_J3_39

B5_L30N_AB10_J3_37

B5_L29N_Y10_J3_35

B5_L28N_D6_AB9_J3_33

B5_L27N_W9_J3_31

PB1

B5_L25N_AB8_J3_21

R47

060310K

CHOKE_COIL

4

3

2

1

A B C D

20 Cotton Road

Nashua NH 03063

A B C D

4

3

2

1

PH 1-800-ANALOGD

C

Title

Size Board No

Date Sheet of

DEVICESANALOG

DNP = Do Not Populate

Rev

BLACKFIN FPGA EZ-EXTENDER

A0199-2005 10

25V

33V

VIN

EN

SW

GND

FB

VIN

EN

SW

GND

FB

VIN

EN

SW

GND

FB

4

3

5

2

1

VR3

SOT23-5LM3475MF

1

2

5

3

4

VR2

SOT23-5LM3475MF

4

3

5

2

1

VR1

SOT23-5LM3475MF

12119-27-2005_1124

1

32

Q2

SI2

343D

SS

OT

23D

1

32

Q3

SI2

343D

SS

OT

23D

2 3

1S

I234

3DS

Q1

SO

T23

D

316KR17

0603

215KR18

0603

0603

R11105K

DNPC73

0603

0603

C72DNP

805

C741000PF

0R58

0603

1000PFC10

805

0603

R1910K

C100UFCT2

CT3100UFC

IND005

L110UH

10UHL3

IND005

10UHL2

IND005

1

2 D3

DO214ABSCHOT_RECT

3A

0603

R20200K

805

C639NF

390PFC7

0603

2

1 3A

SCHOT_RECTDO214AB

D2

499KR13

0603

1

2 D1

DO214ABSCHOT_RECT

3A

33V_EI

3

1

2

3X1IDC3X1

P13

UNREG_IN

12V

CT1100UFC

80510UFC71

R1200603

5V_EI

8051000PFC2

FER2

0603

060301UFC3

POWER

FUS00125AF1

4

1

3

2

FER1

DO-214AA

S2A_RECT

2AD5

8051000PFC1 C4

10UFC

3

1

2

3X1IDC3X1

P12

UNREG_IN

1

2

3

CON00525MM_JACK

POWER

J4

2

1P42

IDC2X12X1DNP

1

2

DNP2X1IDC2X1

P43

06030R15

C810UF805

80510UFC9

R1600603

UNREG_IN

0603

R1410K

0603

R590

4

3

2

1

A B C D

20 Cotton Road

Nashua NH 03063

A B C D

4

3

2

1

PH 1-800-ANALOGD

C

Title

Size Board No

Date Sheet of

DEVICESANALOG

DNP = Do Not Populate

Rev

BLACKFIN FPGA EZ-EXTENDER

A0199-2005 1012129-14-2005_1204

5

2

4

8

10

6

1

3

9

11

13

15

17

19

12

14

16

20

18

7

P20

SOIC20

PROTO AREA

1

3

2

SOT23D

P39

2

3

1

SOT23D

P38

2

4

5 6

3

1

SOT23-6

P411

3

65

4

2

SOT23-6

P40

PRT_NUM=DNE

11

13

15 16

14

12

2

4

6

8

109

7

5

3

1

SOIC16

P191

3

5

7

9 10

8

6

4

2

12

14

1615

13

11

SOIC16

P18

21P37

805

1 2

805

P36

21P35

805

1 2

805

P34

1 2

805

P33

21P32

805

1 2

805

P31

21P30

805

1 2

805

P29

21P28

805

1 2

805

P27

21P26

805

21P25

805

1 2

805

P24

21P23

805

1 2

805

P22

TP86

TP85

TP84

TP83

TP82

TP81

TP80

TP79 TP77

TP76

TP75

TP74

TP73

TP72

TP71

TP70

TP68

TP67

TP66

TP65

TP64

TP62

TP61

TP60

TP59

TP58

TP57

TP56

TP55

TP54

TP53

TP51

TP50

TP49

TP48

TP47

TP46

TP45

TP44

TP43

TP41

TP40

TP39

TP38

TP37

TP36

TP35

TP34

TP33

TP32

TP30

TP29

TP28

TP27

TP26

TP25

TP24

TP23

TP22

TP21

TP19

TP18

TP17

TP16

TP15

TP14

TP13

TP12

TP11

TP9

TP8

TP7

TP6

TP5

TP4

TP125

TP124

TP123

TP122

TP121

TP120

TP119

TP118

TP117

TP116

TP114

TP113

TP112

TP111

TP110

TP109

TP108

TP107TP106

TP105TP103

TP102TP101 TP100TP99

TP98 TP97

TP96 TP95

TP94TP93

TP92TP91

TP90 TP89

TP88 TP87

TP78TP69

TP63 TP52

TP42 TP31

TP20 TP10

TP115TP104

7

18

20

16

14

12

19

17

15

13

11

9

3

1

6

10

8

4

2

5

SOIC20

P21

I INDEX

Numerics connectors

25V header (P42) 2-17

AADSP-BF5333761 EZ-KIT Lite interface 2-1ADSP-BF5333761 processors boot mode

settings 2-14architecture of this EZ-Extender 2-2asynchronous static random access memory

(SRAM) xauxiliary oscillator x

Bbill of materials A-1block diagram of this EZ-Extender 2-2boot jumper See JP4

Cconfiguration jumpers See JP2 JP3

map of locations 2-18J1-3 (expansion) 2-19P1-3 (expansion) 2-19P14 (IDC) 2-19P15 (JTAG header) 2-4P16-17 (IDC) 2-19P4 (high-speed) 2-20P5 (IDC) 2-20P6 (JTAG) 2-7P7 (IDC) 2-20P8 (IDC) 2-19

customer support xiii

Ddone LED (LED10) 2-17

Eexpansion interface

connectors (P1-3 J1-3) 2-19of ADSP-BF5333761 EZ-KIT Lites ix

1-3external power supply 1-3 2-8

FField-Programmable Gate Array See FPGA

Blackfin FPGA EZ-Extender Manual I-1

INDEX

FPGAdocumentation 1-2input jumpers (JP5) 2-14softwarefirmware 1-2Xilinx Spartan package x 1-3

FPGA pinsAB10 (LED3) 2-17AB11 (JP58) 2-15AB8 (LED7) 2-17AB9 (LED5) 2-17C11 (PB1SW3) 2-15H5 (PB2SW3) 2-16M2-0 (JP4) 2-14U10 (JP56) 2-15U11 (LED1) 2-17V10 (LED8) 2-17W11 (LED2) 2-17W9 (LED6) 2-17Y10 (LED4) 2-17Y3-2 (JP52-54) 2-15

FPGA programmingblock diagram 2-3via ADSP-BF533376 processors 2-6via JTAG header 2-4via serial ROM 2-5

GGCLK1 (global clock 1) pin 1-4GCLK6 (global clock 6) pin 1-4general-purpose input push buttons 2-15 2-16

Hhigh-speed connector (P4) 2-20

IIDC connectors x 2-19 2-20installation of this EZ-Extender 1-1

JJTAG

cable 1-4 2-7header (P6) 1-5 2-4 2-7 2-14

jumpersmap of locations 2-11JP1 (boot jumper) 2-5 2-12JP2 (confug done) 2-12JP3 (config program) 2-13JP41-46 (boot mode select) 2-5 2-6 2-14JP52-56 (FPGA input) 2-14

LLEDs

map of locations 2-15LED10 (FPGA done pin) 2-4 2-5 2-17LED1-8 (status) 2-17LED9 (power) 2-17

MM2-0 (JP4) pins 2-5master serial boot mode 2-6MCS-86 Hexadecimal Object (mcs) file

format 2-6

Nnotation conventions xvi

Ooscillator x 1-4

PP12 (power in) header 2-9P13 (33V header) 2-9P42 (25V header) 2-10P43 (12V header) 2-10PB1 push button (SW3) 2-15

I-2 Blackfin FPGA EZ-Extender Manual

INDEX

PB2 push button (SW4) 2-16PF14 flag pin (ADSP-BF537 EZ-KIT Lite)

2-12PF3 flag pin (ADSP-BF53361 EZ-KIT Lite)

2-12power

12V header (P43) 2-1025V header (P42) 2-1033V header (P13) 2-9in header (P12) 2-9LED (LED9) 2-17limitations 2-8supplies 1-3 2-8

printed circuit board (PCB) 1-2product overview ixprogram push button (SW1) 2-4 2-15push buttons

See also SWx map of locations 2-15

Sserial ROM 1-5

boot jumper (JP1) 2-12 2-14programming via JTAG Header 2-7

setup of this EZ-Extender 1-1slave serial mode 2-6

SRAM memory banks 1-4status reporting 1-4 2-17SW1 (program) push button 2-4 2-15SW3 (PB1) push button 2-15SW4 (PB2) push button 2-16switching regulators 2-8

TTCK signal 2-7TDI signal 2-7TDO signal 2-7TMS signal 2-7

VVisualDSP++

flash programming utility 1-4 2-6FPGA documentation 2-6

VR1-3 regulators 2-8

XXilinx

JTAG cablesoftware 1-4 2-4 2-7JTAG header 2-12serial ROM 1-5

Blackfin FPGA EZ-Extender Manual I-3

INDEX

I-4 Blackfin FPGA EZ-Extender Manual

• Blackfin FPGA EZ-Extender Manual
• Contents
• Preface
• • Product Overview
  • Purpose of This Manual
  • Intended Audience
  • Manual Contents
  • Whatrsquos New in This Manual
  • Technical or Customer Support
  • Supported Products
  • Product Information
  • • Related Documents
    • • Table 1 Related Processor Publications
      • Table 2 Related VisualDSP++ Publications
      • • Notation Conventions
        • • 1 FPGA EZ-Extender Interfaces
          • • FPGA EZ-Extender Setup
            • • Figure 1-1 FPGA EZ-Extender Setup
              • • FPGA Software and Firmware
                • FPGA EZ-Extender Overview
                • • 2 FPGA EZ-Extender Hardware Reference
                  • • System Architecture
                    • • Figure 2-1 Block Diagram
                      • • Programming the FPGA
                        • • Figure 2-2 FPGA Programming Block Diagram
                          • FPGA Programming via JTAG
                          • • Table 2-1 P15 Connections for PFGA Programming via JTAG
                            • Table 2-2 JP1 Settings for FPGA Programming via JTAG
                            • Table 2-3 JP4 Settings for FPGA Programming via JTAG
                            • • FPGA Programming via Serial ROM
                              • • Table 2-4 JP1 Settings for FPGA Programming via Serial ROM
                                • Table 2-5 JP4 Settings for FPGA Programming in Master Serial Mode
                                • • FPGA Programming via Blackfin Application
                                  • • Table 2-6 JP1 Settings for FPGA Programming via Blackfin Processor
                                    • Table 2-7 JP4 Settings for FPGA Programming via Blackfin Processor
                                    • • Programming the Serial ROM
                                      • • Serial ROM via JTAG Header
                                        • • Table 2-8 P6 Connections for Serial ROM
                                          • • Power
                                            • • Table 2-9 Power Limitations
                                              • Power In Header (P12)
                                              • 33V Header (P13)
                                              • 25V Header (P42)
                                              • 12V Header (P43)
                                              • • Jumpers
                                                • • Figure 2-3 Jumper Locations
                                                  • Serial ROM Boot Jumper (JP1)
                                                  • • Table 2-10 JP1 Settings
                                                    • • Config Done Jumper (JP2)
                                                      • • Table 2-11 JP2 Settings
                                                        • • Config Program Jumper (JP3)
                                                          • • Table 2-12 JP3 Settings
                                                            • • Boot Jumper (JP4)
                                                              • • Table 2-13 JP4 Settings
                                                                • • FPGA Input Jumpers (JP5)
                                                                  • • Table 2-14 JP5 Settings
                                                                    • • Push Buttons and LEDs
                                                                      • • Figure 2-4 Push Button and LED Locations
                                                                        • Program Push Button (SW1)
                                                                        • PB1 Push Button (SW3)
                                                                        • PB2 Push Button (SW4)
                                                                        • Status LEDs (LED1-8)
                                                                        • • Table 2-15 Status LED (LED1-8) Settings
                                                                          • • Power LED (LED9)
                                                                            • Done LED (LED10)
                                                                            • • Connectors
                                                                              • • Figure 2-5 Connector Locations
                                                                                • Expansion Interface (P1-3 and J1-3)
                                                                                • IDC Connectors (P8 P14 P16 and P17)
                                                                                • IDC Connectors (P5 and P7)
                                                                                • High-Speed Connector (P4)
                                                                                • • A Bill Of Materials
                                                                                  • B Schematics
                                                                                  • • Title
                                                                                    • FPGA Config
                                                                                    • SRAM FPGA Banks 7 and 8
                                                                                    • Expansion Interface Connector 1
                                                                                    • FPGA Banks 0 and 1
                                                                                    • Expansion Interface Connectors 2
                                                                                    • FPGA Banks 2 and 3
                                                                                    • Expansion Interface Connector 1
                                                                                    • FPGA Banks 4 and 5
                                                                                    • User IO
                                                                                    • Power
                                                                                    • Proto Area
                                                                                    • • I Index
                                                                                      • • Numerics
                                                                                        • A
                                                                                        • B
                                                                                        • C
                                                                                        • D
                                                                                        • E
                                                                                        • F
                                                                                        • G
                                                                                        • H
                                                                                        • I
                                                                                        • J
                                                                                        • L
                                                                                        • M
                                                                                        • N
                                                                                        • O
                                                                                        • P
                                                                                        • S
                                                                                        • T
                                                                                        • V
                                                                                        • X

33V 33V

4

3

2

1

A B C D

20 Cotton Road

Nashua NH 03063

A B C D

4

3

2

1

PH 1-800-ANALOGD

C

Title

Size Board No

Date Sheet of

DEVICESANALOG

DNP = Do Not Populate

Rev

BLACKFIN FPGA EZ-EXTENDER

A0199-2005 10

33V

33V

A18

A1

A10

A11

A12

A13

A14

A16

A2

A3

A4

A5

A6

A7

A8

A9

D0

D1

D10

D11

D2

D3

D4

D5

D6

D7

D8

D9

BHE

BLE

CE

OE

WE

A17

D15

D14

D13

D12

A0

A15

A18

A1

A10

A11

A12

A13

A14

A16

A2

A3

A4

A5

A6

A7

A8

A9

D0

D1

D10

D11

D2

D3

D4

D5

D6

D7

D8

D9

BHE

BLE

CE

OE

WE

A17

D15

D14

D13

D12

A0

A15

VCCO_6_M7

VCCO_6_N7

VCCO_6_P7

VCCO_6_R3

VCCO_6_R6

IO_Y1

IO_L16N_6_W4

IO_L16P_6_W3

IO_L17N_6_W2

IO_L17P_6_VREF_6_W1

IO_L19N_6_V5

IO_L19P_6_U5

IO_L20N_6_V4

IO_L20P_6_V3

IO_L21N_6_V2

IO_L21P_6_V1

IO_L22N_6_T6

IO_L22P_6_T5

IO_L23N_6_U4

IO_L23P_6_T4

IO_L24N_6_VREF_6_U3

IO_L24P_6_U2

IO_L26N_6_T3

IO_L26P_6_R4

IO_L27N_6_T2

IO_L27P_6_T1

IO_L28N_6_R5

IO_L28P_6_P6

IO_L29N_6_R2

IO_L29P_6_R1

IO_L31N_6_P5

IO_L31P_6_P4

IO_L32N_6_P2

IO_L32P_6_P1

IO_L33N_6_N6

IO_L33P_6_N5

IO_L34N_6_VREF_6_N4

IO_L34P_6_N3

IO_L35N_6_N2

IO_L35P_6_N1

IO_L38N_6_M6

IO_L38P_6_M5

IO_L39N_6_M4

IO_L39P_6_M3

IO_L40N_6_M2

IO_L40P_6_VREF_6_M1

IO_L01N_6_VRP_6_Y3

IO_L01P_6_VRN_6_Y2

VCCO_7_H3

VCCO_7_H6

VCCO_7_J7

VCCO_7_K7

VCCO_7_L7

IO_C2

IO_L16N_7_D1

IO_L16P_7_VREF_7_C1

IO_L17N_7_E4

IO_L17P_7_D4

IO_L19N_7_VREF_7_D3

IO_L19P_7_D2

IO_L20N_7_F4

IO_L20P_7_E3

IO_L21N_7_E1

IO_L21P_7_E2

IO_L22N_7_G6

IO_L22P_7_F5

IO_L23N_7_F2

IO_L23P_7_F3

IO_L24N_7_H5

IO_L24P_7_G5

IO_L26N_7_G3

IO_L26P_7_G4

IO_L27N_7_G1

IO_L27P_7_VREF_7_G2

IO_L28N_7_H1

IO_L28P_7_H2

IO_L29N_7_J4

IO_L29P_7_H4

IO_L31N_7_J5

IO_L31P_7_J6

IO_L32N_7_J1

IO_L32P_7_J2

IO_L33N_7_K5

IO_L33P_7_K6

IO_L34N_7_K3

IO_L34P_7_K4

IO_L35N_7_K1

IO_L35P_7_K2

IO_L38N_7_L5

IO_L38P_7_L6

IO_L39N_7_L3

IO_L39P_7_L4

IO_L40N_7_VREF_7_L1

IO_L40P_7_L2

IO_L01N_7_VRP_7_C3

IO_L01P_7_VRN_7_C4

(512k x 16bits x 2chips)2MBYTES FPGA SRAM

FPGASRAM SRAM

SRAM_A9

9-27-2005_1144 3 12

FLASH_TDO

FLASH_TMS

FLASH_TDI

FLASH_TCK

M7

N7

P7

R3

R6

Y1

W4

W3

W2

W1

V5

U5

V4

V3

V2

V1

T6

T5

U4

T4

U3

U2

T3

R4

T2

T1

R5

P6

R2

R1

P5

P4

P2

P1

N6

N5

N4

N3

N2

N1

M6

M5

M4

M3

M2

M1

Y3

Y2

H3

H6

J7

K7

L7

C2

D1

C1

E4

D4

D3

D2

F4

E3

E1

E2

G6

F5

F2

F3

H5

G5

G3

G4

G1

G2

H1

H2

J4

H4

J5

J6

J1

J2

K5

K6

K3

K4

K1

K2

L5

L6

L3

L4

L1

L2

C3

C4

U1

FG456XC3S1000

28

2

23

24

25

26

27

43

3

4

5

18

19

20

21

22

7

8

31

32

9

10

13

14

15

16

29

30

40

39

6

41

17

44

38

37

36

35

1

42

U3

TSOP44IS61LV51216

42

1

35

36

37

38

44

17

41

6

39

40

30

29

16

15

14

13

10

9

32

31

8

7

22

21

20

19

18

5

4

3

43

27

26

25

24

23

2

28

U5

TSOP44IS61LV51216

SRAM_D7

SRAM_D6

SRAM_D3

SRAM_D2

SRAM_D0

SRAM_D8

SRAM_D9

SRAM_D5

SRAM_D4

SRAM_D13

SRAM_D1

SRAM_D10

SRAM_D11

SRAM_D12

SRAM_D14

SRAM_D15

SRAM_CE

SRAM_A7

SRAM_A0

SRAM_A5

SRAM_A3

SRAM_A1

SRAM_WE

SRAM_A8

SRAM_A6

SRAM_A4

SRAM_A2

SRAM_A17

SRAM_OE

SRAM_A12

SRAM_A13

SRAM_A15

SRAM_A16

SRAM_A14

SRAM_A18

SRAM_A11

SRAM_A10

SRAM_D22

SRAM_D20

SRAM_D18

SRAM_D17

SRAM_D16

SRAM_D26

SRAM_D21

SRAM_D24

SRAM_D19

SRAM_D31

SRAM_D25

SRAM_D27

SRAM_D28

SRAM_D30

SRAM_D29

PB2

A11

A5

D1

A15

A3

A9

D13

D7

A13

A19

A7

A1

A18

A6

A2

A12

D6

A8

A14

D2

D0

A10

A4

D3

A16

SRAM FPGA BANKS 7 + 8

SRAM_CE

SRAM_WE

SRAM_OE

SRAM_A18

SRAM_A0 SRAM_D0

SRAM_D1

SRAM_D2

SRAM_D3

SRAM_D4

SRAM_D5

SRAM_D6

SRAM_D7

SRAM_D8

SRAM_D9

SRAM_D10

SRAM_D11

SRAM_D12

SRAM_D13

SRAM_D14

SRAM_D15

SRAM_D16

SRAM_D17

SRAM_D18

SRAM_D19

SRAM_D20

SRAM_D21

SRAM_D22

SRAM_D23

SRAM_D24

SRAM_D25

SRAM_D26

SRAM_D27

SRAM_D28

SRAM_D29

SRAM_D30

SRAM_D31

SRAM_A1

SRAM_A2

SRAM_A3

SRAM_A4

SRAM_A5

SRAM_A6

SRAM_A7

SRAM_A8

SRAM_A9

SRAM_A10

SRAM_A11

SRAM_A12

SRAM_A13

SRAM_A14

SRAM_A15

SRAM_A16

SRAM_A17

SRAM_A1

SRAM_A2

SRAM_A3

SRAM_A4

SRAM_A5

SRAM_A6

SRAM_A7

SRAM_A8

SRAM_A9

SRAM_A10

SRAM_A11

SRAM_A12

SRAM_A13

SRAM_A14

SRAM_A15

SRAM_A16

SRAM_A17

SRAM_A18

SRAM_A0

SRAM_OE

SRAM_WE

SRAM_CE

C33

0603001UF

C34

0603001UF001UF

0603

C37001UF0603

C36

C42

0603001UF 001UF

0603

C41 C40

0603001UF001UF

0603

C39001UF0603

C46 C45

0603001UF 001UF

0603

C44C43

0603001UF

B6_L01P_Y2

B6_L01N_Y3

SRAM_D23

4

3

2

1

A B C D

20 Cotton Road

Nashua NH 03063

A B C D

4

3

2

1

PH 1-800-ANALOGD

C

Title

Size Board No

Date Sheet of

DEVICESANALOG

DNP = Do Not Populate

Rev

BLACKFIN FPGA EZ-EXTENDER

A0199-2005 10

EXPANSION INTERFACE TYPE B

P1Expanison Connector

Top Of BoardBottom Of Board

Expansion Connector 1

10-18-2005_1616 4 12

EXPANSION INTERFACE CONNECTOR 1

C3510UF805

01UF0603

C38

5V_EI

5V_EI

1

10

11 12

13 14

15 16

17 18

19

2

20

21 22

23 24

25 26

27 28

29

3

30

31 32

33 34

35 36

37 38

39

4

40

41 42

43 44

45 46

47 48

49

5

50

51 52

53 54

55 56

57 58

59

6

60

61 62

63 64

65 66

67 68

69

7

70

71 72

73 74

75 76

77 78

79

8

80

81 82

83 84

85 86

87 88

89

9

90

P1

CON01845X2

1

10

1112

1314

1516

1718

19

2

20

2122

2324

2526

2728

29

3

30

3132

3334

3536

3738

39

4

40

4142

4344

4546

4748

49

5

50

5152

5354

5556

5758

59

6

60

6162

6364

6566

6768

69

7

70

7172

7374

7576

7778

79

8

80

8182

8384

8586

8788

89

9

90

J1

CON01945X2

PP1

EXPANSION_PPI_CLK

PP3

UDEF2

UDEF4

UDEF6

UDEF8

UDEF10

D9

D7

D15

D13

D11

D5

D1

D3

D15

D9

D5

D1

D3

D0

D2

D4

D6

D8

D10

D14

D12

P1_5

P1_25

P1_27

P1_29

P1_31

P1_33

P1_55

P1_57

P1_59

P1_61

P1_63

P1_65

P1_67

P1_69

P1_35

P1_26

P1_28

P1_30

P1_32

P1_34

P1_56

P1_58

P1_60

P1_62

P1_64

P1_66

P1_68

P1_70

P1_36

P1_26

P1_28

P1_30

P1_32

P1_34

P1_36

P1_56

P1_58

P1_60

P1_62

P1_64

P1_66

P1_68

P1_70

P1_5

P1_25

P1_27

P1_29

P1_31

P1_33

P1_35

P1_55

P1_57

P1_59

P1_61

P1_63

P1_65

P1_67

P1_69

P1_[586]

A5

A6A7

A8A9

A10A11

A12A13

A14A15

A16A17

A18A19

D0

D2

D4

D6D7

D8

D10D11

D12D13

D14

A1

A2

B1_L24N_D15_J1_71B1_L24P_E15_J1_72

B1_L22N_A16_J1_73B1_L22P_B16_J1_74

B1_L19N_C16_J1_75B1_L19P_D16_J1_76

B1_L16N_B17_J1_77B1_L16P_C17_J1_78

B1_L15N_D17_J1_79

A3

B1_L15P_E17_J1_80

B1_L10N_A18_J1_81B1_L10P_B18_J1_82

B1_L09N_C18_J1_83B1_L09P_D18_J1_84

B1_L06N_A19_J1_85B1_L06P_B19_J1_86

A4A5

A6 A7

A8 A9

A10 A11

A12 A13

A14 A15

A16 A17

A18 A19

A1

A2

PP0

PP2

UDEF1

UDEF3

A3

UDEF5

UDEF7

UDEF9

UDEF11

A4

33V

25V 33V

33V

33V

33V

4

3

2

1

A B C D

20 Cotton Road

Nashua NH 03063

A B C D

4

3

2

1

PH 1-800-ANALOGD

C

Title

Size Board No

Date Sheet of

DEVICESANALOG

DNP = Do Not Populate

Rev

BLACKFIN FPGA EZ-EXTENDER

A0199-2005 10

VCCO_0_C8

VCCO_0_F8

VCCO_0_G9

VCCO_0_G10

VCCO_0_G11

IO_A10

IO_D9

IO_D10

IO_F6

IO_VREF_0_A3

IO_VREF_0_C7

IO_VREF_0_E5

IO_VREF_0_F7

IO_L06N_0_D5

IO_L06P_0_C5

IO_L09N_0_B5

IO_L09P_0_A5

IO_L10N_0_E6

IO_L10P_0_D6

IO_L15N_0_C6

IO_L15P_0_B6

IO_L16N_0_E7

IO_L16P_0_D7

IO_L19N_0_B7

IO_L19P_0_A7

IO_L22N_0_E8

IO_L22P_0_D8

IO_L24N_0_B8

IO_L24P_0_A8

IO_L25N_0_F9

IO_L25P_0_E9

IO_L27N_0_B9

IO_L27P_0_A9

IO_L28N_0_F10

IO_L28P_0_E10

IO_L29N_0_C10

IO_L29P_0_B10

IO_L30N_0_F11

IO_L30P_0_E11

IO_L31N_0_D11

IO_L31P_0_VREF_0_C11

IO_L01N_0_VRP_0_B4

IO_L01P_0_VRN_0_A4

IO_L32N_0_GCLK7_B11

IO_L32P_0_GCLK6_A11

VCCO_1_C15

VCCO_1_F15

VCCO_1_G12

VCCO_1_G13

VCCO_1_G14

IO_A12

IO_E16

IO_F12

IO_F13

IO_F16

IO_F17

IO_VREF_1_E13

IO_VREF_1_F14

IO_L06N_1_VREF_1_A19

IO_L06P_1_B19

IO_L09N_1_C18

IO_L09P_1_D18

IO_L10N_1_VREF_1_A18

IO_L10P_1_B18

IO_L15N_1_D17

IO_L15P_1_E17

IO_L16N_1_B17

IO_L16P_1_C17

IO_L19N_1_C16

IO_L19P_1_D16

IO_L22N_1_A16

IO_L22P_1_B16

IO_L24N_1_D15

IO_L24P_1_E15

IO_L25N_1_B15

IO_L25P_1_A15

IO_L27N_1_D14

IO_L27P_1_E14

IO_L28N_1_A14

IO_L28P_1_B14

IO_L29N_1_C13

IO_L29P_1_D13

IO_L30N_1_A13

IO_L30P_1_B13

IO_L31N_1_VREF_1_D12

IO_L31P_1_E12

IO_L01N_1_VRP_1_C19

IO_L01P_1_VRN_1_B20

IO_L32N_1_GCLK5_B12

IO_L32P_1_GCLK4_C12

FPGAFPGA

LAYOUT NOTE PLACE NEAR FPGA

5 129-27-2005_1144

C8

F8

G9

G10

G11

A10

D9

D10

F6

A3

C7

E5

F7

D5

C5

B5

A5

E6

D6

C6

B6

E7

D7

B7

A7

E8

D8

B8

A8

F9

E9

B9

A9

F10

E10

C10

B10

F11

E11

D11

C11

B4

A4

B11

A11

C15

F15

G12

G13

G14

A12

E16

F12

F13

F16

F17

E13

F14

A19

B19

C18

D18

A18

B18

D17

E17

B17

C17

C16

D16

A16

B16

D15

E15

B15

A15

D14

E14

A14

B14

C13

D13

A13

B13

D12

E12

C19

B20

B12

C12

U1

FG456XC3S1000

1

10

11 12

13 14

15 16

17 18

19

2

20

21 22

23 24

25 26

27 28

29

3

30

31 32

33 34

35 36

37 38

4

5 6

7 8

9

39 40

41

43

45

47

49

42

44

46

48

50

25X2CON041

P4

5

1

18

20

22

26

24

16

14

12

25

23

21

19

17

15

13

11

9

3

6

10

8

4

2

7

P8

IDC13X213X2

5

1

18

20

22

26

24

16

14

12

25

23

21

19

17

15

13

11

9

3

6

10

8

4

2

7

P14

IDC13X213X2

FPGA BANKS 0 + 1

001UF0603

C50

DNP0603

R52

B1_L10N_A18_J1_81

B1_L15P_E17_J1_80

R53

0603DNP

B1_L16P_C17_J1_78

R27

06030

B1_L10P_B18_J1_82B1_L10N_A18_J1_81

B1_L15N_D17_J1_79

B1_L16N_B17_J1_77

B1_L24N_D15_J1_71

B1_L22N_A16_J1_73

B1_L19N_C16_J1_75

R51

0603DNPDNP

0603

R50DNP0603

R48

R31

0603DNP

B1_L19N_C16_J1_75

B1_L22N_A16_J1_73

B1_L24N_D15_J1_71

B1_L15N_D17_J1_79

B1_L15P_E17_J1_80

B1_L16N_B17_J1_77

B1_L16P_C17_J1_78

DNP0603

R30

VCCO_1

VCCO_1

C47

0603001UF

VCCO_1

B1_L27N_D14

PB1

AOE

B1_L01P_VRN_B20

B1_L01N_VRP_C19

IO_L32_0_GCLK6_A11

IO_L32_0_GCLK7_B11

IO_L32_0_GCLK7_B11

B1_L32N_GCLK5_B12

B1_L32P_GCLK4_C12 B1_L06P_B19_J1_86

B1_L09P_D18_J1_84

B1_L15P_E17_J1_80

B1_L16P_C17_J1_78

B1_L19P_D16_J1_76

B1_L16N_B17_J1_77

B1_L15N_D17_J1_79

B1_L09N_C18_J1_83

B1_L06N_A19_J1_85

B1_L31P_E12

B1_L31N_D12

B1_L06N_A19_J1_85

B1_L09N_C18_J1_83

B1_L09P_D18_J1_84

B1_L06P_B19_J1_86

B1_F17

B1_F16

B1_E16

B1_F13

B1_E13

B1_F12

B1_A12

B1_F14

B1_L01N_VRP_C19

B1_L01P_VRN_B20

B1_L32P_GCLK4_C12

B1_L32N_GCLK5_B12

AMS3

D5

D4

AMS0

UDEF1

ARE

ARDY

AMS1

AMS2

UDEF11

UDEF9

UDEF7

UDEF5

UDEF3

PP2

PP0

D15

D11

D9

A17

B1_L16P_C17_J1_78

B1_L19P_D16_J1_76

B1_L19N_C16_J1_75

B1_L22P_B16_J1_74

B1_L24N_D15_J1_71

B1_L22N_A16_J1_73

B1_L24P_E15_J1_72

B1_L16N_B17_J1_77

B1_L10P_B18_J1_82

B1_L15P_E17_J1_80

B1_L15N_D17_J1_79

B1_L10N_A18_J1_81

B1_L09P_D18_J1_84

B1_L09N_C18_J1_83

B1_L06P_B19_J1_86

B1_L06N_A19_J1_85

B1_L31N_D12

B1_L30N_A13

B1_L29N_C13

B1_L28N_A14

B1_L27N_D14

B1_L25N_B15

B1_F16

B1_F14

B1_F13

B1_F12

B1_L31P_E12

B1_L30P_B13

B1_L29P_D13

B1_L28P_B14

B1_L27P_E14

B1_L25P_A15

B1_F17

B1_E13

B1_E16

B1_A12

UDEF10

ABE3

ABE1

ABE0

ABE2

AWE

UDEF6

UDEF8

PP3

UDEF4

UDEF2

PP1

D14

D8

D10

D12

B1_L25P_A15B1_L25N_B15

B1_L22N_A16_J1_73

B1_L24N_D15_J1_71

B1_L19N_C16_J1_75

B1_L24P_E15_J1_72

B1_L22P_B16_J1_74

B1_L27P_E14

B1_L19P_D16_J1_76

B1_L22P_B16_J1_74

B1_L24P_E15_J1_72

B1_L25N_B15

B1_L25P_A15

B1_L27N_D14

B1_L27P_E14

B1_L28N_A14

B1_L28P_B14

B1_L29N_C13

B1_L29P_D13

B1_L30N_A13

B1_L30P_B13

B1_L10N_A18_J1_81

B1_L10P_B18_J1_82

3

2

1

3X1IDC3X1

P9

EXPANSION_PPI_CLK

B1_F16 B1_F17

B1_L28P_B14

B1_L29P_D13

B1_L30P_B13

B1_L31P_E12

B1_L28N_A14

B1_L29N_C13

B1_L30N_A13

B1_L31N_D12

B1_E16

B1_E13

B1_A12

B1_L01P_VRN_B20

B1_L32P_GCLK4_C12

B1_F14

B1_L01N_VRP_C19

B1_L32N_GCLK5_B12

B1_F13

B1_F12

B1_L01P_VRN_B20

B1_L01N_VRP_C19

001UF0603

C48 C49

0603001UF

C51

0603001UF 001UF

0603

C52 C53

0603001UF001UF

0603

C54

VCCO_1

R49

0603DNP

B1_L10P_B18_J1_82

DNP0603

R54

4

3

2

1

A B C D

20 Cotton Road

Nashua NH 03063

A B C D

4

3

2

1

PH 1-800-ANALOGD

C

Title

Size Board No

Date Sheet of

DEVICESANALOG

DNP = Do Not Populate

Rev

BLACKFIN FPGA EZ-EXTENDER

A0199-2005 10Expanison ConnectorP2

Bottom Of Board Top Of Board

Expansion Connector 2

33V_EI

6 129-14-2005_1203

EXPANSION INTERFACE CONNECTOR 2

SCK

NMI

TMR1

PF1

PF3

PF5

PF7

PF9

PF11

PF13

PF15

1

10

11 12

13 14

15 16

17 18

19 20

21 22

23 24

25 26

27 28

29

3

30

31 32

33 34

35 36

37 38

39

4

40

41 42

43 44

45 46

47 48

49

5

50

51 52

53 54

55 56

57 58

59

6

60

61 62

63 64

65 66

67 68

69

7

70

71 72

73 74

75 76

77 78

79

8

80

81 82

83 84

85 86

87 88

89

9

90

2P2

CON01845X2

1

10

1112

1314

1516

1718

19

2

20

2122

2324

2526

2728

29

3

30

3132

3334

3536

3738

39

4

40

4142

4344

4546

4748

49

5

50

5152

5354

5556

5758

59

6

60

6162

6364

6566

6768

69

7

70

7172

7374

7576

7778

79

8

80

8182

8384

8586

8788

89

9

90

J2

CON01945X2

ARE

ARDY

AMS0

AMS1

P2_21

P2_19

P2_7

P2_21

P2_71

P2_73

P2_77

P2_79

P2_83

P2_85

P2_81

P2_19

P2_15

P2_5 P2_6

P2_8

P2_22

P2_86

P2_84

P2_82

P2_80

P2_78

P2_74

P2_72

P2_20

P2_18

P2_22

P2_74

P2_78

P2_82

P2_84

P2_86

P2_80

P2_72

P2_20

P2_18

P2_8

P2_6

P2_[586]

P2_5

P2_7

P2_15

P2_85

P2_83

P2_81

P2_79

P2_77

P2_73

P2_71AWE

AOE

ABE0

ABE1

ABE2

ABE3

TSCLK0

TFS0

DT0PRI

DT0SEC

CONFIG_CLK_TSCLK1

CONFIG_INIT_B_TFS1

DT1PRI

DT1SEC

TMR0

TMR2

PF14

PF12

PF10

PF8

PF4

PF6

PF2

PF0

B2_L40N_L21_J2_9

B2_L39N_L19_J2_11

B2_C22_J2_17

B2_L38N_L17_J2_23

B2_L35N_K21_J2_25

B2_L34N_K19_J2_27

B2_L33N_K17_J2_29

B2_L32N_J21_J2_31

B2_L31N_J18_J2_33

B2_L29N_H21_J2_35

B2_L28N_H18_J2_37

B2_L27N_G21_J2_39

B2_L26N_G20_J2_41

B2_L22N_G17_J2_43

B2_L24N_F20_J2_45

B2_L23N_F19_J2_47

B2_L21N_E21_J2_49

B2_L20N_E19_J2_51

B2_L19N_E18_J2_53

B2_L17N_D21_J2_55

B2_L16N_D20_J2_57B2_L16P_D19_J2_58

B2_L17P_D22_J2_56

B2_L19P_F18_J2_54

B2_L20P_E20_J2_52

B2_L21P_E22_J2_50

B2_L23P_G19_J2_48

B2_L24P_F21_J2_46

B2_L22P_G18_J2_44

B2_L26P_H19_J2_42

B2_L27P_G22_J2_40

B2_L28P_J17_J2_38

B2_L29P_H22_J2_36

B2_L31P_J19_J2_34

B2_L32P_J22_J2_32

B2_L33P_K18_J2_30

B2_L34P_K20_J2_28

B2_L35P_K22_J2_26

B2_L38P_L18_J2_24

IO_L01P_2_VRN_2_C21_J2_16

B2_L40P_L22_J2_10

B2_L39P_L20_J2_12

MOSI

MISO

UDEF12

AMS3

AMS2

AMS0

ARDY

AMS1

AREAWE

AOE

ABE0

ABE1

ABE2

ABE3

RSCLK1

RSCLK0

RFS1

DR1PRI

DR1SEC

AMS2

AMS3

DR0SEC

DR0PRI

RFS0

TMR3

SPIDS0

C56

060301UF

80510UFC55

33V_EI

33V

4

3

2

1

A B C D

20 Cotton Road

Nashua NH 03063

A B C D

4

3

2

1

PH 1-800-ANALOGD

C

Title

Size Board No

Date Sheet of

DEVICESANALOG

DNP = Do Not Populate

Rev

BLACKFIN FPGA EZ-EXTENDER

A0199-2005 10

33V

25V33V

33V

33V

VCCO_2_H17

VCCO_2_H20

VCCO_2_J16

VCCO_2_K16

VCCO_2_L16

IO_C22

IO_L16N_2_D20

IO_L16P_2_D19

IO_L17N_2_D21

IO_L17P_2_VREF_2_D22

IO_L19N_2_E18

IO_L19P_2_F18

IO_L20N_2_E19

IO_L20P_2_E20

IO_L21N_2_E21

IO_L21P_2_E22

IO_L22N_2_G17

IO_L22P_2_G18

IO_L23N_2_VREF_2_F19

IO_L23P_2_G19

IO_L24N_2_F20

IO_L24P_2_F21

IO_L26N_2_G20

IO_L26P_2_H19

IO_L27N_2_G21

IO_L27P_2_G22

IO_L28N_2_H18

IO_L28P_2_J17

IO_L29N_2_H21

IO_L29P_2_H22

IO_L31N_2_J18

IO_L31P_2_J19

IO_L32N_2_J21

IO_L32P_2_J22

IO_L33N_2_K17

IO_L33P_2_K18

IO_L34N_2_VREF_2_K19

IO_L34P_2_K20

IO_L35N_2_K21

IO_L35P_2_K22

IO_L38N_2_L17

IO_L38P_2_L18

IO_L39N_2_L19

IO_L39P_2_L20

IO_L40N_2_L21

IO_L40P_2_VREF_2_L22

IO_L01N_2_VRP_2_C20

IO_L01P_2_VRN_2_C21

VCCO_3_M16

VCCO_3_N16

VCCO_3_P16

VCCO_3_R17

VCCO_3_R20

IO_L16N_3_W22

IO_L16P_3_Y22

IO_L17N_3_V19

IO_L17P_3_VREF_3_W19

IO_L19N_3_W21

IO_L19P_3_W20

IO_L20N_3_U19

IO_L20P_3_V20

IO_L21N_3_V22

IO_L21P_3_V21

IO_L22N_3_T17

IO_L22P_3_U18

IO_L23N_3_U21

IO_L23P_3_VREF_3_U20

IO_L24N_3_R18

IO_L24P_3_T18

IO_L26N_3_T20

IO_L26P_3_T19

IO_L27N_3_T22

IO_L27P_3_T21

IO_L28N_3_R22

IO_L28P_3_R21

IO_L29N_3_P19

IO_L29P_3_R19

IO_L31N_3_P18

IO_L31P_3_P17

IO_L32N_3_P22

IO_L32P_3_P21

IO_L33N_3_N18

IO_L33P_3_N17

IO_L34N_3_N20

IO_L34P_3_VREF_3_N19

IO_L35N_3_N22

IO_L35P_3_N21

IO_L38N_3_M18

IO_L38P_3_M17

IO_L39N_3_M20

IO_L39P_3_M19

IO_L40N_3_VREF_3_M22

IO_L40P_3_M21

IO_L01N_3_VRP_3_Y20

IO_L01P_3_VRN_3_Y19

IO_Y21

FPGAFPGA

LAYOUT NOTE PLACE NEAR FPGA

9-27-2005_1144 7 12

H17

H20

J16

K16

L16

C22

D20

D19

D21

D22

E18

F18

E19

E20

E21

E22

G17

G18

F19

G19

F20

F21

G20

H19

G21

G22

H18

J17

H21

H22

J18

J19

J21

J22

K17

K18

K19

K20

K21

K22

L17

L18

L19

L20

L21

L22

C20

C21

M16

N16

P16

R17

R20

W22

Y22

V19

W19

W21

W20

U19

V20

V22

V21

T17

U18

U21

U20

R18

T18

T20

T19

T22

T21

R22

R21

P19

R19

P18

P17

P22

P21

N18

N17

N20

N19

N22

N21

M18

M17

M20

M19

M22

M21

Y20

Y19

Y21

U1

FG456XC3S1000

2

4

8

10

6

12

14

16

24

22

20

18

26

28

3

5

7

9

11

13

15

17

19

21

23

25

27

1P5

IDC14X214X2

1

27

25

23

21

19

17

15

13

11

9

7

5

3

28

26

18

20

22

24

16

14

12

6

10

8

4

2P7

IDC14X214X2

VCCO_2

B2_L26P_H19_J2_42

DNP0603

R55B2_L24P_F21_J2_46

R56

0603DNP

B2_L23P_G19_J2_48

B2_L26N_G20_J2_41

B2_L24N_F20_J2_45

B2_L23N_F19_J2_47 B2_L23P_G19_J2_48

B2_L24P_F21_J2_46

B2_L26P_H19_J2_42

R32

0603DNP

TMR0

VCCO_2

PF221

2X1IDC2X1

JP3

CONFIG_PROG_B

1 2JP2

IDC2X12X1

PF3

CONFIG_INIT_B_TFS1

CONFIG_CLK_TSCLK1

RSCLK1

RFS1

IO_L01N_2_VRP_2_C20

IO_L01P_2_VRN_2_C21_J2_16

B2_L22N_G17_J2_43

B2_L22P_G18_J2_44

B2_L32N_J21_J2_31

SPIDS0

PF0

SCK

NMI

TMR1

DR1SEC

TMR3

DR0PRI

DR1PRI

RFS0

DR0SEC

PF15

PF13

RSCLK0

PF7

PF9

PF6

PF11

PF1

PF3

PF5

MOSI

MISO

UDEF12

TMR2

DT1SEC

DT1PRI

DT0SEC

TSCLK0

PF14

PF12

PF10

PF8

PF4

PF2

FPGA BANKS 2 + 3

DT0PRI

TFS0

B2_L40P_L22_J2_10

B2_L40N_L21_J2_9

B2_L39P_L20_J2_12

B2_L39N_L19_J2_11

B2_L38P_L18_J2_24

B2_L38N_L17_J2_23

B2_L35P_K22_J2_26

B2_L35N_K21_J2_25

B2_L34P_K20_J2_28

B2_L34N_K19_J2_27

B2_L33P_K18_J2_30

B2_L33N_K17_J2_29

B2_L32P_J22_J2_32

B2_L31P_J19_J2_34

B2_L31N_J18_J2_33

B2_L29P_H22_J2_36

B2_L29N_H21_J2_35

B2_L28P_J17_J2_38

B2_L28N_H18_J2_37

B2_L27P_G22_J2_40

B2_L27N_G21_J2_39

B2_L26P_H19_J2_42

B2_L26N_G20_J2_41

B2_L24P_F21_J2_46

B2_L24N_F20_J2_45

B2_L23P_G19_J2_48

B2_L23N_F19_J2_47

B2_L21P_E22_J2_50

B2_L21N_E21_J2_49

B2_L20P_E20_J2_52

B2_L20N_E19_J2_51

B2_L19P_F18_J2_54

B2_L19N_E18_J2_53

B2_L17P_D22_J2_56

B2_L17N_D21_J2_55

B2_L16P_D19_J2_58

B2_L16N_D20_J2_57

B2_C22_J2_17

3

2

1

3X1IDC3X1

P10

IO_L01P_2_VRN_2_C21_J2_16

IO_L01N_2_VRP_2_C20

VCCO_2

CONFIG_DONE

B2_L22N_G17_J2_43

B2_L17N_D21_J2_55

B2_L19N_E18_J2_53

B2_L20N_E19_J2_51

B2_L21N_E21_J2_49

B2_L16N_D20_J2_57

IO_L01N_2_VRP_2_C20

B2_L16P_D19_J2_58

B2_L20P_E20_J2_52

B2_L19P_F18_J2_54

B2_L17P_D22_J2_56

B2_L22P_G18_J2_44

B2_L21P_E22_J2_50

B2_C22_J2_17

IO_L01P_2_VRN_2_C21_J2_16

B2_L40N_L21_J2_9

B2_L39N_L19_J2_11

B2_L38N_L17_J2_23

B2_L35N_K21_J2_25

B2_L34N_K19_J2_27

B2_L33N_K17_J2_29

B2_L32N_J21_J2_31

B2_L31N_J18_J2_33

B2_L29N_H21_J2_35

B2_L28N_H18_J2_37

B2_L27N_G21_J2_39

B2_L40P_L22_J2_10

B2_L34P_K20_J2_28

B2_L35P_K22_J2_26

B2_L38P_L18_J2_24

B2_L39P_L20_J2_12

B2_L33P_K18_J2_30

B2_L32P_J22_J2_32

B2_L28P_J17_J2_38

B2_L31P_J19_J2_34

B2_L29P_H22_J2_36

B2_L27P_G22_J2_40

DNP0603

R33

B2_L23N_F19_J2_47

B2_L24N_F20_J2_45

B2_L26N_G20_J2_41

DNP0603

R57

001UF0603

C60 C59

0603001UF 001UF

0603

C58 C57

0603001UF

C82

0603001UF 001UF

0603

C81 C62

0603001UF001UF

0603

C61

VCCO_2

4

3

2

1

A B C D

20 Cotton Road

Nashua NH 03063

A B C D

4

3

2

1

PH 1-800-ANALOGD

C

Title

Size Board No

Date Sheet of

DEVICESANALOG

DNP = Do Not Populate

Rev

BLACKFIN FPGA EZ-EXTENDER

A0199-2005 10

Expanison ConnectorExpanison Connector

Bottom Of Board Top Of BoardExpansion Connector 3

EXPANSION INTERFACE (TYPE B)

P3P3

9-9-2005_1029 128

EXPANSION INTERFACE CONNECTOR 1

33V_EI5V_EI

1

10

11 12

13 14

15 16

17 18

19

2

20

21 22

23 24

25 26

27 28

29

3

30

31 32

33 34

35 36

37 38

39

4

40

41 42

43 44

45 46

47 48

49

5

50

51 52

53 54

55 56

57 58

59

6

60

61 62

63 64

65 66

67 68

69

7

70

71 72

73 74

75 76

77 78

79

8

80

81 82

83 84

85 86

87 88

89

9

90

P3

CON01845X2

1

10

1112

1314

1516

1718

19

2

20

2122

2324

2526

2728

29

3

30

3132

3334

3536

3738

39

4

40

4142

4344

4546

4748

49

5

50

5152

5354

5556

5758

59

6

60

6162

6364

6566

6768

69

7

70

7172

7374

7576

7778

79

8

80

8182

8384

8586

8788

89

9

90

J3

CON01945X2

TX0

TX1

UDEF17

UDEF19

UDEF21

UDEF23

UDEF25

UDEF29

UDEF27

RESET

UDEF32

UDEF34

UDEF36

UDEF38

UDEF40

B5_L01N_RDWR_B_Y4_J3_1

P3_42

P3_[190]

P3_86

P3_84

P3_82

P3_80

P3_78

P3_76

P3_74

P3_72

P3_70

P3_68

P3_64

P3_62

P3_60

P3_58

P3_56

P3_54

P3_52

P3_50

P3_48

P3_46

P3_42

P3_79

P3_89

P3_77

P3_75

P3_73

P3_71

P3_69

P3_67

P3_63

P3_61

P3_59

P3_57

P3_55

P3_53

P3_51

P3_49

P3_47

P3_45

P3_51

P3_79

P3_89

P3_77

P3_75

P3_73

P3_71

P3_69

P3_67

P3_63

P3_61

P3_59

P3_57

P3_55

P3_53

P3_49

P3_47

P3_45

P3_86

P3_84

P3_82

P3_80

P3_78

P3_76

P3_74

P3_72

P3_70

P3_68

P3_64

P3_62

P3_60

P3_58

P3_56

P3_54

P3_52

P3_50

P3_48

P3_46

B5_L27N_W9_J3_31

B5_L28N_D6_AB9_J3_33

B5_L29N_Y10_J3_35

B5_L30N_AB10_J3_37

B5_L31N_D4_W11_J3_39

B5_L10N_VRP_AB5_J3_9

B5_L25N_AB8_J3_21

B5_L24N_W8_J3_19

B5_L22N_AB7_J3_17

B5_L19N_Y7_J3_15

B5_L16N_AA6_J3_13

B5_L15N_W6_J3_11

B5_L09N_Y5_J3_7

B5_L06N_AB4_J3_5

B5_U6_J3_23

B5_V7_J3_29

B5_U9_J3_41

B5_L31P_D5_V11_J3_40

B5_L30P_AA10_J3_38

B5_L29P_W10_J3_36

B5_L28P_D7_AA9_J3_34

B5_L27P_V9_J3_32

B5_L32N_GCLK3_AA11_J3_30

B5_U7_J3_28

B5_L25P_AA8_J3_22

B5_L24P_V8_J3_20

B5_L22P_AA7_J3_18

B5_L19P_W7_J3_16

B5_L16P_Y6_J3_14

B5_L15P_V6_J3_12

B5_L10P_VRN_AA5_J3_10

B5_L09P_W5_J3_8

B5_L06P_AA4_J3_6

B5_L01P_CS_B_AA3_J3_2

B5_AB11_J3_90

B5_U11_J3_83

B5_V10_J3_85

B5_U10_J3_81

UDEF43

BGH

BG

BR

UDEF30

UDEF28

UDEF26

UDEF24

UDEF22

UDEF20

UDEF18

UDEF16

RX1

RX0

UDEF14 UDEF15

CLK_OUT_EXP1

UDEF31

UDEF33

UDEF35

UDEF37

UDEF39

UDEF41

33V_EI

C84

060301UF

80510UFC83

C8610UF805

01UF0603

C85

5V_EI

33V

33V

25V 33V

33V

33V

33V

4

3

2

1

A B C D

20 Cotton Road

Nashua NH 03063

A B C D

4

3

2

1

PH 1-800-ANALOGD

C

Title

Size Board No

Date Sheet of

DEVICESANALOG

DNP = Do Not Populate

Rev

BLACKFIN FPGA EZ-EXTENDER

A0199-2005 10

VCCO_4_T12

VCCO_4_T13

VCCO_4_T14

VCCO_4_U15

VCCO_4_Y15

IO_U16

IO_U17

IO_W13

IO_W14

IO_VREF_4_V18

IO_VREF_4_Y16

IO_VREF_4_AB13

IO_L05N_4_AA19

IO_L05P_4_AB19

IO_L06N_4_VREF_4_W18

IO_L06P_4_Y18

IO_L09N_4_AA18

IO_L09P_4_AB18

IO_L10N_4_V17

IO_L10P_4_W17

IO_L15N_4_Y17

IO_L15P_4_AA17

IO_L16N_4_V16

IO_L16P_4_W16

IO_L19N_4_AA16

IO_L19P_4_AB16

IO_L22N_4_VREF_4_V15

IO_L22P_4_W15

IO_L24N_4_AA15

IO_L24P_4_AB15

IO_L25N_4_U14

IO_L25P_4_V14

IO_L27N_4_DIN_D0_AA14

IO_L27P_4_D1_AB14

IO_L28N_4_U13

IO_L28P_4_V13

IO_L29N_4_Y13

IO_L29P_4_AA13

IO_L30N_4_D2_U12

IO_L30P_4_D3_V12

IO_L31N_4_INIT_B_W12

IO_L31P_4_DOUT_BUSY_Y12

IO_L01N_4_VRP_4_AA20

IO_L01P_4_VRN_4_AB20

IO_L32N_4_GCLK1_AA12

IO_L32P_4_GCLK0_AB12

VCCO_5_T9

VCCO_5_T10

VCCO_5_T11

VCCO_5_U8

VCCO_5_Y8

IO_U7

IO_U9

IO_U10

IO_U11

IO_V7

IO_V10

IO_VREF_5_U6

IO_VREF_5_AB11

IO_L01N_5_RDWR_B_Y4

IO_L01P_5_CS_B_AA3

IO_L06N_5_AB4

IO_L06P_5_AA4

IO_L09N_5_Y5

IO_L09P_5_W5

IO_L15N_5_W6

IO_L15P_5_V6

IO_L16N_5_AA6

IO_L16P_5_Y6

IO_L19N_5_Y7

IO_L19P_5_VREF_5_W7

IO_L22N_5_AB7

IO_L22P_5_AA7

IO_L24N_5_W8

IO_L24P_5_V8

IO_L25N_5_AB8

IO_L25P_5_AA8

IO_L27N_5_VREF_5_W9

IO_L27P_5_V9

IO_L28N_5_D6_AB9

IO_L28P_5_D7_AA9

IO_L29N_5_Y10

IO_L29P_5_VREF_5_W10

IO_L30N_5_AB10

IO_L30P_5_AA10

IO_L31N_5_D4_W11

IO_L31P_5_D5_V11

IO_L32N_5_GCLK3_AA11

IO_L32P_5_GCLK2_Y11

IO_L10N_5_VRP_5_AB5

IO_L10P_5_VRN_5_AA5

FPGAFPGA

1299-27-2005_1144

T12

T13

T14

U15

Y15

U16

U17

W13

W14

V18

Y16

AB13

AA19

AB19

W18

Y18

AA18

AB18

V17

W17

Y17

AA17

V16

W16

AA16

AB16

V15

W15

AA15

AB15

U14

V14

AA14

AB14

U13

V13

Y13

AA13

U12

V12

W12

Y12

AA20

AB20

AA12

AB12

T9

T10

T11

U8

Y8

U7

U9

U10

U11

V7

V10

U6

AB11

Y4

AA3

AB4

AA4

Y5

W5

W6

V6

AA6

Y6

Y7

W7

AB7

AA7

W8

V8

AB8

AA8

W9

V9

AB9

AA9

Y10

W10

AB10

AA10

W11

V11

AA11

Y11

AB5

AA5

U1

FG456XC3S1000

7

2

4

8

10

6

3

9

11

13

15

17

19

21

23

25

12

14

16

24

26

22

20

18

1

5

P16

IDC13X213X2

5

1

18

20

22

26

24

16

14

12

25

23

21

19

17

15

13

11

9

3

6

10

8

4

2

7

P17

IDC13X213X2

R46

060310K

R43

0603DNP

FPGA BANKS 4 + 5

VCCO_5

CONFIG_INIT_B_TFS1

CLK_OUT_EXP1

B4_L32N_GCKL1_AA12

R9

06030

B5_L10N_VRP_AB5_J3_9

B5_L10N_VRP_AB5_J3_9

B5_L10P_VRN_AA5_J3_10

VCCO_5

B5_L32P_GCLK2_Y1

B5_L32N_GCLK3_AA11_J3_30

CONFIG_DIN_DT1PRI

UDEF16

UDEF38

UDEF14

RX0

TX0

RX1

TX1

UDEF20

UDEF21

UDEF23

UDEF17

UDEF25

UDEF24

UDEF22

RESET

UDEF30

UDEF29

UDEF27

UDEF26

UDEF35

UDEF34

UDEF33

UDEF32

UDEF31

UDEF15

UDEF28

UDEF41

UDEF40

UDEF39

UDEF37

UDEF36

BR

UDEF43

BG

BGH

UDEF19

B5_L31P_D5_V11_J3_40

B5_L31N_D4_W11_J3_39

B5_L30P_AA10_J3_38

B5_L30N_AB10_J3_37

B5_L29P_W10_J3_36

B5_L29N_Y10_J3_35

B5_L28P_D7_AA9_J3_34

B5_L28N_D6_AB9_J3_33

B5_L27P_V9_J3_32

B5_L27N_W9_J3_31

B5_L25P_AA8_J3_22

B5_L25N_AB8_J3_21

B5_L24P_V8_J3_20

B5_L24N_W8_J3_19

B5_L22P_AA7_J3_18

B5_L22N_AB7_J3_17

B5_L19P_W7_J3_16

B5_L19N_Y7_J3_15

B5_L16P_Y6_J3_14

B5_L16N_AA6_J3_13

B5_L15P_V6_J3_12

B5_L15N_W6_J3_11

B5_L09P_W5_J3_8

B5_L09N_Y5_J3_7

B5_L06P_AA4_J3_6

B5_L06N_AB4_J3_5

B5_L01P_CS_B_AA3_J3_2

B5_L01N_RDWR_B_Y4_J3_1

B5_AB11_J3_90

B5_U6_J3_23

B5_V10_J3_85

B5_V7_J3_29

B5_U11_J3_83

B5_U10_J3_81

B5_U9_J3_41

B5_U7_J3_28

UDEF18

3

2

1

3X1IDC3X1

P11

B5_L29N_Y10_J3_35

B5_L30N_AB10_J3_37

B5_L31N_D4_W11_J3_39

B5_U11_J3_83

B5_V10_J3_85B5_AB11_J3_90

B5_U10_J3_81

B5_L31P_D5_V11_J3_40

B5_L30P_AA10_J3_38

B5_L29P_W10_J3_36

B5_L28P_D7_AA9_J3_34

B5_L27P_V9_J3_32

B5_L28N_D6_AB9_J3_33

B5_L27N_W9_J3_31

B5_L25N_AB8_J3_21B5_L25P_AA8_J3_22

B5_L24N_W8_J3_19B5_L24P_V8_J3_20

B5_U9_J3_41B5_U6_J3_23

VCCO_5

B5_L10P_VRN_AA5_J3_10

C70

0603001UF 001UF

0603

C69 C68

0603001UF001UF

0603

C67001UF0603

C66 C65

0603001UF 001UF

0603

C64C63

0603001UF

B5_L09N_Y5_J3_7

B5_U7_J3_28 B5_V7_J3_29

B5_L10P_VRN_AA5_J3_10 B5_L10N_VRP_AB5_J3_9

B5_L15P_V6_J3_12 B5_L15N_W6_J3_11

B5_L16P_Y6_J3_14 B5_L16N_AA6_J3_13

B5_L19P_W7_J3_16 B5_L19N_Y7_J3_15

B5_L22P_AA7_J3_18 B5_L22N_AB7_J3_17

B5_L32N_GCLK3_AA11_J3_30 B5_L32P_GCLK2_Y1

B5_L01P_CS_B_AA3_J3_2 B5_L01N_RDWR_B_Y4_J3_1

B5_L06P_AA4_J3_6 B5_L06N_AB4_J3_5

B5_L09P_W5_J3_8

VCCO_5

DNP0603

R45

25V

33V

33V

4

3

2

1

A B C D

20 Cotton Road

Nashua NH 03063

A B C D

4

3

2

1

PH 1-800-ANALOGD

C

Title

Size Board No

Date Sheet of

DEVICESANALOG

DNP = Do Not Populate

Rev

BLACKFIN FPGA EZ-EXTENDER

A0199-2005 10

SN74LVC1G125

12109-27-2005_1144

2 4

1

SOT23-5SN74LVC1G125

U8

USER IO

C80

0603001UF

SW4SWT013SPST-MOMENTARY

SPST-MOMENTARYSWT013SW3

060310R42

C5

06031UF

R413300603

LED001AMBER-SMTLED8

0603330R40

LED7AMBER-SMTLED001

R393300603

R1033006030603

330R34R35

33006030603

330R36

0603330R37 R38

3300603

LED001AMBER-SMTLED2

AMBER-SMTLED001

LED3AMBER-SMTLED001

LED4AMBER-SMTLED001

LED5

LED001AMBER-SMTLED6

LED9GREEN-SMTLED001

402100R23

1 2

3 4

5 6

7 8

JP5

IDC4X24X2

AMBER-SMTLED001

LED1

B6_L01N_Y3

B6_L01P_Y2

B5_U10_J3_81

B5_AB11_J3_90

PB2

B5_V10_J3_85

B5_U11_J3_83

B5_L31N_D4_W11_J3_39

B5_L30N_AB10_J3_37

B5_L29N_Y10_J3_35

B5_L28N_D6_AB9_J3_33

B5_L27N_W9_J3_31

PB1

B5_L25N_AB8_J3_21

R47

060310K

CHOKE_COIL

4

3

2

1

A B C D

20 Cotton Road

Nashua NH 03063

A B C D

4

3

2

1

PH 1-800-ANALOGD

C

Title

Size Board No

Date Sheet of

DEVICESANALOG

DNP = Do Not Populate

Rev

BLACKFIN FPGA EZ-EXTENDER

A0199-2005 10

25V

33V

VIN

EN

SW

GND

FB

VIN

EN

SW

GND

FB

VIN

EN

SW

GND

FB

4

3

5

2

1

VR3

SOT23-5LM3475MF

1

2

5

3

4

VR2

SOT23-5LM3475MF

4

3

5

2

1

VR1

SOT23-5LM3475MF

12119-27-2005_1124

1

32

Q2

SI2

343D

SS

OT

23D

1

32

Q3

SI2

343D

SS

OT

23D

2 3

1S

I234

3DS

Q1

SO

T23

D

316KR17

0603

215KR18

0603

0603

R11105K

DNPC73

0603

0603

C72DNP

805

C741000PF

0R58

0603

1000PFC10

805

0603

R1910K

C100UFCT2

CT3100UFC

IND005

L110UH

10UHL3

IND005

10UHL2

IND005

1

2 D3

DO214ABSCHOT_RECT

3A

0603

R20200K

805

C639NF

390PFC7

0603

2

1 3A

SCHOT_RECTDO214AB

D2

499KR13

0603

1

2 D1

DO214ABSCHOT_RECT

3A

33V_EI

3

1

2

3X1IDC3X1

P13

UNREG_IN

12V

CT1100UFC

80510UFC71

R1200603

5V_EI

8051000PFC2

FER2

0603

060301UFC3

POWER

FUS00125AF1

4

1

3

2

FER1

DO-214AA

S2A_RECT

2AD5

8051000PFC1 C4

10UFC

3

1

2

3X1IDC3X1

P12

UNREG_IN

1

2

3

CON00525MM_JACK

POWER

J4

2

1P42

IDC2X12X1DNP

1

2

DNP2X1IDC2X1

P43

06030R15

C810UF805

80510UFC9

R1600603

UNREG_IN

0603

R1410K

0603

R590

4

3

2

1

A B C D

20 Cotton Road

Nashua NH 03063

A B C D

4

3

2

1

PH 1-800-ANALOGD

C

Title

Size Board No

Date Sheet of

DEVICESANALOG

DNP = Do Not Populate

Rev

BLACKFIN FPGA EZ-EXTENDER

A0199-2005 1012129-14-2005_1204

5

2

4

8

10

6

1

3

9

11

13

15

17

19

12

14

16

20

18

7

P20

SOIC20

PROTO AREA

1

3

2

SOT23D

P39

2

3

1

SOT23D

P38

2

4

5 6

3

1

SOT23-6

P411

3

65

4

2

SOT23-6

P40

PRT_NUM=DNE

11

13

15 16

14

12

2

4

6

8

109

7

5

3

1

SOIC16

P191

3

5

7

9 10

8

6

4

2

12

14

1615

13

11

SOIC16

P18

21P37

805

1 2

805

P36

21P35

805

1 2

805

P34

1 2

805

P33

21P32

805

1 2

805

P31

21P30

805

1 2

805

P29

21P28

805

1 2

805

P27

21P26

805

21P25

805

1 2

805

P24

21P23

805

1 2

805

P22

TP86

TP85

TP84

TP83

TP82

TP81

TP80

TP79 TP77

TP76

TP75

TP74

TP73

TP72

TP71

TP70

TP68

TP67

TP66

TP65

TP64

TP62

TP61

TP60

TP59

TP58

TP57

TP56

TP55

TP54

TP53

TP51

TP50

TP49

TP48

TP47

TP46

TP45

TP44

TP43

TP41

TP40

TP39

TP38

TP37

TP36

TP35

TP34

TP33

TP32

TP30

TP29

TP28

TP27

TP26

TP25

TP24

TP23

TP22

TP21

TP19

TP18

TP17

TP16

TP15

TP14

TP13

TP12

TP11

TP9

TP8

TP7

TP6

TP5

TP4

TP125

TP124

TP123

TP122

TP121

TP120

TP119

TP118

TP117

TP116

TP114

TP113

TP112

TP111

TP110

TP109

TP108

TP107TP106

TP105TP103

TP102TP101 TP100TP99

TP98 TP97

TP96 TP95

TP94TP93

TP92TP91

TP90 TP89

TP88 TP87

TP78TP69

TP63 TP52

TP42 TP31

TP20 TP10

TP115TP104

7

18

20

16

14

12

19

17

15

13

11

9

3

1

6

10

8

4

2

5

SOIC20

P21

I INDEX

Numerics connectors

25V header (P42) 2-17

AADSP-BF5333761 EZ-KIT Lite interface 2-1ADSP-BF5333761 processors boot mode

settings 2-14architecture of this EZ-Extender 2-2asynchronous static random access memory

(SRAM) xauxiliary oscillator x

Bbill of materials A-1block diagram of this EZ-Extender 2-2boot jumper See JP4

Cconfiguration jumpers See JP2 JP3

map of locations 2-18J1-3 (expansion) 2-19P1-3 (expansion) 2-19P14 (IDC) 2-19P15 (JTAG header) 2-4P16-17 (IDC) 2-19P4 (high-speed) 2-20P5 (IDC) 2-20P6 (JTAG) 2-7P7 (IDC) 2-20P8 (IDC) 2-19

customer support xiii

Ddone LED (LED10) 2-17

Eexpansion interface

connectors (P1-3 J1-3) 2-19of ADSP-BF5333761 EZ-KIT Lites ix

1-3external power supply 1-3 2-8

FField-Programmable Gate Array See FPGA

Blackfin FPGA EZ-Extender Manual I-1

INDEX

FPGAdocumentation 1-2input jumpers (JP5) 2-14softwarefirmware 1-2Xilinx Spartan package x 1-3

FPGA pinsAB10 (LED3) 2-17AB11 (JP58) 2-15AB8 (LED7) 2-17AB9 (LED5) 2-17C11 (PB1SW3) 2-15H5 (PB2SW3) 2-16M2-0 (JP4) 2-14U10 (JP56) 2-15U11 (LED1) 2-17V10 (LED8) 2-17W11 (LED2) 2-17W9 (LED6) 2-17Y10 (LED4) 2-17Y3-2 (JP52-54) 2-15

FPGA programmingblock diagram 2-3via ADSP-BF533376 processors 2-6via JTAG header 2-4via serial ROM 2-5

GGCLK1 (global clock 1) pin 1-4GCLK6 (global clock 6) pin 1-4general-purpose input push buttons 2-15 2-16

Hhigh-speed connector (P4) 2-20

IIDC connectors x 2-19 2-20installation of this EZ-Extender 1-1

JJTAG

cable 1-4 2-7header (P6) 1-5 2-4 2-7 2-14

jumpersmap of locations 2-11JP1 (boot jumper) 2-5 2-12JP2 (confug done) 2-12JP3 (config program) 2-13JP41-46 (boot mode select) 2-5 2-6 2-14JP52-56 (FPGA input) 2-14

LLEDs

map of locations 2-15LED10 (FPGA done pin) 2-4 2-5 2-17LED1-8 (status) 2-17LED9 (power) 2-17

MM2-0 (JP4) pins 2-5master serial boot mode 2-6MCS-86 Hexadecimal Object (mcs) file

format 2-6

Nnotation conventions xvi

Ooscillator x 1-4

PP12 (power in) header 2-9P13 (33V header) 2-9P42 (25V header) 2-10P43 (12V header) 2-10PB1 push button (SW3) 2-15

I-2 Blackfin FPGA EZ-Extender Manual

INDEX

PB2 push button (SW4) 2-16PF14 flag pin (ADSP-BF537 EZ-KIT Lite)

2-12PF3 flag pin (ADSP-BF53361 EZ-KIT Lite)

2-12power

12V header (P43) 2-1025V header (P42) 2-1033V header (P13) 2-9in header (P12) 2-9LED (LED9) 2-17limitations 2-8supplies 1-3 2-8

printed circuit board (PCB) 1-2product overview ixprogram push button (SW1) 2-4 2-15push buttons

See also SWx map of locations 2-15

Sserial ROM 1-5

boot jumper (JP1) 2-12 2-14programming via JTAG Header 2-7

setup of this EZ-Extender 1-1slave serial mode 2-6

SRAM memory banks 1-4status reporting 1-4 2-17SW1 (program) push button 2-4 2-15SW3 (PB1) push button 2-15SW4 (PB2) push button 2-16switching regulators 2-8

TTCK signal 2-7TDI signal 2-7TDO signal 2-7TMS signal 2-7

VVisualDSP++

flash programming utility 1-4 2-6FPGA documentation 2-6

VR1-3 regulators 2-8

XXilinx

JTAG cablesoftware 1-4 2-4 2-7JTAG header 2-12serial ROM 1-5

Blackfin FPGA EZ-Extender Manual I-3

INDEX

I-4 Blackfin FPGA EZ-Extender Manual

• Blackfin FPGA EZ-Extender Manual
• Contents
• Preface
• • Product Overview
  • Purpose of This Manual
  • Intended Audience
  • Manual Contents
  • Whatrsquos New in This Manual
  • Technical or Customer Support
  • Supported Products
  • Product Information
  • • Related Documents
    • • Table 1 Related Processor Publications
      • Table 2 Related VisualDSP++ Publications
      • • Notation Conventions
        • • 1 FPGA EZ-Extender Interfaces
          • • FPGA EZ-Extender Setup
            • • Figure 1-1 FPGA EZ-Extender Setup
              • • FPGA Software and Firmware
                • FPGA EZ-Extender Overview
                • • 2 FPGA EZ-Extender Hardware Reference
                  • • System Architecture
                    • • Figure 2-1 Block Diagram
                      • • Programming the FPGA
                        • • Figure 2-2 FPGA Programming Block Diagram
                          • FPGA Programming via JTAG
                          • • Table 2-1 P15 Connections for PFGA Programming via JTAG
                            • Table 2-2 JP1 Settings for FPGA Programming via JTAG
                            • Table 2-3 JP4 Settings for FPGA Programming via JTAG
                            • • FPGA Programming via Serial ROM
                              • • Table 2-4 JP1 Settings for FPGA Programming via Serial ROM
                                • Table 2-5 JP4 Settings for FPGA Programming in Master Serial Mode
                                • • FPGA Programming via Blackfin Application
                                  • • Table 2-6 JP1 Settings for FPGA Programming via Blackfin Processor
                                    • Table 2-7 JP4 Settings for FPGA Programming via Blackfin Processor
                                    • • Programming the Serial ROM
                                      • • Serial ROM via JTAG Header
                                        • • Table 2-8 P6 Connections for Serial ROM
                                          • • Power
                                            • • Table 2-9 Power Limitations
                                              • Power In Header (P12)
                                              • 33V Header (P13)
                                              • 25V Header (P42)
                                              • 12V Header (P43)
                                              • • Jumpers
                                                • • Figure 2-3 Jumper Locations
                                                  • Serial ROM Boot Jumper (JP1)
                                                  • • Table 2-10 JP1 Settings
                                                    • • Config Done Jumper (JP2)
                                                      • • Table 2-11 JP2 Settings
                                                        • • Config Program Jumper (JP3)
                                                          • • Table 2-12 JP3 Settings
                                                            • • Boot Jumper (JP4)
                                                              • • Table 2-13 JP4 Settings
                                                                • • FPGA Input Jumpers (JP5)
                                                                  • • Table 2-14 JP5 Settings
                                                                    • • Push Buttons and LEDs
                                                                      • • Figure 2-4 Push Button and LED Locations
                                                                        • Program Push Button (SW1)
                                                                        • PB1 Push Button (SW3)
                                                                        • PB2 Push Button (SW4)
                                                                        • Status LEDs (LED1-8)
                                                                        • • Table 2-15 Status LED (LED1-8) Settings
                                                                          • • Power LED (LED9)
                                                                            • Done LED (LED10)
                                                                            • • Connectors
                                                                              • • Figure 2-5 Connector Locations
                                                                                • Expansion Interface (P1-3 and J1-3)
                                                                                • IDC Connectors (P8 P14 P16 and P17)
                                                                                • IDC Connectors (P5 and P7)
                                                                                • High-Speed Connector (P4)
                                                                                • • A Bill Of Materials
                                                                                  • B Schematics
                                                                                  • • Title
                                                                                    • FPGA Config
                                                                                    • SRAM FPGA Banks 7 and 8
                                                                                    • Expansion Interface Connector 1
                                                                                    • FPGA Banks 0 and 1
                                                                                    • Expansion Interface Connectors 2
                                                                                    • FPGA Banks 2 and 3
                                                                                    • Expansion Interface Connector 1
                                                                                    • FPGA Banks 4 and 5
                                                                                    • User IO
                                                                                    • Power
                                                                                    • Proto Area
                                                                                    • • I Index
                                                                                      • • Numerics
                                                                                        • A
                                                                                        • B
                                                                                        • C
                                                                                        • D
                                                                                        • E
                                                                                        • F
                                                                                        • G
                                                                                        • H
                                                                                        • I
                                                                                        • J
                                                                                        • L
                                                                                        • M
                                                                                        • N
                                                                                        • O
                                                                                        • P
                                                                                        • S
                                                                                        • T
                                                                                        • V
                                                                                        • X

4

3

2

1

A B C D

20 Cotton Road

Nashua NH 03063

A B C D

4

3

2

1

PH 1-800-ANALOGD

C

Title

Size Board No

Date Sheet of

DEVICESANALOG

DNP = Do Not Populate

Rev

BLACKFIN FPGA EZ-EXTENDER

A0199-2005 10

EXPANSION INTERFACE TYPE B

P1Expanison Connector

Top Of BoardBottom Of Board

Expansion Connector 1

10-18-2005_1616 4 12

EXPANSION INTERFACE CONNECTOR 1

C3510UF805

01UF0603

C38

5V_EI

5V_EI

1

10

11 12

13 14

15 16

17 18

19

2

20

21 22

23 24

25 26

27 28

29

3

30

31 32

33 34

35 36

37 38

39

4

40

41 42

43 44

45 46

47 48

49

5

50

51 52

53 54

55 56

57 58

59

6

60

61 62

63 64

65 66

67 68

69

7

70

71 72

73 74

75 76

77 78

79

8

80

81 82

83 84

85 86

87 88

89

9

90

P1

CON01845X2

1

10

1112

1314

1516

1718

19

2

20

2122

2324

2526

2728

29

3

30

3132

3334

3536

3738

39

4

40

4142

4344

4546

4748

49

5

50

5152

5354

5556

5758

59

6

60

6162

6364

6566

6768

69

7

70

7172

7374

7576

7778

79

8

80

8182

8384

8586

8788

89

9

90

J1

CON01945X2

PP1

EXPANSION_PPI_CLK

PP3

UDEF2

UDEF4

UDEF6

UDEF8

UDEF10

D9

D7

D15

D13

D11

D5

D1

D3

D15

D9

D5

D1

D3

D0

D2

D4

D6

D8

D10

D14

D12

P1_5

P1_25

P1_27

P1_29

P1_31

P1_33

P1_55

P1_57

P1_59

P1_61

P1_63

P1_65

P1_67

P1_69

P1_35

P1_26

P1_28

P1_30

P1_32

P1_34

P1_56

P1_58

P1_60

P1_62

P1_64

P1_66

P1_68

P1_70

P1_36

P1_26

P1_28

P1_30

P1_32

P1_34

P1_36

P1_56

P1_58

P1_60

P1_62

P1_64

P1_66

P1_68

P1_70

P1_5

P1_25

P1_27

P1_29

P1_31

P1_33

P1_35

P1_55

P1_57

P1_59

P1_61

P1_63

P1_65

P1_67

P1_69

P1_[586]

A5

A6A7

A8A9

A10A11

A12A13

A14A15

A16A17

A18A19

D0

D2

D4

D6D7

D8

D10D11

D12D13

D14

A1

A2

B1_L24N_D15_J1_71B1_L24P_E15_J1_72

B1_L22N_A16_J1_73B1_L22P_B16_J1_74

B1_L19N_C16_J1_75B1_L19P_D16_J1_76

B1_L16N_B17_J1_77B1_L16P_C17_J1_78

B1_L15N_D17_J1_79

A3

B1_L15P_E17_J1_80

B1_L10N_A18_J1_81B1_L10P_B18_J1_82

B1_L09N_C18_J1_83B1_L09P_D18_J1_84

B1_L06N_A19_J1_85B1_L06P_B19_J1_86

A4A5

A6 A7

A8 A9

A10 A11

A12 A13

A14 A15

A16 A17

A18 A19

A1

A2

PP0

PP2

UDEF1

UDEF3

A3

UDEF5

UDEF7

UDEF9

UDEF11

A4

33V

25V 33V

33V

33V

33V

4

3

2

1

A B C D

20 Cotton Road

Nashua NH 03063

A B C D

4

3

2

1

PH 1-800-ANALOGD

C

Title

Size Board No

Date Sheet of

DEVICESANALOG

DNP = Do Not Populate

Rev

BLACKFIN FPGA EZ-EXTENDER

A0199-2005 10

VCCO_0_C8

VCCO_0_F8

VCCO_0_G9

VCCO_0_G10

VCCO_0_G11

IO_A10

IO_D9

IO_D10

IO_F6

IO_VREF_0_A3

IO_VREF_0_C7

IO_VREF_0_E5

IO_VREF_0_F7

IO_L06N_0_D5

IO_L06P_0_C5

IO_L09N_0_B5

IO_L09P_0_A5

IO_L10N_0_E6

IO_L10P_0_D6

IO_L15N_0_C6

IO_L15P_0_B6

IO_L16N_0_E7

IO_L16P_0_D7

IO_L19N_0_B7

IO_L19P_0_A7

IO_L22N_0_E8

IO_L22P_0_D8

IO_L24N_0_B8

IO_L24P_0_A8

IO_L25N_0_F9

IO_L25P_0_E9

IO_L27N_0_B9

IO_L27P_0_A9

IO_L28N_0_F10

IO_L28P_0_E10

IO_L29N_0_C10

IO_L29P_0_B10

IO_L30N_0_F11

IO_L30P_0_E11

IO_L31N_0_D11

IO_L31P_0_VREF_0_C11

IO_L01N_0_VRP_0_B4

IO_L01P_0_VRN_0_A4

IO_L32N_0_GCLK7_B11

IO_L32P_0_GCLK6_A11

VCCO_1_C15

VCCO_1_F15

VCCO_1_G12

VCCO_1_G13

VCCO_1_G14

IO_A12

IO_E16

IO_F12

IO_F13

IO_F16

IO_F17

IO_VREF_1_E13

IO_VREF_1_F14

IO_L06N_1_VREF_1_A19

IO_L06P_1_B19

IO_L09N_1_C18

IO_L09P_1_D18

IO_L10N_1_VREF_1_A18

IO_L10P_1_B18

IO_L15N_1_D17

IO_L15P_1_E17

IO_L16N_1_B17

IO_L16P_1_C17

IO_L19N_1_C16

IO_L19P_1_D16

IO_L22N_1_A16

IO_L22P_1_B16

IO_L24N_1_D15

IO_L24P_1_E15

IO_L25N_1_B15

IO_L25P_1_A15

IO_L27N_1_D14

IO_L27P_1_E14

IO_L28N_1_A14

IO_L28P_1_B14

IO_L29N_1_C13

IO_L29P_1_D13

IO_L30N_1_A13

IO_L30P_1_B13

IO_L31N_1_VREF_1_D12

IO_L31P_1_E12

IO_L01N_1_VRP_1_C19

IO_L01P_1_VRN_1_B20

IO_L32N_1_GCLK5_B12

IO_L32P_1_GCLK4_C12

FPGAFPGA

LAYOUT NOTE PLACE NEAR FPGA

5 129-27-2005_1144

C8

F8

G9

G10

G11

A10

D9

D10

F6

A3

C7

E5

F7

D5

C5

B5

A5

E6

D6

C6

B6

E7

D7

B7

A7

E8

D8

B8

A8

F9

E9

B9

A9

F10

E10

C10

B10

F11

E11

D11

C11

B4

A4

B11

A11

C15

F15

G12

G13

G14

A12

E16

F12

F13

F16

F17

E13

F14

A19

B19

C18

D18

A18

B18

D17

E17

B17

C17

C16

D16

A16

B16

D15

E15

B15

A15

D14

E14

A14

B14

C13

D13

A13

B13

D12

E12

C19

B20

B12

C12

U1

FG456XC3S1000

1

10

11 12

13 14

15 16

17 18

19

2

20

21 22

23 24

25 26

27 28

29

3

30

31 32

33 34

35 36

37 38

4

5 6

7 8

9

39 40

41

43

45

47

49

42

44

46

48

50

25X2CON041

P4

5

1

18

20

22

26

24

16

14

12

25

23

21

19

17

15

13

11

9

3

6

10

8

4

2

7

P8

IDC13X213X2

5

1

18

20

22

26

24

16

14

12

25

23

21

19

17

15

13

11

9

3

6

10

8

4

2

7

P14

IDC13X213X2

FPGA BANKS 0 + 1

001UF0603

C50

DNP0603

R52

B1_L10N_A18_J1_81

B1_L15P_E17_J1_80

R53

0603DNP

B1_L16P_C17_J1_78

R27

06030

B1_L10P_B18_J1_82B1_L10N_A18_J1_81

B1_L15N_D17_J1_79

B1_L16N_B17_J1_77

B1_L24N_D15_J1_71

B1_L22N_A16_J1_73

B1_L19N_C16_J1_75

R51

0603DNPDNP

0603

R50DNP0603

R48

R31

0603DNP

B1_L19N_C16_J1_75

B1_L22N_A16_J1_73

B1_L24N_D15_J1_71

B1_L15N_D17_J1_79

B1_L15P_E17_J1_80

B1_L16N_B17_J1_77

B1_L16P_C17_J1_78

DNP0603

R30

VCCO_1

VCCO_1

C47

0603001UF

VCCO_1

B1_L27N_D14

PB1

AOE

B1_L01P_VRN_B20

B1_L01N_VRP_C19

IO_L32_0_GCLK6_A11

IO_L32_0_GCLK7_B11

IO_L32_0_GCLK7_B11

B1_L32N_GCLK5_B12

B1_L32P_GCLK4_C12 B1_L06P_B19_J1_86

B1_L09P_D18_J1_84

B1_L15P_E17_J1_80

B1_L16P_C17_J1_78

B1_L19P_D16_J1_76

B1_L16N_B17_J1_77

B1_L15N_D17_J1_79

B1_L09N_C18_J1_83

B1_L06N_A19_J1_85

B1_L31P_E12

B1_L31N_D12

B1_L06N_A19_J1_85

B1_L09N_C18_J1_83

B1_L09P_D18_J1_84

B1_L06P_B19_J1_86

B1_F17

B1_F16

B1_E16

B1_F13

B1_E13

B1_F12

B1_A12

B1_F14

B1_L01N_VRP_C19

B1_L01P_VRN_B20

B1_L32P_GCLK4_C12

B1_L32N_GCLK5_B12

AMS3

D5

D4

AMS0

UDEF1

ARE

ARDY

AMS1

AMS2

UDEF11

UDEF9

UDEF7

UDEF5

UDEF3

PP2

PP0

D15

D11

D9

A17

B1_L16P_C17_J1_78

B1_L19P_D16_J1_76

B1_L19N_C16_J1_75

B1_L22P_B16_J1_74

B1_L24N_D15_J1_71

B1_L22N_A16_J1_73

B1_L24P_E15_J1_72

B1_L16N_B17_J1_77

B1_L10P_B18_J1_82

B1_L15P_E17_J1_80

B1_L15N_D17_J1_79

B1_L10N_A18_J1_81

B1_L09P_D18_J1_84

B1_L09N_C18_J1_83

B1_L06P_B19_J1_86

B1_L06N_A19_J1_85

B1_L31N_D12

B1_L30N_A13

B1_L29N_C13

B1_L28N_A14

B1_L27N_D14

B1_L25N_B15

B1_F16

B1_F14

B1_F13

B1_F12

B1_L31P_E12

B1_L30P_B13

B1_L29P_D13

B1_L28P_B14

B1_L27P_E14

B1_L25P_A15

B1_F17

B1_E13

B1_E16

B1_A12

UDEF10

ABE3

ABE1

ABE0

ABE2

AWE

UDEF6

UDEF8

PP3

UDEF4

UDEF2

PP1

D14

D8

D10

D12

B1_L25P_A15B1_L25N_B15

B1_L22N_A16_J1_73

B1_L24N_D15_J1_71

B1_L19N_C16_J1_75

B1_L24P_E15_J1_72

B1_L22P_B16_J1_74

B1_L27P_E14

B1_L19P_D16_J1_76

B1_L22P_B16_J1_74

B1_L24P_E15_J1_72

B1_L25N_B15

B1_L25P_A15

B1_L27N_D14

B1_L27P_E14

B1_L28N_A14

B1_L28P_B14

B1_L29N_C13

B1_L29P_D13

B1_L30N_A13

B1_L30P_B13

B1_L10N_A18_J1_81

B1_L10P_B18_J1_82

3

2

1

3X1IDC3X1

P9

EXPANSION_PPI_CLK

B1_F16 B1_F17

B1_L28P_B14

B1_L29P_D13

B1_L30P_B13

B1_L31P_E12

B1_L28N_A14

B1_L29N_C13

B1_L30N_A13

B1_L31N_D12

B1_E16

B1_E13

B1_A12

B1_L01P_VRN_B20

B1_L32P_GCLK4_C12

B1_F14

B1_L01N_VRP_C19

B1_L32N_GCLK5_B12

B1_F13

B1_F12

B1_L01P_VRN_B20

B1_L01N_VRP_C19

001UF0603

C48 C49

0603001UF

C51

0603001UF 001UF

0603

C52 C53

0603001UF001UF

0603

C54

VCCO_1

R49

0603DNP

B1_L10P_B18_J1_82

DNP0603

R54

4

3

2

1

A B C D

20 Cotton Road

Nashua NH 03063

A B C D

4

3

2

1

PH 1-800-ANALOGD

C

Title

Size Board No

Date Sheet of

DEVICESANALOG

DNP = Do Not Populate

Rev

BLACKFIN FPGA EZ-EXTENDER

A0199-2005 10Expanison ConnectorP2

Bottom Of Board Top Of Board

Expansion Connector 2

33V_EI

6 129-14-2005_1203

EXPANSION INTERFACE CONNECTOR 2

SCK

NMI

TMR1

PF1

PF3

PF5

PF7

PF9

PF11

PF13

PF15

1

10

11 12

13 14

15 16

17 18

19 20

21 22

23 24

25 26

27 28

29

3

30

31 32

33 34

35 36

37 38

39

4

40

41 42

43 44

45 46

47 48

49

5

50

51 52

53 54

55 56

57 58

59

6

60

61 62

63 64

65 66

67 68

69

7

70

71 72

73 74

75 76

77 78

79

8

80

81 82

83 84

85 86

87 88

89

9

90

2P2

CON01845X2

1

10

1112

1314

1516

1718

19

2

20

2122

2324

2526

2728

29

3

30

3132

3334

3536

3738

39

4

40

4142

4344

4546

4748

49

5

50

5152

5354

5556

5758

59

6

60

6162

6364

6566

6768

69

7

70

7172

7374

7576

7778

79

8

80

8182

8384

8586

8788

89

9

90

J2

CON01945X2

ARE

ARDY

AMS0

AMS1

P2_21

P2_19

P2_7

P2_21

P2_71

P2_73

P2_77

P2_79

P2_83

P2_85

P2_81

P2_19

P2_15

P2_5 P2_6

P2_8

P2_22

P2_86

P2_84

P2_82

P2_80

P2_78

P2_74

P2_72

P2_20

P2_18

P2_22

P2_74

P2_78

P2_82

P2_84

P2_86

P2_80

P2_72

P2_20

P2_18

P2_8

P2_6

P2_[586]

P2_5

P2_7

P2_15

P2_85

P2_83

P2_81

P2_79

P2_77

P2_73

P2_71AWE

AOE

ABE0

ABE1

ABE2

ABE3

TSCLK0

TFS0

DT0PRI

DT0SEC

CONFIG_CLK_TSCLK1

CONFIG_INIT_B_TFS1

DT1PRI

DT1SEC

TMR0

TMR2

PF14

PF12

PF10

PF8

PF4

PF6

PF2

PF0

B2_L40N_L21_J2_9

B2_L39N_L19_J2_11

B2_C22_J2_17

B2_L38N_L17_J2_23

B2_L35N_K21_J2_25

B2_L34N_K19_J2_27

B2_L33N_K17_J2_29

B2_L32N_J21_J2_31

B2_L31N_J18_J2_33

B2_L29N_H21_J2_35

B2_L28N_H18_J2_37

B2_L27N_G21_J2_39

B2_L26N_G20_J2_41

B2_L22N_G17_J2_43

B2_L24N_F20_J2_45

B2_L23N_F19_J2_47

B2_L21N_E21_J2_49

B2_L20N_E19_J2_51

B2_L19N_E18_J2_53

B2_L17N_D21_J2_55

B2_L16N_D20_J2_57B2_L16P_D19_J2_58

B2_L17P_D22_J2_56

B2_L19P_F18_J2_54

B2_L20P_E20_J2_52

B2_L21P_E22_J2_50

B2_L23P_G19_J2_48

B2_L24P_F21_J2_46

B2_L22P_G18_J2_44

B2_L26P_H19_J2_42

B2_L27P_G22_J2_40

B2_L28P_J17_J2_38

B2_L29P_H22_J2_36

B2_L31P_J19_J2_34

B2_L32P_J22_J2_32

B2_L33P_K18_J2_30

B2_L34P_K20_J2_28

B2_L35P_K22_J2_26

B2_L38P_L18_J2_24

IO_L01P_2_VRN_2_C21_J2_16

B2_L40P_L22_J2_10

B2_L39P_L20_J2_12

MOSI

MISO

UDEF12

AMS3

AMS2

AMS0

ARDY

AMS1

AREAWE

AOE

ABE0

ABE1

ABE2

ABE3

RSCLK1

RSCLK0

RFS1

DR1PRI

DR1SEC

AMS2

AMS3

DR0SEC

DR0PRI

RFS0

TMR3

SPIDS0

C56

060301UF

80510UFC55

33V_EI

33V

4

3

2

1

A B C D

20 Cotton Road

Nashua NH 03063

A B C D

4

3

2

1

PH 1-800-ANALOGD

C

Title

Size Board No

Date Sheet of

DEVICESANALOG

DNP = Do Not Populate

Rev

BLACKFIN FPGA EZ-EXTENDER

A0199-2005 10

33V

25V33V

33V

33V

VCCO_2_H17

VCCO_2_H20

VCCO_2_J16

VCCO_2_K16

VCCO_2_L16

IO_C22

IO_L16N_2_D20

IO_L16P_2_D19

IO_L17N_2_D21

IO_L17P_2_VREF_2_D22

IO_L19N_2_E18

IO_L19P_2_F18

IO_L20N_2_E19

IO_L20P_2_E20

IO_L21N_2_E21

IO_L21P_2_E22

IO_L22N_2_G17

IO_L22P_2_G18

IO_L23N_2_VREF_2_F19

IO_L23P_2_G19

IO_L24N_2_F20

IO_L24P_2_F21

IO_L26N_2_G20

IO_L26P_2_H19

IO_L27N_2_G21

IO_L27P_2_G22

IO_L28N_2_H18

IO_L28P_2_J17

IO_L29N_2_H21

IO_L29P_2_H22

IO_L31N_2_J18

IO_L31P_2_J19

IO_L32N_2_J21

IO_L32P_2_J22

IO_L33N_2_K17

IO_L33P_2_K18

IO_L34N_2_VREF_2_K19

IO_L34P_2_K20

IO_L35N_2_K21

IO_L35P_2_K22

IO_L38N_2_L17

IO_L38P_2_L18

IO_L39N_2_L19

IO_L39P_2_L20

IO_L40N_2_L21

IO_L40P_2_VREF_2_L22

IO_L01N_2_VRP_2_C20

IO_L01P_2_VRN_2_C21

VCCO_3_M16

VCCO_3_N16

VCCO_3_P16

VCCO_3_R17

VCCO_3_R20

IO_L16N_3_W22

IO_L16P_3_Y22

IO_L17N_3_V19

IO_L17P_3_VREF_3_W19

IO_L19N_3_W21

IO_L19P_3_W20

IO_L20N_3_U19

IO_L20P_3_V20

IO_L21N_3_V22

IO_L21P_3_V21

IO_L22N_3_T17

IO_L22P_3_U18

IO_L23N_3_U21

IO_L23P_3_VREF_3_U20

IO_L24N_3_R18

IO_L24P_3_T18

IO_L26N_3_T20

IO_L26P_3_T19

IO_L27N_3_T22

IO_L27P_3_T21

IO_L28N_3_R22

IO_L28P_3_R21

IO_L29N_3_P19

IO_L29P_3_R19

IO_L31N_3_P18

IO_L31P_3_P17

IO_L32N_3_P22

IO_L32P_3_P21

IO_L33N_3_N18

IO_L33P_3_N17

IO_L34N_3_N20

IO_L34P_3_VREF_3_N19

IO_L35N_3_N22

IO_L35P_3_N21

IO_L38N_3_M18

IO_L38P_3_M17

IO_L39N_3_M20

IO_L39P_3_M19

IO_L40N_3_VREF_3_M22

IO_L40P_3_M21

IO_L01N_3_VRP_3_Y20

IO_L01P_3_VRN_3_Y19

IO_Y21

FPGAFPGA

LAYOUT NOTE PLACE NEAR FPGA

9-27-2005_1144 7 12

H17

H20

J16

K16

L16

C22

D20

D19

D21

D22

E18

F18

E19

E20

E21

E22

G17

G18

F19

G19

F20

F21

G20

H19

G21

G22

H18

J17

H21

H22

J18

J19

J21

J22

K17

K18

K19

K20

K21

K22

L17

L18

L19

L20

L21

L22

C20

C21

M16

N16

P16

R17

R20

W22

Y22

V19

W19

W21

W20

U19

V20

V22

V21

T17

U18

U21

U20

R18

T18

T20

T19

T22

T21

R22

R21

P19

R19

P18

P17

P22

P21

N18

N17

N20

N19

N22

N21

M18

M17

M20

M19

M22

M21

Y20

Y19

Y21

U1

FG456XC3S1000

2

4

8

10

6

12

14

16

24

22

20

18

26

28

3

5

7

9

11

13

15

17

19

21

23

25

27

1P5

IDC14X214X2

1

27

25

23

21

19

17

15

13

11

9

7

5

3

28

26

18

20

22

24

16

14

12

6

10

8

4

2P7

IDC14X214X2

VCCO_2

B2_L26P_H19_J2_42

DNP0603

R55B2_L24P_F21_J2_46

R56

0603DNP

B2_L23P_G19_J2_48

B2_L26N_G20_J2_41

B2_L24N_F20_J2_45

B2_L23N_F19_J2_47 B2_L23P_G19_J2_48

B2_L24P_F21_J2_46

B2_L26P_H19_J2_42

R32

0603DNP

TMR0

VCCO_2

PF221

2X1IDC2X1

JP3

CONFIG_PROG_B

1 2JP2

IDC2X12X1

PF3

CONFIG_INIT_B_TFS1

CONFIG_CLK_TSCLK1

RSCLK1

RFS1

IO_L01N_2_VRP_2_C20

IO_L01P_2_VRN_2_C21_J2_16

B2_L22N_G17_J2_43

B2_L22P_G18_J2_44

B2_L32N_J21_J2_31

SPIDS0

PF0

SCK

NMI

TMR1

DR1SEC

TMR3

DR0PRI

DR1PRI

RFS0

DR0SEC

PF15

PF13

RSCLK0

PF7

PF9

PF6

PF11

PF1

PF3

PF5

MOSI

MISO

UDEF12

TMR2

DT1SEC

DT1PRI

DT0SEC

TSCLK0

PF14

PF12

PF10

PF8

PF4

PF2

FPGA BANKS 2 + 3

DT0PRI

TFS0

B2_L40P_L22_J2_10

B2_L40N_L21_J2_9

B2_L39P_L20_J2_12

B2_L39N_L19_J2_11

B2_L38P_L18_J2_24

B2_L38N_L17_J2_23

B2_L35P_K22_J2_26

B2_L35N_K21_J2_25

B2_L34P_K20_J2_28

B2_L34N_K19_J2_27

B2_L33P_K18_J2_30

B2_L33N_K17_J2_29

B2_L32P_J22_J2_32

B2_L31P_J19_J2_34

B2_L31N_J18_J2_33

B2_L29P_H22_J2_36

B2_L29N_H21_J2_35

B2_L28P_J17_J2_38

B2_L28N_H18_J2_37

B2_L27P_G22_J2_40

B2_L27N_G21_J2_39

B2_L26P_H19_J2_42

B2_L26N_G20_J2_41

B2_L24P_F21_J2_46

B2_L24N_F20_J2_45

B2_L23P_G19_J2_48

B2_L23N_F19_J2_47

B2_L21P_E22_J2_50

B2_L21N_E21_J2_49

B2_L20P_E20_J2_52

B2_L20N_E19_J2_51

B2_L19P_F18_J2_54

B2_L19N_E18_J2_53

B2_L17P_D22_J2_56

B2_L17N_D21_J2_55

B2_L16P_D19_J2_58

B2_L16N_D20_J2_57

B2_C22_J2_17

3

2

1

3X1IDC3X1

P10

IO_L01P_2_VRN_2_C21_J2_16

IO_L01N_2_VRP_2_C20

VCCO_2

CONFIG_DONE

B2_L22N_G17_J2_43

B2_L17N_D21_J2_55

B2_L19N_E18_J2_53

B2_L20N_E19_J2_51

B2_L21N_E21_J2_49

B2_L16N_D20_J2_57

IO_L01N_2_VRP_2_C20

B2_L16P_D19_J2_58

B2_L20P_E20_J2_52

B2_L19P_F18_J2_54

B2_L17P_D22_J2_56

B2_L22P_G18_J2_44

B2_L21P_E22_J2_50

B2_C22_J2_17

IO_L01P_2_VRN_2_C21_J2_16

B2_L40N_L21_J2_9

B2_L39N_L19_J2_11

B2_L38N_L17_J2_23

B2_L35N_K21_J2_25

B2_L34N_K19_J2_27

B2_L33N_K17_J2_29

B2_L32N_J21_J2_31

B2_L31N_J18_J2_33

B2_L29N_H21_J2_35

B2_L28N_H18_J2_37

B2_L27N_G21_J2_39

B2_L40P_L22_J2_10

B2_L34P_K20_J2_28

B2_L35P_K22_J2_26

B2_L38P_L18_J2_24

B2_L39P_L20_J2_12

B2_L33P_K18_J2_30

B2_L32P_J22_J2_32

B2_L28P_J17_J2_38

B2_L31P_J19_J2_34

B2_L29P_H22_J2_36

B2_L27P_G22_J2_40

DNP0603

R33

B2_L23N_F19_J2_47

B2_L24N_F20_J2_45

B2_L26N_G20_J2_41

DNP0603

R57

001UF0603

C60 C59

0603001UF 001UF

0603

C58 C57

0603001UF

C82

0603001UF 001UF

0603

C81 C62

0603001UF001UF

0603

C61

VCCO_2

4

3

2

1

A B C D

20 Cotton Road

Nashua NH 03063

A B C D

4

3

2

1

PH 1-800-ANALOGD

C

Title

Size Board No

Date Sheet of

DEVICESANALOG

DNP = Do Not Populate

Rev

BLACKFIN FPGA EZ-EXTENDER

A0199-2005 10

Expanison ConnectorExpanison Connector

Bottom Of Board Top Of BoardExpansion Connector 3

EXPANSION INTERFACE (TYPE B)

P3P3

9-9-2005_1029 128

EXPANSION INTERFACE CONNECTOR 1

33V_EI5V_EI

1

10

11 12

13 14

15 16

17 18

19

2

20

21 22

23 24

25 26

27 28

29

3

30

31 32

33 34

35 36

37 38

39

4

40

41 42

43 44

45 46

47 48

49

5

50

51 52

53 54

55 56

57 58

59

6

60

61 62

63 64

65 66

67 68

69

7

70

71 72

73 74

75 76

77 78

79

8

80

81 82

83 84

85 86

87 88

89

9

90

P3

CON01845X2

1

10

1112

1314

1516

1718

19

2

20

2122

2324

2526

2728

29

3

30

3132

3334

3536

3738

39

4

40

4142

4344

4546

4748

49

5

50

5152

5354

5556

5758

59

6

60

6162

6364

6566

6768

69

7

70

7172

7374

7576

7778

79

8

80

8182

8384

8586

8788

89

9

90

J3

CON01945X2

TX0

TX1

UDEF17

UDEF19

UDEF21

UDEF23

UDEF25

UDEF29

UDEF27

RESET

UDEF32

UDEF34

UDEF36

UDEF38

UDEF40

B5_L01N_RDWR_B_Y4_J3_1

P3_42

P3_[190]

P3_86

P3_84

P3_82

P3_80

P3_78

P3_76

P3_74

P3_72

P3_70

P3_68

P3_64

P3_62

P3_60

P3_58

P3_56

P3_54

P3_52

P3_50

P3_48

P3_46

P3_42

P3_79

P3_89

P3_77

P3_75

P3_73

P3_71

P3_69

P3_67

P3_63

P3_61

P3_59

P3_57

P3_55

P3_53

P3_51

P3_49

P3_47

P3_45

P3_51

P3_79

P3_89

P3_77

P3_75

P3_73

P3_71

P3_69

P3_67

P3_63

P3_61

P3_59

P3_57

P3_55

P3_53

P3_49

P3_47

P3_45

P3_86

P3_84

P3_82

P3_80

P3_78

P3_76

P3_74

P3_72

P3_70

P3_68

P3_64

P3_62

P3_60

P3_58

P3_56

P3_54

P3_52

P3_50

P3_48

P3_46

B5_L27N_W9_J3_31

B5_L28N_D6_AB9_J3_33

B5_L29N_Y10_J3_35

B5_L30N_AB10_J3_37

B5_L31N_D4_W11_J3_39

B5_L10N_VRP_AB5_J3_9

B5_L25N_AB8_J3_21

B5_L24N_W8_J3_19

B5_L22N_AB7_J3_17

B5_L19N_Y7_J3_15

B5_L16N_AA6_J3_13

B5_L15N_W6_J3_11

B5_L09N_Y5_J3_7

B5_L06N_AB4_J3_5

B5_U6_J3_23

B5_V7_J3_29

B5_U9_J3_41

B5_L31P_D5_V11_J3_40

B5_L30P_AA10_J3_38

B5_L29P_W10_J3_36

B5_L28P_D7_AA9_J3_34

B5_L27P_V9_J3_32

B5_L32N_GCLK3_AA11_J3_30

B5_U7_J3_28

B5_L25P_AA8_J3_22

B5_L24P_V8_J3_20

B5_L22P_AA7_J3_18

B5_L19P_W7_J3_16

B5_L16P_Y6_J3_14

B5_L15P_V6_J3_12

B5_L10P_VRN_AA5_J3_10

B5_L09P_W5_J3_8

B5_L06P_AA4_J3_6

B5_L01P_CS_B_AA3_J3_2

B5_AB11_J3_90

B5_U11_J3_83

B5_V10_J3_85

B5_U10_J3_81

UDEF43

BGH

BG

BR

UDEF30

UDEF28

UDEF26

UDEF24

UDEF22

UDEF20

UDEF18

UDEF16

RX1

RX0

UDEF14 UDEF15

CLK_OUT_EXP1

UDEF31

UDEF33

UDEF35

UDEF37

UDEF39

UDEF41

33V_EI

C84

060301UF

80510UFC83

C8610UF805

01UF0603

C85

5V_EI

33V

33V

25V 33V

33V

33V

33V

4

3

2

1

A B C D

20 Cotton Road

Nashua NH 03063

A B C D

4

3

2

1

PH 1-800-ANALOGD

C

Title

Size Board No

Date Sheet of

DEVICESANALOG

DNP = Do Not Populate

Rev

BLACKFIN FPGA EZ-EXTENDER

A0199-2005 10

VCCO_4_T12

VCCO_4_T13

VCCO_4_T14

VCCO_4_U15

VCCO_4_Y15

IO_U16

IO_U17

IO_W13

IO_W14

IO_VREF_4_V18

IO_VREF_4_Y16

IO_VREF_4_AB13

IO_L05N_4_AA19

IO_L05P_4_AB19

IO_L06N_4_VREF_4_W18

IO_L06P_4_Y18

IO_L09N_4_AA18

IO_L09P_4_AB18

IO_L10N_4_V17

IO_L10P_4_W17

IO_L15N_4_Y17

IO_L15P_4_AA17

IO_L16N_4_V16

IO_L16P_4_W16

IO_L19N_4_AA16

IO_L19P_4_AB16

IO_L22N_4_VREF_4_V15

IO_L22P_4_W15

IO_L24N_4_AA15

IO_L24P_4_AB15

IO_L25N_4_U14

IO_L25P_4_V14

IO_L27N_4_DIN_D0_AA14

IO_L27P_4_D1_AB14

IO_L28N_4_U13

IO_L28P_4_V13

IO_L29N_4_Y13

IO_L29P_4_AA13

IO_L30N_4_D2_U12

IO_L30P_4_D3_V12

IO_L31N_4_INIT_B_W12

IO_L31P_4_DOUT_BUSY_Y12

IO_L01N_4_VRP_4_AA20

IO_L01P_4_VRN_4_AB20

IO_L32N_4_GCLK1_AA12

IO_L32P_4_GCLK0_AB12

VCCO_5_T9

VCCO_5_T10

VCCO_5_T11

VCCO_5_U8

VCCO_5_Y8

IO_U7

IO_U9

IO_U10

IO_U11

IO_V7

IO_V10

IO_VREF_5_U6

IO_VREF_5_AB11

IO_L01N_5_RDWR_B_Y4

IO_L01P_5_CS_B_AA3

IO_L06N_5_AB4

IO_L06P_5_AA4

IO_L09N_5_Y5

IO_L09P_5_W5

IO_L15N_5_W6

IO_L15P_5_V6

IO_L16N_5_AA6

IO_L16P_5_Y6

IO_L19N_5_Y7

IO_L19P_5_VREF_5_W7

IO_L22N_5_AB7

IO_L22P_5_AA7

IO_L24N_5_W8

IO_L24P_5_V8

IO_L25N_5_AB8

IO_L25P_5_AA8

IO_L27N_5_VREF_5_W9

IO_L27P_5_V9

IO_L28N_5_D6_AB9

IO_L28P_5_D7_AA9

IO_L29N_5_Y10

IO_L29P_5_VREF_5_W10

IO_L30N_5_AB10

IO_L30P_5_AA10

IO_L31N_5_D4_W11

IO_L31P_5_D5_V11

IO_L32N_5_GCLK3_AA11

IO_L32P_5_GCLK2_Y11

IO_L10N_5_VRP_5_AB5

IO_L10P_5_VRN_5_AA5

FPGAFPGA

1299-27-2005_1144

T12

T13

T14

U15

Y15

U16

U17

W13

W14

V18

Y16

AB13

AA19

AB19

W18

Y18

AA18

AB18

V17

W17

Y17

AA17

V16

W16

AA16

AB16

V15

W15

AA15

AB15

U14

V14

AA14

AB14

U13

V13

Y13

AA13

U12

V12

W12

Y12

AA20

AB20

AA12

AB12

T9

T10

T11

U8

Y8

U7

U9

U10

U11

V7

V10

U6

AB11

Y4

AA3

AB4

AA4

Y5

W5

W6

V6

AA6

Y6

Y7

W7

AB7

AA7

W8

V8

AB8

AA8

W9

V9

AB9

AA9

Y10

W10

AB10

AA10

W11

V11

AA11

Y11

AB5

AA5

U1

FG456XC3S1000

7

2

4

8

10

6

3

9

11

13

15

17

19

21

23

25

12

14

16

24

26

22

20

18

1

5

P16

IDC13X213X2

5

1

18

20

22

26

24

16

14

12

25

23

21

19

17

15

13

11

9

3

6

10

8

4

2

7

P17

IDC13X213X2

R46

060310K

R43

0603DNP

FPGA BANKS 4 + 5

VCCO_5

CONFIG_INIT_B_TFS1

CLK_OUT_EXP1

B4_L32N_GCKL1_AA12

R9

06030

B5_L10N_VRP_AB5_J3_9

B5_L10N_VRP_AB5_J3_9

B5_L10P_VRN_AA5_J3_10

VCCO_5

B5_L32P_GCLK2_Y1

B5_L32N_GCLK3_AA11_J3_30

CONFIG_DIN_DT1PRI

UDEF16

UDEF38

UDEF14

RX0

TX0

RX1

TX1

UDEF20

UDEF21

UDEF23

UDEF17

UDEF25

UDEF24

UDEF22

RESET

UDEF30

UDEF29

UDEF27

UDEF26

UDEF35

UDEF34

UDEF33

UDEF32

UDEF31

UDEF15

UDEF28

UDEF41

UDEF40

UDEF39

UDEF37

UDEF36

BR

UDEF43

BG

BGH

UDEF19

B5_L31P_D5_V11_J3_40

B5_L31N_D4_W11_J3_39

B5_L30P_AA10_J3_38

B5_L30N_AB10_J3_37

B5_L29P_W10_J3_36

B5_L29N_Y10_J3_35

B5_L28P_D7_AA9_J3_34

B5_L28N_D6_AB9_J3_33

B5_L27P_V9_J3_32

B5_L27N_W9_J3_31

B5_L25P_AA8_J3_22

B5_L25N_AB8_J3_21

B5_L24P_V8_J3_20

B5_L24N_W8_J3_19

B5_L22P_AA7_J3_18

B5_L22N_AB7_J3_17

B5_L19P_W7_J3_16

B5_L19N_Y7_J3_15

B5_L16P_Y6_J3_14

B5_L16N_AA6_J3_13

B5_L15P_V6_J3_12

B5_L15N_W6_J3_11

B5_L09P_W5_J3_8

B5_L09N_Y5_J3_7

B5_L06P_AA4_J3_6

B5_L06N_AB4_J3_5

B5_L01P_CS_B_AA3_J3_2

B5_L01N_RDWR_B_Y4_J3_1

B5_AB11_J3_90

B5_U6_J3_23

B5_V10_J3_85

B5_V7_J3_29

B5_U11_J3_83

B5_U10_J3_81

B5_U9_J3_41

B5_U7_J3_28

UDEF18

3

2

1

3X1IDC3X1

P11

B5_L29N_Y10_J3_35

B5_L30N_AB10_J3_37

B5_L31N_D4_W11_J3_39

B5_U11_J3_83

B5_V10_J3_85B5_AB11_J3_90

B5_U10_J3_81

B5_L31P_D5_V11_J3_40

B5_L30P_AA10_J3_38

B5_L29P_W10_J3_36

B5_L28P_D7_AA9_J3_34

B5_L27P_V9_J3_32

B5_L28N_D6_AB9_J3_33

B5_L27N_W9_J3_31

B5_L25N_AB8_J3_21B5_L25P_AA8_J3_22

B5_L24N_W8_J3_19B5_L24P_V8_J3_20

B5_U9_J3_41B5_U6_J3_23

VCCO_5

B5_L10P_VRN_AA5_J3_10

C70

0603001UF 001UF

0603

C69 C68

0603001UF001UF

0603

C67001UF0603

C66 C65

0603001UF 001UF

0603

C64C63

0603001UF

B5_L09N_Y5_J3_7

B5_U7_J3_28 B5_V7_J3_29

B5_L10P_VRN_AA5_J3_10 B5_L10N_VRP_AB5_J3_9

B5_L15P_V6_J3_12 B5_L15N_W6_J3_11

B5_L16P_Y6_J3_14 B5_L16N_AA6_J3_13

B5_L19P_W7_J3_16 B5_L19N_Y7_J3_15

B5_L22P_AA7_J3_18 B5_L22N_AB7_J3_17

B5_L32N_GCLK3_AA11_J3_30 B5_L32P_GCLK2_Y1

B5_L01P_CS_B_AA3_J3_2 B5_L01N_RDWR_B_Y4_J3_1

B5_L06P_AA4_J3_6 B5_L06N_AB4_J3_5

B5_L09P_W5_J3_8

VCCO_5

DNP0603

R45

25V

33V

33V

4

3

2

1

A B C D

20 Cotton Road

Nashua NH 03063

A B C D

4

3

2

1

PH 1-800-ANALOGD

C

Title

Size Board No

Date Sheet of

DEVICESANALOG

DNP = Do Not Populate

Rev

BLACKFIN FPGA EZ-EXTENDER

A0199-2005 10

SN74LVC1G125

12109-27-2005_1144

2 4

1

SOT23-5SN74LVC1G125

U8

USER IO

C80

0603001UF

SW4SWT013SPST-MOMENTARY

SPST-MOMENTARYSWT013SW3

060310R42

C5

06031UF

R413300603

LED001AMBER-SMTLED8

0603330R40

LED7AMBER-SMTLED001

R393300603

R1033006030603

330R34R35

33006030603

330R36

0603330R37 R38

3300603

LED001AMBER-SMTLED2

AMBER-SMTLED001

LED3AMBER-SMTLED001

LED4AMBER-SMTLED001

LED5

LED001AMBER-SMTLED6

LED9GREEN-SMTLED001

402100R23

1 2

3 4

5 6

7 8

JP5

IDC4X24X2

AMBER-SMTLED001

LED1

B6_L01N_Y3

B6_L01P_Y2

B5_U10_J3_81

B5_AB11_J3_90

PB2

B5_V10_J3_85

B5_U11_J3_83

B5_L31N_D4_W11_J3_39

B5_L30N_AB10_J3_37

B5_L29N_Y10_J3_35

B5_L28N_D6_AB9_J3_33

B5_L27N_W9_J3_31

PB1

B5_L25N_AB8_J3_21

R47

060310K

CHOKE_COIL

4

3

2

1

A B C D

20 Cotton Road

Nashua NH 03063

A B C D

4

3

2

1

PH 1-800-ANALOGD

C

Title

Size Board No

Date Sheet of

DEVICESANALOG

DNP = Do Not Populate

Rev

BLACKFIN FPGA EZ-EXTENDER

A0199-2005 10

25V

33V

VIN

EN

SW

GND

FB

VIN

EN

SW

GND

FB

VIN

EN

SW

GND

FB

4

3

5

2

1

VR3

SOT23-5LM3475MF

1

2

5

3

4

VR2

SOT23-5LM3475MF

4

3

5

2

1

VR1

SOT23-5LM3475MF

12119-27-2005_1124

1

32

Q2

SI2

343D

SS

OT

23D

1

32

Q3

SI2

343D

SS

OT

23D

2 3

1S

I234

3DS

Q1

SO

T23

D

316KR17

0603

215KR18

0603

0603

R11105K

DNPC73

0603

0603

C72DNP

805

C741000PF

0R58

0603

1000PFC10

805

0603

R1910K

C100UFCT2

CT3100UFC

IND005

L110UH

10UHL3

IND005

10UHL2

IND005

1

2 D3

DO214ABSCHOT_RECT

3A

0603

R20200K

805

C639NF

390PFC7

0603

2

1 3A

SCHOT_RECTDO214AB

D2

499KR13

0603

1

2 D1

DO214ABSCHOT_RECT

3A

33V_EI

3

1

2

3X1IDC3X1

P13

UNREG_IN

12V

CT1100UFC

80510UFC71

R1200603

5V_EI

8051000PFC2

FER2

0603

060301UFC3

POWER

FUS00125AF1

4

1

3

2

FER1

DO-214AA

S2A_RECT

2AD5

8051000PFC1 C4

10UFC

3

1

2

3X1IDC3X1

P12

UNREG_IN

1

2

3

CON00525MM_JACK

POWER

J4

2

1P42

IDC2X12X1DNP

1

2

DNP2X1IDC2X1

P43

06030R15

C810UF805

80510UFC9

R1600603

UNREG_IN

0603

R1410K

0603

R590

4

3

2

1

A B C D

20 Cotton Road

Nashua NH 03063

A B C D

4

3

2

1

PH 1-800-ANALOGD

C

Title

Size Board No

Date Sheet of

DEVICESANALOG

DNP = Do Not Populate

Rev

BLACKFIN FPGA EZ-EXTENDER

A0199-2005 1012129-14-2005_1204

5

2

4

8

10

6

1

3

9

11

13

15

17

19

12

14

16

20

18

7

P20

SOIC20

PROTO AREA

1

3

2

SOT23D

P39

2

3

1

SOT23D

P38

2

4

5 6

3

1

SOT23-6

P411

3

65

4

2

SOT23-6

P40

PRT_NUM=DNE

11

13

15 16

14

12

2

4

6

8

109

7

5

3

1

SOIC16

P191

3

5

7

9 10

8

6

4

2

12

14

1615

13

11

SOIC16

P18

21P37

805

1 2

805

P36

21P35

805

1 2

805

P34

1 2

805

P33

21P32

805

1 2

805

P31

21P30

805

1 2

805

P29

21P28

805

1 2

805

P27

21P26

805

21P25

805

1 2

805

P24

21P23

805

1 2

805

P22

TP86

TP85

TP84

TP83

TP82

TP81

TP80

TP79 TP77

TP76

TP75

TP74

TP73

TP72

TP71

TP70

TP68

TP67

TP66

TP65

TP64

TP62

TP61

TP60

TP59

TP58

TP57

TP56

TP55

TP54

TP53

TP51

TP50

TP49

TP48

TP47

TP46

TP45

TP44

TP43

TP41

TP40

TP39

TP38

TP37

TP36

TP35

TP34

TP33

TP32

TP30

TP29

TP28

TP27

TP26

TP25

TP24

TP23

TP22

TP21

TP19

TP18

TP17

TP16

TP15

TP14

TP13

TP12

TP11

TP9

TP8

TP7

TP6

TP5

TP4

TP125

TP124

TP123

TP122

TP121

TP120

TP119

TP118

TP117

TP116

TP114

TP113

TP112

TP111

TP110

TP109

TP108

TP107TP106

TP105TP103

TP102TP101 TP100TP99

TP98 TP97

TP96 TP95

TP94TP93

TP92TP91

TP90 TP89

TP88 TP87

TP78TP69

TP63 TP52

TP42 TP31

TP20 TP10

TP115TP104

7

18

20

16

14

12

19

17

15

13

11

9

3

1

6

10

8

4

2

5

SOIC20

P21

I INDEX

Numerics connectors

25V header (P42) 2-17

AADSP-BF5333761 EZ-KIT Lite interface 2-1ADSP-BF5333761 processors boot mode

settings 2-14architecture of this EZ-Extender 2-2asynchronous static random access memory

(SRAM) xauxiliary oscillator x

Bbill of materials A-1block diagram of this EZ-Extender 2-2boot jumper See JP4

Cconfiguration jumpers See JP2 JP3

map of locations 2-18J1-3 (expansion) 2-19P1-3 (expansion) 2-19P14 (IDC) 2-19P15 (JTAG header) 2-4P16-17 (IDC) 2-19P4 (high-speed) 2-20P5 (IDC) 2-20P6 (JTAG) 2-7P7 (IDC) 2-20P8 (IDC) 2-19

customer support xiii

Ddone LED (LED10) 2-17

Eexpansion interface

connectors (P1-3 J1-3) 2-19of ADSP-BF5333761 EZ-KIT Lites ix

1-3external power supply 1-3 2-8

FField-Programmable Gate Array See FPGA

Blackfin FPGA EZ-Extender Manual I-1

INDEX

FPGAdocumentation 1-2input jumpers (JP5) 2-14softwarefirmware 1-2Xilinx Spartan package x 1-3

FPGA pinsAB10 (LED3) 2-17AB11 (JP58) 2-15AB8 (LED7) 2-17AB9 (LED5) 2-17C11 (PB1SW3) 2-15H5 (PB2SW3) 2-16M2-0 (JP4) 2-14U10 (JP56) 2-15U11 (LED1) 2-17V10 (LED8) 2-17W11 (LED2) 2-17W9 (LED6) 2-17Y10 (LED4) 2-17Y3-2 (JP52-54) 2-15

FPGA programmingblock diagram 2-3via ADSP-BF533376 processors 2-6via JTAG header 2-4via serial ROM 2-5

GGCLK1 (global clock 1) pin 1-4GCLK6 (global clock 6) pin 1-4general-purpose input push buttons 2-15 2-16

Hhigh-speed connector (P4) 2-20

IIDC connectors x 2-19 2-20installation of this EZ-Extender 1-1

JJTAG

cable 1-4 2-7header (P6) 1-5 2-4 2-7 2-14

jumpersmap of locations 2-11JP1 (boot jumper) 2-5 2-12JP2 (confug done) 2-12JP3 (config program) 2-13JP41-46 (boot mode select) 2-5 2-6 2-14JP52-56 (FPGA input) 2-14

LLEDs

map of locations 2-15LED10 (FPGA done pin) 2-4 2-5 2-17LED1-8 (status) 2-17LED9 (power) 2-17

MM2-0 (JP4) pins 2-5master serial boot mode 2-6MCS-86 Hexadecimal Object (mcs) file

format 2-6

Nnotation conventions xvi

Ooscillator x 1-4

PP12 (power in) header 2-9P13 (33V header) 2-9P42 (25V header) 2-10P43 (12V header) 2-10PB1 push button (SW3) 2-15

I-2 Blackfin FPGA EZ-Extender Manual

INDEX

PB2 push button (SW4) 2-16PF14 flag pin (ADSP-BF537 EZ-KIT Lite)

2-12PF3 flag pin (ADSP-BF53361 EZ-KIT Lite)

2-12power

12V header (P43) 2-1025V header (P42) 2-1033V header (P13) 2-9in header (P12) 2-9LED (LED9) 2-17limitations 2-8supplies 1-3 2-8

printed circuit board (PCB) 1-2product overview ixprogram push button (SW1) 2-4 2-15push buttons

See also SWx map of locations 2-15

Sserial ROM 1-5

boot jumper (JP1) 2-12 2-14programming via JTAG Header 2-7

setup of this EZ-Extender 1-1slave serial mode 2-6

SRAM memory banks 1-4status reporting 1-4 2-17SW1 (program) push button 2-4 2-15SW3 (PB1) push button 2-15SW4 (PB2) push button 2-16switching regulators 2-8

TTCK signal 2-7TDI signal 2-7TDO signal 2-7TMS signal 2-7

VVisualDSP++

flash programming utility 1-4 2-6FPGA documentation 2-6

VR1-3 regulators 2-8

XXilinx

JTAG cablesoftware 1-4 2-4 2-7JTAG header 2-12serial ROM 1-5

Blackfin FPGA EZ-Extender Manual I-3

INDEX

I-4 Blackfin FPGA EZ-Extender Manual

• Blackfin FPGA EZ-Extender Manual
• Contents
• Preface
• • Product Overview
  • Purpose of This Manual
  • Intended Audience
  • Manual Contents
  • Whatrsquos New in This Manual
  • Technical or Customer Support
  • Supported Products
  • Product Information
  • • Related Documents
    • • Table 1 Related Processor Publications
      • Table 2 Related VisualDSP++ Publications
      • • Notation Conventions
        • • 1 FPGA EZ-Extender Interfaces
          • • FPGA EZ-Extender Setup
            • • Figure 1-1 FPGA EZ-Extender Setup
              • • FPGA Software and Firmware
                • FPGA EZ-Extender Overview
                • • 2 FPGA EZ-Extender Hardware Reference
                  • • System Architecture
                    • • Figure 2-1 Block Diagram
                      • • Programming the FPGA
                        • • Figure 2-2 FPGA Programming Block Diagram
                          • FPGA Programming via JTAG
                          • • Table 2-1 P15 Connections for PFGA Programming via JTAG
                            • Table 2-2 JP1 Settings for FPGA Programming via JTAG
                            • Table 2-3 JP4 Settings for FPGA Programming via JTAG
                            • • FPGA Programming via Serial ROM
                              • • Table 2-4 JP1 Settings for FPGA Programming via Serial ROM
                                • Table 2-5 JP4 Settings for FPGA Programming in Master Serial Mode
                                • • FPGA Programming via Blackfin Application
                                  • • Table 2-6 JP1 Settings for FPGA Programming via Blackfin Processor
                                    • Table 2-7 JP4 Settings for FPGA Programming via Blackfin Processor
                                    • • Programming the Serial ROM
                                      • • Serial ROM via JTAG Header
                                        • • Table 2-8 P6 Connections for Serial ROM
                                          • • Power
                                            • • Table 2-9 Power Limitations
                                              • Power In Header (P12)
                                              • 33V Header (P13)
                                              • 25V Header (P42)
                                              • 12V Header (P43)
                                              • • Jumpers
                                                • • Figure 2-3 Jumper Locations
                                                  • Serial ROM Boot Jumper (JP1)
                                                  • • Table 2-10 JP1 Settings
                                                    • • Config Done Jumper (JP2)
                                                      • • Table 2-11 JP2 Settings
                                                        • • Config Program Jumper (JP3)
                                                          • • Table 2-12 JP3 Settings
                                                            • • Boot Jumper (JP4)
                                                              • • Table 2-13 JP4 Settings
                                                                • • FPGA Input Jumpers (JP5)
                                                                  • • Table 2-14 JP5 Settings
                                                                    • • Push Buttons and LEDs
                                                                      • • Figure 2-4 Push Button and LED Locations
                                                                        • Program Push Button (SW1)
                                                                        • PB1 Push Button (SW3)
                                                                        • PB2 Push Button (SW4)
                                                                        • Status LEDs (LED1-8)
                                                                        • • Table 2-15 Status LED (LED1-8) Settings
                                                                          • • Power LED (LED9)
                                                                            • Done LED (LED10)
                                                                            • • Connectors
                                                                              • • Figure 2-5 Connector Locations
                                                                                • Expansion Interface (P1-3 and J1-3)
                                                                                • IDC Connectors (P8 P14 P16 and P17)
                                                                                • IDC Connectors (P5 and P7)
                                                                                • High-Speed Connector (P4)
                                                                                • • A Bill Of Materials
                                                                                  • B Schematics
                                                                                  • • Title
                                                                                    • FPGA Config
                                                                                    • SRAM FPGA Banks 7 and 8
                                                                                    • Expansion Interface Connector 1
                                                                                    • FPGA Banks 0 and 1
                                                                                    • Expansion Interface Connectors 2
                                                                                    • FPGA Banks 2 and 3
                                                                                    • Expansion Interface Connector 1
                                                                                    • FPGA Banks 4 and 5
                                                                                    • User IO
                                                                                    • Power
                                                                                    • Proto Area
                                                                                    • • I Index
                                                                                      • • Numerics
                                                                                        • A
                                                                                        • B
                                                                                        • C
                                                                                        • D
                                                                                        • E
                                                                                        • F
                                                                                        • G
                                                                                        • H
                                                                                        • I
                                                                                        • J
                                                                                        • L
                                                                                        • M
                                                                                        • N
                                                                                        • O
                                                                                        • P
                                                                                        • S
                                                                                        • T
                                                                                        • V
                                                                                        • X

33V

25V 33V

33V

33V

33V

4

3

2

1

A B C D

20 Cotton Road

Nashua NH 03063

A B C D

4

3

2

1

PH 1-800-ANALOGD

C

Title

Size Board No

Date Sheet of

DEVICESANALOG

DNP = Do Not Populate

Rev

BLACKFIN FPGA EZ-EXTENDER

A0199-2005 10

VCCO_0_C8

VCCO_0_F8

VCCO_0_G9

VCCO_0_G10

VCCO_0_G11

IO_A10

IO_D9

IO_D10

IO_F6

IO_VREF_0_A3

IO_VREF_0_C7

IO_VREF_0_E5

IO_VREF_0_F7

IO_L06N_0_D5

IO_L06P_0_C5

IO_L09N_0_B5

IO_L09P_0_A5

IO_L10N_0_E6

IO_L10P_0_D6

IO_L15N_0_C6

IO_L15P_0_B6

IO_L16N_0_E7

IO_L16P_0_D7

IO_L19N_0_B7

IO_L19P_0_A7

IO_L22N_0_E8

IO_L22P_0_D8

IO_L24N_0_B8

IO_L24P_0_A8

IO_L25N_0_F9

IO_L25P_0_E9

IO_L27N_0_B9

IO_L27P_0_A9

IO_L28N_0_F10

IO_L28P_0_E10

IO_L29N_0_C10

IO_L29P_0_B10

IO_L30N_0_F11

IO_L30P_0_E11

IO_L31N_0_D11

IO_L31P_0_VREF_0_C11

IO_L01N_0_VRP_0_B4

IO_L01P_0_VRN_0_A4

IO_L32N_0_GCLK7_B11

IO_L32P_0_GCLK6_A11

VCCO_1_C15

VCCO_1_F15

VCCO_1_G12

VCCO_1_G13

VCCO_1_G14

IO_A12

IO_E16

IO_F12

IO_F13

IO_F16

IO_F17

IO_VREF_1_E13

IO_VREF_1_F14

IO_L06N_1_VREF_1_A19

IO_L06P_1_B19

IO_L09N_1_C18

IO_L09P_1_D18

IO_L10N_1_VREF_1_A18

IO_L10P_1_B18

IO_L15N_1_D17

IO_L15P_1_E17

IO_L16N_1_B17

IO_L16P_1_C17

IO_L19N_1_C16

IO_L19P_1_D16

IO_L22N_1_A16

IO_L22P_1_B16

IO_L24N_1_D15

IO_L24P_1_E15

IO_L25N_1_B15

IO_L25P_1_A15

IO_L27N_1_D14

IO_L27P_1_E14

IO_L28N_1_A14

IO_L28P_1_B14

IO_L29N_1_C13

IO_L29P_1_D13

IO_L30N_1_A13

IO_L30P_1_B13

IO_L31N_1_VREF_1_D12

IO_L31P_1_E12

IO_L01N_1_VRP_1_C19

IO_L01P_1_VRN_1_B20

IO_L32N_1_GCLK5_B12

IO_L32P_1_GCLK4_C12

FPGAFPGA

LAYOUT NOTE PLACE NEAR FPGA

5 129-27-2005_1144

C8

F8

G9

G10

G11

A10

D9

D10

F6

A3

C7

E5

F7

D5

C5

B5

A5

E6

D6

C6

B6

E7

D7

B7

A7

E8

D8

B8

A8

F9

E9

B9

A9

F10

E10

C10

B10

F11

E11

D11

C11

B4

A4

B11

A11

C15

F15

G12

G13

G14

A12

E16

F12

F13

F16

F17

E13

F14

A19

B19

C18

D18

A18

B18

D17

E17

B17

C17

C16

D16

A16

B16

D15

E15

B15

A15

D14

E14

A14

B14

C13

D13

A13

B13

D12

E12

C19

B20

B12

C12

U1

FG456XC3S1000

1

10

11 12

13 14

15 16

17 18

19

2

20

21 22

23 24

25 26

27 28

29

3

30

31 32

33 34

35 36

37 38

4

5 6

7 8

9

39 40

41

43

45

47

49

42

44

46

48

50

25X2CON041

P4

5

1

18

20

22

26

24

16

14

12

25

23

21

19

17

15

13

11

9

3

6

10

8

4

2

7

P8

IDC13X213X2

5

1

18

20

22

26

24

16

14

12

25

23

21

19

17

15

13

11

9

3

6

10

8

4

2

7

P14

IDC13X213X2

FPGA BANKS 0 + 1

001UF0603

C50

DNP0603

R52

B1_L10N_A18_J1_81

B1_L15P_E17_J1_80

R53

0603DNP

B1_L16P_C17_J1_78

R27

06030

B1_L10P_B18_J1_82B1_L10N_A18_J1_81

B1_L15N_D17_J1_79

B1_L16N_B17_J1_77

B1_L24N_D15_J1_71

B1_L22N_A16_J1_73

B1_L19N_C16_J1_75

R51

0603DNPDNP

0603

R50DNP0603

R48

R31

0603DNP

B1_L19N_C16_J1_75

B1_L22N_A16_J1_73

B1_L24N_D15_J1_71

B1_L15N_D17_J1_79

B1_L15P_E17_J1_80

B1_L16N_B17_J1_77

B1_L16P_C17_J1_78

DNP0603

R30

VCCO_1

VCCO_1

C47

0603001UF

VCCO_1

B1_L27N_D14

PB1

AOE

B1_L01P_VRN_B20

B1_L01N_VRP_C19

IO_L32_0_GCLK6_A11

IO_L32_0_GCLK7_B11

IO_L32_0_GCLK7_B11

B1_L32N_GCLK5_B12

B1_L32P_GCLK4_C12 B1_L06P_B19_J1_86

B1_L09P_D18_J1_84

B1_L15P_E17_J1_80

B1_L16P_C17_J1_78

B1_L19P_D16_J1_76

B1_L16N_B17_J1_77

B1_L15N_D17_J1_79

B1_L09N_C18_J1_83

B1_L06N_A19_J1_85

B1_L31P_E12

B1_L31N_D12

B1_L06N_A19_J1_85

B1_L09N_C18_J1_83

B1_L09P_D18_J1_84

B1_L06P_B19_J1_86

B1_F17

B1_F16

B1_E16

B1_F13

B1_E13

B1_F12

B1_A12

B1_F14

B1_L01N_VRP_C19

B1_L01P_VRN_B20

B1_L32P_GCLK4_C12

B1_L32N_GCLK5_B12

AMS3

D5

D4

AMS0

UDEF1

ARE

ARDY

AMS1

AMS2

UDEF11

UDEF9

UDEF7

UDEF5

UDEF3

PP2

PP0

D15

D11

D9

A17

B1_L16P_C17_J1_78

B1_L19P_D16_J1_76

B1_L19N_C16_J1_75

B1_L22P_B16_J1_74

B1_L24N_D15_J1_71

B1_L22N_A16_J1_73

B1_L24P_E15_J1_72

B1_L16N_B17_J1_77

B1_L10P_B18_J1_82

B1_L15P_E17_J1_80

B1_L15N_D17_J1_79

B1_L10N_A18_J1_81

B1_L09P_D18_J1_84

B1_L09N_C18_J1_83

B1_L06P_B19_J1_86

B1_L06N_A19_J1_85

B1_L31N_D12

B1_L30N_A13

B1_L29N_C13

B1_L28N_A14

B1_L27N_D14

B1_L25N_B15

B1_F16

B1_F14

B1_F13

B1_F12

B1_L31P_E12

B1_L30P_B13

B1_L29P_D13

B1_L28P_B14

B1_L27P_E14

B1_L25P_A15

B1_F17

B1_E13

B1_E16

B1_A12

UDEF10

ABE3

ABE1

ABE0

ABE2

AWE

UDEF6

UDEF8

PP3

UDEF4

UDEF2

PP1

D14

D8

D10

D12

B1_L25P_A15B1_L25N_B15

B1_L22N_A16_J1_73

B1_L24N_D15_J1_71

B1_L19N_C16_J1_75

B1_L24P_E15_J1_72

B1_L22P_B16_J1_74

B1_L27P_E14

B1_L19P_D16_J1_76

B1_L22P_B16_J1_74

B1_L24P_E15_J1_72

B1_L25N_B15

B1_L25P_A15

B1_L27N_D14

B1_L27P_E14

B1_L28N_A14

B1_L28P_B14

B1_L29N_C13

B1_L29P_D13

B1_L30N_A13

B1_L30P_B13

B1_L10N_A18_J1_81

B1_L10P_B18_J1_82

3

2

1

3X1IDC3X1

P9

EXPANSION_PPI_CLK

B1_F16 B1_F17

B1_L28P_B14

B1_L29P_D13

B1_L30P_B13

B1_L31P_E12

B1_L28N_A14

B1_L29N_C13

B1_L30N_A13

B1_L31N_D12

B1_E16

B1_E13

B1_A12

B1_L01P_VRN_B20

B1_L32P_GCLK4_C12

B1_F14

B1_L01N_VRP_C19

B1_L32N_GCLK5_B12

B1_F13

B1_F12

B1_L01P_VRN_B20

B1_L01N_VRP_C19

001UF0603

C48 C49

0603001UF

C51

0603001UF 001UF

0603

C52 C53

0603001UF001UF

0603

C54

VCCO_1

R49

0603DNP

B1_L10P_B18_J1_82

DNP0603

R54

4

3

2

1

A B C D

20 Cotton Road

Nashua NH 03063

A B C D

4

3

2

1

PH 1-800-ANALOGD

C

Title

Size Board No

Date Sheet of

DEVICESANALOG

DNP = Do Not Populate

Rev

BLACKFIN FPGA EZ-EXTENDER

A0199-2005 10Expanison ConnectorP2

Bottom Of Board Top Of Board

Expansion Connector 2

33V_EI

6 129-14-2005_1203

EXPANSION INTERFACE CONNECTOR 2

SCK

NMI

TMR1

PF1

PF3

PF5

PF7

PF9

PF11

PF13

PF15

1

10

11 12

13 14

15 16

17 18

19 20

21 22

23 24

25 26

27 28

29

3

30

31 32

33 34

35 36

37 38

39

4

40

41 42

43 44

45 46

47 48

49

5

50

51 52

53 54

55 56

57 58

59

6

60

61 62

63 64

65 66

67 68

69

7

70

71 72

73 74

75 76

77 78

79

8

80

81 82

83 84

85 86

87 88

89

9

90

2P2

CON01845X2

1

10

1112

1314

1516

1718

19

2

20

2122

2324

2526

2728

29

3

30

3132

3334

3536

3738

39

4

40

4142

4344

4546

4748

49

5

50

5152

5354

5556

5758

59

6

60

6162

6364

6566

6768

69

7

70

7172

7374

7576

7778

79

8

80

8182

8384

8586

8788

89

9

90

J2

CON01945X2

ARE

ARDY

AMS0

AMS1

P2_21

P2_19

P2_7

P2_21

P2_71

P2_73

P2_77

P2_79

P2_83

P2_85

P2_81

P2_19

P2_15

P2_5 P2_6

P2_8

P2_22

P2_86

P2_84

P2_82

P2_80

P2_78

P2_74

P2_72

P2_20

P2_18

P2_22

P2_74

P2_78

P2_82

P2_84

P2_86

P2_80

P2_72

P2_20

P2_18

P2_8

P2_6

P2_[586]

P2_5

P2_7

P2_15

P2_85

P2_83

P2_81

P2_79

P2_77

P2_73

P2_71AWE

AOE

ABE0

ABE1

ABE2

ABE3

TSCLK0

TFS0

DT0PRI

DT0SEC

CONFIG_CLK_TSCLK1

CONFIG_INIT_B_TFS1

DT1PRI

DT1SEC

TMR0

TMR2

PF14

PF12

PF10

PF8

PF4

PF6

PF2

PF0

B2_L40N_L21_J2_9

B2_L39N_L19_J2_11

B2_C22_J2_17

B2_L38N_L17_J2_23

B2_L35N_K21_J2_25

B2_L34N_K19_J2_27

B2_L33N_K17_J2_29

B2_L32N_J21_J2_31

B2_L31N_J18_J2_33

B2_L29N_H21_J2_35

B2_L28N_H18_J2_37

B2_L27N_G21_J2_39

B2_L26N_G20_J2_41

B2_L22N_G17_J2_43

B2_L24N_F20_J2_45

B2_L23N_F19_J2_47

B2_L21N_E21_J2_49

B2_L20N_E19_J2_51

B2_L19N_E18_J2_53

B2_L17N_D21_J2_55

B2_L16N_D20_J2_57B2_L16P_D19_J2_58

B2_L17P_D22_J2_56

B2_L19P_F18_J2_54

B2_L20P_E20_J2_52

B2_L21P_E22_J2_50

B2_L23P_G19_J2_48

B2_L24P_F21_J2_46

B2_L22P_G18_J2_44

B2_L26P_H19_J2_42

B2_L27P_G22_J2_40

B2_L28P_J17_J2_38

B2_L29P_H22_J2_36

B2_L31P_J19_J2_34

B2_L32P_J22_J2_32

B2_L33P_K18_J2_30

B2_L34P_K20_J2_28

B2_L35P_K22_J2_26

B2_L38P_L18_J2_24

IO_L01P_2_VRN_2_C21_J2_16

B2_L40P_L22_J2_10

B2_L39P_L20_J2_12

MOSI

MISO

UDEF12

AMS3

AMS2

AMS0

ARDY

AMS1

AREAWE

AOE

ABE0

ABE1

ABE2

ABE3

RSCLK1

RSCLK0

RFS1

DR1PRI

DR1SEC

AMS2

AMS3

DR0SEC

DR0PRI

RFS0

TMR3

SPIDS0

C56

060301UF

80510UFC55

33V_EI

33V

4

3

2

1

A B C D

20 Cotton Road

Nashua NH 03063

A B C D

4

3

2

1

PH 1-800-ANALOGD

C

Title

Size Board No

Date Sheet of

DEVICESANALOG

DNP = Do Not Populate

Rev

BLACKFIN FPGA EZ-EXTENDER

A0199-2005 10

33V

25V33V

33V

33V

VCCO_2_H17

VCCO_2_H20

VCCO_2_J16

VCCO_2_K16

VCCO_2_L16

IO_C22

IO_L16N_2_D20

IO_L16P_2_D19

IO_L17N_2_D21

IO_L17P_2_VREF_2_D22

IO_L19N_2_E18

IO_L19P_2_F18

IO_L20N_2_E19

IO_L20P_2_E20

IO_L21N_2_E21

IO_L21P_2_E22

IO_L22N_2_G17

IO_L22P_2_G18

IO_L23N_2_VREF_2_F19

IO_L23P_2_G19

IO_L24N_2_F20

IO_L24P_2_F21

IO_L26N_2_G20

IO_L26P_2_H19

IO_L27N_2_G21

IO_L27P_2_G22

IO_L28N_2_H18

IO_L28P_2_J17

IO_L29N_2_H21

IO_L29P_2_H22

IO_L31N_2_J18

IO_L31P_2_J19

IO_L32N_2_J21

IO_L32P_2_J22

IO_L33N_2_K17

IO_L33P_2_K18

IO_L34N_2_VREF_2_K19

IO_L34P_2_K20

IO_L35N_2_K21

IO_L35P_2_K22

IO_L38N_2_L17

IO_L38P_2_L18

IO_L39N_2_L19

IO_L39P_2_L20

IO_L40N_2_L21

IO_L40P_2_VREF_2_L22

IO_L01N_2_VRP_2_C20

IO_L01P_2_VRN_2_C21

VCCO_3_M16

VCCO_3_N16

VCCO_3_P16

VCCO_3_R17

VCCO_3_R20

IO_L16N_3_W22

IO_L16P_3_Y22

IO_L17N_3_V19

IO_L17P_3_VREF_3_W19

IO_L19N_3_W21

IO_L19P_3_W20

IO_L20N_3_U19

IO_L20P_3_V20

IO_L21N_3_V22

IO_L21P_3_V21

IO_L22N_3_T17

IO_L22P_3_U18

IO_L23N_3_U21

IO_L23P_3_VREF_3_U20

IO_L24N_3_R18

IO_L24P_3_T18

IO_L26N_3_T20

IO_L26P_3_T19

IO_L27N_3_T22

IO_L27P_3_T21

IO_L28N_3_R22

IO_L28P_3_R21

IO_L29N_3_P19

IO_L29P_3_R19

IO_L31N_3_P18

IO_L31P_3_P17

IO_L32N_3_P22

IO_L32P_3_P21

IO_L33N_3_N18

IO_L33P_3_N17

IO_L34N_3_N20

IO_L34P_3_VREF_3_N19

IO_L35N_3_N22

IO_L35P_3_N21

IO_L38N_3_M18

IO_L38P_3_M17

IO_L39N_3_M20

IO_L39P_3_M19

IO_L40N_3_VREF_3_M22

IO_L40P_3_M21

IO_L01N_3_VRP_3_Y20

IO_L01P_3_VRN_3_Y19

IO_Y21

FPGAFPGA

LAYOUT NOTE PLACE NEAR FPGA

9-27-2005_1144 7 12

H17

H20

J16

K16

L16

C22

D20

D19

D21

D22

E18

F18

E19

E20

E21

E22

G17

G18

F19

G19

F20

F21

G20

H19

G21

G22

H18

J17

H21

H22

J18

J19

J21

J22

K17

K18

K19

K20

K21

K22

L17

L18

L19

L20

L21

L22

C20

C21

M16

N16

P16

R17

R20

W22

Y22

V19

W19

W21

W20

U19

V20

V22

V21

T17

U18

U21

U20

R18

T18

T20

T19

T22

T21

R22

R21

P19

R19

P18

P17

P22

P21

N18

N17

N20

N19

N22

N21

M18

M17

M20

M19

M22

M21

Y20

Y19

Y21

U1

FG456XC3S1000

2

4

8

10

6

12

14

16

24

22

20

18

26

28

3

5

7

9

11

13

15

17

19

21

23

25

27

1P5

IDC14X214X2

1

27

25

23

21

19

17

15

13

11

9

7

5

3

28

26

18

20

22

24

16

14

12

6

10

8

4

2P7

IDC14X214X2

VCCO_2

B2_L26P_H19_J2_42

DNP0603

R55B2_L24P_F21_J2_46

R56

0603DNP

B2_L23P_G19_J2_48

B2_L26N_G20_J2_41

B2_L24N_F20_J2_45

B2_L23N_F19_J2_47 B2_L23P_G19_J2_48

B2_L24P_F21_J2_46

B2_L26P_H19_J2_42

R32

0603DNP

TMR0

VCCO_2

PF221

2X1IDC2X1

JP3

CONFIG_PROG_B

1 2JP2

IDC2X12X1

PF3

CONFIG_INIT_B_TFS1

CONFIG_CLK_TSCLK1

RSCLK1

RFS1

IO_L01N_2_VRP_2_C20

IO_L01P_2_VRN_2_C21_J2_16

B2_L22N_G17_J2_43

B2_L22P_G18_J2_44

B2_L32N_J21_J2_31

SPIDS0

PF0

SCK

NMI

TMR1

DR1SEC

TMR3

DR0PRI

DR1PRI

RFS0

DR0SEC

PF15

PF13

RSCLK0

PF7

PF9

PF6

PF11

PF1

PF3

PF5

MOSI

MISO

UDEF12

TMR2

DT1SEC

DT1PRI

DT0SEC

TSCLK0

PF14

PF12

PF10

PF8

PF4

PF2

FPGA BANKS 2 + 3

DT0PRI

TFS0

B2_L40P_L22_J2_10

B2_L40N_L21_J2_9

B2_L39P_L20_J2_12

B2_L39N_L19_J2_11

B2_L38P_L18_J2_24

B2_L38N_L17_J2_23

B2_L35P_K22_J2_26

B2_L35N_K21_J2_25

B2_L34P_K20_J2_28

B2_L34N_K19_J2_27

B2_L33P_K18_J2_30

B2_L33N_K17_J2_29

B2_L32P_J22_J2_32

B2_L31P_J19_J2_34

B2_L31N_J18_J2_33

B2_L29P_H22_J2_36

B2_L29N_H21_J2_35

B2_L28P_J17_J2_38

B2_L28N_H18_J2_37

B2_L27P_G22_J2_40

B2_L27N_G21_J2_39

B2_L26P_H19_J2_42

B2_L26N_G20_J2_41

B2_L24P_F21_J2_46

B2_L24N_F20_J2_45

B2_L23P_G19_J2_48

B2_L23N_F19_J2_47

B2_L21P_E22_J2_50

B2_L21N_E21_J2_49

B2_L20P_E20_J2_52

B2_L20N_E19_J2_51

B2_L19P_F18_J2_54

B2_L19N_E18_J2_53

B2_L17P_D22_J2_56

B2_L17N_D21_J2_55

B2_L16P_D19_J2_58

B2_L16N_D20_J2_57

B2_C22_J2_17

3

2

1

3X1IDC3X1

P10

IO_L01P_2_VRN_2_C21_J2_16

IO_L01N_2_VRP_2_C20

VCCO_2

CONFIG_DONE

B2_L22N_G17_J2_43

B2_L17N_D21_J2_55

B2_L19N_E18_J2_53

B2_L20N_E19_J2_51

B2_L21N_E21_J2_49

B2_L16N_D20_J2_57

IO_L01N_2_VRP_2_C20

B2_L16P_D19_J2_58

B2_L20P_E20_J2_52

B2_L19P_F18_J2_54

B2_L17P_D22_J2_56

B2_L22P_G18_J2_44

B2_L21P_E22_J2_50

B2_C22_J2_17

IO_L01P_2_VRN_2_C21_J2_16

B2_L40N_L21_J2_9

B2_L39N_L19_J2_11

B2_L38N_L17_J2_23

B2_L35N_K21_J2_25

B2_L34N_K19_J2_27

B2_L33N_K17_J2_29

B2_L32N_J21_J2_31

B2_L31N_J18_J2_33

B2_L29N_H21_J2_35

B2_L28N_H18_J2_37

B2_L27N_G21_J2_39

B2_L40P_L22_J2_10

B2_L34P_K20_J2_28

B2_L35P_K22_J2_26

B2_L38P_L18_J2_24

B2_L39P_L20_J2_12

B2_L33P_K18_J2_30

B2_L32P_J22_J2_32

B2_L28P_J17_J2_38

B2_L31P_J19_J2_34

B2_L29P_H22_J2_36

B2_L27P_G22_J2_40

DNP0603

R33

B2_L23N_F19_J2_47

B2_L24N_F20_J2_45

B2_L26N_G20_J2_41

DNP0603

R57

001UF0603

C60 C59

0603001UF 001UF

0603

C58 C57

0603001UF

C82

0603001UF 001UF

0603

C81 C62

0603001UF001UF

0603

C61

VCCO_2

4

3

2

1

A B C D

20 Cotton Road

Nashua NH 03063

A B C D

4

3

2

1

PH 1-800-ANALOGD

C

Title

Size Board No

Date Sheet of

DEVICESANALOG

DNP = Do Not Populate

Rev

BLACKFIN FPGA EZ-EXTENDER

A0199-2005 10

Expanison ConnectorExpanison Connector

Bottom Of Board Top Of BoardExpansion Connector 3

EXPANSION INTERFACE (TYPE B)

P3P3

9-9-2005_1029 128

EXPANSION INTERFACE CONNECTOR 1

33V_EI5V_EI

1

10

11 12

13 14

15 16

17 18

19

2

20

21 22

23 24

25 26

27 28

29

3

30

31 32

33 34

35 36

37 38

39

4

40

41 42

43 44

45 46

47 48

49

5

50

51 52

53 54

55 56

57 58

59

6

60

61 62

63 64

65 66

67 68

69

7

70

71 72

73 74

75 76

77 78

79

8

80

81 82

83 84

85 86

87 88

89

9

90

P3

CON01845X2

1

10

1112

1314

1516

1718

19

2

20

2122

2324

2526

2728

29

3

30

3132

3334

3536

3738

39

4

40

4142

4344

4546

4748

49

5

50

5152

5354

5556

5758

59

6

60

6162

6364

6566

6768

69

7

70

7172

7374

7576

7778

79

8

80

8182

8384

8586

8788

89

9

90

J3

CON01945X2

TX0

TX1

UDEF17

UDEF19

UDEF21

UDEF23

UDEF25

UDEF29

UDEF27

RESET

UDEF32

UDEF34

UDEF36

UDEF38

UDEF40

B5_L01N_RDWR_B_Y4_J3_1

P3_42

P3_[190]

P3_86

P3_84

P3_82

P3_80

P3_78

P3_76

P3_74

P3_72

P3_70

P3_68

P3_64

P3_62

P3_60

P3_58

P3_56

P3_54

P3_52

P3_50

P3_48

P3_46

P3_42

P3_79

P3_89

P3_77

P3_75

P3_73

P3_71

P3_69

P3_67

P3_63

P3_61

P3_59

P3_57

P3_55

P3_53

P3_51

P3_49

P3_47

P3_45

P3_51

P3_79

P3_89

P3_77

P3_75

P3_73

P3_71

P3_69

P3_67

P3_63

P3_61

P3_59

P3_57

P3_55

P3_53

P3_49

P3_47

P3_45

P3_86

P3_84

P3_82

P3_80

P3_78

P3_76

P3_74

P3_72

P3_70

P3_68

P3_64

P3_62

P3_60

P3_58

P3_56

P3_54

P3_52

P3_50

P3_48

P3_46

B5_L27N_W9_J3_31

B5_L28N_D6_AB9_J3_33

B5_L29N_Y10_J3_35

B5_L30N_AB10_J3_37

B5_L31N_D4_W11_J3_39

B5_L10N_VRP_AB5_J3_9

B5_L25N_AB8_J3_21

B5_L24N_W8_J3_19

B5_L22N_AB7_J3_17

B5_L19N_Y7_J3_15

B5_L16N_AA6_J3_13

B5_L15N_W6_J3_11

B5_L09N_Y5_J3_7

B5_L06N_AB4_J3_5

B5_U6_J3_23

B5_V7_J3_29

B5_U9_J3_41

B5_L31P_D5_V11_J3_40

B5_L30P_AA10_J3_38

B5_L29P_W10_J3_36

B5_L28P_D7_AA9_J3_34

B5_L27P_V9_J3_32

B5_L32N_GCLK3_AA11_J3_30

B5_U7_J3_28

B5_L25P_AA8_J3_22

B5_L24P_V8_J3_20

B5_L22P_AA7_J3_18

B5_L19P_W7_J3_16

B5_L16P_Y6_J3_14

B5_L15P_V6_J3_12

B5_L10P_VRN_AA5_J3_10

B5_L09P_W5_J3_8

B5_L06P_AA4_J3_6

B5_L01P_CS_B_AA3_J3_2

B5_AB11_J3_90

B5_U11_J3_83

B5_V10_J3_85

B5_U10_J3_81

UDEF43

BGH

BG

BR

UDEF30

UDEF28

UDEF26

UDEF24

UDEF22

UDEF20

UDEF18

UDEF16

RX1

RX0

UDEF14 UDEF15

CLK_OUT_EXP1

UDEF31

UDEF33

UDEF35

UDEF37

UDEF39

UDEF41

33V_EI

C84

060301UF

80510UFC83

C8610UF805

01UF0603

C85

5V_EI

33V

33V

25V 33V

33V

33V

33V

4

3

2

1

A B C D

20 Cotton Road

Nashua NH 03063

A B C D

4

3

2

1

PH 1-800-ANALOGD

C

Title

Size Board No

Date Sheet of

DEVICESANALOG

DNP = Do Not Populate

Rev

BLACKFIN FPGA EZ-EXTENDER

A0199-2005 10

VCCO_4_T12

VCCO_4_T13

VCCO_4_T14

VCCO_4_U15

VCCO_4_Y15

IO_U16

IO_U17

IO_W13

IO_W14

IO_VREF_4_V18

IO_VREF_4_Y16

IO_VREF_4_AB13

IO_L05N_4_AA19

IO_L05P_4_AB19

IO_L06N_4_VREF_4_W18

IO_L06P_4_Y18

IO_L09N_4_AA18

IO_L09P_4_AB18

IO_L10N_4_V17

IO_L10P_4_W17

IO_L15N_4_Y17

IO_L15P_4_AA17

IO_L16N_4_V16

IO_L16P_4_W16

IO_L19N_4_AA16

IO_L19P_4_AB16

IO_L22N_4_VREF_4_V15

IO_L22P_4_W15

IO_L24N_4_AA15

IO_L24P_4_AB15

IO_L25N_4_U14

IO_L25P_4_V14

IO_L27N_4_DIN_D0_AA14

IO_L27P_4_D1_AB14

IO_L28N_4_U13

IO_L28P_4_V13

IO_L29N_4_Y13

IO_L29P_4_AA13

IO_L30N_4_D2_U12

IO_L30P_4_D3_V12

IO_L31N_4_INIT_B_W12

IO_L31P_4_DOUT_BUSY_Y12

IO_L01N_4_VRP_4_AA20

IO_L01P_4_VRN_4_AB20

IO_L32N_4_GCLK1_AA12

IO_L32P_4_GCLK0_AB12

VCCO_5_T9

VCCO_5_T10

VCCO_5_T11

VCCO_5_U8

VCCO_5_Y8

IO_U7

IO_U9

IO_U10

IO_U11

IO_V7

IO_V10

IO_VREF_5_U6

IO_VREF_5_AB11

IO_L01N_5_RDWR_B_Y4

IO_L01P_5_CS_B_AA3

IO_L06N_5_AB4

IO_L06P_5_AA4

IO_L09N_5_Y5

IO_L09P_5_W5

IO_L15N_5_W6

IO_L15P_5_V6

IO_L16N_5_AA6

IO_L16P_5_Y6

IO_L19N_5_Y7

IO_L19P_5_VREF_5_W7

IO_L22N_5_AB7

IO_L22P_5_AA7

IO_L24N_5_W8

IO_L24P_5_V8

IO_L25N_5_AB8

IO_L25P_5_AA8

IO_L27N_5_VREF_5_W9

IO_L27P_5_V9

IO_L28N_5_D6_AB9

IO_L28P_5_D7_AA9

IO_L29N_5_Y10

IO_L29P_5_VREF_5_W10

IO_L30N_5_AB10

IO_L30P_5_AA10

IO_L31N_5_D4_W11

IO_L31P_5_D5_V11

IO_L32N_5_GCLK3_AA11

IO_L32P_5_GCLK2_Y11

IO_L10N_5_VRP_5_AB5

IO_L10P_5_VRN_5_AA5

FPGAFPGA

1299-27-2005_1144

T12

T13

T14

U15

Y15

U16

U17

W13

W14

V18

Y16

AB13

AA19

AB19

W18

Y18

AA18

AB18

V17

W17

Y17

AA17

V16

W16

AA16

AB16

V15

W15

AA15

AB15

U14

V14

AA14

AB14

U13

V13

Y13

AA13

U12

V12

W12

Y12

AA20

AB20

AA12

AB12

T9

T10

T11

U8

Y8

U7

U9

U10

U11

V7

V10

U6

AB11

Y4

AA3

AB4

AA4

Y5

W5

W6

V6

AA6

Y6

Y7

W7

AB7

AA7

W8

V8

AB8

AA8

W9

V9

AB9

AA9

Y10

W10

AB10

AA10

W11

V11

AA11

Y11

AB5

AA5

U1

FG456XC3S1000

7

2

4

8

10

6

3

9

11

13

15

17

19

21

23

25

12

14

16

24

26

22

20

18

1

5

P16

IDC13X213X2

5

1

18

20

22

26

24

16

14

12

25

23

21

19

17

15

13

11

9

3

6

10

8

4

2

7

P17

IDC13X213X2

R46

060310K

R43

0603DNP

FPGA BANKS 4 + 5

VCCO_5

CONFIG_INIT_B_TFS1

CLK_OUT_EXP1

B4_L32N_GCKL1_AA12

R9

06030

B5_L10N_VRP_AB5_J3_9

B5_L10N_VRP_AB5_J3_9

B5_L10P_VRN_AA5_J3_10

VCCO_5

B5_L32P_GCLK2_Y1

B5_L32N_GCLK3_AA11_J3_30

CONFIG_DIN_DT1PRI

UDEF16

UDEF38

UDEF14

RX0

TX0

RX1

TX1

UDEF20

UDEF21

UDEF23

UDEF17

UDEF25

UDEF24

UDEF22

RESET

UDEF30

UDEF29

UDEF27

UDEF26

UDEF35

UDEF34

UDEF33

UDEF32

UDEF31

UDEF15

UDEF28

UDEF41

UDEF40

UDEF39

UDEF37

UDEF36

BR

UDEF43

BG

BGH

UDEF19

B5_L31P_D5_V11_J3_40

B5_L31N_D4_W11_J3_39

B5_L30P_AA10_J3_38

B5_L30N_AB10_J3_37

B5_L29P_W10_J3_36

B5_L29N_Y10_J3_35

B5_L28P_D7_AA9_J3_34

B5_L28N_D6_AB9_J3_33

B5_L27P_V9_J3_32

B5_L27N_W9_J3_31

B5_L25P_AA8_J3_22

B5_L25N_AB8_J3_21

B5_L24P_V8_J3_20

B5_L24N_W8_J3_19

B5_L22P_AA7_J3_18

B5_L22N_AB7_J3_17

B5_L19P_W7_J3_16

B5_L19N_Y7_J3_15

B5_L16P_Y6_J3_14

B5_L16N_AA6_J3_13

B5_L15P_V6_J3_12

B5_L15N_W6_J3_11

B5_L09P_W5_J3_8

B5_L09N_Y5_J3_7

B5_L06P_AA4_J3_6

B5_L06N_AB4_J3_5

B5_L01P_CS_B_AA3_J3_2

B5_L01N_RDWR_B_Y4_J3_1

B5_AB11_J3_90

B5_U6_J3_23

B5_V10_J3_85

B5_V7_J3_29

B5_U11_J3_83

B5_U10_J3_81

B5_U9_J3_41

B5_U7_J3_28

UDEF18

3

2

1

3X1IDC3X1

P11

B5_L29N_Y10_J3_35

B5_L30N_AB10_J3_37

B5_L31N_D4_W11_J3_39

B5_U11_J3_83

B5_V10_J3_85B5_AB11_J3_90

B5_U10_J3_81

B5_L31P_D5_V11_J3_40

B5_L30P_AA10_J3_38

B5_L29P_W10_J3_36

B5_L28P_D7_AA9_J3_34

B5_L27P_V9_J3_32

B5_L28N_D6_AB9_J3_33

B5_L27N_W9_J3_31

B5_L25N_AB8_J3_21B5_L25P_AA8_J3_22

B5_L24N_W8_J3_19B5_L24P_V8_J3_20

B5_U9_J3_41B5_U6_J3_23

VCCO_5

B5_L10P_VRN_AA5_J3_10

C70

0603001UF 001UF

0603

C69 C68

0603001UF001UF

0603

C67001UF0603

C66 C65

0603001UF 001UF

0603

C64C63

0603001UF

B5_L09N_Y5_J3_7

B5_U7_J3_28 B5_V7_J3_29

B5_L10P_VRN_AA5_J3_10 B5_L10N_VRP_AB5_J3_9

B5_L15P_V6_J3_12 B5_L15N_W6_J3_11

B5_L16P_Y6_J3_14 B5_L16N_AA6_J3_13

B5_L19P_W7_J3_16 B5_L19N_Y7_J3_15

B5_L22P_AA7_J3_18 B5_L22N_AB7_J3_17

B5_L32N_GCLK3_AA11_J3_30 B5_L32P_GCLK2_Y1

B5_L01P_CS_B_AA3_J3_2 B5_L01N_RDWR_B_Y4_J3_1

B5_L06P_AA4_J3_6 B5_L06N_AB4_J3_5

B5_L09P_W5_J3_8

VCCO_5

DNP0603

R45

25V

33V

33V

4

3

2

1

A B C D

20 Cotton Road

Nashua NH 03063

A B C D

4

3

2

1

PH 1-800-ANALOGD

C

Title

Size Board No

Date Sheet of

DEVICESANALOG

DNP = Do Not Populate

Rev

BLACKFIN FPGA EZ-EXTENDER

A0199-2005 10

SN74LVC1G125

12109-27-2005_1144

2 4

1

SOT23-5SN74LVC1G125

U8

USER IO

C80

0603001UF

SW4SWT013SPST-MOMENTARY

SPST-MOMENTARYSWT013SW3

060310R42

C5

06031UF

R413300603

LED001AMBER-SMTLED8

0603330R40

LED7AMBER-SMTLED001

R393300603

R1033006030603

330R34R35

33006030603

330R36

0603330R37 R38

3300603

LED001AMBER-SMTLED2

AMBER-SMTLED001

LED3AMBER-SMTLED001

LED4AMBER-SMTLED001

LED5

LED001AMBER-SMTLED6

LED9GREEN-SMTLED001

402100R23

1 2

3 4

5 6

7 8

JP5

IDC4X24X2

AMBER-SMTLED001

LED1

B6_L01N_Y3

B6_L01P_Y2

B5_U10_J3_81

B5_AB11_J3_90

PB2

B5_V10_J3_85

B5_U11_J3_83

B5_L31N_D4_W11_J3_39

B5_L30N_AB10_J3_37

B5_L29N_Y10_J3_35

B5_L28N_D6_AB9_J3_33

B5_L27N_W9_J3_31

PB1

B5_L25N_AB8_J3_21

R47

060310K

CHOKE_COIL

4

3

2

1

A B C D

20 Cotton Road

Nashua NH 03063

A B C D

4

3

2

1

PH 1-800-ANALOGD

C

Title

Size Board No

Date Sheet of

DEVICESANALOG

DNP = Do Not Populate

Rev

BLACKFIN FPGA EZ-EXTENDER

A0199-2005 10

25V

33V

VIN

EN

SW

GND

FB

VIN

EN

SW

GND

FB

VIN

EN

SW

GND

FB

4

3

5

2

1

VR3

SOT23-5LM3475MF

1

2

5

3

4

VR2

SOT23-5LM3475MF

4

3

5

2

1

VR1

SOT23-5LM3475MF

12119-27-2005_1124

1

32

Q2

SI2

343D

SS

OT

23D

1

32

Q3

SI2

343D

SS

OT

23D

2 3

1S

I234

3DS

Q1

SO

T23

D

316KR17

0603

215KR18

0603

0603

R11105K

DNPC73

0603

0603

C72DNP

805

C741000PF

0R58

0603

1000PFC10

805

0603

R1910K

C100UFCT2

CT3100UFC

IND005

L110UH

10UHL3

IND005

10UHL2

IND005

1

2 D3

DO214ABSCHOT_RECT

3A

0603

R20200K

805

C639NF

390PFC7

0603

2

1 3A

SCHOT_RECTDO214AB

D2

499KR13

0603

1

2 D1

DO214ABSCHOT_RECT

3A

33V_EI

3

1

2

3X1IDC3X1

P13

UNREG_IN

12V

CT1100UFC

80510UFC71

R1200603

5V_EI

8051000PFC2

FER2

0603

060301UFC3

POWER

FUS00125AF1

4

1

3

2

FER1

DO-214AA

S2A_RECT

2AD5

8051000PFC1 C4

10UFC

3

1

2

3X1IDC3X1

P12

UNREG_IN

1

2

3

CON00525MM_JACK

POWER

J4

2

1P42

IDC2X12X1DNP

1

2

DNP2X1IDC2X1

P43

06030R15

C810UF805

80510UFC9

R1600603

UNREG_IN

0603

R1410K

0603

R590

4

3

2

1

A B C D

20 Cotton Road

Nashua NH 03063

A B C D

4

3

2

1

PH 1-800-ANALOGD

C

Title

Size Board No

Date Sheet of

DEVICESANALOG

DNP = Do Not Populate

Rev

BLACKFIN FPGA EZ-EXTENDER

A0199-2005 1012129-14-2005_1204

5

2

4

8

10

6

1

3

9

11

13

15

17

19

12

14

16

20

18

7

P20

SOIC20

PROTO AREA

1

3

2

SOT23D

P39

2

3

1

SOT23D

P38

2

4

5 6

3

1

SOT23-6

P411

3

65

4

2

SOT23-6

P40

PRT_NUM=DNE

11

13

15 16

14

12

2

4

6

8

109

7

5

3

1

SOIC16

P191

3

5

7

9 10

8

6

4

2

12

14

1615

13

11

SOIC16

P18

21P37

805

1 2

805

P36

21P35

805

1 2

805

P34

1 2

805

P33

21P32

805

1 2

805

P31

21P30

805

1 2

805

P29

21P28

805

1 2

805

P27

21P26

805

21P25

805

1 2

805

P24

21P23

805

1 2

805

P22

TP86

TP85

TP84

TP83

TP82

TP81

TP80

TP79 TP77

TP76

TP75

TP74

TP73

TP72

TP71

TP70

TP68

TP67

TP66

TP65

TP64

TP62

TP61

TP60

TP59

TP58

TP57

TP56

TP55

TP54

TP53

TP51

TP50

TP49

TP48

TP47

TP46

TP45

TP44

TP43

TP41

TP40

TP39

TP38

TP37

TP36

TP35

TP34

TP33

TP32

TP30

TP29

TP28

TP27

TP26

TP25

TP24

TP23

TP22

TP21

TP19

TP18

TP17

TP16

TP15

TP14

TP13

TP12

TP11

TP9

TP8

TP7

TP6

TP5

TP4

TP125

TP124

TP123

TP122

TP121

TP120

TP119

TP118

TP117

TP116

TP114

TP113

TP112

TP111

TP110

TP109

TP108

TP107TP106

TP105TP103

TP102TP101 TP100TP99

TP98 TP97

TP96 TP95

TP94TP93

TP92TP91

TP90 TP89

TP88 TP87

TP78TP69

TP63 TP52

TP42 TP31

TP20 TP10

TP115TP104

7

18

20

16

14

12

19

17

15

13

11

9

3

1

6

10

8

4

2

5

SOIC20

P21

I INDEX

Numerics connectors

25V header (P42) 2-17

AADSP-BF5333761 EZ-KIT Lite interface 2-1ADSP-BF5333761 processors boot mode

settings 2-14architecture of this EZ-Extender 2-2asynchronous static random access memory

(SRAM) xauxiliary oscillator x

Bbill of materials A-1block diagram of this EZ-Extender 2-2boot jumper See JP4

Cconfiguration jumpers See JP2 JP3

map of locations 2-18J1-3 (expansion) 2-19P1-3 (expansion) 2-19P14 (IDC) 2-19P15 (JTAG header) 2-4P16-17 (IDC) 2-19P4 (high-speed) 2-20P5 (IDC) 2-20P6 (JTAG) 2-7P7 (IDC) 2-20P8 (IDC) 2-19

customer support xiii

Ddone LED (LED10) 2-17

Eexpansion interface

connectors (P1-3 J1-3) 2-19of ADSP-BF5333761 EZ-KIT Lites ix

1-3external power supply 1-3 2-8

FField-Programmable Gate Array See FPGA

Blackfin FPGA EZ-Extender Manual I-1

INDEX

FPGAdocumentation 1-2input jumpers (JP5) 2-14softwarefirmware 1-2Xilinx Spartan package x 1-3

FPGA pinsAB10 (LED3) 2-17AB11 (JP58) 2-15AB8 (LED7) 2-17AB9 (LED5) 2-17C11 (PB1SW3) 2-15H5 (PB2SW3) 2-16M2-0 (JP4) 2-14U10 (JP56) 2-15U11 (LED1) 2-17V10 (LED8) 2-17W11 (LED2) 2-17W9 (LED6) 2-17Y10 (LED4) 2-17Y3-2 (JP52-54) 2-15

FPGA programmingblock diagram 2-3via ADSP-BF533376 processors 2-6via JTAG header 2-4via serial ROM 2-5

GGCLK1 (global clock 1) pin 1-4GCLK6 (global clock 6) pin 1-4general-purpose input push buttons 2-15 2-16

Hhigh-speed connector (P4) 2-20

IIDC connectors x 2-19 2-20installation of this EZ-Extender 1-1

JJTAG

cable 1-4 2-7header (P6) 1-5 2-4 2-7 2-14

jumpersmap of locations 2-11JP1 (boot jumper) 2-5 2-12JP2 (confug done) 2-12JP3 (config program) 2-13JP41-46 (boot mode select) 2-5 2-6 2-14JP52-56 (FPGA input) 2-14

LLEDs

map of locations 2-15LED10 (FPGA done pin) 2-4 2-5 2-17LED1-8 (status) 2-17LED9 (power) 2-17

MM2-0 (JP4) pins 2-5master serial boot mode 2-6MCS-86 Hexadecimal Object (mcs) file

format 2-6

Nnotation conventions xvi

Ooscillator x 1-4

PP12 (power in) header 2-9P13 (33V header) 2-9P42 (25V header) 2-10P43 (12V header) 2-10PB1 push button (SW3) 2-15

I-2 Blackfin FPGA EZ-Extender Manual

INDEX

PB2 push button (SW4) 2-16PF14 flag pin (ADSP-BF537 EZ-KIT Lite)

2-12PF3 flag pin (ADSP-BF53361 EZ-KIT Lite)

2-12power

12V header (P43) 2-1025V header (P42) 2-1033V header (P13) 2-9in header (P12) 2-9LED (LED9) 2-17limitations 2-8supplies 1-3 2-8

printed circuit board (PCB) 1-2product overview ixprogram push button (SW1) 2-4 2-15push buttons

See also SWx map of locations 2-15

Sserial ROM 1-5

boot jumper (JP1) 2-12 2-14programming via JTAG Header 2-7

setup of this EZ-Extender 1-1slave serial mode 2-6

SRAM memory banks 1-4status reporting 1-4 2-17SW1 (program) push button 2-4 2-15SW3 (PB1) push button 2-15SW4 (PB2) push button 2-16switching regulators 2-8

TTCK signal 2-7TDI signal 2-7TDO signal 2-7TMS signal 2-7

VVisualDSP++

flash programming utility 1-4 2-6FPGA documentation 2-6

VR1-3 regulators 2-8

XXilinx

JTAG cablesoftware 1-4 2-4 2-7JTAG header 2-12serial ROM 1-5

Blackfin FPGA EZ-Extender Manual I-3

INDEX

I-4 Blackfin FPGA EZ-Extender Manual

• Blackfin FPGA EZ-Extender Manual
• Contents
• Preface
• • Product Overview
  • Purpose of This Manual
  • Intended Audience
  • Manual Contents
  • Whatrsquos New in This Manual
  • Technical or Customer Support
  • Supported Products
  • Product Information
  • • Related Documents
    • • Table 1 Related Processor Publications
      • Table 2 Related VisualDSP++ Publications
      • • Notation Conventions
        • • 1 FPGA EZ-Extender Interfaces
          • • FPGA EZ-Extender Setup
            • • Figure 1-1 FPGA EZ-Extender Setup
              • • FPGA Software and Firmware
                • FPGA EZ-Extender Overview
                • • 2 FPGA EZ-Extender Hardware Reference
                  • • System Architecture
                    • • Figure 2-1 Block Diagram
                      • • Programming the FPGA
                        • • Figure 2-2 FPGA Programming Block Diagram
                          • FPGA Programming via JTAG
                          • • Table 2-1 P15 Connections for PFGA Programming via JTAG
                            • Table 2-2 JP1 Settings for FPGA Programming via JTAG
                            • Table 2-3 JP4 Settings for FPGA Programming via JTAG
                            • • FPGA Programming via Serial ROM
                              • • Table 2-4 JP1 Settings for FPGA Programming via Serial ROM
                                • Table 2-5 JP4 Settings for FPGA Programming in Master Serial Mode
                                • • FPGA Programming via Blackfin Application
                                  • • Table 2-6 JP1 Settings for FPGA Programming via Blackfin Processor
                                    • Table 2-7 JP4 Settings for FPGA Programming via Blackfin Processor
                                    • • Programming the Serial ROM
                                      • • Serial ROM via JTAG Header
                                        • • Table 2-8 P6 Connections for Serial ROM
                                          • • Power
                                            • • Table 2-9 Power Limitations
                                              • Power In Header (P12)
                                              • 33V Header (P13)
                                              • 25V Header (P42)
                                              • 12V Header (P43)
                                              • • Jumpers
                                                • • Figure 2-3 Jumper Locations
                                                  • Serial ROM Boot Jumper (JP1)
                                                  • • Table 2-10 JP1 Settings
                                                    • • Config Done Jumper (JP2)
                                                      • • Table 2-11 JP2 Settings
                                                        • • Config Program Jumper (JP3)
                                                          • • Table 2-12 JP3 Settings
                                                            • • Boot Jumper (JP4)
                                                              • • Table 2-13 JP4 Settings
                                                                • • FPGA Input Jumpers (JP5)
                                                                  • • Table 2-14 JP5 Settings
                                                                    • • Push Buttons and LEDs
                                                                      • • Figure 2-4 Push Button and LED Locations
                                                                        • Program Push Button (SW1)
                                                                        • PB1 Push Button (SW3)
                                                                        • PB2 Push Button (SW4)
                                                                        • Status LEDs (LED1-8)
                                                                        • • Table 2-15 Status LED (LED1-8) Settings
                                                                          • • Power LED (LED9)
                                                                            • Done LED (LED10)
                                                                            • • Connectors
                                                                              • • Figure 2-5 Connector Locations
                                                                                • Expansion Interface (P1-3 and J1-3)
                                                                                • IDC Connectors (P8 P14 P16 and P17)
                                                                                • IDC Connectors (P5 and P7)
                                                                                • High-Speed Connector (P4)
                                                                                • • A Bill Of Materials
                                                                                  • B Schematics
                                                                                  • • Title
                                                                                    • FPGA Config
                                                                                    • SRAM FPGA Banks 7 and 8
                                                                                    • Expansion Interface Connector 1
                                                                                    • FPGA Banks 0 and 1
                                                                                    • Expansion Interface Connectors 2
                                                                                    • FPGA Banks 2 and 3
                                                                                    • Expansion Interface Connector 1
                                                                                    • FPGA Banks 4 and 5
                                                                                    • User IO
                                                                                    • Power
                                                                                    • Proto Area
                                                                                    • • I Index
                                                                                      • • Numerics
                                                                                        • A
                                                                                        • B
                                                                                        • C
                                                                                        • D
                                                                                        • E
                                                                                        • F
                                                                                        • G
                                                                                        • H
                                                                                        • I
                                                                                        • J
                                                                                        • L
                                                                                        • M
                                                                                        • N
                                                                                        • O
                                                                                        • P
                                                                                        • S
                                                                                        • T
                                                                                        • V
                                                                                        • X

4

3

2

1

A B C D

20 Cotton Road

Nashua NH 03063

A B C D

4

3

2

1

PH 1-800-ANALOGD

C

Title

Size Board No

Date Sheet of

DEVICESANALOG

DNP = Do Not Populate

Rev

BLACKFIN FPGA EZ-EXTENDER

A0199-2005 10Expanison ConnectorP2

Bottom Of Board Top Of Board

Expansion Connector 2

33V_EI

6 129-14-2005_1203

EXPANSION INTERFACE CONNECTOR 2

SCK

NMI

TMR1

PF1

PF3

PF5

PF7

PF9

PF11

PF13

PF15

1

10

11 12

13 14

15 16

17 18

19 20

21 22

23 24

25 26

27 28

29

3

30

31 32

33 34

35 36

37 38

39

4

40

41 42

43 44

45 46

47 48

49

5

50

51 52

53 54

55 56

57 58

59

6

60

61 62

63 64

65 66

67 68

69

7

70

71 72

73 74

75 76

77 78

79

8

80

81 82

83 84

85 86

87 88

89

9

90

2P2

CON01845X2

1

10

1112

1314

1516

1718

19

2

20

2122

2324

2526

2728

29

3

30

3132

3334

3536

3738

39

4

40

4142

4344

4546

4748

49

5

50

5152

5354

5556

5758

59

6

60

6162

6364

6566

6768

69

7

70

7172

7374

7576

7778

79

8

80

8182

8384

8586

8788

89

9

90

J2

CON01945X2

ARE

ARDY

AMS0

AMS1

P2_21

P2_19

P2_7

P2_21

P2_71

P2_73

P2_77

P2_79

P2_83

P2_85

P2_81

P2_19

P2_15

P2_5 P2_6

P2_8

P2_22

P2_86

P2_84

P2_82

P2_80

P2_78

P2_74

P2_72

P2_20

P2_18

P2_22

P2_74

P2_78

P2_82

P2_84

P2_86

P2_80

P2_72

P2_20

P2_18

P2_8

P2_6

P2_[586]

P2_5

P2_7

P2_15

P2_85

P2_83

P2_81

P2_79

P2_77

P2_73

P2_71AWE

AOE

ABE0

ABE1

ABE2

ABE3

TSCLK0

TFS0

DT0PRI

DT0SEC

CONFIG_CLK_TSCLK1

CONFIG_INIT_B_TFS1

DT1PRI

DT1SEC

TMR0

TMR2

PF14

PF12

PF10

PF8

PF4

PF6

PF2

PF0

B2_L40N_L21_J2_9

B2_L39N_L19_J2_11

B2_C22_J2_17

B2_L38N_L17_J2_23

B2_L35N_K21_J2_25

B2_L34N_K19_J2_27

B2_L33N_K17_J2_29

B2_L32N_J21_J2_31

B2_L31N_J18_J2_33

B2_L29N_H21_J2_35

B2_L28N_H18_J2_37

B2_L27N_G21_J2_39

B2_L26N_G20_J2_41

B2_L22N_G17_J2_43

B2_L24N_F20_J2_45

B2_L23N_F19_J2_47

B2_L21N_E21_J2_49

B2_L20N_E19_J2_51

B2_L19N_E18_J2_53

B2_L17N_D21_J2_55

B2_L16N_D20_J2_57B2_L16P_D19_J2_58

B2_L17P_D22_J2_56

B2_L19P_F18_J2_54

B2_L20P_E20_J2_52

B2_L21P_E22_J2_50

B2_L23P_G19_J2_48

B2_L24P_F21_J2_46

B2_L22P_G18_J2_44

B2_L26P_H19_J2_42

B2_L27P_G22_J2_40

B2_L28P_J17_J2_38

B2_L29P_H22_J2_36

B2_L31P_J19_J2_34

B2_L32P_J22_J2_32

B2_L33P_K18_J2_30

B2_L34P_K20_J2_28

B2_L35P_K22_J2_26

B2_L38P_L18_J2_24

IO_L01P_2_VRN_2_C21_J2_16

B2_L40P_L22_J2_10

B2_L39P_L20_J2_12

MOSI

MISO

UDEF12

AMS3

AMS2

AMS0

ARDY

AMS1

AREAWE

AOE

ABE0

ABE1

ABE2

ABE3

RSCLK1

RSCLK0

RFS1

DR1PRI

DR1SEC

AMS2

AMS3

DR0SEC

DR0PRI

RFS0

TMR3

SPIDS0

C56

060301UF

80510UFC55

33V_EI

33V

4

3

2

1

A B C D

20 Cotton Road

Nashua NH 03063

A B C D

4

3

2

1

PH 1-800-ANALOGD

C

Title

Size Board No

Date Sheet of

DEVICESANALOG

DNP = Do Not Populate

Rev

BLACKFIN FPGA EZ-EXTENDER

A0199-2005 10

33V

25V33V

33V

33V

VCCO_2_H17

VCCO_2_H20

VCCO_2_J16

VCCO_2_K16

VCCO_2_L16

IO_C22

IO_L16N_2_D20

IO_L16P_2_D19

IO_L17N_2_D21

IO_L17P_2_VREF_2_D22

IO_L19N_2_E18

IO_L19P_2_F18

IO_L20N_2_E19

IO_L20P_2_E20

IO_L21N_2_E21

IO_L21P_2_E22

IO_L22N_2_G17

IO_L22P_2_G18

IO_L23N_2_VREF_2_F19

IO_L23P_2_G19

IO_L24N_2_F20

IO_L24P_2_F21

IO_L26N_2_G20

IO_L26P_2_H19

IO_L27N_2_G21

IO_L27P_2_G22

IO_L28N_2_H18

IO_L28P_2_J17

IO_L29N_2_H21

IO_L29P_2_H22

IO_L31N_2_J18

IO_L31P_2_J19

IO_L32N_2_J21

IO_L32P_2_J22

IO_L33N_2_K17

IO_L33P_2_K18

IO_L34N_2_VREF_2_K19

IO_L34P_2_K20

IO_L35N_2_K21

IO_L35P_2_K22

IO_L38N_2_L17

IO_L38P_2_L18

IO_L39N_2_L19

IO_L39P_2_L20

IO_L40N_2_L21

IO_L40P_2_VREF_2_L22

IO_L01N_2_VRP_2_C20

IO_L01P_2_VRN_2_C21

VCCO_3_M16

VCCO_3_N16

VCCO_3_P16

VCCO_3_R17

VCCO_3_R20

IO_L16N_3_W22

IO_L16P_3_Y22

IO_L17N_3_V19

IO_L17P_3_VREF_3_W19

IO_L19N_3_W21

IO_L19P_3_W20

IO_L20N_3_U19

IO_L20P_3_V20

IO_L21N_3_V22

IO_L21P_3_V21

IO_L22N_3_T17

IO_L22P_3_U18

IO_L23N_3_U21

IO_L23P_3_VREF_3_U20

IO_L24N_3_R18

IO_L24P_3_T18

IO_L26N_3_T20

IO_L26P_3_T19

IO_L27N_3_T22

IO_L27P_3_T21

IO_L28N_3_R22

IO_L28P_3_R21

IO_L29N_3_P19

IO_L29P_3_R19

IO_L31N_3_P18

IO_L31P_3_P17

IO_L32N_3_P22

IO_L32P_3_P21

IO_L33N_3_N18

IO_L33P_3_N17

IO_L34N_3_N20

IO_L34P_3_VREF_3_N19

IO_L35N_3_N22

IO_L35P_3_N21

IO_L38N_3_M18

IO_L38P_3_M17

IO_L39N_3_M20

IO_L39P_3_M19

IO_L40N_3_VREF_3_M22

IO_L40P_3_M21

IO_L01N_3_VRP_3_Y20

IO_L01P_3_VRN_3_Y19

IO_Y21

FPGAFPGA

LAYOUT NOTE PLACE NEAR FPGA

9-27-2005_1144 7 12

H17

H20

J16

K16

L16

C22

D20

D19

D21

D22

E18

F18

E19

E20

E21

E22

G17

G18

F19

G19

F20

F21

G20

H19

G21

G22

H18

J17

H21

H22

J18

J19

J21

J22

K17

K18

K19

K20

K21

K22

L17

L18

L19

L20

L21

L22

C20

C21

M16

N16

P16

R17

R20

W22

Y22

V19

W19

W21

W20

U19

V20

V22

V21

T17

U18

U21

U20

R18

T18

T20

T19

T22

T21

R22

R21

P19

R19

P18

P17

P22

P21

N18

N17

N20

N19

N22

N21

M18

M17

M20

M19

M22

M21

Y20

Y19

Y21

U1

FG456XC3S1000

2

4

8

10

6

12

14

16

24

22

20

18

26

28

3

5

7

9

11

13

15

17

19

21

23

25

27

1P5

IDC14X214X2

1

27

25

23

21

19

17

15

13

11

9

7

5

3

28

26

18

20

22

24

16

14

12

6

10

8

4

2P7

IDC14X214X2

VCCO_2

B2_L26P_H19_J2_42

DNP0603

R55B2_L24P_F21_J2_46

R56

0603DNP

B2_L23P_G19_J2_48

B2_L26N_G20_J2_41

B2_L24N_F20_J2_45

B2_L23N_F19_J2_47 B2_L23P_G19_J2_48

B2_L24P_F21_J2_46

B2_L26P_H19_J2_42

R32

0603DNP

TMR0

VCCO_2

PF221

2X1IDC2X1

JP3

CONFIG_PROG_B

1 2JP2

IDC2X12X1

PF3

CONFIG_INIT_B_TFS1

CONFIG_CLK_TSCLK1

RSCLK1

RFS1

IO_L01N_2_VRP_2_C20

IO_L01P_2_VRN_2_C21_J2_16

B2_L22N_G17_J2_43

B2_L22P_G18_J2_44

B2_L32N_J21_J2_31

SPIDS0

PF0

SCK

NMI

TMR1

DR1SEC

TMR3

DR0PRI

DR1PRI

RFS0

DR0SEC

PF15

PF13

RSCLK0

PF7

PF9

PF6

PF11

PF1

PF3

PF5

MOSI

MISO

UDEF12

TMR2

DT1SEC

DT1PRI

DT0SEC

TSCLK0

PF14

PF12

PF10

PF8

PF4

PF2

FPGA BANKS 2 + 3

DT0PRI

TFS0

B2_L40P_L22_J2_10

B2_L40N_L21_J2_9

B2_L39P_L20_J2_12

B2_L39N_L19_J2_11

B2_L38P_L18_J2_24

B2_L38N_L17_J2_23

B2_L35P_K22_J2_26

B2_L35N_K21_J2_25

B2_L34P_K20_J2_28

B2_L34N_K19_J2_27

B2_L33P_K18_J2_30

B2_L33N_K17_J2_29

B2_L32P_J22_J2_32

B2_L31P_J19_J2_34

B2_L31N_J18_J2_33

B2_L29P_H22_J2_36

B2_L29N_H21_J2_35

B2_L28P_J17_J2_38

B2_L28N_H18_J2_37

B2_L27P_G22_J2_40

B2_L27N_G21_J2_39

B2_L26P_H19_J2_42

B2_L26N_G20_J2_41

B2_L24P_F21_J2_46

B2_L24N_F20_J2_45

B2_L23P_G19_J2_48

B2_L23N_F19_J2_47

B2_L21P_E22_J2_50

B2_L21N_E21_J2_49

B2_L20P_E20_J2_52

B2_L20N_E19_J2_51

B2_L19P_F18_J2_54

B2_L19N_E18_J2_53

B2_L17P_D22_J2_56

B2_L17N_D21_J2_55

B2_L16P_D19_J2_58

B2_L16N_D20_J2_57

B2_C22_J2_17

3

2

1

3X1IDC3X1

P10

IO_L01P_2_VRN_2_C21_J2_16

IO_L01N_2_VRP_2_C20

VCCO_2

CONFIG_DONE

B2_L22N_G17_J2_43

B2_L17N_D21_J2_55

B2_L19N_E18_J2_53

B2_L20N_E19_J2_51

B2_L21N_E21_J2_49

B2_L16N_D20_J2_57

IO_L01N_2_VRP_2_C20

B2_L16P_D19_J2_58

B2_L20P_E20_J2_52

B2_L19P_F18_J2_54

B2_L17P_D22_J2_56

B2_L22P_G18_J2_44

B2_L21P_E22_J2_50

B2_C22_J2_17

IO_L01P_2_VRN_2_C21_J2_16

B2_L40N_L21_J2_9

B2_L39N_L19_J2_11

B2_L38N_L17_J2_23

B2_L35N_K21_J2_25

B2_L34N_K19_J2_27

B2_L33N_K17_J2_29

B2_L32N_J21_J2_31

B2_L31N_J18_J2_33

B2_L29N_H21_J2_35

B2_L28N_H18_J2_37

B2_L27N_G21_J2_39

B2_L40P_L22_J2_10

B2_L34P_K20_J2_28

B2_L35P_K22_J2_26

B2_L38P_L18_J2_24

B2_L39P_L20_J2_12

B2_L33P_K18_J2_30

B2_L32P_J22_J2_32

B2_L28P_J17_J2_38

B2_L31P_J19_J2_34

B2_L29P_H22_J2_36

B2_L27P_G22_J2_40

DNP0603

R33

B2_L23N_F19_J2_47

B2_L24N_F20_J2_45

B2_L26N_G20_J2_41

DNP0603

R57

001UF0603

C60 C59

0603001UF 001UF

0603

C58 C57

0603001UF

C82

0603001UF 001UF

0603

C81 C62

0603001UF001UF

0603

C61

VCCO_2

4

3

2

1

A B C D

20 Cotton Road

Nashua NH 03063

A B C D

4

3

2

1

PH 1-800-ANALOGD

C

Title

Size Board No

Date Sheet of

DEVICESANALOG

DNP = Do Not Populate

Rev

BLACKFIN FPGA EZ-EXTENDER

A0199-2005 10

Expanison ConnectorExpanison Connector

Bottom Of Board Top Of BoardExpansion Connector 3

EXPANSION INTERFACE (TYPE B)

P3P3

9-9-2005_1029 128

EXPANSION INTERFACE CONNECTOR 1

33V_EI5V_EI

1

10

11 12

13 14

15 16

17 18

19

2

20

21 22

23 24

25 26

27 28

29

3

30

31 32

33 34

35 36

37 38

39

4

40

41 42

43 44

45 46

47 48

49

5

50

51 52

53 54

55 56

57 58

59

6

60

61 62

63 64

65 66

67 68

69

7

70

71 72

73 74

75 76

77 78

79

8

80

81 82

83 84

85 86

87 88

89

9

90

P3

CON01845X2

1

10

1112

1314

1516

1718

19

2

20

2122

2324

2526

2728

29

3

30

3132

3334

3536

3738

39

4

40

4142

4344

4546

4748

49

5

50

5152

5354

5556

5758

59

6

60

6162

6364

6566

6768

69

7

70

7172

7374

7576

7778

79

8

80

8182

8384

8586

8788

89

9

90

J3

CON01945X2

TX0

TX1

UDEF17

UDEF19

UDEF21

UDEF23

UDEF25

UDEF29

UDEF27

RESET

UDEF32

UDEF34

UDEF36

UDEF38

UDEF40

B5_L01N_RDWR_B_Y4_J3_1

P3_42

P3_[190]

P3_86

P3_84

P3_82

P3_80

P3_78

P3_76

P3_74

P3_72

P3_70

P3_68

P3_64

P3_62

P3_60

P3_58

P3_56

P3_54

P3_52

P3_50

P3_48

P3_46

P3_42

P3_79

P3_89

P3_77

P3_75

P3_73

P3_71

P3_69

P3_67

P3_63

P3_61

P3_59

P3_57

P3_55

P3_53

P3_51

P3_49

P3_47

P3_45

P3_51

P3_79

P3_89

P3_77

P3_75

P3_73

P3_71

P3_69

P3_67

P3_63

P3_61

P3_59

P3_57

P3_55

P3_53

P3_49

P3_47

P3_45

P3_86

P3_84

P3_82

P3_80

P3_78

P3_76

P3_74

P3_72

P3_70

P3_68

P3_64

P3_62

P3_60

P3_58

P3_56

P3_54

P3_52

P3_50

P3_48

P3_46

B5_L27N_W9_J3_31

B5_L28N_D6_AB9_J3_33

B5_L29N_Y10_J3_35

B5_L30N_AB10_J3_37

B5_L31N_D4_W11_J3_39

B5_L10N_VRP_AB5_J3_9

B5_L25N_AB8_J3_21

B5_L24N_W8_J3_19

B5_L22N_AB7_J3_17

B5_L19N_Y7_J3_15

B5_L16N_AA6_J3_13

B5_L15N_W6_J3_11

B5_L09N_Y5_J3_7

B5_L06N_AB4_J3_5

B5_U6_J3_23

B5_V7_J3_29

B5_U9_J3_41

B5_L31P_D5_V11_J3_40

B5_L30P_AA10_J3_38

B5_L29P_W10_J3_36

B5_L28P_D7_AA9_J3_34

B5_L27P_V9_J3_32

B5_L32N_GCLK3_AA11_J3_30

B5_U7_J3_28

B5_L25P_AA8_J3_22

B5_L24P_V8_J3_20

B5_L22P_AA7_J3_18

B5_L19P_W7_J3_16

B5_L16P_Y6_J3_14

B5_L15P_V6_J3_12

B5_L10P_VRN_AA5_J3_10

B5_L09P_W5_J3_8

B5_L06P_AA4_J3_6

B5_L01P_CS_B_AA3_J3_2

B5_AB11_J3_90

B5_U11_J3_83

B5_V10_J3_85

B5_U10_J3_81

UDEF43

BGH

BG

BR

UDEF30

UDEF28

UDEF26

UDEF24

UDEF22

UDEF20

UDEF18

UDEF16

RX1

RX0

UDEF14 UDEF15

CLK_OUT_EXP1

UDEF31

UDEF33

UDEF35

UDEF37

UDEF39

UDEF41

33V_EI

C84

060301UF

80510UFC83

C8610UF805

01UF0603

C85

5V_EI

33V

33V

25V 33V

33V

33V

33V

4

3

2

1

A B C D

20 Cotton Road

Nashua NH 03063

A B C D

4

3

2

1

PH 1-800-ANALOGD

C

Title

Size Board No

Date Sheet of

DEVICESANALOG

DNP = Do Not Populate

Rev

BLACKFIN FPGA EZ-EXTENDER

A0199-2005 10

VCCO_4_T12

VCCO_4_T13

VCCO_4_T14

VCCO_4_U15

VCCO_4_Y15

IO_U16

IO_U17

IO_W13

IO_W14

IO_VREF_4_V18

IO_VREF_4_Y16

IO_VREF_4_AB13

IO_L05N_4_AA19

IO_L05P_4_AB19

IO_L06N_4_VREF_4_W18

IO_L06P_4_Y18

IO_L09N_4_AA18

IO_L09P_4_AB18

IO_L10N_4_V17

IO_L10P_4_W17

IO_L15N_4_Y17

IO_L15P_4_AA17

IO_L16N_4_V16

IO_L16P_4_W16

IO_L19N_4_AA16

IO_L19P_4_AB16

IO_L22N_4_VREF_4_V15

IO_L22P_4_W15

IO_L24N_4_AA15

IO_L24P_4_AB15

IO_L25N_4_U14

IO_L25P_4_V14

IO_L27N_4_DIN_D0_AA14

IO_L27P_4_D1_AB14

IO_L28N_4_U13

IO_L28P_4_V13

IO_L29N_4_Y13

IO_L29P_4_AA13

IO_L30N_4_D2_U12

IO_L30P_4_D3_V12

IO_L31N_4_INIT_B_W12

IO_L31P_4_DOUT_BUSY_Y12

IO_L01N_4_VRP_4_AA20

IO_L01P_4_VRN_4_AB20

IO_L32N_4_GCLK1_AA12

IO_L32P_4_GCLK0_AB12

VCCO_5_T9

VCCO_5_T10

VCCO_5_T11

VCCO_5_U8

VCCO_5_Y8

IO_U7

IO_U9

IO_U10

IO_U11

IO_V7

IO_V10

IO_VREF_5_U6

IO_VREF_5_AB11

IO_L01N_5_RDWR_B_Y4

IO_L01P_5_CS_B_AA3

IO_L06N_5_AB4

IO_L06P_5_AA4

IO_L09N_5_Y5

IO_L09P_5_W5

IO_L15N_5_W6

IO_L15P_5_V6

IO_L16N_5_AA6

IO_L16P_5_Y6

IO_L19N_5_Y7

IO_L19P_5_VREF_5_W7

IO_L22N_5_AB7

IO_L22P_5_AA7

IO_L24N_5_W8

IO_L24P_5_V8

IO_L25N_5_AB8

IO_L25P_5_AA8

IO_L27N_5_VREF_5_W9

IO_L27P_5_V9

IO_L28N_5_D6_AB9

IO_L28P_5_D7_AA9

IO_L29N_5_Y10

IO_L29P_5_VREF_5_W10

IO_L30N_5_AB10

IO_L30P_5_AA10

IO_L31N_5_D4_W11

IO_L31P_5_D5_V11

IO_L32N_5_GCLK3_AA11

IO_L32P_5_GCLK2_Y11

IO_L10N_5_VRP_5_AB5

IO_L10P_5_VRN_5_AA5

FPGAFPGA

1299-27-2005_1144

T12

T13

T14

U15

Y15

U16

U17

W13

W14

V18

Y16

AB13

AA19

AB19

W18

Y18

AA18

AB18

V17

W17

Y17

AA17

V16

W16

AA16

AB16

V15

W15

AA15

AB15

U14

V14

AA14

AB14

U13

V13

Y13

AA13

U12

V12

W12

Y12

AA20

AB20

AA12

AB12

T9

T10

T11

U8

Y8

U7

U9

U10

U11

V7

V10

U6

AB11

Y4

AA3

AB4

AA4

Y5

W5

W6

V6

AA6

Y6

Y7

W7

AB7

AA7

W8

V8

AB8

AA8

W9

V9

AB9

AA9

Y10

W10

AB10

AA10

W11

V11

AA11

Y11

AB5

AA5

U1

FG456XC3S1000

7

2

4

8

10

6

3

9

11

13

15

17

19

21

23

25

12

14

16

24

26

22

20

18

1

5

P16

IDC13X213X2

5

1

18

20

22

26

24

16

14

12

25

23

21

19

17

15

13

11

9

3

6

10

8

4

2

7

P17

IDC13X213X2

R46

060310K

R43

0603DNP

FPGA BANKS 4 + 5

VCCO_5

CONFIG_INIT_B_TFS1

CLK_OUT_EXP1

B4_L32N_GCKL1_AA12

R9

06030

B5_L10N_VRP_AB5_J3_9

B5_L10N_VRP_AB5_J3_9

B5_L10P_VRN_AA5_J3_10

VCCO_5

B5_L32P_GCLK2_Y1

B5_L32N_GCLK3_AA11_J3_30

CONFIG_DIN_DT1PRI

UDEF16

UDEF38

UDEF14

RX0

TX0

RX1

TX1

UDEF20

UDEF21

UDEF23

UDEF17

UDEF25

UDEF24

UDEF22

RESET

UDEF30

UDEF29

UDEF27

UDEF26

UDEF35

UDEF34

UDEF33

UDEF32

UDEF31

UDEF15

UDEF28

UDEF41

UDEF40

UDEF39

UDEF37

UDEF36

BR

UDEF43

BG

BGH

UDEF19

B5_L31P_D5_V11_J3_40

B5_L31N_D4_W11_J3_39

B5_L30P_AA10_J3_38

B5_L30N_AB10_J3_37

B5_L29P_W10_J3_36

B5_L29N_Y10_J3_35

B5_L28P_D7_AA9_J3_34

B5_L28N_D6_AB9_J3_33

B5_L27P_V9_J3_32

B5_L27N_W9_J3_31

B5_L25P_AA8_J3_22

B5_L25N_AB8_J3_21

B5_L24P_V8_J3_20

B5_L24N_W8_J3_19

B5_L22P_AA7_J3_18

B5_L22N_AB7_J3_17

B5_L19P_W7_J3_16

B5_L19N_Y7_J3_15

B5_L16P_Y6_J3_14

B5_L16N_AA6_J3_13

B5_L15P_V6_J3_12

B5_L15N_W6_J3_11

B5_L09P_W5_J3_8

B5_L09N_Y5_J3_7

B5_L06P_AA4_J3_6

B5_L06N_AB4_J3_5

B5_L01P_CS_B_AA3_J3_2

B5_L01N_RDWR_B_Y4_J3_1

B5_AB11_J3_90

B5_U6_J3_23

B5_V10_J3_85

B5_V7_J3_29

B5_U11_J3_83

B5_U10_J3_81

B5_U9_J3_41

B5_U7_J3_28

UDEF18

3

2

1

3X1IDC3X1

P11

B5_L29N_Y10_J3_35

B5_L30N_AB10_J3_37

B5_L31N_D4_W11_J3_39

B5_U11_J3_83

B5_V10_J3_85B5_AB11_J3_90

B5_U10_J3_81

B5_L31P_D5_V11_J3_40

B5_L30P_AA10_J3_38

B5_L29P_W10_J3_36

B5_L28P_D7_AA9_J3_34

B5_L27P_V9_J3_32

B5_L28N_D6_AB9_J3_33

B5_L27N_W9_J3_31

B5_L25N_AB8_J3_21B5_L25P_AA8_J3_22

B5_L24N_W8_J3_19B5_L24P_V8_J3_20

B5_U9_J3_41B5_U6_J3_23

VCCO_5

B5_L10P_VRN_AA5_J3_10

C70

0603001UF 001UF

0603

C69 C68

0603001UF001UF

0603

C67001UF0603

C66 C65

0603001UF 001UF

0603

C64C63

0603001UF

B5_L09N_Y5_J3_7

B5_U7_J3_28 B5_V7_J3_29

B5_L10P_VRN_AA5_J3_10 B5_L10N_VRP_AB5_J3_9

B5_L15P_V6_J3_12 B5_L15N_W6_J3_11

B5_L16P_Y6_J3_14 B5_L16N_AA6_J3_13

B5_L19P_W7_J3_16 B5_L19N_Y7_J3_15

B5_L22P_AA7_J3_18 B5_L22N_AB7_J3_17

B5_L32N_GCLK3_AA11_J3_30 B5_L32P_GCLK2_Y1

B5_L01P_CS_B_AA3_J3_2 B5_L01N_RDWR_B_Y4_J3_1

B5_L06P_AA4_J3_6 B5_L06N_AB4_J3_5

B5_L09P_W5_J3_8

VCCO_5

DNP0603

R45

25V

33V

33V

4

3

2

1

A B C D

20 Cotton Road

Nashua NH 03063

A B C D

4

3

2

1

PH 1-800-ANALOGD

C

Title

Size Board No

Date Sheet of

DEVICESANALOG

DNP = Do Not Populate

Rev

BLACKFIN FPGA EZ-EXTENDER

A0199-2005 10

SN74LVC1G125

12109-27-2005_1144

2 4

1

SOT23-5SN74LVC1G125

U8

USER IO

C80

0603001UF

SW4SWT013SPST-MOMENTARY

SPST-MOMENTARYSWT013SW3

060310R42

C5

06031UF

R413300603

LED001AMBER-SMTLED8

0603330R40

LED7AMBER-SMTLED001

R393300603

R1033006030603

330R34R35

33006030603

330R36

0603330R37 R38

3300603

LED001AMBER-SMTLED2

AMBER-SMTLED001

LED3AMBER-SMTLED001

LED4AMBER-SMTLED001

LED5

LED001AMBER-SMTLED6

LED9GREEN-SMTLED001

402100R23

1 2

3 4

5 6

7 8

JP5

IDC4X24X2

AMBER-SMTLED001

LED1

B6_L01N_Y3

B6_L01P_Y2

B5_U10_J3_81

B5_AB11_J3_90

PB2

B5_V10_J3_85

B5_U11_J3_83

B5_L31N_D4_W11_J3_39

B5_L30N_AB10_J3_37

B5_L29N_Y10_J3_35

B5_L28N_D6_AB9_J3_33

B5_L27N_W9_J3_31

PB1

B5_L25N_AB8_J3_21

R47

060310K

CHOKE_COIL

4

3

2

1

A B C D

20 Cotton Road

Nashua NH 03063

A B C D

4

3

2

1

PH 1-800-ANALOGD

C

Title

Size Board No

Date Sheet of

DEVICESANALOG

DNP = Do Not Populate

Rev

BLACKFIN FPGA EZ-EXTENDER

A0199-2005 10

25V

33V

VIN

EN

SW

GND

FB

VIN

EN

SW

GND

FB

VIN

EN

SW

GND

FB

4

3

5

2

1

VR3

SOT23-5LM3475MF

1

2

5

3

4

VR2

SOT23-5LM3475MF

4

3

5

2

1

VR1

SOT23-5LM3475MF

12119-27-2005_1124

1

32

Q2

SI2

343D

SS

OT

23D

1

32

Q3

SI2

343D

SS

OT

23D

2 3

1S

I234

3DS

Q1

SO

T23

D

316KR17

0603

215KR18

0603

0603

R11105K

DNPC73

0603

0603

C72DNP

805

C741000PF

0R58

0603

1000PFC10

805

0603

R1910K

C100UFCT2

CT3100UFC

IND005

L110UH

10UHL3

IND005

10UHL2

IND005

1

2 D3

DO214ABSCHOT_RECT

3A

0603

R20200K

805

C639NF

390PFC7

0603

2

1 3A

SCHOT_RECTDO214AB

D2

499KR13

0603

1

2 D1

DO214ABSCHOT_RECT

3A

33V_EI

3

1

2

3X1IDC3X1

P13

UNREG_IN

12V

CT1100UFC

80510UFC71

R1200603

5V_EI

8051000PFC2

FER2

0603

060301UFC3

POWER

FUS00125AF1

4

1

3

2

FER1

DO-214AA

S2A_RECT

2AD5

8051000PFC1 C4

10UFC

3

1

2

3X1IDC3X1

P12

UNREG_IN

1

2

3

CON00525MM_JACK

POWER

J4

2

1P42

IDC2X12X1DNP

1

2

DNP2X1IDC2X1

P43

06030R15

C810UF805

80510UFC9

R1600603

UNREG_IN

0603

R1410K

0603

R590

4

3

2

1

A B C D

20 Cotton Road

Nashua NH 03063

A B C D

4

3

2

1

PH 1-800-ANALOGD

C

Title

Size Board No

Date Sheet of

DEVICESANALOG

DNP = Do Not Populate

Rev

BLACKFIN FPGA EZ-EXTENDER

A0199-2005 1012129-14-2005_1204

5

2

4

8

10

6

1

3

9

11

13

15

17

19

12

14

16

20

18

7

P20

SOIC20

PROTO AREA

1

3

2

SOT23D

P39

2

3

1

SOT23D

P38

2

4

5 6

3

1

SOT23-6

P411

3

65

4

2

SOT23-6

P40

PRT_NUM=DNE

11

13

15 16

14

12

2

4

6

8

109

7

5

3

1

SOIC16

P191

3

5

7

9 10

8

6

4

2

12

14

1615

13

11

SOIC16

P18

21P37

805

1 2

805

P36

21P35

805

1 2

805

P34

1 2

805

P33

21P32

805

1 2

805

P31

21P30

805

1 2

805

P29

21P28

805

1 2

805

P27

21P26

805

21P25

805

1 2

805

P24

21P23

805

1 2

805

P22

TP86

TP85

TP84

TP83

TP82

TP81

TP80

TP79 TP77

TP76

TP75

TP74

TP73

TP72

TP71

TP70

TP68

TP67

TP66

TP65

TP64

TP62

TP61

TP60

TP59

TP58

TP57

TP56

TP55

TP54

TP53

TP51

TP50

TP49

TP48

TP47

TP46

TP45

TP44

TP43

TP41

TP40

TP39

TP38

TP37

TP36

TP35

TP34

TP33

TP32

TP30

TP29

TP28

TP27

TP26

TP25

TP24

TP23

TP22

TP21

TP19

TP18

TP17

TP16

TP15

TP14

TP13

TP12

TP11

TP9

TP8

TP7

TP6

TP5

TP4

TP125

TP124

TP123

TP122

TP121

TP120

TP119

TP118

TP117

TP116

TP114

TP113

TP112

TP111

TP110

TP109

TP108

TP107TP106

TP105TP103

TP102TP101 TP100TP99

TP98 TP97

TP96 TP95

TP94TP93

TP92TP91

TP90 TP89

TP88 TP87

TP78TP69

TP63 TP52

TP42 TP31

TP20 TP10

TP115TP104

7

18

20

16

14

12

19

17

15

13

11

9

3

1

6

10

8

4

2

5

SOIC20

P21

I INDEX

Numerics connectors

25V header (P42) 2-17

AADSP-BF5333761 EZ-KIT Lite interface 2-1ADSP-BF5333761 processors boot mode

settings 2-14architecture of this EZ-Extender 2-2asynchronous static random access memory

(SRAM) xauxiliary oscillator x

Bbill of materials A-1block diagram of this EZ-Extender 2-2boot jumper See JP4

Cconfiguration jumpers See JP2 JP3

map of locations 2-18J1-3 (expansion) 2-19P1-3 (expansion) 2-19P14 (IDC) 2-19P15 (JTAG header) 2-4P16-17 (IDC) 2-19P4 (high-speed) 2-20P5 (IDC) 2-20P6 (JTAG) 2-7P7 (IDC) 2-20P8 (IDC) 2-19

customer support xiii

Ddone LED (LED10) 2-17

Eexpansion interface

connectors (P1-3 J1-3) 2-19of ADSP-BF5333761 EZ-KIT Lites ix

1-3external power supply 1-3 2-8

FField-Programmable Gate Array See FPGA

Blackfin FPGA EZ-Extender Manual I-1

INDEX

FPGAdocumentation 1-2input jumpers (JP5) 2-14softwarefirmware 1-2Xilinx Spartan package x 1-3

FPGA pinsAB10 (LED3) 2-17AB11 (JP58) 2-15AB8 (LED7) 2-17AB9 (LED5) 2-17C11 (PB1SW3) 2-15H5 (PB2SW3) 2-16M2-0 (JP4) 2-14U10 (JP56) 2-15U11 (LED1) 2-17V10 (LED8) 2-17W11 (LED2) 2-17W9 (LED6) 2-17Y10 (LED4) 2-17Y3-2 (JP52-54) 2-15

FPGA programmingblock diagram 2-3via ADSP-BF533376 processors 2-6via JTAG header 2-4via serial ROM 2-5

GGCLK1 (global clock 1) pin 1-4GCLK6 (global clock 6) pin 1-4general-purpose input push buttons 2-15 2-16

Hhigh-speed connector (P4) 2-20

IIDC connectors x 2-19 2-20installation of this EZ-Extender 1-1

JJTAG

cable 1-4 2-7header (P6) 1-5 2-4 2-7 2-14

jumpersmap of locations 2-11JP1 (boot jumper) 2-5 2-12JP2 (confug done) 2-12JP3 (config program) 2-13JP41-46 (boot mode select) 2-5 2-6 2-14JP52-56 (FPGA input) 2-14

LLEDs

map of locations 2-15LED10 (FPGA done pin) 2-4 2-5 2-17LED1-8 (status) 2-17LED9 (power) 2-17

MM2-0 (JP4) pins 2-5master serial boot mode 2-6MCS-86 Hexadecimal Object (mcs) file

format 2-6

Nnotation conventions xvi

Ooscillator x 1-4

PP12 (power in) header 2-9P13 (33V header) 2-9P42 (25V header) 2-10P43 (12V header) 2-10PB1 push button (SW3) 2-15

I-2 Blackfin FPGA EZ-Extender Manual

INDEX

PB2 push button (SW4) 2-16PF14 flag pin (ADSP-BF537 EZ-KIT Lite)

2-12PF3 flag pin (ADSP-BF53361 EZ-KIT Lite)

2-12power

12V header (P43) 2-1025V header (P42) 2-1033V header (P13) 2-9in header (P12) 2-9LED (LED9) 2-17limitations 2-8supplies 1-3 2-8

printed circuit board (PCB) 1-2product overview ixprogram push button (SW1) 2-4 2-15push buttons

See also SWx map of locations 2-15

Sserial ROM 1-5

boot jumper (JP1) 2-12 2-14programming via JTAG Header 2-7

setup of this EZ-Extender 1-1slave serial mode 2-6

SRAM memory banks 1-4status reporting 1-4 2-17SW1 (program) push button 2-4 2-15SW3 (PB1) push button 2-15SW4 (PB2) push button 2-16switching regulators 2-8

TTCK signal 2-7TDI signal 2-7TDO signal 2-7TMS signal 2-7

VVisualDSP++

flash programming utility 1-4 2-6FPGA documentation 2-6

VR1-3 regulators 2-8

XXilinx

JTAG cablesoftware 1-4 2-4 2-7JTAG header 2-12serial ROM 1-5

Blackfin FPGA EZ-Extender Manual I-3

INDEX

I-4 Blackfin FPGA EZ-Extender Manual

• Blackfin FPGA EZ-Extender Manual
• Contents
• Preface
• • Product Overview
  • Purpose of This Manual
  • Intended Audience
  • Manual Contents
  • Whatrsquos New in This Manual
  • Technical or Customer Support
  • Supported Products
  • Product Information
  • • Related Documents
    • • Table 1 Related Processor Publications
      • Table 2 Related VisualDSP++ Publications
      • • Notation Conventions
        • • 1 FPGA EZ-Extender Interfaces
          • • FPGA EZ-Extender Setup
            • • Figure 1-1 FPGA EZ-Extender Setup
              • • FPGA Software and Firmware
                • FPGA EZ-Extender Overview
                • • 2 FPGA EZ-Extender Hardware Reference
                  • • System Architecture
                    • • Figure 2-1 Block Diagram
                      • • Programming the FPGA
                        • • Figure 2-2 FPGA Programming Block Diagram
                          • FPGA Programming via JTAG
                          • • Table 2-1 P15 Connections for PFGA Programming via JTAG
                            • Table 2-2 JP1 Settings for FPGA Programming via JTAG
                            • Table 2-3 JP4 Settings for FPGA Programming via JTAG
                            • • FPGA Programming via Serial ROM
                              • • Table 2-4 JP1 Settings for FPGA Programming via Serial ROM
                                • Table 2-5 JP4 Settings for FPGA Programming in Master Serial Mode
                                • • FPGA Programming via Blackfin Application
                                  • • Table 2-6 JP1 Settings for FPGA Programming via Blackfin Processor
                                    • Table 2-7 JP4 Settings for FPGA Programming via Blackfin Processor
                                    • • Programming the Serial ROM
                                      • • Serial ROM via JTAG Header
                                        • • Table 2-8 P6 Connections for Serial ROM
                                          • • Power
                                            • • Table 2-9 Power Limitations
                                              • Power In Header (P12)
                                              • 33V Header (P13)
                                              • 25V Header (P42)
                                              • 12V Header (P43)
                                              • • Jumpers
                                                • • Figure 2-3 Jumper Locations
                                                  • Serial ROM Boot Jumper (JP1)
                                                  • • Table 2-10 JP1 Settings
                                                    • • Config Done Jumper (JP2)
                                                      • • Table 2-11 JP2 Settings
                                                        • • Config Program Jumper (JP3)
                                                          • • Table 2-12 JP3 Settings
                                                            • • Boot Jumper (JP4)
                                                              • • Table 2-13 JP4 Settings
                                                                • • FPGA Input Jumpers (JP5)
                                                                  • • Table 2-14 JP5 Settings
                                                                    • • Push Buttons and LEDs
                                                                      • • Figure 2-4 Push Button and LED Locations
                                                                        • Program Push Button (SW1)
                                                                        • PB1 Push Button (SW3)
                                                                        • PB2 Push Button (SW4)
                                                                        • Status LEDs (LED1-8)
                                                                        • • Table 2-15 Status LED (LED1-8) Settings
                                                                          • • Power LED (LED9)
                                                                            • Done LED (LED10)
                                                                            • • Connectors
                                                                              • • Figure 2-5 Connector Locations
                                                                                • Expansion Interface (P1-3 and J1-3)
                                                                                • IDC Connectors (P8 P14 P16 and P17)
                                                                                • IDC Connectors (P5 and P7)
                                                                                • High-Speed Connector (P4)
                                                                                • • A Bill Of Materials
                                                                                  • B Schematics
                                                                                  • • Title
                                                                                    • FPGA Config
                                                                                    • SRAM FPGA Banks 7 and 8
                                                                                    • Expansion Interface Connector 1
                                                                                    • FPGA Banks 0 and 1
                                                                                    • Expansion Interface Connectors 2
                                                                                    • FPGA Banks 2 and 3
                                                                                    • Expansion Interface Connector 1
                                                                                    • FPGA Banks 4 and 5
                                                                                    • User IO
                                                                                    • Power
                                                                                    • Proto Area
                                                                                    • • I Index
                                                                                      • • Numerics
                                                                                        • A
                                                                                        • B
                                                                                        • C
                                                                                        • D
                                                                                        • E
                                                                                        • F
                                                                                        • G
                                                                                        • H
                                                                                        • I
                                                                                        • J
                                                                                        • L
                                                                                        • M
                                                                                        • N
                                                                                        • O
                                                                                        • P
                                                                                        • S
                                                                                        • T
                                                                                        • V
                                                                                        • X

33V

4

3

2

1

A B C D

20 Cotton Road

Nashua NH 03063

A B C D

4

3

2

1

PH 1-800-ANALOGD

C

Title

Size Board No

Date Sheet of

DEVICESANALOG

DNP = Do Not Populate

Rev

BLACKFIN FPGA EZ-EXTENDER

A0199-2005 10

33V

25V33V

33V

33V

VCCO_2_H17

VCCO_2_H20

VCCO_2_J16

VCCO_2_K16

VCCO_2_L16

IO_C22

IO_L16N_2_D20

IO_L16P_2_D19

IO_L17N_2_D21

IO_L17P_2_VREF_2_D22

IO_L19N_2_E18

IO_L19P_2_F18

IO_L20N_2_E19

IO_L20P_2_E20

IO_L21N_2_E21

IO_L21P_2_E22

IO_L22N_2_G17

IO_L22P_2_G18

IO_L23N_2_VREF_2_F19

IO_L23P_2_G19

IO_L24N_2_F20

IO_L24P_2_F21

IO_L26N_2_G20

IO_L26P_2_H19

IO_L27N_2_G21

IO_L27P_2_G22

IO_L28N_2_H18

IO_L28P_2_J17

IO_L29N_2_H21

IO_L29P_2_H22

IO_L31N_2_J18

IO_L31P_2_J19

IO_L32N_2_J21

IO_L32P_2_J22

IO_L33N_2_K17

IO_L33P_2_K18

IO_L34N_2_VREF_2_K19

IO_L34P_2_K20

IO_L35N_2_K21

IO_L35P_2_K22

IO_L38N_2_L17

IO_L38P_2_L18

IO_L39N_2_L19

IO_L39P_2_L20

IO_L40N_2_L21

IO_L40P_2_VREF_2_L22

IO_L01N_2_VRP_2_C20

IO_L01P_2_VRN_2_C21

VCCO_3_M16

VCCO_3_N16

VCCO_3_P16

VCCO_3_R17

VCCO_3_R20

IO_L16N_3_W22

IO_L16P_3_Y22

IO_L17N_3_V19

IO_L17P_3_VREF_3_W19

IO_L19N_3_W21

IO_L19P_3_W20

IO_L20N_3_U19

IO_L20P_3_V20

IO_L21N_3_V22

IO_L21P_3_V21

IO_L22N_3_T17

IO_L22P_3_U18

IO_L23N_3_U21

IO_L23P_3_VREF_3_U20

IO_L24N_3_R18

IO_L24P_3_T18

IO_L26N_3_T20

IO_L26P_3_T19

IO_L27N_3_T22

IO_L27P_3_T21

IO_L28N_3_R22

IO_L28P_3_R21

IO_L29N_3_P19

IO_L29P_3_R19

IO_L31N_3_P18

IO_L31P_3_P17

IO_L32N_3_P22

IO_L32P_3_P21

IO_L33N_3_N18

IO_L33P_3_N17

IO_L34N_3_N20

IO_L34P_3_VREF_3_N19

IO_L35N_3_N22

IO_L35P_3_N21

IO_L38N_3_M18

IO_L38P_3_M17

IO_L39N_3_M20

IO_L39P_3_M19

IO_L40N_3_VREF_3_M22

IO_L40P_3_M21

IO_L01N_3_VRP_3_Y20

IO_L01P_3_VRN_3_Y19

IO_Y21

FPGAFPGA

LAYOUT NOTE PLACE NEAR FPGA

9-27-2005_1144 7 12

H17

H20

J16

K16

L16

C22

D20

D19

D21

D22

E18

F18

E19

E20

E21

E22

G17

G18

F19

G19

F20

F21

G20

H19

G21

G22

H18

J17

H21

H22

J18

J19

J21

J22

K17

K18

K19

K20

K21

K22

L17

L18

L19

L20

L21

L22

C20

C21

M16

N16

P16

R17

R20

W22

Y22

V19

W19

W21

W20

U19

V20

V22

V21

T17

U18

U21

U20

R18

T18

T20

T19

T22

T21

R22

R21

P19

R19

P18

P17

P22

P21

N18

N17

N20

N19

N22

N21

M18

M17

M20

M19

M22

M21

Y20

Y19

Y21

U1

FG456XC3S1000

2

4

8

10

6

12

14

16

24

22

20

18

26

28

3

5

7

9

11

13

15

17

19

21

23

25

27

1P5

IDC14X214X2

1

27

25

23

21

19

17

15

13

11

9

7

5

3

28

26

18

20

22

24

16

14

12

6

10

8

4

2P7

IDC14X214X2

VCCO_2

B2_L26P_H19_J2_42

DNP0603

R55B2_L24P_F21_J2_46

R56

0603DNP

B2_L23P_G19_J2_48

B2_L26N_G20_J2_41

B2_L24N_F20_J2_45

B2_L23N_F19_J2_47 B2_L23P_G19_J2_48

B2_L24P_F21_J2_46

B2_L26P_H19_J2_42

R32

0603DNP

TMR0

VCCO_2

PF221

2X1IDC2X1

JP3

CONFIG_PROG_B

1 2JP2

IDC2X12X1

PF3

CONFIG_INIT_B_TFS1

CONFIG_CLK_TSCLK1

RSCLK1

RFS1

IO_L01N_2_VRP_2_C20

IO_L01P_2_VRN_2_C21_J2_16

B2_L22N_G17_J2_43

B2_L22P_G18_J2_44

B2_L32N_J21_J2_31

SPIDS0

PF0

SCK

NMI

TMR1

DR1SEC

TMR3

DR0PRI

DR1PRI

RFS0

DR0SEC

PF15

PF13

RSCLK0

PF7

PF9

PF6

PF11

PF1

PF3

PF5

MOSI

MISO

UDEF12

TMR2

DT1SEC

DT1PRI

DT0SEC

TSCLK0

PF14

PF12

PF10

PF8

PF4

PF2

FPGA BANKS 2 + 3

DT0PRI

TFS0

B2_L40P_L22_J2_10

B2_L40N_L21_J2_9

B2_L39P_L20_J2_12

B2_L39N_L19_J2_11

B2_L38P_L18_J2_24

B2_L38N_L17_J2_23

B2_L35P_K22_J2_26

B2_L35N_K21_J2_25

B2_L34P_K20_J2_28

B2_L34N_K19_J2_27

B2_L33P_K18_J2_30

B2_L33N_K17_J2_29

B2_L32P_J22_J2_32

B2_L31P_J19_J2_34

B2_L31N_J18_J2_33

B2_L29P_H22_J2_36

B2_L29N_H21_J2_35

B2_L28P_J17_J2_38

B2_L28N_H18_J2_37

B2_L27P_G22_J2_40

B2_L27N_G21_J2_39

B2_L26P_H19_J2_42

B2_L26N_G20_J2_41

B2_L24P_F21_J2_46

B2_L24N_F20_J2_45

B2_L23P_G19_J2_48

B2_L23N_F19_J2_47

B2_L21P_E22_J2_50

B2_L21N_E21_J2_49

B2_L20P_E20_J2_52

B2_L20N_E19_J2_51

B2_L19P_F18_J2_54

B2_L19N_E18_J2_53

B2_L17P_D22_J2_56

B2_L17N_D21_J2_55

B2_L16P_D19_J2_58

B2_L16N_D20_J2_57

B2_C22_J2_17

3

2

1

3X1IDC3X1

P10

IO_L01P_2_VRN_2_C21_J2_16

IO_L01N_2_VRP_2_C20

VCCO_2

CONFIG_DONE

B2_L22N_G17_J2_43

B2_L17N_D21_J2_55

B2_L19N_E18_J2_53

B2_L20N_E19_J2_51

B2_L21N_E21_J2_49

B2_L16N_D20_J2_57

IO_L01N_2_VRP_2_C20

B2_L16P_D19_J2_58

B2_L20P_E20_J2_52

B2_L19P_F18_J2_54

B2_L17P_D22_J2_56

B2_L22P_G18_J2_44

B2_L21P_E22_J2_50

B2_C22_J2_17

IO_L01P_2_VRN_2_C21_J2_16

B2_L40N_L21_J2_9

B2_L39N_L19_J2_11

B2_L38N_L17_J2_23

B2_L35N_K21_J2_25

B2_L34N_K19_J2_27

B2_L33N_K17_J2_29

B2_L32N_J21_J2_31

B2_L31N_J18_J2_33

B2_L29N_H21_J2_35

B2_L28N_H18_J2_37

B2_L27N_G21_J2_39

B2_L40P_L22_J2_10

B2_L34P_K20_J2_28

B2_L35P_K22_J2_26

B2_L38P_L18_J2_24

B2_L39P_L20_J2_12

B2_L33P_K18_J2_30

B2_L32P_J22_J2_32

B2_L28P_J17_J2_38

B2_L31P_J19_J2_34

B2_L29P_H22_J2_36

B2_L27P_G22_J2_40

DNP0603

R33

B2_L23N_F19_J2_47

B2_L24N_F20_J2_45

B2_L26N_G20_J2_41

DNP0603

R57

001UF0603

C60 C59

0603001UF 001UF

0603

C58 C57

0603001UF

C82

0603001UF 001UF

0603

C81 C62

0603001UF001UF

0603

C61

VCCO_2

4

3

2

1

A B C D

20 Cotton Road

Nashua NH 03063

A B C D

4

3

2

1

PH 1-800-ANALOGD

C

Title

Size Board No

Date Sheet of

DEVICESANALOG

DNP = Do Not Populate

Rev

BLACKFIN FPGA EZ-EXTENDER

A0199-2005 10

Expanison ConnectorExpanison Connector

Bottom Of Board Top Of BoardExpansion Connector 3

EXPANSION INTERFACE (TYPE B)

P3P3

9-9-2005_1029 128

EXPANSION INTERFACE CONNECTOR 1

33V_EI5V_EI

1

10

11 12

13 14

15 16

17 18

19

2

20

21 22

23 24

25 26

27 28

29

3

30

31 32

33 34

35 36

37 38

39

4

40

41 42

43 44

45 46

47 48

49

5

50

51 52

53 54

55 56

57 58

59

6

60

61 62

63 64

65 66

67 68

69

7

70

71 72

73 74

75 76

77 78

79

8

80

81 82

83 84

85 86

87 88

89

9

90

P3

CON01845X2

1

10

1112

1314

1516

1718

19

2

20

2122

2324

2526

2728

29

3

30

3132

3334

3536

3738

39

4

40

4142

4344

4546

4748

49

5

50

5152

5354

5556

5758

59

6

60

6162

6364

6566

6768

69

7

70

7172

7374

7576

7778

79

8

80

8182

8384

8586

8788

89

9

90

J3

CON01945X2

TX0

TX1

UDEF17

UDEF19

UDEF21

UDEF23

UDEF25

UDEF29

UDEF27

RESET

UDEF32

UDEF34

UDEF36

UDEF38

UDEF40

B5_L01N_RDWR_B_Y4_J3_1

P3_42

P3_[190]

P3_86

P3_84

P3_82

P3_80

P3_78

P3_76

P3_74

P3_72

P3_70

P3_68

P3_64

P3_62

P3_60

P3_58

P3_56

P3_54

P3_52

P3_50

P3_48

P3_46

P3_42

P3_79

P3_89

P3_77

P3_75

P3_73

P3_71

P3_69

P3_67

P3_63

P3_61

P3_59

P3_57

P3_55

P3_53

P3_51

P3_49

P3_47

P3_45

P3_51

P3_79

P3_89

P3_77

P3_75

P3_73

P3_71

P3_69

P3_67

P3_63

P3_61

P3_59

P3_57

P3_55

P3_53

P3_49

P3_47

P3_45

P3_86

P3_84

P3_82

P3_80

P3_78

P3_76

P3_74

P3_72

P3_70

P3_68

P3_64

P3_62

P3_60

P3_58

P3_56

P3_54

P3_52

P3_50

P3_48

P3_46

B5_L27N_W9_J3_31

B5_L28N_D6_AB9_J3_33

B5_L29N_Y10_J3_35

B5_L30N_AB10_J3_37

B5_L31N_D4_W11_J3_39

B5_L10N_VRP_AB5_J3_9

B5_L25N_AB8_J3_21

B5_L24N_W8_J3_19

B5_L22N_AB7_J3_17

B5_L19N_Y7_J3_15

B5_L16N_AA6_J3_13

B5_L15N_W6_J3_11

B5_L09N_Y5_J3_7

B5_L06N_AB4_J3_5

B5_U6_J3_23

B5_V7_J3_29

B5_U9_J3_41

B5_L31P_D5_V11_J3_40

B5_L30P_AA10_J3_38

B5_L29P_W10_J3_36

B5_L28P_D7_AA9_J3_34

B5_L27P_V9_J3_32

B5_L32N_GCLK3_AA11_J3_30

B5_U7_J3_28

B5_L25P_AA8_J3_22

B5_L24P_V8_J3_20

B5_L22P_AA7_J3_18

B5_L19P_W7_J3_16

B5_L16P_Y6_J3_14

B5_L15P_V6_J3_12

B5_L10P_VRN_AA5_J3_10

B5_L09P_W5_J3_8

B5_L06P_AA4_J3_6

B5_L01P_CS_B_AA3_J3_2

B5_AB11_J3_90

B5_U11_J3_83

B5_V10_J3_85

B5_U10_J3_81

UDEF43

BGH

BG

BR

UDEF30

UDEF28

UDEF26

UDEF24

UDEF22

UDEF20

UDEF18

UDEF16

RX1

RX0

UDEF14 UDEF15

CLK_OUT_EXP1

UDEF31

UDEF33

UDEF35

UDEF37

UDEF39

UDEF41

33V_EI

C84

060301UF

80510UFC83

C8610UF805

01UF0603

C85

5V_EI

33V

33V

25V 33V

33V

33V

33V

4

3

2

1

A B C D

20 Cotton Road

Nashua NH 03063

A B C D

4

3

2

1

PH 1-800-ANALOGD

C

Title

Size Board No

Date Sheet of

DEVICESANALOG

DNP = Do Not Populate

Rev

BLACKFIN FPGA EZ-EXTENDER

A0199-2005 10

VCCO_4_T12

VCCO_4_T13

VCCO_4_T14

VCCO_4_U15

VCCO_4_Y15

IO_U16

IO_U17

IO_W13

IO_W14

IO_VREF_4_V18

IO_VREF_4_Y16

IO_VREF_4_AB13

IO_L05N_4_AA19

IO_L05P_4_AB19

IO_L06N_4_VREF_4_W18

IO_L06P_4_Y18

IO_L09N_4_AA18

IO_L09P_4_AB18

IO_L10N_4_V17

IO_L10P_4_W17

IO_L15N_4_Y17

IO_L15P_4_AA17

IO_L16N_4_V16

IO_L16P_4_W16

IO_L19N_4_AA16

IO_L19P_4_AB16

IO_L22N_4_VREF_4_V15

IO_L22P_4_W15

IO_L24N_4_AA15

IO_L24P_4_AB15

IO_L25N_4_U14

IO_L25P_4_V14

IO_L27N_4_DIN_D0_AA14

IO_L27P_4_D1_AB14

IO_L28N_4_U13

IO_L28P_4_V13

IO_L29N_4_Y13

IO_L29P_4_AA13

IO_L30N_4_D2_U12

IO_L30P_4_D3_V12

IO_L31N_4_INIT_B_W12

IO_L31P_4_DOUT_BUSY_Y12

IO_L01N_4_VRP_4_AA20

IO_L01P_4_VRN_4_AB20

IO_L32N_4_GCLK1_AA12

IO_L32P_4_GCLK0_AB12

VCCO_5_T9

VCCO_5_T10

VCCO_5_T11

VCCO_5_U8

VCCO_5_Y8

IO_U7

IO_U9

IO_U10

IO_U11

IO_V7

IO_V10

IO_VREF_5_U6

IO_VREF_5_AB11

IO_L01N_5_RDWR_B_Y4

IO_L01P_5_CS_B_AA3

IO_L06N_5_AB4

IO_L06P_5_AA4

IO_L09N_5_Y5

IO_L09P_5_W5

IO_L15N_5_W6

IO_L15P_5_V6

IO_L16N_5_AA6

IO_L16P_5_Y6

IO_L19N_5_Y7

IO_L19P_5_VREF_5_W7

IO_L22N_5_AB7

IO_L22P_5_AA7

IO_L24N_5_W8

IO_L24P_5_V8

IO_L25N_5_AB8

IO_L25P_5_AA8

IO_L27N_5_VREF_5_W9

IO_L27P_5_V9

IO_L28N_5_D6_AB9

IO_L28P_5_D7_AA9

IO_L29N_5_Y10

IO_L29P_5_VREF_5_W10

IO_L30N_5_AB10

IO_L30P_5_AA10

IO_L31N_5_D4_W11

IO_L31P_5_D5_V11

IO_L32N_5_GCLK3_AA11

IO_L32P_5_GCLK2_Y11

IO_L10N_5_VRP_5_AB5

IO_L10P_5_VRN_5_AA5

FPGAFPGA

1299-27-2005_1144

T12

T13

T14

U15

Y15

U16

U17

W13

W14

V18

Y16

AB13

AA19

AB19

W18

Y18

AA18

AB18

V17

W17

Y17

AA17

V16

W16

AA16

AB16

V15

W15

AA15

AB15

U14

V14

AA14

AB14

U13

V13

Y13

AA13

U12

V12

W12

Y12

AA20

AB20

AA12

AB12

T9

T10

T11

U8

Y8

U7

U9

U10

U11

V7

V10

U6

AB11

Y4

AA3

AB4

AA4

Y5

W5

W6

V6

AA6

Y6

Y7

W7

AB7

AA7

W8

V8

AB8

AA8

W9

V9

AB9

AA9

Y10

W10

AB10

AA10

W11

V11

AA11

Y11

AB5

AA5

U1

FG456XC3S1000

7

2

4

8

10

6

3

9

11

13

15

17

19

21

23

25

12

14

16

24

26

22

20

18

1

5

P16

IDC13X213X2

5

1

18

20

22

26

24

16

14

12

25

23

21

19

17

15

13

11

9

3

6

10

8

4

2

7

P17

IDC13X213X2

R46

060310K

R43

0603DNP

FPGA BANKS 4 + 5

VCCO_5

CONFIG_INIT_B_TFS1

CLK_OUT_EXP1

B4_L32N_GCKL1_AA12

R9

06030

B5_L10N_VRP_AB5_J3_9

B5_L10N_VRP_AB5_J3_9

B5_L10P_VRN_AA5_J3_10

VCCO_5

B5_L32P_GCLK2_Y1

B5_L32N_GCLK3_AA11_J3_30

CONFIG_DIN_DT1PRI

UDEF16

UDEF38

UDEF14

RX0

TX0

RX1

TX1

UDEF20

UDEF21

UDEF23

UDEF17

UDEF25

UDEF24

UDEF22

RESET

UDEF30

UDEF29

UDEF27

UDEF26

UDEF35

UDEF34

UDEF33

UDEF32

UDEF31

UDEF15

UDEF28

UDEF41

UDEF40

UDEF39

UDEF37

UDEF36

BR

UDEF43

BG

BGH

UDEF19

B5_L31P_D5_V11_J3_40

B5_L31N_D4_W11_J3_39

B5_L30P_AA10_J3_38

B5_L30N_AB10_J3_37

B5_L29P_W10_J3_36

B5_L29N_Y10_J3_35

B5_L28P_D7_AA9_J3_34

B5_L28N_D6_AB9_J3_33

B5_L27P_V9_J3_32

B5_L27N_W9_J3_31

B5_L25P_AA8_J3_22

B5_L25N_AB8_J3_21

B5_L24P_V8_J3_20

B5_L24N_W8_J3_19

B5_L22P_AA7_J3_18

B5_L22N_AB7_J3_17

B5_L19P_W7_J3_16

B5_L19N_Y7_J3_15

B5_L16P_Y6_J3_14

B5_L16N_AA6_J3_13

B5_L15P_V6_J3_12

B5_L15N_W6_J3_11

B5_L09P_W5_J3_8

B5_L09N_Y5_J3_7

B5_L06P_AA4_J3_6

B5_L06N_AB4_J3_5

B5_L01P_CS_B_AA3_J3_2

B5_L01N_RDWR_B_Y4_J3_1

B5_AB11_J3_90

B5_U6_J3_23

B5_V10_J3_85

B5_V7_J3_29

B5_U11_J3_83

B5_U10_J3_81

B5_U9_J3_41

B5_U7_J3_28

UDEF18

3

2

1

3X1IDC3X1

P11

B5_L29N_Y10_J3_35

B5_L30N_AB10_J3_37

B5_L31N_D4_W11_J3_39

B5_U11_J3_83

B5_V10_J3_85B5_AB11_J3_90

B5_U10_J3_81

B5_L31P_D5_V11_J3_40

B5_L30P_AA10_J3_38

B5_L29P_W10_J3_36

B5_L28P_D7_AA9_J3_34

B5_L27P_V9_J3_32

B5_L28N_D6_AB9_J3_33

B5_L27N_W9_J3_31

B5_L25N_AB8_J3_21B5_L25P_AA8_J3_22

B5_L24N_W8_J3_19B5_L24P_V8_J3_20

B5_U9_J3_41B5_U6_J3_23

VCCO_5

B5_L10P_VRN_AA5_J3_10

C70

0603001UF 001UF

0603

C69 C68

0603001UF001UF

0603

C67001UF0603

C66 C65

0603001UF 001UF

0603

C64C63

0603001UF

B5_L09N_Y5_J3_7

B5_U7_J3_28 B5_V7_J3_29

B5_L10P_VRN_AA5_J3_10 B5_L10N_VRP_AB5_J3_9

B5_L15P_V6_J3_12 B5_L15N_W6_J3_11

B5_L16P_Y6_J3_14 B5_L16N_AA6_J3_13

B5_L19P_W7_J3_16 B5_L19N_Y7_J3_15

B5_L22P_AA7_J3_18 B5_L22N_AB7_J3_17

B5_L32N_GCLK3_AA11_J3_30 B5_L32P_GCLK2_Y1

B5_L01P_CS_B_AA3_J3_2 B5_L01N_RDWR_B_Y4_J3_1

B5_L06P_AA4_J3_6 B5_L06N_AB4_J3_5

B5_L09P_W5_J3_8

VCCO_5

DNP0603

R45

25V

33V

33V

4

3

2

1

A B C D

20 Cotton Road

Nashua NH 03063

A B C D

4

3

2

1

PH 1-800-ANALOGD

C

Title

Size Board No

Date Sheet of

DEVICESANALOG

DNP = Do Not Populate

Rev

BLACKFIN FPGA EZ-EXTENDER

A0199-2005 10

SN74LVC1G125

12109-27-2005_1144

2 4

1

SOT23-5SN74LVC1G125

U8

USER IO

C80

0603001UF

SW4SWT013SPST-MOMENTARY

SPST-MOMENTARYSWT013SW3

060310R42

C5

06031UF

R413300603

LED001AMBER-SMTLED8

0603330R40

LED7AMBER-SMTLED001

R393300603

R1033006030603

330R34R35

33006030603

330R36

0603330R37 R38

3300603

LED001AMBER-SMTLED2

AMBER-SMTLED001

LED3AMBER-SMTLED001

LED4AMBER-SMTLED001

LED5

LED001AMBER-SMTLED6

LED9GREEN-SMTLED001

402100R23

1 2

3 4

5 6

7 8

JP5

IDC4X24X2

AMBER-SMTLED001

LED1

B6_L01N_Y3

B6_L01P_Y2

B5_U10_J3_81

B5_AB11_J3_90

PB2

B5_V10_J3_85

B5_U11_J3_83

B5_L31N_D4_W11_J3_39

B5_L30N_AB10_J3_37

B5_L29N_Y10_J3_35

B5_L28N_D6_AB9_J3_33

B5_L27N_W9_J3_31

PB1

B5_L25N_AB8_J3_21

R47

060310K

CHOKE_COIL

4

3

2

1

A B C D

20 Cotton Road

Nashua NH 03063

A B C D

4

3

2

1

PH 1-800-ANALOGD

C

Title

Size Board No

Date Sheet of

DEVICESANALOG

DNP = Do Not Populate

Rev

BLACKFIN FPGA EZ-EXTENDER

A0199-2005 10

25V

33V

VIN

EN

SW

GND

FB

VIN

EN

SW

GND

FB

VIN

EN

SW

GND

FB

4

3

5

2

1

VR3

SOT23-5LM3475MF

1

2

5

3

4

VR2

SOT23-5LM3475MF

4

3

5

2

1

VR1

SOT23-5LM3475MF

12119-27-2005_1124

1

32

Q2

SI2

343D

SS

OT

23D

1

32

Q3

SI2

343D

SS

OT

23D

2 3

1S

I234

3DS

Q1

SO

T23

D

316KR17

0603

215KR18

0603

0603

R11105K

DNPC73

0603

0603

C72DNP

805

C741000PF

0R58

0603

1000PFC10

805

0603

R1910K

C100UFCT2

CT3100UFC

IND005

L110UH

10UHL3

IND005

10UHL2

IND005

1

2 D3

DO214ABSCHOT_RECT

3A

0603

R20200K

805

C639NF

390PFC7

0603

2

1 3A

SCHOT_RECTDO214AB

D2

499KR13

0603

1

2 D1

DO214ABSCHOT_RECT

3A

33V_EI

3

1

2

3X1IDC3X1

P13

UNREG_IN

12V

CT1100UFC

80510UFC71

R1200603

5V_EI

8051000PFC2

FER2

0603

060301UFC3

POWER

FUS00125AF1

4

1

3

2

FER1

DO-214AA

S2A_RECT

2AD5

8051000PFC1 C4

10UFC

3

1

2

3X1IDC3X1

P12

UNREG_IN

1

2

3

CON00525MM_JACK

POWER

J4

2

1P42

IDC2X12X1DNP

1

2

DNP2X1IDC2X1

P43

06030R15

C810UF805

80510UFC9

R1600603

UNREG_IN

0603

R1410K

0603

R590

4

3

2

1

A B C D

20 Cotton Road

Nashua NH 03063

A B C D

4

3

2

1

PH 1-800-ANALOGD

C

Title

Size Board No

Date Sheet of

DEVICESANALOG

DNP = Do Not Populate

Rev

BLACKFIN FPGA EZ-EXTENDER

A0199-2005 1012129-14-2005_1204

5

2

4

8

10

6

1

3

9

11

13

15

17

19

12

14

16

20

18

7

P20

SOIC20

PROTO AREA

1

3

2

SOT23D

P39

2

3

1

SOT23D

P38

2

4

5 6

3

1

SOT23-6

P411

3

65

4

2

SOT23-6

P40

PRT_NUM=DNE

11

13

15 16

14

12

2

4

6

8

109

7

5

3

1

SOIC16

P191

3

5

7

9 10

8

6

4

2

12

14

1615

13

11

SOIC16

P18

21P37

805

1 2

805

P36

21P35

805

1 2

805

P34

1 2

805

P33

21P32

805

1 2

805

P31

21P30

805

1 2

805

P29

21P28

805

1 2

805

P27

21P26

805

21P25

805

1 2

805

P24

21P23

805

1 2

805

P22

TP86

TP85

TP84

TP83

TP82

TP81

TP80

TP79 TP77

TP76

TP75

TP74

TP73

TP72

TP71

TP70

TP68

TP67

TP66

TP65

TP64

TP62

TP61

TP60

TP59

TP58

TP57

TP56

TP55

TP54

TP53

TP51

TP50

TP49

TP48

TP47

TP46

TP45

TP44

TP43

TP41

TP40

TP39

TP38

TP37

TP36

TP35

TP34

TP33

TP32

TP30

TP29

TP28

TP27

TP26

TP25

TP24

TP23

TP22

TP21

TP19

TP18

TP17

TP16

TP15

TP14

TP13

TP12

TP11

TP9

TP8

TP7

TP6

TP5

TP4

TP125

TP124

TP123

TP122

TP121

TP120

TP119

TP118

TP117

TP116

TP114

TP113

TP112

TP111

TP110

TP109

TP108

TP107TP106

TP105TP103

TP102TP101 TP100TP99

TP98 TP97

TP96 TP95

TP94TP93

TP92TP91

TP90 TP89

TP88 TP87

TP78TP69

TP63 TP52

TP42 TP31

TP20 TP10

TP115TP104

7

18

20

16

14

12

19

17

15

13

11

9

3

1

6

10

8

4

2

5

SOIC20

P21

I INDEX

Numerics connectors

25V header (P42) 2-17

AADSP-BF5333761 EZ-KIT Lite interface 2-1ADSP-BF5333761 processors boot mode

settings 2-14architecture of this EZ-Extender 2-2asynchronous static random access memory

(SRAM) xauxiliary oscillator x

Bbill of materials A-1block diagram of this EZ-Extender 2-2boot jumper See JP4

Cconfiguration jumpers See JP2 JP3

map of locations 2-18J1-3 (expansion) 2-19P1-3 (expansion) 2-19P14 (IDC) 2-19P15 (JTAG header) 2-4P16-17 (IDC) 2-19P4 (high-speed) 2-20P5 (IDC) 2-20P6 (JTAG) 2-7P7 (IDC) 2-20P8 (IDC) 2-19

customer support xiii

Ddone LED (LED10) 2-17

Eexpansion interface

connectors (P1-3 J1-3) 2-19of ADSP-BF5333761 EZ-KIT Lites ix

1-3external power supply 1-3 2-8

FField-Programmable Gate Array See FPGA

Blackfin FPGA EZ-Extender Manual I-1

INDEX

FPGAdocumentation 1-2input jumpers (JP5) 2-14softwarefirmware 1-2Xilinx Spartan package x 1-3

FPGA pinsAB10 (LED3) 2-17AB11 (JP58) 2-15AB8 (LED7) 2-17AB9 (LED5) 2-17C11 (PB1SW3) 2-15H5 (PB2SW3) 2-16M2-0 (JP4) 2-14U10 (JP56) 2-15U11 (LED1) 2-17V10 (LED8) 2-17W11 (LED2) 2-17W9 (LED6) 2-17Y10 (LED4) 2-17Y3-2 (JP52-54) 2-15

FPGA programmingblock diagram 2-3via ADSP-BF533376 processors 2-6via JTAG header 2-4via serial ROM 2-5

GGCLK1 (global clock 1) pin 1-4GCLK6 (global clock 6) pin 1-4general-purpose input push buttons 2-15 2-16

Hhigh-speed connector (P4) 2-20

IIDC connectors x 2-19 2-20installation of this EZ-Extender 1-1

JJTAG

cable 1-4 2-7header (P6) 1-5 2-4 2-7 2-14

jumpersmap of locations 2-11JP1 (boot jumper) 2-5 2-12JP2 (confug done) 2-12JP3 (config program) 2-13JP41-46 (boot mode select) 2-5 2-6 2-14JP52-56 (FPGA input) 2-14

LLEDs

map of locations 2-15LED10 (FPGA done pin) 2-4 2-5 2-17LED1-8 (status) 2-17LED9 (power) 2-17

MM2-0 (JP4) pins 2-5master serial boot mode 2-6MCS-86 Hexadecimal Object (mcs) file

format 2-6

Nnotation conventions xvi

Ooscillator x 1-4

PP12 (power in) header 2-9P13 (33V header) 2-9P42 (25V header) 2-10P43 (12V header) 2-10PB1 push button (SW3) 2-15

I-2 Blackfin FPGA EZ-Extender Manual

INDEX

PB2 push button (SW4) 2-16PF14 flag pin (ADSP-BF537 EZ-KIT Lite)

2-12PF3 flag pin (ADSP-BF53361 EZ-KIT Lite)

2-12power

12V header (P43) 2-1025V header (P42) 2-1033V header (P13) 2-9in header (P12) 2-9LED (LED9) 2-17limitations 2-8supplies 1-3 2-8

printed circuit board (PCB) 1-2product overview ixprogram push button (SW1) 2-4 2-15push buttons

See also SWx map of locations 2-15

Sserial ROM 1-5

boot jumper (JP1) 2-12 2-14programming via JTAG Header 2-7

setup of this EZ-Extender 1-1slave serial mode 2-6

SRAM memory banks 1-4status reporting 1-4 2-17SW1 (program) push button 2-4 2-15SW3 (PB1) push button 2-15SW4 (PB2) push button 2-16switching regulators 2-8

TTCK signal 2-7TDI signal 2-7TDO signal 2-7TMS signal 2-7

VVisualDSP++

flash programming utility 1-4 2-6FPGA documentation 2-6

VR1-3 regulators 2-8

XXilinx

JTAG cablesoftware 1-4 2-4 2-7JTAG header 2-12serial ROM 1-5

Blackfin FPGA EZ-Extender Manual I-3

INDEX

I-4 Blackfin FPGA EZ-Extender Manual

• Blackfin FPGA EZ-Extender Manual
• Contents
• Preface
• • Product Overview
  • Purpose of This Manual
  • Intended Audience
  • Manual Contents
  • Whatrsquos New in This Manual
  • Technical or Customer Support
  • Supported Products
  • Product Information
  • • Related Documents
    • • Table 1 Related Processor Publications
      • Table 2 Related VisualDSP++ Publications
      • • Notation Conventions
        • • 1 FPGA EZ-Extender Interfaces
          • • FPGA EZ-Extender Setup
            • • Figure 1-1 FPGA EZ-Extender Setup
              • • FPGA Software and Firmware
                • FPGA EZ-Extender Overview
                • • 2 FPGA EZ-Extender Hardware Reference
                  • • System Architecture
                    • • Figure 2-1 Block Diagram
                      • • Programming the FPGA
                        • • Figure 2-2 FPGA Programming Block Diagram
                          • FPGA Programming via JTAG
                          • • Table 2-1 P15 Connections for PFGA Programming via JTAG
                            • Table 2-2 JP1 Settings for FPGA Programming via JTAG
                            • Table 2-3 JP4 Settings for FPGA Programming via JTAG
                            • • FPGA Programming via Serial ROM
                              • • Table 2-4 JP1 Settings for FPGA Programming via Serial ROM
                                • Table 2-5 JP4 Settings for FPGA Programming in Master Serial Mode
                                • • FPGA Programming via Blackfin Application
                                  • • Table 2-6 JP1 Settings for FPGA Programming via Blackfin Processor
                                    • Table 2-7 JP4 Settings for FPGA Programming via Blackfin Processor
                                    • • Programming the Serial ROM
                                      • • Serial ROM via JTAG Header
                                        • • Table 2-8 P6 Connections for Serial ROM
                                          • • Power
                                            • • Table 2-9 Power Limitations
                                              • Power In Header (P12)
                                              • 33V Header (P13)
                                              • 25V Header (P42)
                                              • 12V Header (P43)
                                              • • Jumpers
                                                • • Figure 2-3 Jumper Locations
                                                  • Serial ROM Boot Jumper (JP1)
                                                  • • Table 2-10 JP1 Settings
                                                    • • Config Done Jumper (JP2)
                                                      • • Table 2-11 JP2 Settings
                                                        • • Config Program Jumper (JP3)
                                                          • • Table 2-12 JP3 Settings
                                                            • • Boot Jumper (JP4)
                                                              • • Table 2-13 JP4 Settings
                                                                • • FPGA Input Jumpers (JP5)
                                                                  • • Table 2-14 JP5 Settings
                                                                    • • Push Buttons and LEDs
                                                                      • • Figure 2-4 Push Button and LED Locations
                                                                        • Program Push Button (SW1)
                                                                        • PB1 Push Button (SW3)
                                                                        • PB2 Push Button (SW4)
                                                                        • Status LEDs (LED1-8)
                                                                        • • Table 2-15 Status LED (LED1-8) Settings
                                                                          • • Power LED (LED9)
                                                                            • Done LED (LED10)
                                                                            • • Connectors
                                                                              • • Figure 2-5 Connector Locations
                                                                                • Expansion Interface (P1-3 and J1-3)
                                                                                • IDC Connectors (P8 P14 P16 and P17)
                                                                                • IDC Connectors (P5 and P7)
                                                                                • High-Speed Connector (P4)
                                                                                • • A Bill Of Materials
                                                                                  • B Schematics
                                                                                  • • Title
                                                                                    • FPGA Config
                                                                                    • SRAM FPGA Banks 7 and 8
                                                                                    • Expansion Interface Connector 1
                                                                                    • FPGA Banks 0 and 1
                                                                                    • Expansion Interface Connectors 2
                                                                                    • FPGA Banks 2 and 3
                                                                                    • Expansion Interface Connector 1
                                                                                    • FPGA Banks 4 and 5
                                                                                    • User IO
                                                                                    • Power
                                                                                    • Proto Area
                                                                                    • • I Index
                                                                                      • • Numerics
                                                                                        • A
                                                                                        • B
                                                                                        • C
                                                                                        • D
                                                                                        • E
                                                                                        • F
                                                                                        • G
                                                                                        • H
                                                                                        • I
                                                                                        • J
                                                                                        • L
                                                                                        • M
                                                                                        • N
                                                                                        • O
                                                                                        • P
                                                                                        • S
                                                                                        • T
                                                                                        • V
                                                                                        • X

4

3

2

1

A B C D

20 Cotton Road

Nashua NH 03063

A B C D

4

3

2

1

PH 1-800-ANALOGD

C

Title

Size Board No

Date Sheet of

DEVICESANALOG

DNP = Do Not Populate

Rev

BLACKFIN FPGA EZ-EXTENDER

A0199-2005 10

Expanison ConnectorExpanison Connector

Bottom Of Board Top Of BoardExpansion Connector 3

EXPANSION INTERFACE (TYPE B)

P3P3

9-9-2005_1029 128

EXPANSION INTERFACE CONNECTOR 1

33V_EI5V_EI

1

10

11 12

13 14

15 16

17 18

19

2

20

21 22

23 24

25 26

27 28

29

3

30

31 32

33 34

35 36

37 38

39

4

40

41 42

43 44

45 46

47 48

49

5

50

51 52

53 54

55 56

57 58

59

6

60

61 62

63 64

65 66

67 68

69

7

70

71 72

73 74

75 76

77 78

79

8

80

81 82

83 84

85 86

87 88

89

9

90

P3

CON01845X2

1

10

1112

1314

1516

1718

19

2

20

2122

2324

2526

2728

29

3

30

3132

3334

3536

3738

39

4

40

4142

4344

4546

4748

49

5

50

5152

5354

5556

5758

59

6

60

6162

6364

6566

6768

69

7

70

7172

7374

7576

7778

79

8

80

8182

8384

8586

8788

89

9

90

J3

CON01945X2

TX0

TX1

UDEF17

UDEF19

UDEF21

UDEF23

UDEF25

UDEF29

UDEF27

RESET

UDEF32

UDEF34

UDEF36

UDEF38

UDEF40

B5_L01N_RDWR_B_Y4_J3_1

P3_42

P3_[190]

P3_86

P3_84

P3_82

P3_80

P3_78

P3_76

P3_74

P3_72

P3_70

P3_68

P3_64

P3_62

P3_60

P3_58

P3_56

P3_54

P3_52

P3_50

P3_48

P3_46

P3_42

P3_79

P3_89

P3_77

P3_75

P3_73

P3_71

P3_69

P3_67

P3_63

P3_61

P3_59

P3_57

P3_55

P3_53

P3_51

P3_49

P3_47

P3_45

P3_51

P3_79

P3_89

P3_77

P3_75

P3_73

P3_71

P3_69

P3_67

P3_63

P3_61

P3_59

P3_57

P3_55

P3_53

P3_49

P3_47

P3_45

P3_86

P3_84

P3_82

P3_80

P3_78

P3_76

P3_74

P3_72

P3_70

P3_68

P3_64

P3_62

P3_60

P3_58

P3_56

P3_54

P3_52

P3_50

P3_48

P3_46

B5_L27N_W9_J3_31

B5_L28N_D6_AB9_J3_33

B5_L29N_Y10_J3_35

B5_L30N_AB10_J3_37

B5_L31N_D4_W11_J3_39

B5_L10N_VRP_AB5_J3_9

B5_L25N_AB8_J3_21

B5_L24N_W8_J3_19

B5_L22N_AB7_J3_17

B5_L19N_Y7_J3_15

B5_L16N_AA6_J3_13

B5_L15N_W6_J3_11

B5_L09N_Y5_J3_7

B5_L06N_AB4_J3_5

B5_U6_J3_23

B5_V7_J3_29

B5_U9_J3_41

B5_L31P_D5_V11_J3_40

B5_L30P_AA10_J3_38

B5_L29P_W10_J3_36

B5_L28P_D7_AA9_J3_34

B5_L27P_V9_J3_32

B5_L32N_GCLK3_AA11_J3_30

B5_U7_J3_28

B5_L25P_AA8_J3_22

B5_L24P_V8_J3_20

B5_L22P_AA7_J3_18

B5_L19P_W7_J3_16

B5_L16P_Y6_J3_14

B5_L15P_V6_J3_12

B5_L10P_VRN_AA5_J3_10

B5_L09P_W5_J3_8

B5_L06P_AA4_J3_6

B5_L01P_CS_B_AA3_J3_2

B5_AB11_J3_90

B5_U11_J3_83

B5_V10_J3_85

B5_U10_J3_81

UDEF43

BGH

BG

BR

UDEF30

UDEF28

UDEF26

UDEF24

UDEF22

UDEF20

UDEF18

UDEF16

RX1

RX0

UDEF14 UDEF15

CLK_OUT_EXP1

UDEF31

UDEF33

UDEF35

UDEF37

UDEF39

UDEF41

33V_EI

C84

060301UF

80510UFC83

C8610UF805

01UF0603

C85

5V_EI

33V

33V

25V 33V

33V

33V

33V

4

3

2

1

A B C D

20 Cotton Road

Nashua NH 03063

A B C D

4

3

2

1

PH 1-800-ANALOGD

C

Title

Size Board No

Date Sheet of

DEVICESANALOG

DNP = Do Not Populate

Rev

BLACKFIN FPGA EZ-EXTENDER

A0199-2005 10

VCCO_4_T12

VCCO_4_T13

VCCO_4_T14

VCCO_4_U15

VCCO_4_Y15

IO_U16

IO_U17

IO_W13

IO_W14

IO_VREF_4_V18

IO_VREF_4_Y16

IO_VREF_4_AB13

IO_L05N_4_AA19

IO_L05P_4_AB19

IO_L06N_4_VREF_4_W18

IO_L06P_4_Y18

IO_L09N_4_AA18

IO_L09P_4_AB18

IO_L10N_4_V17

IO_L10P_4_W17

IO_L15N_4_Y17

IO_L15P_4_AA17

IO_L16N_4_V16

IO_L16P_4_W16

IO_L19N_4_AA16

IO_L19P_4_AB16

IO_L22N_4_VREF_4_V15

IO_L22P_4_W15

IO_L24N_4_AA15

IO_L24P_4_AB15

IO_L25N_4_U14

IO_L25P_4_V14

IO_L27N_4_DIN_D0_AA14

IO_L27P_4_D1_AB14

IO_L28N_4_U13

IO_L28P_4_V13

IO_L29N_4_Y13

IO_L29P_4_AA13

IO_L30N_4_D2_U12

IO_L30P_4_D3_V12

IO_L31N_4_INIT_B_W12

IO_L31P_4_DOUT_BUSY_Y12

IO_L01N_4_VRP_4_AA20

IO_L01P_4_VRN_4_AB20

IO_L32N_4_GCLK1_AA12

IO_L32P_4_GCLK0_AB12

VCCO_5_T9

VCCO_5_T10

VCCO_5_T11

VCCO_5_U8

VCCO_5_Y8

IO_U7

IO_U9

IO_U10

IO_U11

IO_V7

IO_V10

IO_VREF_5_U6

IO_VREF_5_AB11

IO_L01N_5_RDWR_B_Y4

IO_L01P_5_CS_B_AA3

IO_L06N_5_AB4

IO_L06P_5_AA4

IO_L09N_5_Y5

IO_L09P_5_W5

IO_L15N_5_W6

IO_L15P_5_V6

IO_L16N_5_AA6

IO_L16P_5_Y6

IO_L19N_5_Y7

IO_L19P_5_VREF_5_W7

IO_L22N_5_AB7

IO_L22P_5_AA7

IO_L24N_5_W8

IO_L24P_5_V8

IO_L25N_5_AB8

IO_L25P_5_AA8

IO_L27N_5_VREF_5_W9

IO_L27P_5_V9

IO_L28N_5_D6_AB9

IO_L28P_5_D7_AA9

IO_L29N_5_Y10

IO_L29P_5_VREF_5_W10

IO_L30N_5_AB10

IO_L30P_5_AA10

IO_L31N_5_D4_W11

IO_L31P_5_D5_V11

IO_L32N_5_GCLK3_AA11

IO_L32P_5_GCLK2_Y11

IO_L10N_5_VRP_5_AB5

IO_L10P_5_VRN_5_AA5

FPGAFPGA

1299-27-2005_1144

T12

T13

T14

U15

Y15

U16

U17

W13

W14

V18

Y16

AB13

AA19

AB19

W18

Y18

AA18

AB18

V17

W17

Y17

AA17

V16

W16

AA16

AB16

V15

W15

AA15

AB15

U14

V14

AA14

AB14

U13

V13

Y13

AA13

U12

V12

W12

Y12

AA20

AB20

AA12

AB12

T9

T10

T11

U8

Y8

U7

U9

U10

U11

V7

V10

U6

AB11

Y4

AA3

AB4

AA4

Y5

W5

W6

V6

AA6

Y6

Y7

W7

AB7

AA7

W8

V8

AB8

AA8

W9

V9

AB9

AA9

Y10

W10

AB10

AA10

W11

V11

AA11

Y11

AB5

AA5

U1

FG456XC3S1000

7

2

4

8

10

6

3

9

11

13

15

17

19

21

23

25

12

14

16

24

26

22

20

18

1

5

P16

IDC13X213X2

5

1

18

20

22

26

24

16

14

12

25

23

21

19

17

15

13

11

9

3

6

10

8

4

2

7

P17

IDC13X213X2

R46

060310K

R43

0603DNP

FPGA BANKS 4 + 5

VCCO_5

CONFIG_INIT_B_TFS1

CLK_OUT_EXP1

B4_L32N_GCKL1_AA12

R9

06030

B5_L10N_VRP_AB5_J3_9

B5_L10N_VRP_AB5_J3_9

B5_L10P_VRN_AA5_J3_10

VCCO_5

B5_L32P_GCLK2_Y1

B5_L32N_GCLK3_AA11_J3_30

CONFIG_DIN_DT1PRI

UDEF16

UDEF38

UDEF14

RX0

TX0

RX1

TX1

UDEF20

UDEF21

UDEF23

UDEF17

UDEF25

UDEF24

UDEF22

RESET

UDEF30

UDEF29

UDEF27

UDEF26

UDEF35

UDEF34

UDEF33

UDEF32

UDEF31

UDEF15

UDEF28

UDEF41

UDEF40

UDEF39

UDEF37

UDEF36

BR

UDEF43

BG

BGH

UDEF19

B5_L31P_D5_V11_J3_40

B5_L31N_D4_W11_J3_39

B5_L30P_AA10_J3_38

B5_L30N_AB10_J3_37

B5_L29P_W10_J3_36

B5_L29N_Y10_J3_35

B5_L28P_D7_AA9_J3_34

B5_L28N_D6_AB9_J3_33

B5_L27P_V9_J3_32

B5_L27N_W9_J3_31

B5_L25P_AA8_J3_22

B5_L25N_AB8_J3_21

B5_L24P_V8_J3_20

B5_L24N_W8_J3_19

B5_L22P_AA7_J3_18

B5_L22N_AB7_J3_17

B5_L19P_W7_J3_16

B5_L19N_Y7_J3_15

B5_L16P_Y6_J3_14

B5_L16N_AA6_J3_13

B5_L15P_V6_J3_12

B5_L15N_W6_J3_11

B5_L09P_W5_J3_8

B5_L09N_Y5_J3_7

B5_L06P_AA4_J3_6

B5_L06N_AB4_J3_5

B5_L01P_CS_B_AA3_J3_2

B5_L01N_RDWR_B_Y4_J3_1

B5_AB11_J3_90

B5_U6_J3_23

B5_V10_J3_85

B5_V7_J3_29

B5_U11_J3_83

B5_U10_J3_81

B5_U9_J3_41

B5_U7_J3_28

UDEF18

3

2

1

3X1IDC3X1

P11

B5_L29N_Y10_J3_35

B5_L30N_AB10_J3_37

B5_L31N_D4_W11_J3_39

B5_U11_J3_83

B5_V10_J3_85B5_AB11_J3_90

B5_U10_J3_81

B5_L31P_D5_V11_J3_40

B5_L30P_AA10_J3_38

B5_L29P_W10_J3_36

B5_L28P_D7_AA9_J3_34

B5_L27P_V9_J3_32

B5_L28N_D6_AB9_J3_33

B5_L27N_W9_J3_31

B5_L25N_AB8_J3_21B5_L25P_AA8_J3_22

B5_L24N_W8_J3_19B5_L24P_V8_J3_20

B5_U9_J3_41B5_U6_J3_23

VCCO_5

B5_L10P_VRN_AA5_J3_10

C70

0603001UF 001UF

0603

C69 C68

0603001UF001UF

0603

C67001UF0603

C66 C65

0603001UF 001UF

0603

C64C63

0603001UF

B5_L09N_Y5_J3_7

B5_U7_J3_28 B5_V7_J3_29

B5_L10P_VRN_AA5_J3_10 B5_L10N_VRP_AB5_J3_9

B5_L15P_V6_J3_12 B5_L15N_W6_J3_11

B5_L16P_Y6_J3_14 B5_L16N_AA6_J3_13

B5_L19P_W7_J3_16 B5_L19N_Y7_J3_15

B5_L22P_AA7_J3_18 B5_L22N_AB7_J3_17

B5_L32N_GCLK3_AA11_J3_30 B5_L32P_GCLK2_Y1

B5_L01P_CS_B_AA3_J3_2 B5_L01N_RDWR_B_Y4_J3_1

B5_L06P_AA4_J3_6 B5_L06N_AB4_J3_5

B5_L09P_W5_J3_8

VCCO_5

DNP0603

R45

25V

33V

33V

4

3

2

1

A B C D

20 Cotton Road

Nashua NH 03063

A B C D

4

3

2

1

PH 1-800-ANALOGD

C

Title

Size Board No

Date Sheet of

DEVICESANALOG

DNP = Do Not Populate

Rev

BLACKFIN FPGA EZ-EXTENDER

A0199-2005 10

SN74LVC1G125

12109-27-2005_1144

2 4

1

SOT23-5SN74LVC1G125

U8

USER IO

C80

0603001UF

SW4SWT013SPST-MOMENTARY

SPST-MOMENTARYSWT013SW3

060310R42

C5

06031UF

R413300603

LED001AMBER-SMTLED8

0603330R40

LED7AMBER-SMTLED001

R393300603

R1033006030603

330R34R35

33006030603

330R36

0603330R37 R38

3300603

LED001AMBER-SMTLED2

AMBER-SMTLED001

LED3AMBER-SMTLED001

LED4AMBER-SMTLED001

LED5

LED001AMBER-SMTLED6

LED9GREEN-SMTLED001

402100R23

1 2

3 4

5 6

7 8

JP5

IDC4X24X2

AMBER-SMTLED001

LED1

B6_L01N_Y3

B6_L01P_Y2

B5_U10_J3_81

B5_AB11_J3_90

PB2

B5_V10_J3_85

B5_U11_J3_83

B5_L31N_D4_W11_J3_39

B5_L30N_AB10_J3_37

B5_L29N_Y10_J3_35

B5_L28N_D6_AB9_J3_33

B5_L27N_W9_J3_31

PB1

B5_L25N_AB8_J3_21

R47

060310K

CHOKE_COIL

4

3

2

1

A B C D

20 Cotton Road

Nashua NH 03063

A B C D

4

3

2

1

PH 1-800-ANALOGD

C

Title

Size Board No

Date Sheet of

DEVICESANALOG

DNP = Do Not Populate

Rev

BLACKFIN FPGA EZ-EXTENDER

A0199-2005 10

25V

33V

VIN

EN

SW

GND

FB

VIN

EN

SW

GND

FB

VIN

EN

SW

GND

FB

4

3

5

2

1

VR3

SOT23-5LM3475MF

1

2

5

3

4

VR2

SOT23-5LM3475MF

4

3

5

2

1

VR1

SOT23-5LM3475MF

12119-27-2005_1124

1

32

Q2

SI2

343D

SS

OT

23D

1

32

Q3

SI2

343D

SS

OT

23D

2 3

1S

I234

3DS

Q1

SO

T23

D

316KR17

0603

215KR18

0603

0603

R11105K

DNPC73

0603

0603

C72DNP

805

C741000PF

0R58

0603

1000PFC10

805

0603

R1910K

C100UFCT2

CT3100UFC

IND005

L110UH

10UHL3

IND005

10UHL2

IND005

1

2 D3

DO214ABSCHOT_RECT

3A

0603

R20200K

805

C639NF

390PFC7

0603

2

1 3A

SCHOT_RECTDO214AB

D2

499KR13

0603

1

2 D1

DO214ABSCHOT_RECT

3A

33V_EI

3

1

2

3X1IDC3X1

P13

UNREG_IN

12V

CT1100UFC

80510UFC71

R1200603

5V_EI

8051000PFC2

FER2

0603

060301UFC3

POWER

FUS00125AF1

4

1

3

2

FER1

DO-214AA

S2A_RECT

2AD5

8051000PFC1 C4

10UFC

3

1

2

3X1IDC3X1

P12

UNREG_IN

1

2

3

CON00525MM_JACK

POWER

J4

2

1P42

IDC2X12X1DNP

1

2

DNP2X1IDC2X1

P43

06030R15

C810UF805

80510UFC9

R1600603

UNREG_IN

0603

R1410K

0603

R590

4

3

2

1

A B C D

20 Cotton Road

Nashua NH 03063

A B C D

4

3

2

1

PH 1-800-ANALOGD

C

Title

Size Board No

Date Sheet of

DEVICESANALOG

DNP = Do Not Populate

Rev

BLACKFIN FPGA EZ-EXTENDER

A0199-2005 1012129-14-2005_1204

5

2

4

8

10

6

1

3

9

11

13

15

17

19

12

14

16

20

18

7

P20

SOIC20

PROTO AREA

1

3

2

SOT23D

P39

2

3

1

SOT23D

P38

2

4

5 6

3

1

SOT23-6

P411

3

65

4

2

SOT23-6

P40

PRT_NUM=DNE

11

13

15 16

14

12

2

4

6

8

109

7

5

3

1

SOIC16

P191

3

5

7

9 10

8

6

4

2

12

14

1615

13

11

SOIC16

P18

21P37

805

1 2

805

P36

21P35

805

1 2

805

P34

1 2

805

P33

21P32

805

1 2

805

P31

21P30

805

1 2

805

P29

21P28

805

1 2

805

P27

21P26

805

21P25

805

1 2

805

P24

21P23

805

1 2

805

P22

TP86

TP85

TP84

TP83

TP82

TP81

TP80

TP79 TP77

TP76

TP75

TP74

TP73

TP72

TP71

TP70

TP68

TP67

TP66

TP65

TP64

TP62

TP61

TP60

TP59

TP58

TP57

TP56

TP55

TP54

TP53

TP51

TP50

TP49

TP48

TP47

TP46

TP45

TP44

TP43

TP41

TP40

TP39

TP38

TP37

TP36

TP35

TP34

TP33

TP32

TP30

TP29

TP28

TP27

TP26

TP25

TP24

TP23

TP22

TP21

TP19

TP18

TP17

TP16

TP15

TP14

TP13

TP12

TP11

TP9

TP8

TP7

TP6

TP5

TP4

TP125

TP124

TP123

TP122

TP121

TP120

TP119

TP118

TP117

TP116

TP114

TP113

TP112

TP111

TP110

TP109

TP108

TP107TP106

TP105TP103

TP102TP101 TP100TP99

TP98 TP97

TP96 TP95

TP94TP93

TP92TP91

TP90 TP89

TP88 TP87

TP78TP69

TP63 TP52

TP42 TP31

TP20 TP10

TP115TP104

7

18

20

16

14

12

19

17

15

13

11

9

3

1

6

10

8

4

2

5

SOIC20

P21

I INDEX

Numerics connectors

25V header (P42) 2-17

AADSP-BF5333761 EZ-KIT Lite interface 2-1ADSP-BF5333761 processors boot mode

settings 2-14architecture of this EZ-Extender 2-2asynchronous static random access memory

(SRAM) xauxiliary oscillator x

Bbill of materials A-1block diagram of this EZ-Extender 2-2boot jumper See JP4

Cconfiguration jumpers See JP2 JP3

map of locations 2-18J1-3 (expansion) 2-19P1-3 (expansion) 2-19P14 (IDC) 2-19P15 (JTAG header) 2-4P16-17 (IDC) 2-19P4 (high-speed) 2-20P5 (IDC) 2-20P6 (JTAG) 2-7P7 (IDC) 2-20P8 (IDC) 2-19

customer support xiii

Ddone LED (LED10) 2-17

Eexpansion interface

connectors (P1-3 J1-3) 2-19of ADSP-BF5333761 EZ-KIT Lites ix

1-3external power supply 1-3 2-8

FField-Programmable Gate Array See FPGA

Blackfin FPGA EZ-Extender Manual I-1

INDEX

FPGAdocumentation 1-2input jumpers (JP5) 2-14softwarefirmware 1-2Xilinx Spartan package x 1-3

FPGA pinsAB10 (LED3) 2-17AB11 (JP58) 2-15AB8 (LED7) 2-17AB9 (LED5) 2-17C11 (PB1SW3) 2-15H5 (PB2SW3) 2-16M2-0 (JP4) 2-14U10 (JP56) 2-15U11 (LED1) 2-17V10 (LED8) 2-17W11 (LED2) 2-17W9 (LED6) 2-17Y10 (LED4) 2-17Y3-2 (JP52-54) 2-15

FPGA programmingblock diagram 2-3via ADSP-BF533376 processors 2-6via JTAG header 2-4via serial ROM 2-5

GGCLK1 (global clock 1) pin 1-4GCLK6 (global clock 6) pin 1-4general-purpose input push buttons 2-15 2-16

Hhigh-speed connector (P4) 2-20

IIDC connectors x 2-19 2-20installation of this EZ-Extender 1-1

JJTAG

cable 1-4 2-7header (P6) 1-5 2-4 2-7 2-14

jumpersmap of locations 2-11JP1 (boot jumper) 2-5 2-12JP2 (confug done) 2-12JP3 (config program) 2-13JP41-46 (boot mode select) 2-5 2-6 2-14JP52-56 (FPGA input) 2-14

LLEDs

map of locations 2-15LED10 (FPGA done pin) 2-4 2-5 2-17LED1-8 (status) 2-17LED9 (power) 2-17

MM2-0 (JP4) pins 2-5master serial boot mode 2-6MCS-86 Hexadecimal Object (mcs) file

format 2-6

Nnotation conventions xvi

Ooscillator x 1-4

PP12 (power in) header 2-9P13 (33V header) 2-9P42 (25V header) 2-10P43 (12V header) 2-10PB1 push button (SW3) 2-15

I-2 Blackfin FPGA EZ-Extender Manual

INDEX

PB2 push button (SW4) 2-16PF14 flag pin (ADSP-BF537 EZ-KIT Lite)

2-12PF3 flag pin (ADSP-BF53361 EZ-KIT Lite)

2-12power

12V header (P43) 2-1025V header (P42) 2-1033V header (P13) 2-9in header (P12) 2-9LED (LED9) 2-17limitations 2-8supplies 1-3 2-8

printed circuit board (PCB) 1-2product overview ixprogram push button (SW1) 2-4 2-15push buttons

See also SWx map of locations 2-15

Sserial ROM 1-5

boot jumper (JP1) 2-12 2-14programming via JTAG Header 2-7

setup of this EZ-Extender 1-1slave serial mode 2-6

SRAM memory banks 1-4status reporting 1-4 2-17SW1 (program) push button 2-4 2-15SW3 (PB1) push button 2-15SW4 (PB2) push button 2-16switching regulators 2-8

TTCK signal 2-7TDI signal 2-7TDO signal 2-7TMS signal 2-7

VVisualDSP++

flash programming utility 1-4 2-6FPGA documentation 2-6

VR1-3 regulators 2-8

XXilinx

JTAG cablesoftware 1-4 2-4 2-7JTAG header 2-12serial ROM 1-5

Blackfin FPGA EZ-Extender Manual I-3

INDEX

I-4 Blackfin FPGA EZ-Extender Manual

• Blackfin FPGA EZ-Extender Manual
• Contents
• Preface
• • Product Overview
  • Purpose of This Manual
  • Intended Audience
  • Manual Contents
  • Whatrsquos New in This Manual
  • Technical or Customer Support
  • Supported Products
  • Product Information
  • • Related Documents
    • • Table 1 Related Processor Publications
      • Table 2 Related VisualDSP++ Publications
      • • Notation Conventions
        • • 1 FPGA EZ-Extender Interfaces
          • • FPGA EZ-Extender Setup
            • • Figure 1-1 FPGA EZ-Extender Setup
              • • FPGA Software and Firmware
                • FPGA EZ-Extender Overview
                • • 2 FPGA EZ-Extender Hardware Reference
                  • • System Architecture
                    • • Figure 2-1 Block Diagram
                      • • Programming the FPGA
                        • • Figure 2-2 FPGA Programming Block Diagram
                          • FPGA Programming via JTAG
                          • • Table 2-1 P15 Connections for PFGA Programming via JTAG
                            • Table 2-2 JP1 Settings for FPGA Programming via JTAG
                            • Table 2-3 JP4 Settings for FPGA Programming via JTAG
                            • • FPGA Programming via Serial ROM
                              • • Table 2-4 JP1 Settings for FPGA Programming via Serial ROM
                                • Table 2-5 JP4 Settings for FPGA Programming in Master Serial Mode
                                • • FPGA Programming via Blackfin Application
                                  • • Table 2-6 JP1 Settings for FPGA Programming via Blackfin Processor
                                    • Table 2-7 JP4 Settings for FPGA Programming via Blackfin Processor
                                    • • Programming the Serial ROM
                                      • • Serial ROM via JTAG Header
                                        • • Table 2-8 P6 Connections for Serial ROM
                                          • • Power
                                            • • Table 2-9 Power Limitations
                                              • Power In Header (P12)
                                              • 33V Header (P13)
                                              • 25V Header (P42)
                                              • 12V Header (P43)
                                              • • Jumpers
                                                • • Figure 2-3 Jumper Locations
                                                  • Serial ROM Boot Jumper (JP1)
                                                  • • Table 2-10 JP1 Settings
                                                    • • Config Done Jumper (JP2)
                                                      • • Table 2-11 JP2 Settings
                                                        • • Config Program Jumper (JP3)
                                                          • • Table 2-12 JP3 Settings
                                                            • • Boot Jumper (JP4)
                                                              • • Table 2-13 JP4 Settings
                                                                • • FPGA Input Jumpers (JP5)
                                                                  • • Table 2-14 JP5 Settings
                                                                    • • Push Buttons and LEDs
                                                                      • • Figure 2-4 Push Button and LED Locations
                                                                        • Program Push Button (SW1)
                                                                        • PB1 Push Button (SW3)
                                                                        • PB2 Push Button (SW4)
                                                                        • Status LEDs (LED1-8)
                                                                        • • Table 2-15 Status LED (LED1-8) Settings
                                                                          • • Power LED (LED9)
                                                                            • Done LED (LED10)
                                                                            • • Connectors
                                                                              • • Figure 2-5 Connector Locations
                                                                                • Expansion Interface (P1-3 and J1-3)
                                                                                • IDC Connectors (P8 P14 P16 and P17)
                                                                                • IDC Connectors (P5 and P7)
                                                                                • High-Speed Connector (P4)
                                                                                • • A Bill Of Materials
                                                                                  • B Schematics
                                                                                  • • Title
                                                                                    • FPGA Config
                                                                                    • SRAM FPGA Banks 7 and 8
                                                                                    • Expansion Interface Connector 1
                                                                                    • FPGA Banks 0 and 1
                                                                                    • Expansion Interface Connectors 2
                                                                                    • FPGA Banks 2 and 3
                                                                                    • Expansion Interface Connector 1
                                                                                    • FPGA Banks 4 and 5
                                                                                    • User IO
                                                                                    • Power
                                                                                    • Proto Area
                                                                                    • • I Index
                                                                                      • • Numerics
                                                                                        • A
                                                                                        • B
                                                                                        • C
                                                                                        • D
                                                                                        • E
                                                                                        • F
                                                                                        • G
                                                                                        • H
                                                                                        • I
                                                                                        • J
                                                                                        • L
                                                                                        • M
                                                                                        • N
                                                                                        • O
                                                                                        • P
                                                                                        • S
                                                                                        • T
                                                                                        • V
                                                                                        • X

33V

33V

25V 33V

33V

33V

33V

4

3

2

1

A B C D

20 Cotton Road

Nashua NH 03063

A B C D

4

3

2

1

PH 1-800-ANALOGD

C

Title

Size Board No

Date Sheet of

DEVICESANALOG

DNP = Do Not Populate

Rev

BLACKFIN FPGA EZ-EXTENDER

A0199-2005 10

VCCO_4_T12

VCCO_4_T13

VCCO_4_T14

VCCO_4_U15

VCCO_4_Y15

IO_U16

IO_U17

IO_W13

IO_W14

IO_VREF_4_V18

IO_VREF_4_Y16

IO_VREF_4_AB13

IO_L05N_4_AA19

IO_L05P_4_AB19

IO_L06N_4_VREF_4_W18

IO_L06P_4_Y18

IO_L09N_4_AA18

IO_L09P_4_AB18

IO_L10N_4_V17

IO_L10P_4_W17

IO_L15N_4_Y17

IO_L15P_4_AA17

IO_L16N_4_V16

IO_L16P_4_W16

IO_L19N_4_AA16

IO_L19P_4_AB16

IO_L22N_4_VREF_4_V15

IO_L22P_4_W15

IO_L24N_4_AA15

IO_L24P_4_AB15

IO_L25N_4_U14

IO_L25P_4_V14

IO_L27N_4_DIN_D0_AA14

IO_L27P_4_D1_AB14

IO_L28N_4_U13

IO_L28P_4_V13

IO_L29N_4_Y13

IO_L29P_4_AA13

IO_L30N_4_D2_U12

IO_L30P_4_D3_V12

IO_L31N_4_INIT_B_W12

IO_L31P_4_DOUT_BUSY_Y12

IO_L01N_4_VRP_4_AA20

IO_L01P_4_VRN_4_AB20

IO_L32N_4_GCLK1_AA12

IO_L32P_4_GCLK0_AB12

VCCO_5_T9

VCCO_5_T10

VCCO_5_T11

VCCO_5_U8

VCCO_5_Y8

IO_U7

IO_U9

IO_U10

IO_U11

IO_V7

IO_V10

IO_VREF_5_U6

IO_VREF_5_AB11

IO_L01N_5_RDWR_B_Y4

IO_L01P_5_CS_B_AA3

IO_L06N_5_AB4

IO_L06P_5_AA4

IO_L09N_5_Y5

IO_L09P_5_W5

IO_L15N_5_W6

IO_L15P_5_V6

IO_L16N_5_AA6

IO_L16P_5_Y6

IO_L19N_5_Y7

IO_L19P_5_VREF_5_W7

IO_L22N_5_AB7

IO_L22P_5_AA7

IO_L24N_5_W8

IO_L24P_5_V8

IO_L25N_5_AB8

IO_L25P_5_AA8

IO_L27N_5_VREF_5_W9

IO_L27P_5_V9

IO_L28N_5_D6_AB9

IO_L28P_5_D7_AA9

IO_L29N_5_Y10

IO_L29P_5_VREF_5_W10

IO_L30N_5_AB10

IO_L30P_5_AA10

IO_L31N_5_D4_W11

IO_L31P_5_D5_V11

IO_L32N_5_GCLK3_AA11

IO_L32P_5_GCLK2_Y11

IO_L10N_5_VRP_5_AB5

IO_L10P_5_VRN_5_AA5

FPGAFPGA

1299-27-2005_1144

T12

T13

T14

U15

Y15

U16

U17

W13

W14

V18

Y16

AB13

AA19

AB19

W18

Y18

AA18

AB18

V17

W17

Y17

AA17

V16

W16

AA16

AB16

V15

W15

AA15

AB15

U14

V14

AA14

AB14

U13

V13

Y13

AA13

U12

V12

W12

Y12

AA20

AB20

AA12

AB12

T9

T10

T11

U8

Y8

U7

U9

U10

U11

V7

V10

U6

AB11

Y4

AA3

AB4

AA4

Y5

W5

W6

V6

AA6

Y6

Y7

W7

AB7

AA7

W8

V8

AB8

AA8

W9

V9

AB9

AA9

Y10

W10

AB10

AA10

W11

V11

AA11

Y11

AB5

AA5

U1

FG456XC3S1000

7

2

4

8

10

6

3

9

11

13

15

17

19

21

23

25

12

14

16

24

26

22

20

18

1

5

P16

IDC13X213X2

5

1

18

20

22

26

24

16

14

12

25

23

21

19

17

15

13

11

9

3

6

10

8

4

2

7

P17

IDC13X213X2

R46

060310K

R43

0603DNP

FPGA BANKS 4 + 5

VCCO_5

CONFIG_INIT_B_TFS1

CLK_OUT_EXP1

B4_L32N_GCKL1_AA12

R9

06030

B5_L10N_VRP_AB5_J3_9

B5_L10N_VRP_AB5_J3_9

B5_L10P_VRN_AA5_J3_10

VCCO_5

B5_L32P_GCLK2_Y1

B5_L32N_GCLK3_AA11_J3_30

CONFIG_DIN_DT1PRI

UDEF16

UDEF38

UDEF14

RX0

TX0

RX1

TX1

UDEF20

UDEF21

UDEF23

UDEF17

UDEF25

UDEF24

UDEF22

RESET

UDEF30

UDEF29

UDEF27

UDEF26

UDEF35

UDEF34

UDEF33

UDEF32

UDEF31

UDEF15

UDEF28

UDEF41

UDEF40

UDEF39

UDEF37

UDEF36

BR

UDEF43

BG

BGH

UDEF19

B5_L31P_D5_V11_J3_40

B5_L31N_D4_W11_J3_39

B5_L30P_AA10_J3_38

B5_L30N_AB10_J3_37

B5_L29P_W10_J3_36

B5_L29N_Y10_J3_35

B5_L28P_D7_AA9_J3_34

B5_L28N_D6_AB9_J3_33

B5_L27P_V9_J3_32

B5_L27N_W9_J3_31

B5_L25P_AA8_J3_22

B5_L25N_AB8_J3_21

B5_L24P_V8_J3_20

B5_L24N_W8_J3_19

B5_L22P_AA7_J3_18

B5_L22N_AB7_J3_17

B5_L19P_W7_J3_16

B5_L19N_Y7_J3_15

B5_L16P_Y6_J3_14

B5_L16N_AA6_J3_13

B5_L15P_V6_J3_12

B5_L15N_W6_J3_11

B5_L09P_W5_J3_8

B5_L09N_Y5_J3_7

B5_L06P_AA4_J3_6

B5_L06N_AB4_J3_5

B5_L01P_CS_B_AA3_J3_2

B5_L01N_RDWR_B_Y4_J3_1

B5_AB11_J3_90

B5_U6_J3_23

B5_V10_J3_85

B5_V7_J3_29

B5_U11_J3_83

B5_U10_J3_81

B5_U9_J3_41

B5_U7_J3_28

UDEF18

3

2

1

3X1IDC3X1

P11

B5_L29N_Y10_J3_35

B5_L30N_AB10_J3_37

B5_L31N_D4_W11_J3_39

B5_U11_J3_83

B5_V10_J3_85B5_AB11_J3_90

B5_U10_J3_81

B5_L31P_D5_V11_J3_40

B5_L30P_AA10_J3_38

B5_L29P_W10_J3_36

B5_L28P_D7_AA9_J3_34

B5_L27P_V9_J3_32

B5_L28N_D6_AB9_J3_33

B5_L27N_W9_J3_31

B5_L25N_AB8_J3_21B5_L25P_AA8_J3_22

B5_L24N_W8_J3_19B5_L24P_V8_J3_20

B5_U9_J3_41B5_U6_J3_23

VCCO_5

B5_L10P_VRN_AA5_J3_10

C70

0603001UF 001UF

0603

C69 C68

0603001UF001UF

0603

C67001UF0603

C66 C65

0603001UF 001UF

0603

C64C63

0603001UF

B5_L09N_Y5_J3_7

B5_U7_J3_28 B5_V7_J3_29

B5_L10P_VRN_AA5_J3_10 B5_L10N_VRP_AB5_J3_9

B5_L15P_V6_J3_12 B5_L15N_W6_J3_11

B5_L16P_Y6_J3_14 B5_L16N_AA6_J3_13

B5_L19P_W7_J3_16 B5_L19N_Y7_J3_15

B5_L22P_AA7_J3_18 B5_L22N_AB7_J3_17

B5_L32N_GCLK3_AA11_J3_30 B5_L32P_GCLK2_Y1

B5_L01P_CS_B_AA3_J3_2 B5_L01N_RDWR_B_Y4_J3_1

B5_L06P_AA4_J3_6 B5_L06N_AB4_J3_5

B5_L09P_W5_J3_8

VCCO_5

DNP0603

R45

25V

33V

33V

4

3

2

1

A B C D

20 Cotton Road

Nashua NH 03063

A B C D

4

3

2

1

PH 1-800-ANALOGD

C

Title

Size Board No

Date Sheet of

DEVICESANALOG

DNP = Do Not Populate

Rev

BLACKFIN FPGA EZ-EXTENDER

A0199-2005 10

SN74LVC1G125

12109-27-2005_1144

2 4

1

SOT23-5SN74LVC1G125

U8

USER IO

C80

0603001UF

SW4SWT013SPST-MOMENTARY

SPST-MOMENTARYSWT013SW3

060310R42

C5

06031UF

R413300603

LED001AMBER-SMTLED8

0603330R40

LED7AMBER-SMTLED001

R393300603

R1033006030603

330R34R35

33006030603

330R36

0603330R37 R38

3300603

LED001AMBER-SMTLED2

AMBER-SMTLED001

LED3AMBER-SMTLED001

LED4AMBER-SMTLED001

LED5

LED001AMBER-SMTLED6

LED9GREEN-SMTLED001

402100R23

1 2

3 4

5 6

7 8

JP5

IDC4X24X2

AMBER-SMTLED001

LED1

B6_L01N_Y3

B6_L01P_Y2

B5_U10_J3_81

B5_AB11_J3_90

PB2

B5_V10_J3_85

B5_U11_J3_83

B5_L31N_D4_W11_J3_39

B5_L30N_AB10_J3_37

B5_L29N_Y10_J3_35

B5_L28N_D6_AB9_J3_33

B5_L27N_W9_J3_31

PB1

B5_L25N_AB8_J3_21

R47

060310K

CHOKE_COIL

4

3

2

1

A B C D

20 Cotton Road

Nashua NH 03063

A B C D

4

3

2

1

PH 1-800-ANALOGD

C

Title

Size Board No

Date Sheet of

DEVICESANALOG

DNP = Do Not Populate

Rev

BLACKFIN FPGA EZ-EXTENDER

A0199-2005 10

25V

33V

VIN

EN

SW

GND

FB

VIN

EN

SW

GND

FB

VIN

EN

SW

GND

FB

4

3

5

2

1

VR3

SOT23-5LM3475MF

1

2

5

3

4

VR2

SOT23-5LM3475MF

4

3

5

2

1

VR1

SOT23-5LM3475MF

12119-27-2005_1124

1

32

Q2

SI2

343D

SS

OT

23D

1

32

Q3

SI2

343D

SS

OT

23D

2 3

1S

I234

3DS

Q1

SO

T23

D

316KR17

0603

215KR18

0603

0603

R11105K

DNPC73

0603

0603

C72DNP

805

C741000PF

0R58

0603

1000PFC10

805

0603

R1910K

C100UFCT2

CT3100UFC

IND005

L110UH

10UHL3

IND005

10UHL2

IND005

1

2 D3

DO214ABSCHOT_RECT

3A

0603

R20200K

805

C639NF

390PFC7

0603

2

1 3A

SCHOT_RECTDO214AB

D2

499KR13

0603

1

2 D1

DO214ABSCHOT_RECT

3A

33V_EI

3

1

2

3X1IDC3X1

P13

UNREG_IN

12V

CT1100UFC

80510UFC71

R1200603

5V_EI

8051000PFC2

FER2

0603

060301UFC3

POWER

FUS00125AF1

4

1

3

2

FER1

DO-214AA

S2A_RECT

2AD5

8051000PFC1 C4

10UFC

3

1

2

3X1IDC3X1

P12

UNREG_IN

1

2

3

CON00525MM_JACK

POWER

J4

2

1P42

IDC2X12X1DNP

1

2

DNP2X1IDC2X1

P43

06030R15

C810UF805

80510UFC9

R1600603

UNREG_IN

0603

R1410K

0603

R590

4

3

2

1

A B C D

20 Cotton Road

Nashua NH 03063

A B C D

4

3

2

1

PH 1-800-ANALOGD

C

Title

Size Board No

Date Sheet of

DEVICESANALOG

DNP = Do Not Populate

Rev

BLACKFIN FPGA EZ-EXTENDER

A0199-2005 1012129-14-2005_1204

5

2

4

8

10

6

1

3

9

11

13

15

17

19

12

14

16

20

18

7

P20

SOIC20

PROTO AREA

1

3

2

SOT23D

P39

2

3

1

SOT23D

P38

2

4

5 6

3

1

SOT23-6

P411

3

65

4

2

SOT23-6

P40

PRT_NUM=DNE

11

13

15 16

14

12

2

4

6

8

109

7

5

3

1

SOIC16

P191

3

5

7

9 10

8

6

4

2

12

14

1615

13

11

SOIC16

P18

21P37

805

1 2

805

P36

21P35

805

1 2

805

P34

1 2

805

P33

21P32

805

1 2

805

P31

21P30

805

1 2

805

P29

21P28

805

1 2

805

P27

21P26

805

21P25

805

1 2

805

P24

21P23

805

1 2

805

P22

TP86

TP85

TP84

TP83

TP82

TP81

TP80

TP79 TP77

TP76

TP75

TP74

TP73

TP72

TP71

TP70

TP68

TP67

TP66

TP65

TP64

TP62

TP61

TP60

TP59

TP58

TP57

TP56

TP55

TP54

TP53

TP51

TP50

TP49

TP48

TP47

TP46

TP45

TP44

TP43

TP41

TP40

TP39

TP38

TP37

TP36

TP35

TP34

TP33

TP32

TP30

TP29

TP28

TP27

TP26

TP25

TP24

TP23

TP22

TP21

TP19

TP18

TP17

TP16

TP15

TP14

TP13

TP12

TP11

TP9

TP8

TP7

TP6

TP5

TP4

TP125

TP124

TP123

TP122

TP121

TP120

TP119

TP118

TP117

TP116

TP114

TP113

TP112

TP111

TP110

TP109

TP108

TP107TP106

TP105TP103

TP102TP101 TP100TP99

TP98 TP97

TP96 TP95

TP94TP93

TP92TP91

TP90 TP89

TP88 TP87

TP78TP69

TP63 TP52

TP42 TP31

TP20 TP10

TP115TP104

7

18

20

16

14

12

19

17

15

13

11

9

3

1

6

10

8

4

2

5

SOIC20

P21

I INDEX

Numerics connectors

25V header (P42) 2-17

AADSP-BF5333761 EZ-KIT Lite interface 2-1ADSP-BF5333761 processors boot mode

settings 2-14architecture of this EZ-Extender 2-2asynchronous static random access memory

(SRAM) xauxiliary oscillator x

Bbill of materials A-1block diagram of this EZ-Extender 2-2boot jumper See JP4

Cconfiguration jumpers See JP2 JP3

map of locations 2-18J1-3 (expansion) 2-19P1-3 (expansion) 2-19P14 (IDC) 2-19P15 (JTAG header) 2-4P16-17 (IDC) 2-19P4 (high-speed) 2-20P5 (IDC) 2-20P6 (JTAG) 2-7P7 (IDC) 2-20P8 (IDC) 2-19

customer support xiii

Ddone LED (LED10) 2-17

Eexpansion interface

connectors (P1-3 J1-3) 2-19of ADSP-BF5333761 EZ-KIT Lites ix

1-3external power supply 1-3 2-8

FField-Programmable Gate Array See FPGA

Blackfin FPGA EZ-Extender Manual I-1

INDEX

FPGAdocumentation 1-2input jumpers (JP5) 2-14softwarefirmware 1-2Xilinx Spartan package x 1-3

FPGA pinsAB10 (LED3) 2-17AB11 (JP58) 2-15AB8 (LED7) 2-17AB9 (LED5) 2-17C11 (PB1SW3) 2-15H5 (PB2SW3) 2-16M2-0 (JP4) 2-14U10 (JP56) 2-15U11 (LED1) 2-17V10 (LED8) 2-17W11 (LED2) 2-17W9 (LED6) 2-17Y10 (LED4) 2-17Y3-2 (JP52-54) 2-15

FPGA programmingblock diagram 2-3via ADSP-BF533376 processors 2-6via JTAG header 2-4via serial ROM 2-5

GGCLK1 (global clock 1) pin 1-4GCLK6 (global clock 6) pin 1-4general-purpose input push buttons 2-15 2-16

Hhigh-speed connector (P4) 2-20

IIDC connectors x 2-19 2-20installation of this EZ-Extender 1-1

JJTAG

cable 1-4 2-7header (P6) 1-5 2-4 2-7 2-14

jumpersmap of locations 2-11JP1 (boot jumper) 2-5 2-12JP2 (confug done) 2-12JP3 (config program) 2-13JP41-46 (boot mode select) 2-5 2-6 2-14JP52-56 (FPGA input) 2-14

LLEDs

map of locations 2-15LED10 (FPGA done pin) 2-4 2-5 2-17LED1-8 (status) 2-17LED9 (power) 2-17

MM2-0 (JP4) pins 2-5master serial boot mode 2-6MCS-86 Hexadecimal Object (mcs) file

format 2-6

Nnotation conventions xvi

Ooscillator x 1-4

PP12 (power in) header 2-9P13 (33V header) 2-9P42 (25V header) 2-10P43 (12V header) 2-10PB1 push button (SW3) 2-15

I-2 Blackfin FPGA EZ-Extender Manual

INDEX

PB2 push button (SW4) 2-16PF14 flag pin (ADSP-BF537 EZ-KIT Lite)

2-12PF3 flag pin (ADSP-BF53361 EZ-KIT Lite)

2-12power

12V header (P43) 2-1025V header (P42) 2-1033V header (P13) 2-9in header (P12) 2-9LED (LED9) 2-17limitations 2-8supplies 1-3 2-8

printed circuit board (PCB) 1-2product overview ixprogram push button (SW1) 2-4 2-15push buttons

See also SWx map of locations 2-15

Sserial ROM 1-5

boot jumper (JP1) 2-12 2-14programming via JTAG Header 2-7

setup of this EZ-Extender 1-1slave serial mode 2-6

SRAM memory banks 1-4status reporting 1-4 2-17SW1 (program) push button 2-4 2-15SW3 (PB1) push button 2-15SW4 (PB2) push button 2-16switching regulators 2-8

TTCK signal 2-7TDI signal 2-7TDO signal 2-7TMS signal 2-7

VVisualDSP++

flash programming utility 1-4 2-6FPGA documentation 2-6

VR1-3 regulators 2-8

XXilinx

JTAG cablesoftware 1-4 2-4 2-7JTAG header 2-12serial ROM 1-5

Blackfin FPGA EZ-Extender Manual I-3

INDEX

I-4 Blackfin FPGA EZ-Extender Manual

• Blackfin FPGA EZ-Extender Manual
• Contents
• Preface
• • Product Overview
  • Purpose of This Manual
  • Intended Audience
  • Manual Contents
  • Whatrsquos New in This Manual
  • Technical or Customer Support
  • Supported Products
  • Product Information
  • • Related Documents
    • • Table 1 Related Processor Publications
      • Table 2 Related VisualDSP++ Publications
      • • Notation Conventions
        • • 1 FPGA EZ-Extender Interfaces
          • • FPGA EZ-Extender Setup
            • • Figure 1-1 FPGA EZ-Extender Setup
              • • FPGA Software and Firmware
                • FPGA EZ-Extender Overview
                • • 2 FPGA EZ-Extender Hardware Reference
                  • • System Architecture
                    • • Figure 2-1 Block Diagram
                      • • Programming the FPGA
                        • • Figure 2-2 FPGA Programming Block Diagram
                          • FPGA Programming via JTAG
                          • • Table 2-1 P15 Connections for PFGA Programming via JTAG
                            • Table 2-2 JP1 Settings for FPGA Programming via JTAG
                            • Table 2-3 JP4 Settings for FPGA Programming via JTAG
                            • • FPGA Programming via Serial ROM
                              • • Table 2-4 JP1 Settings for FPGA Programming via Serial ROM
                                • Table 2-5 JP4 Settings for FPGA Programming in Master Serial Mode
                                • • FPGA Programming via Blackfin Application
                                  • • Table 2-6 JP1 Settings for FPGA Programming via Blackfin Processor
                                    • Table 2-7 JP4 Settings for FPGA Programming via Blackfin Processor
                                    • • Programming the Serial ROM
                                      • • Serial ROM via JTAG Header
                                        • • Table 2-8 P6 Connections for Serial ROM
                                          • • Power
                                            • • Table 2-9 Power Limitations
                                              • Power In Header (P12)
                                              • 33V Header (P13)
                                              • 25V Header (P42)
                                              • 12V Header (P43)
                                              • • Jumpers
                                                • • Figure 2-3 Jumper Locations
                                                  • Serial ROM Boot Jumper (JP1)
                                                  • • Table 2-10 JP1 Settings
                                                    • • Config Done Jumper (JP2)
                                                      • • Table 2-11 JP2 Settings
                                                        • • Config Program Jumper (JP3)
                                                          • • Table 2-12 JP3 Settings
                                                            • • Boot Jumper (JP4)
                                                              • • Table 2-13 JP4 Settings
                                                                • • FPGA Input Jumpers (JP5)
                                                                  • • Table 2-14 JP5 Settings
                                                                    • • Push Buttons and LEDs
                                                                      • • Figure 2-4 Push Button and LED Locations
                                                                        • Program Push Button (SW1)
                                                                        • PB1 Push Button (SW3)
                                                                        • PB2 Push Button (SW4)
                                                                        • Status LEDs (LED1-8)
                                                                        • • Table 2-15 Status LED (LED1-8) Settings
                                                                          • • Power LED (LED9)
                                                                            • Done LED (LED10)
                                                                            • • Connectors
                                                                              • • Figure 2-5 Connector Locations
                                                                                • Expansion Interface (P1-3 and J1-3)
                                                                                • IDC Connectors (P8 P14 P16 and P17)
                                                                                • IDC Connectors (P5 and P7)
                                                                                • High-Speed Connector (P4)
                                                                                • • A Bill Of Materials
                                                                                  • B Schematics
                                                                                  • • Title
                                                                                    • FPGA Config
                                                                                    • SRAM FPGA Banks 7 and 8
                                                                                    • Expansion Interface Connector 1
                                                                                    • FPGA Banks 0 and 1
                                                                                    • Expansion Interface Connectors 2
                                                                                    • FPGA Banks 2 and 3
                                                                                    • Expansion Interface Connector 1
                                                                                    • FPGA Banks 4 and 5
                                                                                    • User IO
                                                                                    • Power
                                                                                    • Proto Area
                                                                                    • • I Index
                                                                                      • • Numerics
                                                                                        • A
                                                                                        • B
                                                                                        • C
                                                                                        • D
                                                                                        • E
                                                                                        • F
                                                                                        • G
                                                                                        • H
                                                                                        • I
                                                                                        • J
                                                                                        • L
                                                                                        • M
                                                                                        • N
                                                                                        • O
                                                                                        • P
                                                                                        • S
                                                                                        • T
                                                                                        • V
                                                                                        • X

25V

33V

33V

4

3

2

1

A B C D

20 Cotton Road

Nashua NH 03063

A B C D

4

3

2

1

PH 1-800-ANALOGD

C

Title

Size Board No

Date Sheet of

DEVICESANALOG

DNP = Do Not Populate

Rev

BLACKFIN FPGA EZ-EXTENDER

A0199-2005 10

SN74LVC1G125

12109-27-2005_1144

2 4

1

SOT23-5SN74LVC1G125

U8

USER IO

C80

0603001UF

SW4SWT013SPST-MOMENTARY

SPST-MOMENTARYSWT013SW3

060310R42

C5

06031UF

R413300603

LED001AMBER-SMTLED8

0603330R40

LED7AMBER-SMTLED001

R393300603

R1033006030603

330R34R35

33006030603

330R36

0603330R37 R38

3300603

LED001AMBER-SMTLED2

AMBER-SMTLED001

LED3AMBER-SMTLED001

LED4AMBER-SMTLED001

LED5

LED001AMBER-SMTLED6

LED9GREEN-SMTLED001

402100R23

1 2

3 4

5 6

7 8

JP5

IDC4X24X2

AMBER-SMTLED001

LED1

B6_L01N_Y3

B6_L01P_Y2

B5_U10_J3_81

B5_AB11_J3_90

PB2

B5_V10_J3_85

B5_U11_J3_83

B5_L31N_D4_W11_J3_39

B5_L30N_AB10_J3_37

B5_L29N_Y10_J3_35

B5_L28N_D6_AB9_J3_33

B5_L27N_W9_J3_31

PB1

B5_L25N_AB8_J3_21

R47

060310K

CHOKE_COIL

4

3

2

1

A B C D

20 Cotton Road

Nashua NH 03063

A B C D

4

3

2

1

PH 1-800-ANALOGD

C

Title

Size Board No

Date Sheet of

DEVICESANALOG

DNP = Do Not Populate

Rev

BLACKFIN FPGA EZ-EXTENDER

A0199-2005 10

25V

33V

VIN

EN

SW

GND

FB

VIN

EN

SW

GND

FB

VIN

EN

SW

GND

FB

4

3

5

2

1

VR3

SOT23-5LM3475MF

1

2

5

3

4

VR2

SOT23-5LM3475MF

4

3

5

2

1

VR1

SOT23-5LM3475MF

12119-27-2005_1124

1

32

Q2

SI2

343D

SS

OT

23D

1

32

Q3

SI2

343D

SS

OT

23D

2 3

1S

I234

3DS

Q1

SO

T23

D

316KR17

0603

215KR18

0603

0603

R11105K

DNPC73

0603

0603

C72DNP

805

C741000PF

0R58

0603

1000PFC10

805

0603

R1910K

C100UFCT2

CT3100UFC

IND005

L110UH

10UHL3

IND005

10UHL2

IND005

1

2 D3

DO214ABSCHOT_RECT

3A

0603

R20200K

805

C639NF

390PFC7

0603

2

1 3A

SCHOT_RECTDO214AB

D2

499KR13

0603

1

2 D1

DO214ABSCHOT_RECT

3A

33V_EI

3

1

2

3X1IDC3X1

P13

UNREG_IN

12V

CT1100UFC

80510UFC71

R1200603

5V_EI

8051000PFC2

FER2

0603

060301UFC3

POWER

FUS00125AF1

4

1

3

2

FER1

DO-214AA

S2A_RECT

2AD5

8051000PFC1 C4

10UFC

3

1

2

3X1IDC3X1

P12

UNREG_IN

1

2

3

CON00525MM_JACK

POWER

J4

2

1P42

IDC2X12X1DNP

1

2

DNP2X1IDC2X1

P43

06030R15

C810UF805

80510UFC9

R1600603

UNREG_IN

0603

R1410K

0603

R590

4

3

2

1

A B C D

20 Cotton Road

Nashua NH 03063

A B C D

4

3

2

1

PH 1-800-ANALOGD

C

Title

Size Board No

Date Sheet of

DEVICESANALOG

DNP = Do Not Populate

Rev

BLACKFIN FPGA EZ-EXTENDER

A0199-2005 1012129-14-2005_1204

5

2

4

8

10

6

1

3

9

11

13

15

17

19

12

14

16

20

18

7

P20

SOIC20

PROTO AREA

1

3

2

SOT23D

P39

2

3

1

SOT23D

P38

2

4

5 6

3

1

SOT23-6

P411

3

65

4

2

SOT23-6

P40

PRT_NUM=DNE

11

13

15 16

14

12

2

4

6

8

109

7

5

3

1

SOIC16

P191

3

5

7

9 10

8

6

4

2

12

14

1615

13

11

SOIC16

P18

21P37

805

1 2

805

P36

21P35

805

1 2

805

P34

1 2

805

P33

21P32

805

1 2

805

P31

21P30

805

1 2

805

P29

21P28

805

1 2

805

P27

21P26

805

21P25

805

1 2

805

P24

21P23

805

1 2

805

P22

TP86

TP85

TP84

TP83

TP82

TP81

TP80

TP79 TP77

TP76

TP75

TP74

TP73

TP72

TP71

TP70

TP68

TP67

TP66

TP65

TP64

TP62

TP61

TP60

TP59

TP58

TP57

TP56

TP55

TP54

TP53

TP51

TP50

TP49

TP48

TP47

TP46

TP45

TP44

TP43

TP41

TP40

TP39

TP38

TP37

TP36

TP35

TP34

TP33

TP32

TP30

TP29

TP28

TP27

TP26

TP25

TP24

TP23

TP22

TP21

TP19

TP18

TP17

TP16

TP15

TP14

TP13

TP12

TP11

TP9

TP8

TP7

TP6

TP5

TP4

TP125

TP124

TP123

TP122

TP121

TP120

TP119

TP118

TP117

TP116

TP114

TP113

TP112

TP111

TP110

TP109

TP108

TP107TP106

TP105TP103

TP102TP101 TP100TP99

TP98 TP97

TP96 TP95

TP94TP93

TP92TP91

TP90 TP89

TP88 TP87

TP78TP69

TP63 TP52

TP42 TP31

TP20 TP10

TP115TP104

7

18

20

16

14

12

19

17

15

13

11

9

3

1

6

10

8

4

2

5

SOIC20

P21

I INDEX

Numerics connectors

25V header (P42) 2-17

AADSP-BF5333761 EZ-KIT Lite interface 2-1ADSP-BF5333761 processors boot mode

settings 2-14architecture of this EZ-Extender 2-2asynchronous static random access memory

(SRAM) xauxiliary oscillator x

Bbill of materials A-1block diagram of this EZ-Extender 2-2boot jumper See JP4

Cconfiguration jumpers See JP2 JP3

map of locations 2-18J1-3 (expansion) 2-19P1-3 (expansion) 2-19P14 (IDC) 2-19P15 (JTAG header) 2-4P16-17 (IDC) 2-19P4 (high-speed) 2-20P5 (IDC) 2-20P6 (JTAG) 2-7P7 (IDC) 2-20P8 (IDC) 2-19

customer support xiii

Ddone LED (LED10) 2-17

Eexpansion interface

connectors (P1-3 J1-3) 2-19of ADSP-BF5333761 EZ-KIT Lites ix

1-3external power supply 1-3 2-8

FField-Programmable Gate Array See FPGA

Blackfin FPGA EZ-Extender Manual I-1

INDEX

FPGAdocumentation 1-2input jumpers (JP5) 2-14softwarefirmware 1-2Xilinx Spartan package x 1-3

FPGA pinsAB10 (LED3) 2-17AB11 (JP58) 2-15AB8 (LED7) 2-17AB9 (LED5) 2-17C11 (PB1SW3) 2-15H5 (PB2SW3) 2-16M2-0 (JP4) 2-14U10 (JP56) 2-15U11 (LED1) 2-17V10 (LED8) 2-17W11 (LED2) 2-17W9 (LED6) 2-17Y10 (LED4) 2-17Y3-2 (JP52-54) 2-15

FPGA programmingblock diagram 2-3via ADSP-BF533376 processors 2-6via JTAG header 2-4via serial ROM 2-5

GGCLK1 (global clock 1) pin 1-4GCLK6 (global clock 6) pin 1-4general-purpose input push buttons 2-15 2-16

Hhigh-speed connector (P4) 2-20

IIDC connectors x 2-19 2-20installation of this EZ-Extender 1-1

JJTAG

cable 1-4 2-7header (P6) 1-5 2-4 2-7 2-14

jumpersmap of locations 2-11JP1 (boot jumper) 2-5 2-12JP2 (confug done) 2-12JP3 (config program) 2-13JP41-46 (boot mode select) 2-5 2-6 2-14JP52-56 (FPGA input) 2-14

LLEDs

map of locations 2-15LED10 (FPGA done pin) 2-4 2-5 2-17LED1-8 (status) 2-17LED9 (power) 2-17

MM2-0 (JP4) pins 2-5master serial boot mode 2-6MCS-86 Hexadecimal Object (mcs) file

format 2-6

Nnotation conventions xvi

Ooscillator x 1-4

PP12 (power in) header 2-9P13 (33V header) 2-9P42 (25V header) 2-10P43 (12V header) 2-10PB1 push button (SW3) 2-15

I-2 Blackfin FPGA EZ-Extender Manual

INDEX

PB2 push button (SW4) 2-16PF14 flag pin (ADSP-BF537 EZ-KIT Lite)

2-12PF3 flag pin (ADSP-BF53361 EZ-KIT Lite)

2-12power

12V header (P43) 2-1025V header (P42) 2-1033V header (P13) 2-9in header (P12) 2-9LED (LED9) 2-17limitations 2-8supplies 1-3 2-8

printed circuit board (PCB) 1-2product overview ixprogram push button (SW1) 2-4 2-15push buttons

See also SWx map of locations 2-15

Sserial ROM 1-5

boot jumper (JP1) 2-12 2-14programming via JTAG Header 2-7

setup of this EZ-Extender 1-1slave serial mode 2-6

SRAM memory banks 1-4status reporting 1-4 2-17SW1 (program) push button 2-4 2-15SW3 (PB1) push button 2-15SW4 (PB2) push button 2-16switching regulators 2-8

TTCK signal 2-7TDI signal 2-7TDO signal 2-7TMS signal 2-7

VVisualDSP++

flash programming utility 1-4 2-6FPGA documentation 2-6

VR1-3 regulators 2-8

XXilinx

JTAG cablesoftware 1-4 2-4 2-7JTAG header 2-12serial ROM 1-5

Blackfin FPGA EZ-Extender Manual I-3

INDEX

I-4 Blackfin FPGA EZ-Extender Manual

• Blackfin FPGA EZ-Extender Manual
• Contents
• Preface
• • Product Overview
  • Purpose of This Manual
  • Intended Audience
  • Manual Contents
  • Whatrsquos New in This Manual
  • Technical or Customer Support
  • Supported Products
  • Product Information
  • • Related Documents
    • • Table 1 Related Processor Publications
      • Table 2 Related VisualDSP++ Publications
      • • Notation Conventions
        • • 1 FPGA EZ-Extender Interfaces
          • • FPGA EZ-Extender Setup
            • • Figure 1-1 FPGA EZ-Extender Setup
              • • FPGA Software and Firmware
                • FPGA EZ-Extender Overview
                • • 2 FPGA EZ-Extender Hardware Reference
                  • • System Architecture
                    • • Figure 2-1 Block Diagram
                      • • Programming the FPGA
                        • • Figure 2-2 FPGA Programming Block Diagram
                          • FPGA Programming via JTAG
                          • • Table 2-1 P15 Connections for PFGA Programming via JTAG
                            • Table 2-2 JP1 Settings for FPGA Programming via JTAG
                            • Table 2-3 JP4 Settings for FPGA Programming via JTAG
                            • • FPGA Programming via Serial ROM
                              • • Table 2-4 JP1 Settings for FPGA Programming via Serial ROM
                                • Table 2-5 JP4 Settings for FPGA Programming in Master Serial Mode
                                • • FPGA Programming via Blackfin Application
                                  • • Table 2-6 JP1 Settings for FPGA Programming via Blackfin Processor
                                    • Table 2-7 JP4 Settings for FPGA Programming via Blackfin Processor
                                    • • Programming the Serial ROM
                                      • • Serial ROM via JTAG Header
                                        • • Table 2-8 P6 Connections for Serial ROM
                                          • • Power
                                            • • Table 2-9 Power Limitations
                                              • Power In Header (P12)
                                              • 33V Header (P13)
                                              • 25V Header (P42)
                                              • 12V Header (P43)
                                              • • Jumpers
                                                • • Figure 2-3 Jumper Locations
                                                  • Serial ROM Boot Jumper (JP1)
                                                  • • Table 2-10 JP1 Settings
                                                    • • Config Done Jumper (JP2)
                                                      • • Table 2-11 JP2 Settings
                                                        • • Config Program Jumper (JP3)
                                                          • • Table 2-12 JP3 Settings
                                                            • • Boot Jumper (JP4)
                                                              • • Table 2-13 JP4 Settings
                                                                • • FPGA Input Jumpers (JP5)
                                                                  • • Table 2-14 JP5 Settings
                                                                    • • Push Buttons and LEDs
                                                                      • • Figure 2-4 Push Button and LED Locations
                                                                        • Program Push Button (SW1)
                                                                        • PB1 Push Button (SW3)
                                                                        • PB2 Push Button (SW4)
                                                                        • Status LEDs (LED1-8)
                                                                        • • Table 2-15 Status LED (LED1-8) Settings
                                                                          • • Power LED (LED9)
                                                                            • Done LED (LED10)
                                                                            • • Connectors
                                                                              • • Figure 2-5 Connector Locations
                                                                                • Expansion Interface (P1-3 and J1-3)
                                                                                • IDC Connectors (P8 P14 P16 and P17)
                                                                                • IDC Connectors (P5 and P7)
                                                                                • High-Speed Connector (P4)
                                                                                • • A Bill Of Materials
                                                                                  • B Schematics
                                                                                  • • Title
                                                                                    • FPGA Config
                                                                                    • SRAM FPGA Banks 7 and 8
                                                                                    • Expansion Interface Connector 1
                                                                                    • FPGA Banks 0 and 1
                                                                                    • Expansion Interface Connectors 2
                                                                                    • FPGA Banks 2 and 3
                                                                                    • Expansion Interface Connector 1
                                                                                    • FPGA Banks 4 and 5
                                                                                    • User IO
                                                                                    • Power
                                                                                    • Proto Area
                                                                                    • • I Index
                                                                                      • • Numerics
                                                                                        • A
                                                                                        • B
                                                                                        • C
                                                                                        • D
                                                                                        • E
                                                                                        • F
                                                                                        • G
                                                                                        • H
                                                                                        • I
                                                                                        • J
                                                                                        • L
                                                                                        • M
                                                                                        • N
                                                                                        • O
                                                                                        • P
                                                                                        • S
                                                                                        • T
                                                                                        • V
                                                                                        • X

CHOKE_COIL

4

3

2

1

A B C D

20 Cotton Road

Nashua NH 03063

A B C D

4

3

2

1

PH 1-800-ANALOGD

C

Title

Size Board No

Date Sheet of

DEVICESANALOG

DNP = Do Not Populate

Rev

BLACKFIN FPGA EZ-EXTENDER

A0199-2005 10

25V

33V

VIN

EN

SW

GND

FB

VIN

EN

SW

GND

FB

VIN

EN

SW

GND

FB

4

3

5

2

1

VR3

SOT23-5LM3475MF

1

2

5

3

4

VR2

SOT23-5LM3475MF

4

3

5

2

1

VR1

SOT23-5LM3475MF

12119-27-2005_1124

1

32

Q2

SI2

343D

SS

OT

23D

1

32

Q3

SI2

343D

SS

OT

23D

2 3

1S

I234

3DS

Q1

SO

T23

D

316KR17

0603

215KR18

0603

0603

R11105K

DNPC73

0603

0603

C72DNP

805

C741000PF

0R58

0603

1000PFC10

805

0603

R1910K

C100UFCT2

CT3100UFC

IND005

L110UH

10UHL3

IND005

10UHL2

IND005

1

2 D3

DO214ABSCHOT_RECT

3A

0603

R20200K

805

C639NF

390PFC7

0603

2

1 3A

SCHOT_RECTDO214AB

D2

499KR13

0603

1

2 D1

DO214ABSCHOT_RECT

3A

33V_EI

3

1

2

3X1IDC3X1

P13

UNREG_IN

12V

CT1100UFC

80510UFC71

R1200603

5V_EI

8051000PFC2

FER2

0603

060301UFC3

POWER

FUS00125AF1

4

1

3

2

FER1

DO-214AA

S2A_RECT

2AD5

8051000PFC1 C4

10UFC

3

1

2

3X1IDC3X1

P12

UNREG_IN

1

2

3

CON00525MM_JACK

POWER

J4

2

1P42

IDC2X12X1DNP

1

2

DNP2X1IDC2X1

P43

06030R15

C810UF805

80510UFC9

R1600603

UNREG_IN

0603

R1410K

0603

R590

4

3

2

1

A B C D

20 Cotton Road

Nashua NH 03063

A B C D

4

3

2

1

PH 1-800-ANALOGD

C

Title

Size Board No

Date Sheet of

DEVICESANALOG

DNP = Do Not Populate

Rev

BLACKFIN FPGA EZ-EXTENDER

A0199-2005 1012129-14-2005_1204

5

2

4

8

10

6

1

3

9

11

13

15

17

19

12

14

16

20

18

7

P20

SOIC20

PROTO AREA

1

3

2

SOT23D

P39

2

3

1

SOT23D

P38

2

4

5 6

3

1

SOT23-6

P411

3

65

4

2

SOT23-6

P40

PRT_NUM=DNE

11

13

15 16

14

12

2

4

6

8

109

7

5

3

1

SOIC16

P191

3

5

7

9 10

8

6

4

2

12

14

1615

13

11

SOIC16

P18

21P37

805

1 2

805

P36

21P35

805

1 2

805

P34

1 2

805

P33

21P32

805

1 2

805

P31

21P30

805

1 2

805

P29

21P28

805

1 2

805

P27

21P26

805

21P25

805

1 2

805

P24

21P23

805

1 2

805

P22

TP86

TP85

TP84

TP83

TP82

TP81

TP80

TP79 TP77

TP76

TP75

TP74

TP73

TP72

TP71

TP70

TP68

TP67

TP66

TP65

TP64

TP62

TP61

TP60

TP59

TP58

TP57

TP56

TP55

TP54

TP53

TP51

TP50

TP49

TP48

TP47

TP46

TP45

TP44

TP43

TP41

TP40

TP39

TP38

TP37

TP36

TP35

TP34

TP33

TP32

TP30

TP29

TP28

TP27

TP26

TP25

TP24

TP23

TP22

TP21

TP19

TP18

TP17

TP16

TP15

TP14

TP13

TP12

TP11

TP9

TP8

TP7

TP6

TP5

TP4

TP125

TP124

TP123

TP122

TP121

TP120

TP119

TP118

TP117

TP116

TP114

TP113

TP112

TP111

TP110

TP109

TP108

TP107TP106

TP105TP103

TP102TP101 TP100TP99

TP98 TP97

TP96 TP95

TP94TP93

TP92TP91

TP90 TP89

TP88 TP87

TP78TP69

TP63 TP52

TP42 TP31

TP20 TP10

TP115TP104

7

18

20

16

14

12

19

17

15

13

11

9

3

1

6

10

8

4

2

5

SOIC20

P21

I INDEX

Numerics connectors

25V header (P42) 2-17

AADSP-BF5333761 EZ-KIT Lite interface 2-1ADSP-BF5333761 processors boot mode

settings 2-14architecture of this EZ-Extender 2-2asynchronous static random access memory

(SRAM) xauxiliary oscillator x

Bbill of materials A-1block diagram of this EZ-Extender 2-2boot jumper See JP4

Cconfiguration jumpers See JP2 JP3

map of locations 2-18J1-3 (expansion) 2-19P1-3 (expansion) 2-19P14 (IDC) 2-19P15 (JTAG header) 2-4P16-17 (IDC) 2-19P4 (high-speed) 2-20P5 (IDC) 2-20P6 (JTAG) 2-7P7 (IDC) 2-20P8 (IDC) 2-19

customer support xiii

Ddone LED (LED10) 2-17

Eexpansion interface

connectors (P1-3 J1-3) 2-19of ADSP-BF5333761 EZ-KIT Lites ix

1-3external power supply 1-3 2-8

FField-Programmable Gate Array See FPGA

Blackfin FPGA EZ-Extender Manual I-1

INDEX

FPGAdocumentation 1-2input jumpers (JP5) 2-14softwarefirmware 1-2Xilinx Spartan package x 1-3

FPGA pinsAB10 (LED3) 2-17AB11 (JP58) 2-15AB8 (LED7) 2-17AB9 (LED5) 2-17C11 (PB1SW3) 2-15H5 (PB2SW3) 2-16M2-0 (JP4) 2-14U10 (JP56) 2-15U11 (LED1) 2-17V10 (LED8) 2-17W11 (LED2) 2-17W9 (LED6) 2-17Y10 (LED4) 2-17Y3-2 (JP52-54) 2-15

FPGA programmingblock diagram 2-3via ADSP-BF533376 processors 2-6via JTAG header 2-4via serial ROM 2-5

GGCLK1 (global clock 1) pin 1-4GCLK6 (global clock 6) pin 1-4general-purpose input push buttons 2-15 2-16

Hhigh-speed connector (P4) 2-20

IIDC connectors x 2-19 2-20installation of this EZ-Extender 1-1

JJTAG

cable 1-4 2-7header (P6) 1-5 2-4 2-7 2-14

jumpersmap of locations 2-11JP1 (boot jumper) 2-5 2-12JP2 (confug done) 2-12JP3 (config program) 2-13JP41-46 (boot mode select) 2-5 2-6 2-14JP52-56 (FPGA input) 2-14

LLEDs

map of locations 2-15LED10 (FPGA done pin) 2-4 2-5 2-17LED1-8 (status) 2-17LED9 (power) 2-17

MM2-0 (JP4) pins 2-5master serial boot mode 2-6MCS-86 Hexadecimal Object (mcs) file

format 2-6

Nnotation conventions xvi

Ooscillator x 1-4

PP12 (power in) header 2-9P13 (33V header) 2-9P42 (25V header) 2-10P43 (12V header) 2-10PB1 push button (SW3) 2-15

I-2 Blackfin FPGA EZ-Extender Manual

INDEX

PB2 push button (SW4) 2-16PF14 flag pin (ADSP-BF537 EZ-KIT Lite)

2-12PF3 flag pin (ADSP-BF53361 EZ-KIT Lite)

2-12power

12V header (P43) 2-1025V header (P42) 2-1033V header (P13) 2-9in header (P12) 2-9LED (LED9) 2-17limitations 2-8supplies 1-3 2-8

printed circuit board (PCB) 1-2product overview ixprogram push button (SW1) 2-4 2-15push buttons

See also SWx map of locations 2-15

Sserial ROM 1-5

boot jumper (JP1) 2-12 2-14programming via JTAG Header 2-7

setup of this EZ-Extender 1-1slave serial mode 2-6

SRAM memory banks 1-4status reporting 1-4 2-17SW1 (program) push button 2-4 2-15SW3 (PB1) push button 2-15SW4 (PB2) push button 2-16switching regulators 2-8

TTCK signal 2-7TDI signal 2-7TDO signal 2-7TMS signal 2-7

VVisualDSP++

flash programming utility 1-4 2-6FPGA documentation 2-6

VR1-3 regulators 2-8

XXilinx

JTAG cablesoftware 1-4 2-4 2-7JTAG header 2-12serial ROM 1-5

Blackfin FPGA EZ-Extender Manual I-3

INDEX

I-4 Blackfin FPGA EZ-Extender Manual

• Blackfin FPGA EZ-Extender Manual
• Contents
• Preface
• • Product Overview
  • Purpose of This Manual
  • Intended Audience
  • Manual Contents
  • Whatrsquos New in This Manual
  • Technical or Customer Support
  • Supported Products
  • Product Information
  • • Related Documents
    • • Table 1 Related Processor Publications
      • Table 2 Related VisualDSP++ Publications
      • • Notation Conventions
        • • 1 FPGA EZ-Extender Interfaces
          • • FPGA EZ-Extender Setup
            • • Figure 1-1 FPGA EZ-Extender Setup
              • • FPGA Software and Firmware
                • FPGA EZ-Extender Overview
                • • 2 FPGA EZ-Extender Hardware Reference
                  • • System Architecture
                    • • Figure 2-1 Block Diagram
                      • • Programming the FPGA
                        • • Figure 2-2 FPGA Programming Block Diagram
                          • FPGA Programming via JTAG
                          • • Table 2-1 P15 Connections for PFGA Programming via JTAG
                            • Table 2-2 JP1 Settings for FPGA Programming via JTAG
                            • Table 2-3 JP4 Settings for FPGA Programming via JTAG
                            • • FPGA Programming via Serial ROM
                              • • Table 2-4 JP1 Settings for FPGA Programming via Serial ROM
                                • Table 2-5 JP4 Settings for FPGA Programming in Master Serial Mode
                                • • FPGA Programming via Blackfin Application
                                  • • Table 2-6 JP1 Settings for FPGA Programming via Blackfin Processor
                                    • Table 2-7 JP4 Settings for FPGA Programming via Blackfin Processor
                                    • • Programming the Serial ROM
                                      • • Serial ROM via JTAG Header
                                        • • Table 2-8 P6 Connections for Serial ROM
                                          • • Power
                                            • • Table 2-9 Power Limitations
                                              • Power In Header (P12)
                                              • 33V Header (P13)
                                              • 25V Header (P42)
                                              • 12V Header (P43)
                                              • • Jumpers
                                                • • Figure 2-3 Jumper Locations
                                                  • Serial ROM Boot Jumper (JP1)
                                                  • • Table 2-10 JP1 Settings
                                                    • • Config Done Jumper (JP2)
                                                      • • Table 2-11 JP2 Settings
                                                        • • Config Program Jumper (JP3)
                                                          • • Table 2-12 JP3 Settings
                                                            • • Boot Jumper (JP4)
                                                              • • Table 2-13 JP4 Settings
                                                                • • FPGA Input Jumpers (JP5)
                                                                  • • Table 2-14 JP5 Settings
                                                                    • • Push Buttons and LEDs
                                                                      • • Figure 2-4 Push Button and LED Locations
                                                                        • Program Push Button (SW1)
                                                                        • PB1 Push Button (SW3)
                                                                        • PB2 Push Button (SW4)
                                                                        • Status LEDs (LED1-8)
                                                                        • • Table 2-15 Status LED (LED1-8) Settings
                                                                          • • Power LED (LED9)
                                                                            • Done LED (LED10)
                                                                            • • Connectors
                                                                              • • Figure 2-5 Connector Locations
                                                                                • Expansion Interface (P1-3 and J1-3)
                                                                                • IDC Connectors (P8 P14 P16 and P17)
                                                                                • IDC Connectors (P5 and P7)
                                                                                • High-Speed Connector (P4)
                                                                                • • A Bill Of Materials
                                                                                  • B Schematics
                                                                                  • • Title
                                                                                    • FPGA Config
                                                                                    • SRAM FPGA Banks 7 and 8
                                                                                    • Expansion Interface Connector 1
                                                                                    • FPGA Banks 0 and 1
                                                                                    • Expansion Interface Connectors 2
                                                                                    • FPGA Banks 2 and 3
                                                                                    • Expansion Interface Connector 1
                                                                                    • FPGA Banks 4 and 5
                                                                                    • User IO
                                                                                    • Power
                                                                                    • Proto Area
                                                                                    • • I Index
                                                                                      • • Numerics
                                                                                        • A
                                                                                        • B
                                                                                        • C
                                                                                        • D
                                                                                        • E
                                                                                        • F
                                                                                        • G
                                                                                        • H
                                                                                        • I
                                                                                        • J
                                                                                        • L
                                                                                        • M
                                                                                        • N
                                                                                        • O
                                                                                        • P
                                                                                        • S
                                                                                        • T
                                                                                        • V
                                                                                        • X

4

3

2

1

A B C D

20 Cotton Road

Nashua NH 03063

A B C D

4

3

2

1

PH 1-800-ANALOGD

C

Title

Size Board No

Date Sheet of

DEVICESANALOG

DNP = Do Not Populate

Rev

BLACKFIN FPGA EZ-EXTENDER

A0199-2005 1012129-14-2005_1204

5

2

4

8

10

6

1

3

9

11

13

15

17

19

12

14

16

20

18

7

P20

SOIC20

PROTO AREA

1

3

2

SOT23D

P39

2

3

1

SOT23D

P38

2

4

5 6

3

1

SOT23-6

P411

3

65

4

2

SOT23-6

P40

PRT_NUM=DNE

11

13

15 16

14

12

2

4

6

8

109

7

5

3

1

SOIC16

P191

3

5

7

9 10

8

6

4

2

12

14

1615

13

11

SOIC16

P18

21P37

805

1 2

805

P36

21P35

805

1 2

805

P34

1 2

805

P33

21P32

805

1 2

805

P31

21P30

805

1 2

805

P29

21P28

805

1 2

805

P27

21P26

805

21P25

805

1 2

805

P24

21P23

805

1 2

805

P22

TP86

TP85

TP84

TP83

TP82

TP81

TP80

TP79 TP77

TP76

TP75

TP74

TP73

TP72

TP71

TP70

TP68

TP67

TP66

TP65

TP64

TP62

TP61

TP60

TP59

TP58

TP57

TP56

TP55

TP54

TP53

TP51

TP50

TP49

TP48

TP47

TP46

TP45

TP44

TP43

TP41

TP40

TP39

TP38

TP37

TP36

TP35

TP34

TP33

TP32

TP30

TP29

TP28

TP27

TP26

TP25

TP24

TP23

TP22

TP21

TP19

TP18

TP17

TP16

TP15

TP14

TP13

TP12

TP11

TP9

TP8

TP7

TP6

TP5

TP4

TP125

TP124

TP123

TP122

TP121

TP120

TP119

TP118

TP117

TP116

TP114

TP113

TP112

TP111

TP110

TP109

TP108

TP107TP106

TP105TP103

TP102TP101 TP100TP99

TP98 TP97

TP96 TP95

TP94TP93

TP92TP91

TP90 TP89

TP88 TP87

TP78TP69

TP63 TP52

TP42 TP31

TP20 TP10

TP115TP104

7

18

20

16

14

12

19

17

15

13

11

9

3

1

6

10

8

4

2

5

SOIC20

P21

I INDEX

Numerics connectors

25V header (P42) 2-17

AADSP-BF5333761 EZ-KIT Lite interface 2-1ADSP-BF5333761 processors boot mode

settings 2-14architecture of this EZ-Extender 2-2asynchronous static random access memory

(SRAM) xauxiliary oscillator x

Bbill of materials A-1block diagram of this EZ-Extender 2-2boot jumper See JP4

Cconfiguration jumpers See JP2 JP3

map of locations 2-18J1-3 (expansion) 2-19P1-3 (expansion) 2-19P14 (IDC) 2-19P15 (JTAG header) 2-4P16-17 (IDC) 2-19P4 (high-speed) 2-20P5 (IDC) 2-20P6 (JTAG) 2-7P7 (IDC) 2-20P8 (IDC) 2-19

customer support xiii

Ddone LED (LED10) 2-17

Eexpansion interface

connectors (P1-3 J1-3) 2-19of ADSP-BF5333761 EZ-KIT Lites ix

1-3external power supply 1-3 2-8

FField-Programmable Gate Array See FPGA

Blackfin FPGA EZ-Extender Manual I-1

INDEX

FPGAdocumentation 1-2input jumpers (JP5) 2-14softwarefirmware 1-2Xilinx Spartan package x 1-3

FPGA pinsAB10 (LED3) 2-17AB11 (JP58) 2-15AB8 (LED7) 2-17AB9 (LED5) 2-17C11 (PB1SW3) 2-15H5 (PB2SW3) 2-16M2-0 (JP4) 2-14U10 (JP56) 2-15U11 (LED1) 2-17V10 (LED8) 2-17W11 (LED2) 2-17W9 (LED6) 2-17Y10 (LED4) 2-17Y3-2 (JP52-54) 2-15

FPGA programmingblock diagram 2-3via ADSP-BF533376 processors 2-6via JTAG header 2-4via serial ROM 2-5

GGCLK1 (global clock 1) pin 1-4GCLK6 (global clock 6) pin 1-4general-purpose input push buttons 2-15 2-16

Hhigh-speed connector (P4) 2-20

IIDC connectors x 2-19 2-20installation of this EZ-Extender 1-1

JJTAG

cable 1-4 2-7header (P6) 1-5 2-4 2-7 2-14

jumpersmap of locations 2-11JP1 (boot jumper) 2-5 2-12JP2 (confug done) 2-12JP3 (config program) 2-13JP41-46 (boot mode select) 2-5 2-6 2-14JP52-56 (FPGA input) 2-14

LLEDs

map of locations 2-15LED10 (FPGA done pin) 2-4 2-5 2-17LED1-8 (status) 2-17LED9 (power) 2-17

MM2-0 (JP4) pins 2-5master serial boot mode 2-6MCS-86 Hexadecimal Object (mcs) file

format 2-6

Nnotation conventions xvi

Ooscillator x 1-4

PP12 (power in) header 2-9P13 (33V header) 2-9P42 (25V header) 2-10P43 (12V header) 2-10PB1 push button (SW3) 2-15

I-2 Blackfin FPGA EZ-Extender Manual

INDEX

PB2 push button (SW4) 2-16PF14 flag pin (ADSP-BF537 EZ-KIT Lite)

2-12PF3 flag pin (ADSP-BF53361 EZ-KIT Lite)

2-12power

12V header (P43) 2-1025V header (P42) 2-1033V header (P13) 2-9in header (P12) 2-9LED (LED9) 2-17limitations 2-8supplies 1-3 2-8

printed circuit board (PCB) 1-2product overview ixprogram push button (SW1) 2-4 2-15push buttons

See also SWx map of locations 2-15

Sserial ROM 1-5

boot jumper (JP1) 2-12 2-14programming via JTAG Header 2-7

setup of this EZ-Extender 1-1slave serial mode 2-6

SRAM memory banks 1-4status reporting 1-4 2-17SW1 (program) push button 2-4 2-15SW3 (PB1) push button 2-15SW4 (PB2) push button 2-16switching regulators 2-8

TTCK signal 2-7TDI signal 2-7TDO signal 2-7TMS signal 2-7

VVisualDSP++

flash programming utility 1-4 2-6FPGA documentation 2-6

VR1-3 regulators 2-8

XXilinx

JTAG cablesoftware 1-4 2-4 2-7JTAG header 2-12serial ROM 1-5

Blackfin FPGA EZ-Extender Manual I-3

INDEX

I-4 Blackfin FPGA EZ-Extender Manual

• Blackfin FPGA EZ-Extender Manual
• Contents
• Preface
• • Product Overview
  • Purpose of This Manual
  • Intended Audience
  • Manual Contents
  • Whatrsquos New in This Manual
  • Technical or Customer Support
  • Supported Products
  • Product Information
  • • Related Documents
    • • Table 1 Related Processor Publications
      • Table 2 Related VisualDSP++ Publications
      • • Notation Conventions
        • • 1 FPGA EZ-Extender Interfaces
          • • FPGA EZ-Extender Setup
            • • Figure 1-1 FPGA EZ-Extender Setup
              • • FPGA Software and Firmware
                • FPGA EZ-Extender Overview
                • • 2 FPGA EZ-Extender Hardware Reference
                  • • System Architecture
                    • • Figure 2-1 Block Diagram
                      • • Programming the FPGA
                        • • Figure 2-2 FPGA Programming Block Diagram
                          • FPGA Programming via JTAG
                          • • Table 2-1 P15 Connections for PFGA Programming via JTAG
                            • Table 2-2 JP1 Settings for FPGA Programming via JTAG
                            • Table 2-3 JP4 Settings for FPGA Programming via JTAG
                            • • FPGA Programming via Serial ROM
                              • • Table 2-4 JP1 Settings for FPGA Programming via Serial ROM
                                • Table 2-5 JP4 Settings for FPGA Programming in Master Serial Mode
                                • • FPGA Programming via Blackfin Application
                                  • • Table 2-6 JP1 Settings for FPGA Programming via Blackfin Processor
                                    • Table 2-7 JP4 Settings for FPGA Programming via Blackfin Processor
                                    • • Programming the Serial ROM
                                      • • Serial ROM via JTAG Header
                                        • • Table 2-8 P6 Connections for Serial ROM
                                          • • Power
                                            • • Table 2-9 Power Limitations
                                              • Power In Header (P12)
                                              • 33V Header (P13)
                                              • 25V Header (P42)
                                              • 12V Header (P43)
                                              • • Jumpers
                                                • • Figure 2-3 Jumper Locations
                                                  • Serial ROM Boot Jumper (JP1)
                                                  • • Table 2-10 JP1 Settings
                                                    • • Config Done Jumper (JP2)
                                                      • • Table 2-11 JP2 Settings
                                                        • • Config Program Jumper (JP3)
                                                          • • Table 2-12 JP3 Settings
                                                            • • Boot Jumper (JP4)
                                                              • • Table 2-13 JP4 Settings
                                                                • • FPGA Input Jumpers (JP5)
                                                                  • • Table 2-14 JP5 Settings
                                                                    • • Push Buttons and LEDs
                                                                      • • Figure 2-4 Push Button and LED Locations
                                                                        • Program Push Button (SW1)
                                                                        • PB1 Push Button (SW3)
                                                                        • PB2 Push Button (SW4)
                                                                        • Status LEDs (LED1-8)
                                                                        • • Table 2-15 Status LED (LED1-8) Settings
                                                                          • • Power LED (LED9)
                                                                            • Done LED (LED10)
                                                                            • • Connectors
                                                                              • • Figure 2-5 Connector Locations
                                                                                • Expansion Interface (P1-3 and J1-3)
                                                                                • IDC Connectors (P8 P14 P16 and P17)
                                                                                • IDC Connectors (P5 and P7)
                                                                                • High-Speed Connector (P4)
                                                                                • • A Bill Of Materials
                                                                                  • B Schematics
                                                                                  • • Title
                                                                                    • FPGA Config
                                                                                    • SRAM FPGA Banks 7 and 8
                                                                                    • Expansion Interface Connector 1
                                                                                    • FPGA Banks 0 and 1
                                                                                    • Expansion Interface Connectors 2
                                                                                    • FPGA Banks 2 and 3
                                                                                    • Expansion Interface Connector 1
                                                                                    • FPGA Banks 4 and 5
                                                                                    • User IO
                                                                                    • Power
                                                                                    • Proto Area
                                                                                    • • I Index
                                                                                      • • Numerics
                                                                                        • A
                                                                                        • B
                                                                                        • C
                                                                                        • D
                                                                                        • E
                                                                                        • F
                                                                                        • G
                                                                                        • H
                                                                                        • I
                                                                                        • J
                                                                                        • L
                                                                                        • M
                                                                                        • N
                                                                                        • O
                                                                                        • P
                                                                                        • S
                                                                                        • T
                                                                                        • V
                                                                                        • X

I INDEX

Numerics connectors

25V header (P42) 2-17

AADSP-BF5333761 EZ-KIT Lite interface 2-1ADSP-BF5333761 processors boot mode

settings 2-14architecture of this EZ-Extender 2-2asynchronous static random access memory

(SRAM) xauxiliary oscillator x

Bbill of materials A-1block diagram of this EZ-Extender 2-2boot jumper See JP4

Cconfiguration jumpers See JP2 JP3

map of locations 2-18J1-3 (expansion) 2-19P1-3 (expansion) 2-19P14 (IDC) 2-19P15 (JTAG header) 2-4P16-17 (IDC) 2-19P4 (high-speed) 2-20P5 (IDC) 2-20P6 (JTAG) 2-7P7 (IDC) 2-20P8 (IDC) 2-19

customer support xiii

Ddone LED (LED10) 2-17

Eexpansion interface

connectors (P1-3 J1-3) 2-19of ADSP-BF5333761 EZ-KIT Lites ix

1-3external power supply 1-3 2-8

FField-Programmable Gate Array See FPGA

Blackfin FPGA EZ-Extender Manual I-1

INDEX

FPGAdocumentation 1-2input jumpers (JP5) 2-14softwarefirmware 1-2Xilinx Spartan package x 1-3

FPGA pinsAB10 (LED3) 2-17AB11 (JP58) 2-15AB8 (LED7) 2-17AB9 (LED5) 2-17C11 (PB1SW3) 2-15H5 (PB2SW3) 2-16M2-0 (JP4) 2-14U10 (JP56) 2-15U11 (LED1) 2-17V10 (LED8) 2-17W11 (LED2) 2-17W9 (LED6) 2-17Y10 (LED4) 2-17Y3-2 (JP52-54) 2-15

FPGA programmingblock diagram 2-3via ADSP-BF533376 processors 2-6via JTAG header 2-4via serial ROM 2-5

GGCLK1 (global clock 1) pin 1-4GCLK6 (global clock 6) pin 1-4general-purpose input push buttons 2-15 2-16

Hhigh-speed connector (P4) 2-20

IIDC connectors x 2-19 2-20installation of this EZ-Extender 1-1

JJTAG

cable 1-4 2-7header (P6) 1-5 2-4 2-7 2-14

jumpersmap of locations 2-11JP1 (boot jumper) 2-5 2-12JP2 (confug done) 2-12JP3 (config program) 2-13JP41-46 (boot mode select) 2-5 2-6 2-14JP52-56 (FPGA input) 2-14

LLEDs

map of locations 2-15LED10 (FPGA done pin) 2-4 2-5 2-17LED1-8 (status) 2-17LED9 (power) 2-17

MM2-0 (JP4) pins 2-5master serial boot mode 2-6MCS-86 Hexadecimal Object (mcs) file

format 2-6

Nnotation conventions xvi

Ooscillator x 1-4

PP12 (power in) header 2-9P13 (33V header) 2-9P42 (25V header) 2-10P43 (12V header) 2-10PB1 push button (SW3) 2-15

I-2 Blackfin FPGA EZ-Extender Manual

INDEX

PB2 push button (SW4) 2-16PF14 flag pin (ADSP-BF537 EZ-KIT Lite)

2-12PF3 flag pin (ADSP-BF53361 EZ-KIT Lite)

2-12power

12V header (P43) 2-1025V header (P42) 2-1033V header (P13) 2-9in header (P12) 2-9LED (LED9) 2-17limitations 2-8supplies 1-3 2-8

printed circuit board (PCB) 1-2product overview ixprogram push button (SW1) 2-4 2-15push buttons

See also SWx map of locations 2-15

Sserial ROM 1-5

boot jumper (JP1) 2-12 2-14programming via JTAG Header 2-7

setup of this EZ-Extender 1-1slave serial mode 2-6

SRAM memory banks 1-4status reporting 1-4 2-17SW1 (program) push button 2-4 2-15SW3 (PB1) push button 2-15SW4 (PB2) push button 2-16switching regulators 2-8

TTCK signal 2-7TDI signal 2-7TDO signal 2-7TMS signal 2-7

VVisualDSP++

flash programming utility 1-4 2-6FPGA documentation 2-6

VR1-3 regulators 2-8

XXilinx

JTAG cablesoftware 1-4 2-4 2-7JTAG header 2-12serial ROM 1-5

Blackfin FPGA EZ-Extender Manual I-3

INDEX

I-4 Blackfin FPGA EZ-Extender Manual

• Blackfin FPGA EZ-Extender Manual
• Contents
• Preface
• • Product Overview
  • Purpose of This Manual
  • Intended Audience
  • Manual Contents
  • Whatrsquos New in This Manual
  • Technical or Customer Support
  • Supported Products
  • Product Information
  • • Related Documents
    • • Table 1 Related Processor Publications
      • Table 2 Related VisualDSP++ Publications
      • • Notation Conventions
        • • 1 FPGA EZ-Extender Interfaces
          • • FPGA EZ-Extender Setup
            • • Figure 1-1 FPGA EZ-Extender Setup
              • • FPGA Software and Firmware
                • FPGA EZ-Extender Overview
                • • 2 FPGA EZ-Extender Hardware Reference
                  • • System Architecture
                    • • Figure 2-1 Block Diagram
                      • • Programming the FPGA
                        • • Figure 2-2 FPGA Programming Block Diagram
                          • FPGA Programming via JTAG
                          • • Table 2-1 P15 Connections for PFGA Programming via JTAG
                            • Table 2-2 JP1 Settings for FPGA Programming via JTAG
                            • Table 2-3 JP4 Settings for FPGA Programming via JTAG
                            • • FPGA Programming via Serial ROM
                              • • Table 2-4 JP1 Settings for FPGA Programming via Serial ROM
                                • Table 2-5 JP4 Settings for FPGA Programming in Master Serial Mode
                                • • FPGA Programming via Blackfin Application
                                  • • Table 2-6 JP1 Settings for FPGA Programming via Blackfin Processor
                                    • Table 2-7 JP4 Settings for FPGA Programming via Blackfin Processor
                                    • • Programming the Serial ROM
                                      • • Serial ROM via JTAG Header
                                        • • Table 2-8 P6 Connections for Serial ROM
                                          • • Power
                                            • • Table 2-9 Power Limitations
                                              • Power In Header (P12)
                                              • 33V Header (P13)
                                              • 25V Header (P42)
                                              • 12V Header (P43)
                                              • • Jumpers
                                                • • Figure 2-3 Jumper Locations
                                                  • Serial ROM Boot Jumper (JP1)
                                                  • • Table 2-10 JP1 Settings
                                                    • • Config Done Jumper (JP2)
                                                      • • Table 2-11 JP2 Settings
                                                        • • Config Program Jumper (JP3)
                                                          • • Table 2-12 JP3 Settings
                                                            • • Boot Jumper (JP4)
                                                              • • Table 2-13 JP4 Settings
                                                                • • FPGA Input Jumpers (JP5)
                                                                  • • Table 2-14 JP5 Settings
                                                                    • • Push Buttons and LEDs
                                                                      • • Figure 2-4 Push Button and LED Locations
                                                                        • Program Push Button (SW1)
                                                                        • PB1 Push Button (SW3)
                                                                        • PB2 Push Button (SW4)
                                                                        • Status LEDs (LED1-8)
                                                                        • • Table 2-15 Status LED (LED1-8) Settings
                                                                          • • Power LED (LED9)
                                                                            • Done LED (LED10)
                                                                            • • Connectors
                                                                              • • Figure 2-5 Connector Locations
                                                                                • Expansion Interface (P1-3 and J1-3)
                                                                                • IDC Connectors (P8 P14 P16 and P17)
                                                                                • IDC Connectors (P5 and P7)
                                                                                • High-Speed Connector (P4)
                                                                                • • A Bill Of Materials
                                                                                  • B Schematics
                                                                                  • • Title
                                                                                    • FPGA Config
                                                                                    • SRAM FPGA Banks 7 and 8
                                                                                    • Expansion Interface Connector 1
                                                                                    • FPGA Banks 0 and 1
                                                                                    • Expansion Interface Connectors 2
                                                                                    • FPGA Banks 2 and 3
                                                                                    • Expansion Interface Connector 1
                                                                                    • FPGA Banks 4 and 5
                                                                                    • User IO
                                                                                    • Power
                                                                                    • Proto Area
                                                                                    • • I Index
                                                                                      • • Numerics
                                                                                        • A
                                                                                        • B
                                                                                        • C
                                                                                        • D
                                                                                        • E
                                                                                        • F
                                                                                        • G
                                                                                        • H
                                                                                        • I
                                                                                        • J
                                                                                        • L
                                                                                        • M
                                                                                        • N
                                                                                        • O
                                                                                        • P
                                                                                        • S
                                                                                        • T
                                                                                        • V
                                                                                        • X

INDEX

FPGAdocumentation 1-2input jumpers (JP5) 2-14softwarefirmware 1-2Xilinx Spartan package x 1-3

FPGA pinsAB10 (LED3) 2-17AB11 (JP58) 2-15AB8 (LED7) 2-17AB9 (LED5) 2-17C11 (PB1SW3) 2-15H5 (PB2SW3) 2-16M2-0 (JP4) 2-14U10 (JP56) 2-15U11 (LED1) 2-17V10 (LED8) 2-17W11 (LED2) 2-17W9 (LED6) 2-17Y10 (LED4) 2-17Y3-2 (JP52-54) 2-15

FPGA programmingblock diagram 2-3via ADSP-BF533376 processors 2-6via JTAG header 2-4via serial ROM 2-5

GGCLK1 (global clock 1) pin 1-4GCLK6 (global clock 6) pin 1-4general-purpose input push buttons 2-15 2-16

Hhigh-speed connector (P4) 2-20

IIDC connectors x 2-19 2-20installation of this EZ-Extender 1-1

JJTAG

cable 1-4 2-7header (P6) 1-5 2-4 2-7 2-14

jumpersmap of locations 2-11JP1 (boot jumper) 2-5 2-12JP2 (confug done) 2-12JP3 (config program) 2-13JP41-46 (boot mode select) 2-5 2-6 2-14JP52-56 (FPGA input) 2-14

LLEDs

map of locations 2-15LED10 (FPGA done pin) 2-4 2-5 2-17LED1-8 (status) 2-17LED9 (power) 2-17

MM2-0 (JP4) pins 2-5master serial boot mode 2-6MCS-86 Hexadecimal Object (mcs) file

format 2-6

Nnotation conventions xvi

Ooscillator x 1-4

PP12 (power in) header 2-9P13 (33V header) 2-9P42 (25V header) 2-10P43 (12V header) 2-10PB1 push button (SW3) 2-15

I-2 Blackfin FPGA EZ-Extender Manual

INDEX

PB2 push button (SW4) 2-16PF14 flag pin (ADSP-BF537 EZ-KIT Lite)

2-12PF3 flag pin (ADSP-BF53361 EZ-KIT Lite)

2-12power

12V header (P43) 2-1025V header (P42) 2-1033V header (P13) 2-9in header (P12) 2-9LED (LED9) 2-17limitations 2-8supplies 1-3 2-8

printed circuit board (PCB) 1-2product overview ixprogram push button (SW1) 2-4 2-15push buttons

See also SWx map of locations 2-15

Sserial ROM 1-5

boot jumper (JP1) 2-12 2-14programming via JTAG Header 2-7

setup of this EZ-Extender 1-1slave serial mode 2-6

SRAM memory banks 1-4status reporting 1-4 2-17SW1 (program) push button 2-4 2-15SW3 (PB1) push button 2-15SW4 (PB2) push button 2-16switching regulators 2-8

TTCK signal 2-7TDI signal 2-7TDO signal 2-7TMS signal 2-7

VVisualDSP++

flash programming utility 1-4 2-6FPGA documentation 2-6

VR1-3 regulators 2-8

XXilinx

JTAG cablesoftware 1-4 2-4 2-7JTAG header 2-12serial ROM 1-5

Blackfin FPGA EZ-Extender Manual I-3

INDEX

I-4 Blackfin FPGA EZ-Extender Manual

• Blackfin FPGA EZ-Extender Manual
• Contents
• Preface
• • Product Overview
  • Purpose of This Manual
  • Intended Audience
  • Manual Contents
  • Whatrsquos New in This Manual
  • Technical or Customer Support
  • Supported Products
  • Product Information
  • • Related Documents
    • • Table 1 Related Processor Publications
      • Table 2 Related VisualDSP++ Publications
      • • Notation Conventions
        • • 1 FPGA EZ-Extender Interfaces
          • • FPGA EZ-Extender Setup
            • • Figure 1-1 FPGA EZ-Extender Setup
              • • FPGA Software and Firmware
                • FPGA EZ-Extender Overview
                • • 2 FPGA EZ-Extender Hardware Reference
                  • • System Architecture
                    • • Figure 2-1 Block Diagram
                      • • Programming the FPGA
                        • • Figure 2-2 FPGA Programming Block Diagram
                          • FPGA Programming via JTAG
                          • • Table 2-1 P15 Connections for PFGA Programming via JTAG
                            • Table 2-2 JP1 Settings for FPGA Programming via JTAG
                            • Table 2-3 JP4 Settings for FPGA Programming via JTAG
                            • • FPGA Programming via Serial ROM
                              • • Table 2-4 JP1 Settings for FPGA Programming via Serial ROM
                                • Table 2-5 JP4 Settings for FPGA Programming in Master Serial Mode
                                • • FPGA Programming via Blackfin Application
                                  • • Table 2-6 JP1 Settings for FPGA Programming via Blackfin Processor
                                    • Table 2-7 JP4 Settings for FPGA Programming via Blackfin Processor
                                    • • Programming the Serial ROM
                                      • • Serial ROM via JTAG Header
                                        • • Table 2-8 P6 Connections for Serial ROM
                                          • • Power
                                            • • Table 2-9 Power Limitations
                                              • Power In Header (P12)
                                              • 33V Header (P13)
                                              • 25V Header (P42)
                                              • 12V Header (P43)
                                              • • Jumpers
                                                • • Figure 2-3 Jumper Locations
                                                  • Serial ROM Boot Jumper (JP1)
                                                  • • Table 2-10 JP1 Settings
                                                    • • Config Done Jumper (JP2)
                                                      • • Table 2-11 JP2 Settings
                                                        • • Config Program Jumper (JP3)
                                                          • • Table 2-12 JP3 Settings
                                                            • • Boot Jumper (JP4)
                                                              • • Table 2-13 JP4 Settings
                                                                • • FPGA Input Jumpers (JP5)
                                                                  • • Table 2-14 JP5 Settings
                                                                    • • Push Buttons and LEDs
                                                                      • • Figure 2-4 Push Button and LED Locations
                                                                        • Program Push Button (SW1)
                                                                        • PB1 Push Button (SW3)
                                                                        • PB2 Push Button (SW4)
                                                                        • Status LEDs (LED1-8)
                                                                        • • Table 2-15 Status LED (LED1-8) Settings
                                                                          • • Power LED (LED9)
                                                                            • Done LED (LED10)
                                                                            • • Connectors
                                                                              • • Figure 2-5 Connector Locations
                                                                                • Expansion Interface (P1-3 and J1-3)
                                                                                • IDC Connectors (P8 P14 P16 and P17)
                                                                                • IDC Connectors (P5 and P7)
                                                                                • High-Speed Connector (P4)
                                                                                • • A Bill Of Materials
                                                                                  • B Schematics
                                                                                  • • Title
                                                                                    • FPGA Config
                                                                                    • SRAM FPGA Banks 7 and 8
                                                                                    • Expansion Interface Connector 1
                                                                                    • FPGA Banks 0 and 1
                                                                                    • Expansion Interface Connectors 2
                                                                                    • FPGA Banks 2 and 3
                                                                                    • Expansion Interface Connector 1
                                                                                    • FPGA Banks 4 and 5
                                                                                    • User IO
                                                                                    • Power
                                                                                    • Proto Area
                                                                                    • • I Index
                                                                                      • • Numerics
                                                                                        • A
                                                                                        • B
                                                                                        • C
                                                                                        • D
                                                                                        • E
                                                                                        • F
                                                                                        • G
                                                                                        • H
                                                                                        • I
                                                                                        • J
                                                                                        • L
                                                                                        • M
                                                                                        • N
                                                                                        • O
                                                                                        • P
                                                                                        • S
                                                                                        • T
                                                                                        • V
                                                                                        • X

INDEX

PB2 push button (SW4) 2-16PF14 flag pin (ADSP-BF537 EZ-KIT Lite)

2-12PF3 flag pin (ADSP-BF53361 EZ-KIT Lite)

2-12power

12V header (P43) 2-1025V header (P42) 2-1033V header (P13) 2-9in header (P12) 2-9LED (LED9) 2-17limitations 2-8supplies 1-3 2-8

printed circuit board (PCB) 1-2product overview ixprogram push button (SW1) 2-4 2-15push buttons

See also SWx map of locations 2-15

Sserial ROM 1-5

boot jumper (JP1) 2-12 2-14programming via JTAG Header 2-7

setup of this EZ-Extender 1-1slave serial mode 2-6

SRAM memory banks 1-4status reporting 1-4 2-17SW1 (program) push button 2-4 2-15SW3 (PB1) push button 2-15SW4 (PB2) push button 2-16switching regulators 2-8

TTCK signal 2-7TDI signal 2-7TDO signal 2-7TMS signal 2-7

VVisualDSP++

flash programming utility 1-4 2-6FPGA documentation 2-6

VR1-3 regulators 2-8

XXilinx

JTAG cablesoftware 1-4 2-4 2-7JTAG header 2-12serial ROM 1-5

Blackfin FPGA EZ-Extender Manual I-3

INDEX

I-4 Blackfin FPGA EZ-Extender Manual

• Blackfin FPGA EZ-Extender Manual
• Contents
• Preface
• • Product Overview
  • Purpose of This Manual
  • Intended Audience
  • Manual Contents
  • Whatrsquos New in This Manual
  • Technical or Customer Support
  • Supported Products
  • Product Information
  • • Related Documents
    • • Table 1 Related Processor Publications
      • Table 2 Related VisualDSP++ Publications
      • • Notation Conventions
        • • 1 FPGA EZ-Extender Interfaces
          • • FPGA EZ-Extender Setup
            • • Figure 1-1 FPGA EZ-Extender Setup
              • • FPGA Software and Firmware
                • FPGA EZ-Extender Overview
                • • 2 FPGA EZ-Extender Hardware Reference
                  • • System Architecture
                    • • Figure 2-1 Block Diagram
                      • • Programming the FPGA
                        • • Figure 2-2 FPGA Programming Block Diagram
                          • FPGA Programming via JTAG
                          • • Table 2-1 P15 Connections for PFGA Programming via JTAG
                            • Table 2-2 JP1 Settings for FPGA Programming via JTAG
                            • Table 2-3 JP4 Settings for FPGA Programming via JTAG
                            • • FPGA Programming via Serial ROM
                              • • Table 2-4 JP1 Settings for FPGA Programming via Serial ROM
                                • Table 2-5 JP4 Settings for FPGA Programming in Master Serial Mode
                                • • FPGA Programming via Blackfin Application
                                  • • Table 2-6 JP1 Settings for FPGA Programming via Blackfin Processor
                                    • Table 2-7 JP4 Settings for FPGA Programming via Blackfin Processor
                                    • • Programming the Serial ROM
                                      • • Serial ROM via JTAG Header
                                        • • Table 2-8 P6 Connections for Serial ROM
                                          • • Power
                                            • • Table 2-9 Power Limitations
                                              • Power In Header (P12)
                                              • 33V Header (P13)
                                              • 25V Header (P42)
                                              • 12V Header (P43)
                                              • • Jumpers
                                                • • Figure 2-3 Jumper Locations
                                                  • Serial ROM Boot Jumper (JP1)
                                                  • • Table 2-10 JP1 Settings
                                                    • • Config Done Jumper (JP2)
                                                      • • Table 2-11 JP2 Settings
                                                        • • Config Program Jumper (JP3)
                                                          • • Table 2-12 JP3 Settings
                                                            • • Boot Jumper (JP4)
                                                              • • Table 2-13 JP4 Settings
                                                                • • FPGA Input Jumpers (JP5)
                                                                  • • Table 2-14 JP5 Settings
                                                                    • • Push Buttons and LEDs
                                                                      • • Figure 2-4 Push Button and LED Locations
                                                                        • Program Push Button (SW1)
                                                                        • PB1 Push Button (SW3)
                                                                        • PB2 Push Button (SW4)
                                                                        • Status LEDs (LED1-8)
                                                                        • • Table 2-15 Status LED (LED1-8) Settings
                                                                          • • Power LED (LED9)
                                                                            • Done LED (LED10)
                                                                            • • Connectors
                                                                              • • Figure 2-5 Connector Locations
                                                                                • Expansion Interface (P1-3 and J1-3)
                                                                                • IDC Connectors (P8 P14 P16 and P17)
                                                                                • IDC Connectors (P5 and P7)
                                                                                • High-Speed Connector (P4)
                                                                                • • A Bill Of Materials
                                                                                  • B Schematics
                                                                                  • • Title
                                                                                    • FPGA Config
                                                                                    • SRAM FPGA Banks 7 and 8
                                                                                    • Expansion Interface Connector 1
                                                                                    • FPGA Banks 0 and 1
                                                                                    • Expansion Interface Connectors 2
                                                                                    • FPGA Banks 2 and 3
                                                                                    • Expansion Interface Connector 1
                                                                                    • FPGA Banks 4 and 5
                                                                                    • User IO
                                                                                    • Power
                                                                                    • Proto Area
                                                                                    • • I Index
                                                                                      • • Numerics
                                                                                        • A
                                                                                        • B
                                                                                        • C
                                                                                        • D
                                                                                        • E
                                                                                        • F
                                                                                        • G
                                                                                        • H
                                                                                        • I
                                                                                        • J
                                                                                        • L
                                                                                        • M
                                                                                        • N
                                                                                        • O
                                                                                        • P
                                                                                        • S
                                                                                        • T
                                                                                        • V
                                                                                        • X

INDEX

I-4 Blackfin FPGA EZ-Extender Manual

• Blackfin FPGA EZ-Extender Manual
• Contents
• Preface
• • Product Overview
  • Purpose of This Manual
  • Intended Audience
  • Manual Contents
  • Whatrsquos New in This Manual
  • Technical or Customer Support
  • Supported Products
  • Product Information
  • • Related Documents
    • • Table 1 Related Processor Publications
      • Table 2 Related VisualDSP++ Publications
      • • Notation Conventions
        • • 1 FPGA EZ-Extender Interfaces
          • • FPGA EZ-Extender Setup
            • • Figure 1-1 FPGA EZ-Extender Setup
              • • FPGA Software and Firmware
                • FPGA EZ-Extender Overview
                • • 2 FPGA EZ-Extender Hardware Reference
                  • • System Architecture
                    • • Figure 2-1 Block Diagram
                      • • Programming the FPGA
                        • • Figure 2-2 FPGA Programming Block Diagram
                          • FPGA Programming via JTAG
                          • • Table 2-1 P15 Connections for PFGA Programming via JTAG
                            • Table 2-2 JP1 Settings for FPGA Programming via JTAG
                            • Table 2-3 JP4 Settings for FPGA Programming via JTAG
                            • • FPGA Programming via Serial ROM
                              • • Table 2-4 JP1 Settings for FPGA Programming via Serial ROM
                                • Table 2-5 JP4 Settings for FPGA Programming in Master Serial Mode
                                • • FPGA Programming via Blackfin Application
                                  • • Table 2-6 JP1 Settings for FPGA Programming via Blackfin Processor
                                    • Table 2-7 JP4 Settings for FPGA Programming via Blackfin Processor
                                    • • Programming the Serial ROM
                                      • • Serial ROM via JTAG Header
                                        • • Table 2-8 P6 Connections for Serial ROM
                                          • • Power
                                            • • Table 2-9 Power Limitations
                                              • Power In Header (P12)
                                              • 33V Header (P13)
                                              • 25V Header (P42)
                                              • 12V Header (P43)
                                              • • Jumpers
                                                • • Figure 2-3 Jumper Locations
                                                  • Serial ROM Boot Jumper (JP1)
                                                  • • Table 2-10 JP1 Settings
                                                    • • Config Done Jumper (JP2)
                                                      • • Table 2-11 JP2 Settings
                                                        • • Config Program Jumper (JP3)
                                                          • • Table 2-12 JP3 Settings
                                                            • • Boot Jumper (JP4)
                                                              • • Table 2-13 JP4 Settings
                                                                • • FPGA Input Jumpers (JP5)
                                                                  • • Table 2-14 JP5 Settings
                                                                    • • Push Buttons and LEDs
                                                                      • • Figure 2-4 Push Button and LED Locations
                                                                        • Program Push Button (SW1)
                                                                        • PB1 Push Button (SW3)
                                                                        • PB2 Push Button (SW4)
                                                                        • Status LEDs (LED1-8)
                                                                        • • Table 2-15 Status LED (LED1-8) Settings
                                                                          • • Power LED (LED9)
                                                                            • Done LED (LED10)
                                                                            • • Connectors
                                                                              • • Figure 2-5 Connector Locations
                                                                                • Expansion Interface (P1-3 and J1-3)
                                                                                • IDC Connectors (P8 P14 P16 and P17)
                                                                                • IDC Connectors (P5 and P7)
                                                                                • High-Speed Connector (P4)
                                                                                • • A Bill Of Materials
                                                                                  • B Schematics
                                                                                  • • Title
                                                                                    • FPGA Config
                                                                                    • SRAM FPGA Banks 7 and 8
                                                                                    • Expansion Interface Connector 1
                                                                                    • FPGA Banks 0 and 1
                                                                                    • Expansion Interface Connectors 2
                                                                                    • FPGA Banks 2 and 3
                                                                                    • Expansion Interface Connector 1
                                                                                    • FPGA Banks 4 and 5
                                                                                    • User IO
                                                                                    • Power
                                                                                    • Proto Area
                                                                                    • • I Index
                                                                                      • • Numerics
                                                                                        • A
                                                                                        • B
                                                                                        • C
                                                                                        • D
                                                                                        • E
                                                                                        • F
                                                                                        • G
                                                                                        • H
                                                                                        • I
                                                                                        • J
                                                                                        • L
                                                                                        • M
                                                                                        • N
                                                                                        • O
                                                                                        • P
                                                                                        • S
                                                                                        • T
                                                                                        • V
                                                                                        • X