-
0
06-01-2012_12:08
psec_cc
456 3 2 1
REV
TITLE
SCALE SHEET
SIZE DWG NO
1236 5 4
B
A A
B
C
D
C
D
CofDRAWN BY
The University of ChicagoElectronics Design Group
Mircea Bogdan
GMII[24:0]
SGMII[5:0]
Mngmnt[5:0]
LEDs[5:0]
USB_AUX[7:0]
USB_PA[7:0]
DC0_2[7:0]
USB_FD[15:0]
DC0_1[7:0]
DC1_2[7:0]
DC1_1[7:0]
DC2_2[7:0]
DC2_1[7:0]
DC3_2[7:0]
DC3_1[7:0]
System[7:0]
Block_FPGA
Sheet_2_4
dc_conn1
DC2_1[7:0]
DC1_1[7:0]
DC2_2[7:0]
DC1_2[7:0]
ConnectorDC
Power_block
usb
USB_FD[15:0]
USB_AUX[7:0]
USB_PA[7:0]
Interface
dc_conn2
DC2_1[7:0]
DC1_1[7:0]
DC2_2[7:0]
DC1_2[7:0]
ConnectorDC
ethernetblock
GMII[24:0]
LEDs[5:0]
SGMII[5:0]
Mngmnt[5:0]
10/100/100
PHY
systemconn
System[7:0]
System Conn
System[7:0]
DC0_1[7:0]
DC0_2[7:0]
DC1_2[7:0]
DC1_1[7:0]
DC2_1[7:0]
DC2_2[7:0]
DC3_1[7:0]
DC3_2[7:0] GMII[24:0]
SGMII[5:0]
Mngmnt[5:0]
LEDs[5:0]
USB_AUX[7:0]
USB_FD[15:0]
USB_PA[7:0]
2766 Rev. A
1clk + 2ctrl OUT, 1ctrl IN
1ctrl OUT, 3data IN
1ctrl OUT, 3data IN
1clk + 2ctrl OUT, 1ctrl IN
1clk + 2ctrl OUT, 1ctrl IN
1ctrl OUT, 3data IN
1ctrl OUT, 3data IN
1clk + 2ctrl OUT, 1ctrl IN
1clk + 2ctrl IN, 1ctrl OUT
1/7
To/From Digital CardsRight Side
Top Level
To/From Digital CardsLeft Side
-
block_fpga
23-01-2012_10:35
0
Mircea BogdanofDRAWN BY
TITLE
SIZE
D
DWG NO REV
SHEETSCALE
D
C
B
A A
B
C
D
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
The University of ChicagoElectronics Design Group
GMII[24:0]
USB_FD[15:0]
SGMII[5:0]
21 10
1 4
8
3
6
23
24
28
18
15
19
16
13
pn-IDT5T93GL06
U3
29 3231
171495
25
26
12
7
11
30
2 2720
22
Q3_
A2
Q4
A2_
Q4_
SEL
Q5
Q5_
A1
Q1
GL
Q1_G_
Q2PD_
Q2_
A1_
Q3
Q6
Q6_
VD
D2
VD
D3
VD
D4
VD
D5
VD
D6
VD
D7
VD
D1
GN
D2
GN
D3
GN
D4
GN
D1
FSEL
+2.5V
USB_PA[7:0]
USB_AUX[7:0] DC0_2[7:0]DC0_1[7:0]
DC3_2[7:0]
DC2_2[7:0]
9
8
5 6
7
U5
10
3 4
1 2
pn-jtag_header
7
21
43
65
8
9 10
U4
pn-jtag_header
5 6
3 4
1 2
7
109
87
21
43
65
8
9 10
+3.3V
R5
1 21K
1 2
R1
1K
R2
10k1 2
1 210k
R3
1 210k
R4
+2.5V
+2.5V
1 210k
R6
2
R7
1 0
R8
1 20
U6
1
pn-EPCS64
16
3
5
14
15
4
10
9
6
7
2
8
11
12
13
NC3
NC1
DCLK
nCS
NC4
VCC3
GND
NC2
ASDI
NC8
NC7
NC6
NC5
DATA
VCC2
VCC1
20
R9
1
10k
R10
1 2
10k
R11
1 2
R12
1 210k
R13
1 20
+3.3V
+3.3V
+3.3V
+3.3V
+3.3V
+3.3V
+3.3V
System[7:0]
DC3_1[7:0]
DC2_1[7:0]
DC1_2[7:0]DC1_1[7:0]
6
5
4
3pn-LED_3
2
1
U7
1
2
3
4
5
6
+2.5V
10k R14
12
+2.5V
10k R15
12
10k
2
R16
1+2.5V
2
7
2019
18
15
6
3 4
1
U8
16
13 14
11 12
17
10
pn-header_20
9
8
5
17
1211
1413
1615
18
19 20
7
21
43
65
8
9 10
LEDs[5:0]
R58
2221
+2.5V
+2.5V
+2.5V
+2.5V
+2.5V
+2.5V
0
R17
1 2
12
R24
spac
e
1
2Tp1
pn-tp2
i2
i1
0
R18
1 2
0
R19
1 2
R20
1 20
+2.5V
21U9
34
pn-clk125
EN GND
VCC CLK
+2.5V +2.5V
1
2 0.1uF
C1
+2.5V
+1.1V
1
2 0.1uF
C3
+1.1V_PLL
1
2 0.1uF
C4
+2.5V_PLL
1
2 0.1uF
C5
32
1
pn-SMA
U30
IN1
CS1 CS2
C61
2 0.1uF
C71
2 0.1uF
0.1uF 2
C21 1
2
C48
10uF
R21
12
1k1k
R22
12
R23
124
02
1
2 0.1uF
C8
Mngmnt[5:0]
USB_FD13
DC0in1
USB_FD15
USB_FD2
DC0in2
USB_FD12
USB_FD14
DC0in3
DC0in1_n
DC0out2_n
USB_FD1
USB_FD8
DC0out2ENET_RX_nENET_RXENET_TX_nENET_TXENET_CLK_nENET_CLK
VCCPGM|+3.3V
*
USB_FD5
USB_FD9
USB_FD3
USB_FD7
USB_FD11
USB_FD0
USB_FD6
USB_FD10
USB_FD4
USB_PA3USB_PA4
nCONFIG
nCONFIG
ALTERA_DATA0
ALTERA_DATA0
CONF_DONE
CONF_DONE
ASDO
ASDO
DCLK
DCLK
VCC_CLKIN8C|+2.5VVCC_CLKIN7C|+2.5VVCC_CLKIN4C|+2.5V
VCCBAT|+2.5VVCC_CLKIN3C|+2.5V
VCCPT|+2.5V
VCCPD6A|+2.5VVCCPD6C|+2.5VVCCPD7C|+2.5VVCCPD8C|+2.5V
VCCPD5C|+2.5VVCCPD5A|+2.5VVCCPD4C|+2.5VVCCPD3C|+2.5VVCCPD2C|+2.5VVCCPD2A|+2.5VVCCPD1C|+2.5VVCCPD1A|+2.5V
VCCIO6A|+2.5VVCCIO6C|+2.5VVCCIO7C|+2.5VVCCIO8C|+2.5V
VCCIO5A|+2.5VVCCIO5C|+2.5V
VCCIO3C|+2.5VVCCIO4C|+2.5V
VCCIO2A|+2.5VVCCIO2C|+2.5V
VCCIO1C|+2.5VVCCIO1A|+2.5V
ground
ground
GND
GND|ground
VREFB8CN0|groundVREFB7CN0|groundVREFB6CN0|groundVREFB6AN0|ground
VREFB5AN0|groundVREFB5CN0|ground
VREFB4CN0|groundVREFB3CN0|groundVREFB2CN0|groundVREFB2AN0|groundVREFB1CN0|groundVREFB1AN0|groundTEMPDIODEp|groundTEMPDIODEn|ground
GND+|ground
nIO_PULLUP|ground nCE
nCE
nCSO
nCSO
altera_reserved_tck
altera_reserved_tdo
altera_reserved_tms
altera_reserved_tdi
altera_reserved_ntrst
MSEL0
MSEL1
MSEL2
PORSEL
nSTATUS
ENET_RX_COLENET_RX_CRSENET_RX_D7ENET_RX_D6ENET_RX_D5ENET_RX_D4ENET_RX_D3ENET_RX_D2ENET_RX_D1ENET_RX_D0ENET_RX_ERENET_RX_DVENET_RX_CLKENET_TX_D7ENET_TX_D6ENET_TX_D5ENET_TX_D4ENET_TX_D3ENET_TX_D2ENET_TX_D1ENET_TX_D0ENET_TX_ERENET_TX_ENENET_TX_CLKENET_GTX_CLK
DC0in2_n
systemin0systemin0_nsystemin1systemin1_n
systemclkin
systemclkin
systemclkin_n
systemclkin_nsystemoutsystemout_n
USB_CLKOUTUSB_IFCLKUSB__WAKEUPUSB_CTL0USB_CTL1USB_CTL2USB_RDY0USB_RDy1
USB_PA0USB_PA1USB_PA2
USB_PA5USB_PA6USB_PA7
DC1in1DC1in1_nDC1in2
DC1in3DC1in2_n
DC1out2DC1out2_n
DC2out0DC2out0_nDC2out1
clkout2
clkout2DC2out1_n
DC2in0DC2in0_n
DC2in1DC2in1_nDC2in2
DC2in3DC2in2_n
DC2out2DC2out2_n
DC3out0DC3out0_nDC3out1
clkout3
clkout3DC3out1_n
DC3in0DC3in0_n
DC3in1DC3in1_nDC3in2
DC3in3DC3in2_n
DC3out2DC3out2_n
DC0out0DC0out0_nDC0out1
clkout0
clkout0DC0out1_n
DC0in0DC0in0_n
clkout1
clkout1
DC1out0DC1out0_nDC1out1DC1out1_n
DC1in0DC1in0_n
led_1led_0
led_2
debug2
debug3
debug4
debug6
debug5
debug7
debug8
debug10
debug9 debug19
ENET_LED_LINK1000
clkout3_n
clkout3_n
DCrefclockDCrefclock_n
debug11
debug12
debug13
debug14
debug16
debug15
debug17
debug18
CLOCKINCLOCKIN_n
+1.1V_PLL
VCCD_PLL_R2|+1.1V_PLLVCCD_PLL_T1|+1.1V_PLLVCCD_PLL_B1|+1.1V_PLLVCCD_PLL_L2|+1.1V_PLL
+1.1V
VCCL|+1.1VVCC|+1.1V
ENET_MDIO
ENET_INTnENET_MDC
ENET_RESETn
clkout0_n
clkout0_n
clkout1_n
clkout1_n
clkout2_n
clkout2_n
DC0in3_n
DC1in3_n
DC2in3_n
DC3in3_n
+2.5V_PLL
VCCA_PLL_T1|+2.5V_PLLVCCA_PLL_R2|+2.5V_PLL
VCCA_PLL_L2|+2.5V_PLLVCCA_PLL_B1|+2.5V_PLL
USB_FD[15:0]
LEDs[5:0]
USB_PA[7:0]
SGMII[5:0]
Mngmnt[5:0]
USB_AUX[7:0] DC0_2[7:0]DC0_1[7:0]
DC3_2[7:0]
DC2_2[7:0]
GMII[24:0]
System[7:0]
DC3_1[7:0]
DC2_1[7:0]
DC1_2[7:0]DC1_1[7:0]
GMII[0]GMII[1]
USB_FD[0]
DC3_1[7]
USB_FD[1]USB_FD[2]USB_FD[3]USB_FD[4]USB_FD[5]USB_FD[6]
GMII[2]
USB_FD[7]
GMII[3]GMII[4]GMII[5]GMII[6]GMII[7]GMII[8]GMII[9]GMII[10]GMII[11]GMII[12]GMII[13]GMII[14]GMII[15]GMII[16]GMII[17]GMII[18]GMII[19]GMII[20]
USB_FD[8]
SGMII[0]SGMII[1]
USB_PA[7]
USB_FD[9]USB_FD[10]USB_FD[11]USB_FD[12]USB_FD[13]USB_FD[14]USB_FD[15]
GMII[21]USB_PA[6]USB_PA[5]USB_PA[4]USB_PA[3]USB_PA[2]USB_PA[1]USB_PA[0]
USB_AUX[7]USB_AUX[6]USB_AUX[5]USB_AUX[4]USB_AUX[3]USB_AUX[2]USB_AUX[1]USB_AUX[0]
SGMII[2]SGMII[3]
DC0_2[7]DC0_2[6]
DC0_2[5]DC0_2[4]DC0_2[3]DC0_2[2]DC0_2[1]DC0_2[0]
DC0_1[7]DC0_1[6]
DC0_1[5]DC0_1[4]DC0_1[3]DC0_1[2]DC0_1[1]DC0_1[0]
DC3_2[7]DC3_2[6]
DC3_2[5]DC3_2[4]DC3_2[3]DC3_2[2]DC3_2[1]DC3_2[0]
DC2_2[7]DC2_2[6]
DC2_2[5]DC2_2[4]DC2_2[3]DC2_2[2]DC2_2[1]DC2_2[0]
GMII[22]GMII[23]GMII[24]
System[0]System[1]System[2]System[3]System[4]System[5]System[6]System[7]
DC3_1[6]DC3_1[5]DC3_1[4]DC3_1[3]DC3_1[2]DC3_1[1]DC3_1[0]
DC2_1[7]DC2_1[6]
DC2_1[5]DC2_1[4]DC2_1[3]DC2_1[2]DC2_1[1]DC2_1[0]
DC1_2[7]DC1_2[6]
DC1_2[5]DC1_2[4]DC1_2[3]DC1_2[2]DC1_2[1]DC1_2[0]
DC1_1[7]DC1_1[6]
DC1_1[5]DC1_1[4]DC1_1[3]DC1_1[2]DC1_1[1]DC1_1[0]
SGMII[4]SGMII[5]
LEDs[5]LEDs[4]LEDs[3]LEDs[2]LEDs[1]LEDs[0]
Mngmnt[5]Mngmnt[4]Mngmnt[3]Mngmnt[2]Mngmnt[1]Mngmnt[0]
SM7720HEW-40.0M
2766 Rev. A
4/7 -1
USB-Blaster
JTAG Connector
-
DC2in3
ENET_MDC
DCLK
ASDO
DC0in1
DC0in1_n
DC2in3_n
DC1in0_n
DC1in0
ENET_RX_CLK
ENET_LED_LINK1000
ENET_RX_COL
DC3in1
DC3in1_n
DC3in3_n
DC1in3_n
DC1in3
CONF_DONE
ENET_RESETn
debug3
debug14
DC3in3
DC1in1
ENET_RX_D2
ENET_RX_D1
ENET_RX_D0
ENET_INTn
ENET_MDIO
DC3in0_n
DC0in0
DC0in0_n
DC1in1_n
DC2in1_n
DC2in1
ENET_RX_D4
ENET_RX_DV
ENET_RX_D3
ENET_GTX_CLK
debug11
DC3in0
DC3in2
DC3in2_n
ENET_RX_ER
ENET_RX_D5
ENET_RX_CRS
debug13
DC0in3
DC0in3_n
ENET_led_an
ENET_RX_D6
ENET_RX_D7
debug12
debug16
debug15
DC0in2
DC0in2_n
ENET_RX_n
ENET_RX
ENET_led_char_err
ENETled_link
debug17
debug18
debug10
debug6
ENET_CLK_n
ENET_CLK
ENET_TX_n
ENET_TX
debug5
debug7
DC3out0
DC3out0_n
ENET_TX_ER
ENET_TX_D7
DNU
DC3out1
DC3out1_n
ENET_TX_D6
ALTERA_DATA2
ALTERA_DATA3T
DC3out2
DC3out2_n
debug9
DCrefclock
DCrefclock_n
ENET_TX_D4
ALTERA_DATA6
ALTERA_DATA7
ALTERA_DATA1
ALTERA_DATA5
DC2out0_n
DC1out0_n
DC2out1
DC2out1_n
debug19
ALTERA_DATA4
DC2out0
DC1out0
DC2out2
DC2out2_n
debug8
ENET_TX_CLK
DC1out1_n
DC1out2_n
debug4
altera_reserved_ntrst
ENET_TX_D3
ENET_TX_D1
DC1out1
DC1out2
DC0out0
DC0out0_n
altera_reserved_tdi
DC0out1
DC0out1_n
altera_reserved_tck
altera_reserved_tms
ENET_TX_D2
ENET_TX_EN
DC0out2_n
DC0out2
DC1in2_n
DC1in2
DC2in2_n
DC2in2
ENET_TX_D5
CLOCKIN_n
debug2
DC2in0_n
DC2in0
ENET_led_disp_err
CLOCKIN
altera_reserved_tdo
ENET_TX_D0
PORSEL
nCE
nCSO
nSTATUS
VCCIO4C
VREFB3CN0
VREFB4CN0
USB_FD8
USB_FD10
VCCD_PLL_B1
VCCA_PLL_B1
VCC_CLKIN4C
USB_FD9
USB_FD12
nCEO
USB_FD13
VREFB2AN0
VCCIO3C
VCC_CLKIN3C
led_2
VCCPGM
VREFB5AN0
USB_FD14
Systemin1_n
Systemin1
USB_RDY0
VCCIO2A
VCCPD2A
VCCPD3C
VCCIO5A
VCCIO2C
USB_RDY1
VCCPD4C
VCCPD5A
USB_FD7
VREFB5CN0
Systemin0_n
Systemin0
VREFB2CN0
VCCPD2C
VCCPD5C
VCCIO5C
USB_FD6
USB_CLKOUT
VCCA_PLL_L2
VCCD_PLL_L2
USB_CTL0
VCCPD6C
VCCD_PLL_R2
VCCA_PLL_R2
GND+
VREFB1CN0
USB_PA6
VCCPD1C
VREFB6CN0
USB_PA4
VCCPD1A
VCCL
VCC
VCCIO1C
USB_CTL1
USB_IFCLK
USB_PA1
VCCPD8C
VCCPD7C
VCCPD6A
USB_FD5
USB_FD2
USB_CTL2
USB_PA7
USB__WAKEUP
VREFB1AN0
USB_PA0
VCCD_PLL_T1
MSEL2
VREFB6AN0
USB_FD0
VCCIO6C
USB_FD4
USB_PA3
USB_PA5
VCC_CLKIN8C
VCCA_PLL_T1
VCCPT
USB_SPARE
VREFB8CN0
VCC_CLKIN7C
VREFB7CN0
MSEL0
led_1
USB_FD1
USB_PA2
VCCBAT
VCCIO1A
VCCIO7C
MSEL1
Systemout_n
VCCIO6A
VCCIO8C
Systemout
nCONFIG
nIO_PULLUP
USB_FD15
USB_FD11
TEMPDIODEn
TEMPDIODEp
USB_FD3
led_0
GND
ALTERA_DATA0
0Mircea Bogdan 30-12-2011_15:36
block_fpga
ofDRAWN BY
TITLE
SIZE
D
DWG NO REV
SHEETSCALE
H
G
F
E
D
C
A
4 3 2 1
4 3 2 1
H
G
F
E
D
C
B
A
B
The University of ChicagoElectronics Design Group
USB_FD13
DC0in1
USB_FD15
USB_FD2
DC0in2
USB_FD12
USB_FD14
DC0in3
DC0in1_n
DC0out2_n
USB_FD1
USB_FD8
DC0out2
ENET_RX_n
ENET_RX
ENET_TX_n
ENET_TX
ENET_CLK_n
ENET_CLK
VCCPGM
USB_FD5
USB_FD9
USB_FD3
USB_FD7
USB_FD11
USB_FD0
USB_FD6
USB_FD10
USB_FD4
USB_PA3
USB_PA4
nCONFIG
ALTERA_DATA0
CONF_DONE
ASDO
DCLK
VCCIO4C
VCC_CLKIN4C
VCCIO3C
VCC_CLKIN3C
VCCIO2A
VCCPD2A
VCCPD3C
VCCIO5A
VCCIO2C
VCCPD4C
VCCPD5A
VCCPD2C
VCCPD5C
VCCIO5C
VCCPD6C
VCCPD1C
VCCPD1A
VCCIO1C
VCCPD8C
VCCPD7C
VCCPD6A
VCCIO6C
VCC_CLKIN8C
VCCPT
VCC_CLKIN7C
VCCBAT
VCCIO1A
VCCIO7C
VCCIO6A
VCCIO8C
VREFB3CN0
VREFB4CN0
VREFB2AN0
VREFB5AN0
VREFB5CN0
VREFB2CN0
GND+
VREFB1CN0
VREFB6CN0
VREFB1AN0
VREFB6AN0
VREFB8CN0
VREFB7CN0
nIO_PULLUP
TEMPDIODEn
TEMPDIODEp
GND
nCE
nCSO
altera_reserved_tck
altera_reserved_tdo
altera_reserved_tms
altera_reserved_tdi
altera_reserved_ntrst
MSEL0
MSEL1
MSEL2
PORSEL
nSTATUS
ENET_RX_COL
ENET_RX_CRS
ENET_RX_D7
ENET_RX_D6
ENET_RX_D5
ENET_RX_D4
ENET_RX_D3
ENET_RX_D2
ENET_RX_D1
ENET_RX_D0
ENET_RX_ER
ENET_RX_DV
ENET_RX_CLK
ENET_TX_D7
ENET_TX_D6
ENET_TX_D5
ENET_TX_D4
ENET_TX_D3
ENET_TX_D2
ENET_TX_D1
ENET_TX_D0
ENET_TX_ER
ENET_TX_EN
ENET_TX_CLK
ENET_GTX_CLK
DC0in2_n
Systemin0
Systemin0_n
Systemin1
Systemin1_n
Systemout
Systemout_n
USB_CLKOUT
USB_IFCLK
USB__WAKEUP
USB_CTL0
USB_CTL1
USB_CTL2
USB_RDY0
USB_RDY1
USB_PA0
USB_PA1
USB_PA2
USB_PA5
USB_PA6
USB_PA7
DC1in1
DC1in1_n
DC1in2
DC1in3
DC1in2_n
DC1out2
DC1out2_n
DC2out0
DC2out0_n
DC2out1
DC2out1_n
DC2in0
DC2in0_n
DC2in1
DC2in1_n
DC2in2
DC2in3
DC2in2_n
DC2out2
DC2out2_n
DC3out0
DC3out0_n
DC3out1
DC3out1_n
DC3in0
DC3in0_n
DC3in1
DC3in1_n
DC3in2
DC3in3
DC3in2_n
DC3out2
DC3out2_n
DC0out0
DC0out0_n
DC0out1
DC0out1_n
DC0in0
DC0in0_n
DC1out0
DC1out0_n
DC1out1
DC1out1_n
DC1in0
DC1in0_n
led_1
led_0
led_2
debug2
debug3
debug4
debug6
debug5
debug7
debug8
debug10
debug9
debug19
ENET_LED_LINK1000
DCrefclock
DCrefclock_n
debug11
debug12
debug13
debug14
debug16
debug15
debug17
debug18
CLOCKIN
CLOCKIN_n
USB_SPARE
VCCD_PLL_B1
VCCD_PLL_L2
VCCD_PLL_R2
VCCD_PLL_T1
VCCL
VCC
nCEO
ENET_led_disp_err
ALTERA_DATA4
ALTERA_DATA5
ALTERA_DATA1
ALTERA_DATA7
ALTERA_DATA6
ALTERA_DATA3T
ALTERA_DATA2
DNU
ENETled_link
ENET_led_char_err
ENET_led_an
ENET_MDIO
ENET_INTn
ENET_MDC
ENET_RESETn
DC0in3_n
DC1in3_n
DC2in3_n
DC3in3_n
VCCA_PLL_B1
VCCA_PLL_L2
VCCA_PLL_R2
VCCA_PLL_T1
2766 Rev. A
4/7 -2
-
DC1_1[7:0]
0
dc_conn
23-01-2012_08:43
456 3 2 1
REV
TITLE
SCALE SHEET
SIZE DWG NO
1236 5 4
B
A A
B
C
D
C
D
CofDRAWN BY
The University of ChicagoElectronics Design Group
Mircea Bogdan
1513
111
17
2232
3028
26
37
9
pn-4Port_RJ45
U11
36
35
18
2927
25
2416
1412
10
34
33
20
3123
2119
86
42
75
3
CS3
CS4
CS5
CS1
CS2
2 1L11
10uH
L12
10uH
2 1
1
10uH
2
L8
10uH
2 1L9
DC1_2[7:0]
DC2_2[7:0]
DC2_1[7:0]
21
10uH L10
ground
ground
ground
2datain1n
2datain1
2ctrlout3n
2ctrlout3
2datain2n
2datain2
2datain0
2datain0n
2ctrlout1
2ctrlout1n
2ctrlout2
2ctrlout2n
2clkout
2clkoutn
2ctrlin
2ctrlinn
1ctrlout1
1ctrlout1n
1ctrlout2
1ctrlout2n
1clkout
1clkoutn
1ctrlin
1ctrlinn
1datain0
1datain0n
1datain1
1datain1n
1datain2
1datain2n
1ctrlout3
1ctrlout3n
DC1_1[7:0]
DC1_2[7:0]
DC2_2[7:0]
DC2_1[7:0]
DC1_1[0] DC1_1[1] DC1_1[2] DC1_1[3] DC1_1[4] DC1_1[5] DC1_1[6]
DC1_1[7]
DC1_2[7]DC1_2[6]DC1_2[5]DC1_2[4]DC1_2[3]DC1_2[1]
DC1_2[2]DC1_2[0]
DC2_2[7]DC2_2[6]DC2_2[5]DC2_2[4]DC2_2[3]DC2_2[2]DC2_2[1]DC2_2[0]
DC2_1[7]DC2_1[6]DC2_1[5]DC2_1[4]DC2_1[3]DC2_1[1]
DC2_1[2]DC2_1[0]
2/72766 Rev. A
SS-668804S-A-PG4-AC
Stewart4-Port RJ45
-
19-12-2011_10:45
0
Power_block
456 3 2 1
REV
TITLE
SCALE SHEET
SIZE DWG NO
1236 5 4
B
A A
B
C
D
C
D
CofDRAWN BY
The University of ChicagoElectronics Design Group
Mircea Bogdan
1
0.01
C10
2
C111
2 0.01
C121
2 0.01
C131
2 0.01
1
2
C14
0.01
1
2
C15
0.010.012
C161
0.01
C171
2
1
2 0.01
C18
0.01
C191
2
C20
0.01
1
2
1
2 0.01
C21C221
0.012
C231
2 0.012
1
0.01
C241
2 0.01
C25
+2.5V
pn-fuse
U21 21 2
R42
12
1K37
R43
1K6512
+3.3V
+5V
C50
10uF
1
2
3
2pn-MIC39300
U23
1
GND
OUTIN
pn-LM1084
U293 2
1
GND
OUTIN
10uF
1
2
pn-tp1
Tp_1V1_PLL
pn-tp
Tp_GND_1
1
2 1
10uH
pn-tp
Tp_1V1
1
2 5
7
3 6
4
U24
pn-LP38853T_ADJ
1
GND
OUTIN
BIAS
ADJEN
SS
pn-tp
Tp_2V5_PLL
1
10uF2
1
Tp_GND_2
pn-tp1
L1
2 1
10uH
Tp_3V3
1pn-tp
Tp_2V5
pn-tp1
pn-tp
Tp_GND_3
1
2 10uF
C511
+1.1V_PLL
+2.5V_PLL
pn-tp1
Tp_GND_4
C26
0.01
1
2
1
20.01
C27 C28
0.01
1
2
1
2 0.01
C29
2
1
10uF
C52
+2.5V
+3.3V
1
2 10uF
C53
0.01
1
2
C30
C31
8.2nF
1
2
10uF
C541
2
1
2
C55
10uF
2
C561
10uF
1
2 10uF
C57
pn-fuse
U22 21 2
0.01
C321
2 0.01
1
2
C33
2
C341
0.01
1
2
C35
0.01
C361
2 0.01
C371
2 0.01
1
2 0.01
C38
2 0.01
C391 C40
0.01
1
2 0.01
C411
2
1
2 0.01
C42 C43
0.01
1
2 0.01
C441
2 0.01
C451
2
C461
2 0.01
1
2 0.01
C47
U27
pn-MOLEX_4pin
14
32
12
34
+5V
10uF
1
2
+5V
0.01
1
2
21
pn-fuse2
+3.3V
pn-tp1
5V
1
2 0.010.01
1
2 0.01
1
2
1
2 0.010.01
1
2
+1.1V
ground
+3.3V
+2.5V_PLL
+1.1V_PLL
MIC39300-2.5BT
LP38853T_ADJ
LM1084IT-3.3
2766 Rev. A3/7
MOLEX 0026605040
Right Angle Header
-
2
5
4
1
U12
3
TPS3828_33
_MR
_RST
WDI
VDD
GND
10K
2 R33
1
+3.3VUSB
0.1uF
C631
2
Tp_USB_VCC
1
C64
0.1uF
1
2
+3.3VUSB
1
2 0.1uF
C60
10uF
C781
2U13
3 2
1
4
GND
VOUTVIN
ADJ
3
2
65
1
4
U14Dn
Dp
GND
VCC
Sh1 Sh2
C651
2 0.1uF
1
2 10uF
C79
USB_PA[7:0]
USB_AUX[7:0]
C80
2
1
10uF
C591
10pF 2 2 0.1uF
C671
C58
10pF
1
2
10uFC81
1
2
20
30
27
31
16
23
9
36
8
53
U15
CY7C6803_56
52
55
56
54
2
3
38
1211
5
49
34
13
42
10
45
41
43
22
51
29
6
28
50
46
44
15
18
7 4
39 14
17
1
24
37
1935 33
40
48
26
25
21
47
32
FD9
RDY0
CTL0
RDY1
SDA
Dn
FD6
FD2
FD5
IFCLK
_WAKEUP
SCL
PA3
PA1
PA5
AV
CC
PA2
AG
ND
VC
C5
_RESET
CLKOUT
XT
ALO
UT
XT
ALI
N
CTL2
GN
D3
VC
C2
VC
C6
GN
D1
GN
D2
VC
C3
Dp
PA4
PA6
VC
C7
FD3
VC
C1
FD4
FD7
PA7
Res
erve
d
FD0
FD1G
ND
7
PA0
GN
D5
GN
D6
GN
D4
CTL1
VC
C4
FD13
FD15
FD14
FD10
FD12
FD11
FD8
1k
R28
12
R29
12
10k
U16 12 1 20
R34Tp_3V3_USB
1
12
Tp2
i2 i1
C66
0.1uF
1
2
U17
24LC65_SM
18
7
4
6
5
3
2
A0
A1
A2
SDA
SCL
VSS
NC
VCC
0.1uF
1
2
C68
115
R25
12
+3.3VUSB
C691
2 0.1uF
+3.3VUSB
C61
0.1uF
1
20.1uF
1
2
C70C711
2 0.1uF0.1uF
C721
2
+3.3VUSB
+3.3VUSB
1k
R32
12
1
2 0.1uF
C62
12
187
R26
33R31
21
R30
12
10k
usb
09-01-2012_15:47
0
456 3 2 1
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TITLE
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1236 5 4
B
A A
B
C
D
C
D
CofDRAWN BY
The University of ChicagoElectronics Design Group
Mircea Bogdan
0.1uF
C731
2
USB_FD[15:0]
12 R27
1k
ground
USB_PA[7]
USB_PA[6]
USB_PA[5]
USB_PA[4]
USB_PA[3]
USB_PA[2]
USB_PA[1]
USB_PA[0]
+3.3VUSB
+3.3VUSB
USB_D_n
USB_D
USB_RDY_1USB_RDY_0
USB_CTL_2USB_CTL_1USB_CTL_0
USB__WAKEUPUSB_IFCLKUSB_CLKOUT
USB_FD[15]
USB_FD[14]
USB_FD[11]
USB_FD[10]
USB_FD[9]
USB_FD[8]
USB_FD[7]
USB_FD[6]
USB_FD[5]
USB_FD[4]
USB_FD[3]
USB_FD[2]
USB_FD[1]
USB_FD[0]
USB_FD[12]
USB_FD[13]
USB_AUX[7:0]USB_FD[15:0]
USB_PA[7:0]
USB_PA[7]
USB_FD[15]
USB_AUX[0]USB_AUX[1]USB_AUX[2]
USB_PA[6]
USB_PA[5]
USB_PA[4]
USB_PA[3]
USB_PA[2]
USB_AUX[3]
USB_PA[1]
USB_PA[0]
USB_FD[14]
USB_FD[10]
USB_AUX[4]
USB_FD[9]
USB_FD[8]
USB_FD[7]
USB_FD[6]
USB_FD[5]
USB_FD[4]
USB_FD[3]
USB_FD[2]
USB_FD[1]
USB_FD[0]
USB_FD[13]
USB_AUX[5]
USB_AUX[6]
USB_FD[12]
USB_FD[11]
USB_AUX[7]
2766 Rev. A6/7
61729-1011BLF
FCIConnector USB
A
-
DC1_1[7:0]
23-01-2012_08:43
0
dc_conn
456 3 2 1
REV
TITLE
SCALE SHEET
SIZE DWG NO
1236 5 4
B
A A
B
C
D
C
D
CofDRAWN BY
The University of ChicagoElectronics Design Group
Mircea Bogdan
9
86
3123
2119
1
42
75
17
2232
3028
26
37
36
35
18
2927
U10
pn-4Port_RJ45
1513
1125
2416
1412
10
3
34
33
20
CS3
CS4
CS5
CS1
CS2
2 1L6
10uH
10uH
2 1L7
21L3
10uH
L42 1
10uH
DC1_2[7:0]
DC2_2[7:0]
DC2_1[7:0]
10uH
21
L5
ground
ground
ground
2datain1n
2datain1
2ctrlout3n
2ctrlout3
2datain2n
2datain2
2datain0
2datain0n
2ctrlout1
2ctrlout1n
2ctrlout2
2ctrlout2n
2clkout
2clkoutn
2ctrlin
2ctrlinn
1ctrlout1
1ctrlout1n
1ctrlout2
1ctrlout2n
1clkout
1clkoutn
1ctrlin
1ctrlinn
1datain0
1datain0n
1datain1
1datain1n
1datain2
1datain2n
1ctrlout3
1ctrlout3n
DC1_1[7:0]
DC1_2[7:0]
DC2_2[7:0]
DC2_1[7:0]
DC1_1[0] DC1_1[1] DC1_1[2] DC1_1[3] DC1_1[4] DC1_1[5] DC1_1[6]
DC1_1[7]
DC1_2[7]DC1_2[6]DC1_2[5]DC1_2[4]DC1_2[3]DC1_2[1]
DC1_2[2]DC1_2[0]
DC2_2[7]DC2_2[6]DC2_2[5]DC2_2[4]DC2_2[3]DC2_2[2]DC2_2[1]DC2_2[0]
DC2_1[7]DC2_1[6]DC2_1[5]DC2_1[4]DC2_1[3]DC2_1[1]
DC2_1[2]DC2_1[0]
2/72766 Rev. A
SS-668804S-A-PG4-AC
Stewart4-Port RJ45
-
22-12-2011_08:28
0Mircea Bogdan
ethernetblock
ofDRAWN BY
TITLE
SIZE
D
DWG NO REV
SHEETSCALE
D
C
B
A A
B
C
D
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
The University of ChicagoElectronics Design Group
97 115 1227134 9085
100
99
98
95
92
91
105
107
112
113
109
110
114
115
8
55586063656683849394101
102
103
106
33
35
53
62
57
46
41
42
61
56
47
1046459524944 30 9673 89
19152122384043454851108
111
116
119
69
50
67
68
70
72
75
31
76
74
54
32
U18
pn-88E1111RCJpn-88E1111RCJ
77
39
118
117
4
7
29
28
18
26
25
24
20
19
79
127
2 78272317126
120
121
123
80
13
81
16
36
10
37
14
82
124
125
86
126
87
128
88
3RDX0
CONFIG0
RDX1
CONFIG1
RDX2
CONFIG2
RDX3RDX4
CONFIG3
GTX_CLKCOMA
TX_CLKRESETn
TX_EN
CONFIG4
TX_ER
CONFIG5
RDX5RDX6RDX7
DV
DD
1D
VD
D2
DV
DD
3D
VD
D4
DV
DD
5D
VD
D6
DV
DD
7
VS
S1
CONFIG6
TXD1TXD2TXD3TXD4TXD5
TXD0
TXD6TXD7
RXCLKRX_DVRX_ER
CRSCOL
S_CLK_PS_CLK_N
S_IN_PS_IN_N
S_OUT_PS_OUT_N
LED_TXLED_RX
LED_DUPLEXLED_LINK1000LED_LINK100LED_LINK10
DV
DD
8D
VD
D9
VD
DO
X1
VD
DO
X2
VD
DO
1
VD
DO
2V
DD
O3
VD
DO
H1
VD
DO
4
AV
DD
1A
VD
D2
AV
DD
3A
VD
D4
AV
DD
5A
VD
D6
MDI1_NMDI2_P
MDI3_P
MDI0_NMDI0_P
MDI1_P
MDI2_N
MDI3_N
HSDAC_P
MDCMDIO
INT_N
HSDAC_N
VSSC
XTAL1125CLK
XTAL2
TDO
TCKTRST_N
TDI
NC
TMS
VS
S2
VS
S3
VS
S4
VS
S5
VS
S6
VS
S7
VS
S8
VS
S9
VS
S10
VS
S11
VS
S12
VS
S13
VS
S14
VS
S15
VS
S16
VS
S17
VS
S18
VS
S19
VS
S20
VS
S21
VS
S22
VS
S23
VS
S24
VS
S25
VS
S26
VS
S27
VS
S28
VS
S29
VS
S30
VD
DO
H2
VD
DO
H3
DV
DD
10D
VD
D11
DV
DD
12
RSETSEL_FREQ
U19
pn-RJ45_HALO
10
9
1211
8
5
6
3
4
1
2
7TD3_P
TD0_N
TD0_P
TD2_P
TD1_P
TD1_N
TD2_N
TD3_N
CS1CS2
VCC
GND
Mngmnt[5:0]
LEDs[5:0]
1 4.7KR35 2
SGMII[5:0]
GMII[24:0]+2.5V
C9
0.1uF
1
2
pn-res0402
R51 1 2 49
pn-res0603
1 24.7KR37
1 24.9K
pn-res0603
R36
+2.5V
2
pn-res0402
49R44 1
49pn-res0402
R45 1 2
R46 1 2
pn-res0402
49
2 49pn-res0402
R47 1pn-res0402
49R48 1 2
pn-res0402
R49 1 2 49
49R50 1 2
pn-res0402
1 2
0.01uF
C74
C75
1 2
0.01uF
0.01uF
C76
1 2
0.01uF
C77
1 2
pn-res0603
R38 4.7K1 2
pn-res0603
R39 4.7K1 2
4.7K2
pn-res0603
R40 1
34
pn-SG31021
EN GND
VCC CLK
10k
12
pn-res0603
+2.5V
+2.5V
220
12
R52 R55
220
12
U2
pn-LED_3
6
5
4
3
2
11
2
3
4
5
6
220
12
R53 R54
220
12
6
5
4
3
2
1
U26
pn-LED_31
2
3
4
5
6
+2.5V
R56
220
12 R57
220 2
1
+2.5V
+2.5V
1
2 0.01
C82
2 0.01
C83
1 1
0.01
C84
2
1
2 0.01
C85
2 0.01
C86
1 1
2 0.01
C87
2 0.01
C88
1 1
2 0.01
C89C90
1
0.012
C91
1
2 0.01
C92
1
2 0.01
C93
0.01
1
2 0.012
C94
1 1
2
C95
0.01 0.01
C96
1
2 0.012
C97
1
0.01
C98
1
2
1
2 0.01
C99
0.01
C100
1
2
C101
1
2 0.010.01
C102
1
2
C103
1
0.012
C104
1
2 0.010.01
C105
1
2
1
2
C106
0.01
C107
1
2 0.010.01
C108
1
2
1
2 0.01
C109
+1.1V
+1.1V
+2.5V
ENET_RX_COLENET_RX_CRS
ENET_RX_D7ENET_RX_D6ENET_RX_D5ENET_RX_D4ENET_RX_D3ENET_RX_D2ENET_RX_D1ENET_RX_D0
ENET_RX_ERENET_RX_DVENET_RX_CLK
ENET_TX_D7ENET_TX_D6ENET_TX_D5ENET_TX_D4ENET_TX_D3ENET_TX_D2ENET_TX_D1ENET_TX_D0
ENET_TX_ERENET_TX_ENENET_TX_CLKENET_GTX_CLK
ENET_RX_nENET_RXENET_TX_n
ENET_TXENET_CLK_n
ENET_CLK
ENET_RESETn
ENET_RESETn
MDI_N3
MDI_N3
MDI_N0
MDI_N0
MDI_P1
MDI_P1
MDI_N1
MDI_N1
MDI_P2
MDI_P2
MDI_N2
MDI_N2
MDI_P3
MDI_P3
MDI_P0
MDI_P0
ENET_MDIO
ENET_MDIO
ENET_MDC
ENET_MDC
ENET_INTn
ENET_INTn
LED_LINK1000
LED_LINK1000
ENET_RSET
+2.5V
LED_LINK10
LED_LINK10
LED_LINK10
LED_LINK10
LED_RX
LED_RX
LED_RX
LED_DUPLEX
LED_DUPLEX
LED_LINK100
LED_LINK100
LED_TX
LED_TX
LED_TX
+1.1V
GMII[24:0]
Mngmnt[5:0]
LEDs[5:0]
SGMII[5:0]
GMII[5]
Mngmnt[0]Mngmnt[1]Mngmnt[2]Mngmnt[3]
Mngmnt[4]Mngmnt[5]
LEDs[0]LEDs[1]LEDs[2]LEDs[3]LEDs[4]
SGMII[5]SGMII[4]
GMII[24]GMII[23]
GMII[22]
SGMII[3]SGMII[2]
GMII[21]
SGMII[1]SGMII[0]
GMII[20]GMII[19]GMII[18]GMII[17]GMII[16]GMII[15]
GMII[14]GMII[13]GMII[12]
GMII[11]GMII[10]GMII[9]GMII[8]GMII[7]GMII[6]
LEDs[5]
GMII[4]
GMII[3]GMII[2]GMII[1]GMII[0]
HFJ11-1G02E
2766 Rev. A
7/7
-
System[7:0]
CAT5e10 9
8
5
6
3
4
1
2
7
U1
pn-CAT5e
IN7
IN2
IN1
IN4
IN3
IN6
IN5
IN8
CS1CS2
19-12-2011_10:56
systemconn
Mircea Bogdan
0REV
2 134
4 3 2 1
TITLE
SCALE
SIZE DWG NO
A
B B
A
SHEET
BofDRAWN BY
The University of ChicagoElectronics Design Group
systemout_n
sistemout
systemclkin_n
systemclkin
systemin1_n
systemin1
systemin0_n
systemin0
ground
System[7:0]
System[7]System[6]System[5]System[4]System[3]System[2]System[1]System[0]
2766 Rev. A5/7
RJ45-Tyco 5406299-1
-
FPGA_Chip $783I1ep3s50.1
VREFB8CN0 / FPGA_Chip
VREFB7CN0 / FPGA_Chip
VREFB6CN0 / FPGA_Chip
VREFB6AN0 / FPGA_Chip
VREFB5CN0 / FPGA_Chip
VREFB5AN0 / FPGA_Chip
VREFB4CN0 / FPGA_Chip
VREFB3CN0 / FPGA_Chip
VREFB2CN0 / FPGA_Chip
VREFB2AN0 / FPGA_Chip
VREFB1CN0 / FPGA_Chip
VREFB1AN0 / FPGA_Chip
VCC_CLKIN8C / FPGA_Chip
VCC_CLKIN7C / FPGA_Chip
VCC_CLKIN4C / FPGA_Chip
VCC_CLKIN3C / FPGA_Chip
VCCPT / FPGA_Chip
VCCPGM / FPGA_Chip
VCCPD8C / FPGA_Chip
VCCPD7C / FPGA_Chip
VCCPD6C / FPGA_Chip
VCCPD6A / FPGA_Chip
VCCPD5C / FPGA_Chip
VCCPD5A / FPGA_Chip
VCCPD4C / FPGA_Chip
VCCPD3C / FPGA_Chip
VCCPD2C / FPGA_Chip
VCCPD2A / FPGA_Chip
VCCPD1C / FPGA_Chip
VCCPD1A / FPGA_Chip
VCCL / FPGA_Chip
VCCIO8C / FPGA_Chip
VCCIO7C / FPGA_Chip
VCCIO6C / FPGA_Chip
VCCIO6A / FPGA_Chip
VCCIO5C / FPGA_Chip
VCCIO5A / FPGA_Chip
VCCIO4C / FPGA_Chip
VCCIO3C / FPGA_Chip
VCCIO2C / FPGA_Chip
VCCIO2A / FPGA_Chip
VCCIO1C / FPGA_Chip
VCCIO1A / FPGA_Chip
VCCD_PLL_T1 / FPGA_Chip
VCCD_PLL_R2 / FPGA_Chip
VCCD_PLL_L2 / FPGA_Chip
VREFB8CN0 : ...E13 : BI#
VREFB7CN0 : ...E10 : BI#
VREFB6CN0 : ...K5 : BI#
VREFB6AN0 : ...G5 : BI#
VREFB5CN0 : ...P5 : BI#
VREFB5AN0 : ...T5 : BI#
VREFB4CN0 : ...V10 : BI#
VREFB3CN0 : ...V12 : BI#
VREFB2CN0 : ...N18 : BI#
VREFB2AN0 : ...T18 : BI#
VREFB1CN0 : ...K18 : BI#
VREFB1AN0 : ...G18 : BI#
VCC_CLKIN8C : ...F13 : BI#
VCC_CLKIN7C : ...E11 : BI#
VCC_CLKIN4C : ...U10 : BI#
VCC_CLKIN3C : ...T12 : BI#
VCCPT : IN ...
VCCPGM : IN ...
VCCPD8C : IN H13 : BI#
VCCPD7C : IN H11 : BI#
VCCPD6C : IN L8 : BI#
VCCPD6A : IN H8 : BI#
VCCPD5C : IN N8 : BI#
VCCPD5A : IN P8 : BI#
VCCPD4C : IN P10 : BI#
VCCPD3C : IN R12 : BI#
VCCPD2C : IN N15 : BI#
VCCPD2A : IN R15 : BI#
VCCPD1C : IN K15 : BI#
VCCPD1A : IN J15 : BI#
VCCL : IN ...
VCCIO8C : IN ...
VCCIO7C : IN E8 : BI# C8 : B...
VCCIO6C : IN G2 : BI# K6 : B...
VCCIO6A : IN D5 : BI# C3 : B...
VCCIO5C : IN R1 : BI# N7 : B...
VCCIO5A : IN R7 : BI# Y5 : B...
VCCIO4C : IN ...
VCCIO3C : IN ...
VCCIO2C : IN ...
VCCIO2A : IN ...
VCCIO1C : IN ...
VCCIO1A : IN ...
VCCD_PLL_T1 : ...G12 : BI#
VCCD_PLL_R2 : ...L6 : BI#
VCCD_PLL_L2 : ...M17 : BI#
-
FPGA_Chip $783I1ep3s50.1
VCCD_PLL_B1 / FPGA_Chip
VCCBAT / FPGA_Chip
VCCA_PLL_T1 / FPGA_Chip
VCCA_PLL_R2 / FPGA_Chip
VCCA_PLL_L2 / FPGA_Chip
VCCA_PLL_B1 / FPGA_Chip
VCC / FPGA_Chip
USB__WAKEUP / FPGA_Chip
USB_SPARE / FPGA_Chip
USB_RDY1 / FPGA_Chip
USB_RDY0 / FPGA_Chip
USB_PA7 / FPGA_Chip
USB_PA6 / FPGA_Chip
USB_PA5 / FPGA_Chip
USB_PA4 / FPGA_Chip
USB_PA3 / FPGA_Chip
USB_PA2 / FPGA_Chip
USB_PA1 / FPGA_Chip
USB_PA0 / FPGA_Chip
USB_IFCLK / FPGA_Chip
USB_FD9 / FPGA_Chip
USB_FD8 / FPGA_Chip
USB_FD7 / FPGA_Chip
USB_FD6 / FPGA_Chip
USB_FD5 / FPGA_Chip
USB_FD4 / FPGA_Chip
USB_FD3 / FPGA_Chip
USB_FD2 / FPGA_Chip
USB_FD15 / FPGA_Chip
USB_FD14 / FPGA_Chip
USB_FD13 / FPGA_Chip
USB_FD12 / FPGA_Chip
USB_FD11 / FPGA_Chip
USB_FD10 / FPGA_Chip
USB_FD1 / FPGA_Chip
USB_FD0 / FPGA_Chip
USB_CTL2 / FPGA_Chip
USB_CTL1 / FPGA_Chip
USB_CTL0 / FPGA_Chip
USB_CLKOUT / FPGA_Chip
TEMPDIODEp / FPGA_Chip
TEMPDIODEn / FPGA_Chip
Systemout_n / FPGA_Chip
Systemout / FPGA_Chip
Systemin1_n / FPGA_Chip
Systemin1 / FPGA_Chip
VCCD_PLL_B1 : ...U12 : BI#
VCCBAT : IN D4 : BI#
VCCA_PLL_T1 : ...F12 : BI#
VCCA_PLL_R2 : ...L5 : BI#
VCCA_PLL_L2 : ...M18 : BI#
VCCA_PLL_B1 : ...U11 : BI#
VCC : IN ...
USB__WAKEUP : ...G19 : BI#
USB_SPARE : ...E22 : BI#
USB_RDY1 : ... P19 : BI#
USB_RDY0 : ... R18 : BI#
USB_PA7 : IN G20 : BI#
USB_PA6 : IN K16 : BI#
USB_PA5 : IN F20 : BI#
USB_PA4 : IN J19 : BI#
USB_PA3 : IN F22 : BI#
USB_PA2 : IN D22 : BI#
USB_PA1 : IN H16 : BI#
USB_PA0 : IN G15 : BI#
USB_IFCLK : ... H19 : BI#
USB_FD9 : IN U8 : BI#
USB_FD8 : IN V7 : BI#
USB_FD7 : IN P6 : BI#
USB_FD6 : IN N6 : BI#
USB_FD5 : IN H2 : BI#
USB_FD4 : IN G1 : BI#
USB_FD3 : IN A4 : BI#
USB_FD2 : IN H1 : BI#
USB_FD15 : ... AB3 : BI#
USB_FD14 : ... T4 : BI#
USB_FD13 : ... U4 : BI#
USB_FD12 : ... U7 : BI#
USB_FD11 : ... AA1 : BI#
USB_FD10 : ... V3 : BI#
USB_FD1 : IN E2 : BI#
USB_FD0 : IN G4 : BI#
USB_CTL2 : ... G22 : BI#
USB_CTL1 : ... H20 : BI#
USB_CTL0 : ... L16 : BI#
USB_CLKOUT : ...M19 : BI#
TEMPDIODEp : ...A5 : BI#
TEMPDIODEn : ...A6 : BI#
Systemout_n : ...C5 : BI#
Systemout : ... B5 : BI#
Systemin1_n : ...R22 : BI#
Systemin1 : IN R21 : BI#
-
FPGA_Chip $783I1ep3s50.1
Systemin0_n / FPGA_Chip
Systemin0 / FPGA_Chip
PORSEL / FPGA_Chip
nSTATUS / FPGA_Chip
nIO_PULLUP / FPGA_Chip
nCSO / FPGA_Chip
nCONFIG / FPGA_Chip
nCEO / FPGA_Chip
nCE / FPGA_Chip
MSEL2 / FPGA_Chip
MSEL1 / FPGA_Chip
MSEL0 / FPGA_Chip
led_2 / FPGA_Chip
led_1 / FPGA_Chip
led_0 / FPGA_Chip
GND+ / FPGA_Chip
GND / FPGA_Chip
ENET_TX_n / FPGA_Chip
ENET_TX_ER / FPGA_Chip
ENET_TX_EN / FPGA_Chip
ENET_TX_D7 / FPGA_Chip
ENET_TX_D6 / FPGA_Chip
ENET_TX_D5 / FPGA_Chip
ENET_TX_D4 / FPGA_Chip
ENET_TX_D3 / FPGA_Chip
ENET_TX_D2 / FPGA_Chip
ENET_TX_D1 / FPGA_Chip
ENET_TX_D0 / FPGA_Chip
ENET_TX_CLK / FPGA_Chip
ENET_TX / FPGA_Chip
ENET_RX_n / FPGA_Chip
ENET_RX_ER / FPGA_Chip
ENET_RX_DV / FPGA_Chip
ENET_RX_D7 / FPGA_Chip
ENET_RX_D6 / FPGA_Chip
ENET_RX_D5 / FPGA_Chip
ENET_RX_D4 / FPGA_Chip
ENET_RX_D3 / FPGA_Chip
ENET_RX_D2 / FPGA_Chip
ENET_RX_D1 / FPGA_Chip
ENET_RX_D0 / FPGA_Chip
ENET_RX_CRS / FPGA_Chip
ENET_RX_COL / FPGA_Chip
ENET_RX_CLK / FPGA_Chip
ENET_RX / FPGA_Chip
ENET_RESETn / FPGA_Chip
Systemin0_n : ...N20 : BI#
Systemin0 : IN N19 : BI#
PORSEL : IN Y18 : BI#
nSTATUS : IN W18 : BI#
nIO_PULLUP : ...AB4 : BI#
nCSO : IN Y6 : BI#
nCONFIG : IN AB17 : B...
nCEO : IN U5 : BI#
nCE : IN Y17 : BI#
MSEL2 : IN G7 : BI#
MSEL1 : IN C6 : BI#
MSEL0 : IN E7 : BI#
led_2 : IN T7 : BI#
led_1 : IN E3 : BI#
led_0 : IN A2 : BI#
GND+ : IN ...
GND : IN ...
ENET_TX_n : ... M16 : BI#
ENET_TX_ER : ...L20 : BI#
ENET_TX_EN : ...C12 : BI#
ENET_TX_D7 : ...L19 : BI#
ENET_TX_D6 : ...K21 : BI#
ENET_TX_D5 : ...AB14 : B...
ENET_TX_D4 : ...J22 : BI#
ENET_TX_D3 : ...F15 : BI#
ENET_TX_D2 : ...D12 : BI#
ENET_TX_D1 : ...F14 : BI#
ENET_TX_D0 : ...A12 : BI#
ENET_TX_CLK : ...G21 : BI#
ENET_TX : BI M15 : BI#
ENET_RX_n : ... N22 : BI#
ENET_RX_ER : ...R20 : BI#
ENET_RX_DV : ...T17 : BI#
ENET_RX_D7 : ...P16 : BI#
ENET_RX_D6 : ...P17 : BI#
ENET_RX_D5 : ...R19 : BI#
ENET_RX_D4 : ...T19 : BI#
ENET_RX_D3 : ...T15 : BI#
ENET_RX_D2 : ...U19 : BI#
ENET_RX_D1 : ...U16 : BI#
ENET_RX_D0 : ...U15 : BI#
ENET_RX_CRS : ...R13 : BI#
ENET_RX_COL : ...W12 : BI#
ENET_RX_CLK : ...W14 : BI#
ENET_RX : BI N21 : BI#
ENET_RESETn : ...V13 : BI#
-
FPGA_Chip $783I1ep3s50.1
ENET_MDIO / FPGA_Chip
ENET_MDC / FPGA_Chip
ENET_LED_LINK1000 / FPGA_Chip
ENET_led_disp_err / FPGA_Chip
ENET_led_char_err / FPGA_Chip
ENET_led_an / FPGA_Chip
ENET_INTn / FPGA_Chip
ENET_GTX_CLK / FPGA_Chip
ENET_CLK_n / FPGA_Chip
ENET_CLK / FPGA_Chip
ENETled_link / FPGA_Chip
DNU / FPGA_Chip
debug9 / FPGA_Chip
debug8 / FPGA_Chip
debug7 / FPGA_Chip
debug6 / FPGA_Chip
debug5 / FPGA_Chip
debug4 / FPGA_Chip
debug3 / FPGA_Chip
debug2 / FPGA_Chip
debug19 / FPGA_Chip
debug18 / FPGA_Chip
debug17 / FPGA_Chip
debug16 / FPGA_Chip
debug15 / FPGA_Chip
debug14 / FPGA_Chip
debug13 / FPGA_Chip
debug12 / FPGA_Chip
debug11 / FPGA_Chip
debug10 / FPGA_Chip
DCrefclock_n / FPGA_Chip
DCrefclock / FPGA_Chip
DCLK / FPGA_Chip
DC3out2_n / FPGA_Chip
DC3out2 / FPGA_Chip
DC3out1_n / FPGA_Chip
DC3out1 / FPGA_Chip
DC3out0_n / FPGA_Chip
DC3out0 / FPGA_Chip
DC3in3_n / FPGA_Chip
DC3in3 / FPGA_Chip
DC3in2_n / FPGA_Chip
DC3in2 / FPGA_Chip
DC3in1_n / FPGA_Chip
DC3in1 / FPGA_Chip
DC3in0_n / FPGA_Chip
ENET_MDIO : ...U13 : BI#
ENET_MDC : ... Y12 : BI#
ENET_LED_LINK1000 : ...W13 : BI#
ENET_led_disp_err : ...AA15 : B...
ENET_led_char_err : ...N17 : BI#
ENET_led_an : ...P20 : BI#
ENET_INTn : ... U14 : BI#
ENET_GTX_CLK : ...T13 : BI#
ENET_CLK_n : ...M22 : BI#
ENET_CLK : ... M21 : BI#
ENETled_link : ...N16 : BI#
DNU : BI L12 : BI#
debug9 : BI K4 : BI#
debug8 : BI H3 : BI#
debug7 : BI M6 : BI#
debug6 : BI N2 : BI#
debug5 : BI M7 : BI#
debug4 : BI F21 : BI#
debug3 : BI V6 : BI#
debug2 : BI AB1 : BI#
debug19 : BI J1 : BI#
debug18 : BI N4 : BI#
debug17 : BI N5 : BI#
debug16 : BI P4 : BI#
debug15 : BI P3 : BI#
debug14 : BI V4 : BI#
debug13 : BI R6 : BI#
debug12 : BI P7 : BI#
debug11 : BI T8 : BI#
debug10 : BI N3 : BI#
DCrefclock_n : ...K1 : BI#
DCrefclock : ... K2 : BI#
DCLK : BI Y4 : BI#
DC3out2_n : ... K7 : BI#
DC3out2 : BI K8 : BI#
DC3out1_n : ... L3 : BI#
DC3out1 : BI L4 : BI#
DC3out0_n : ... M3 : BI#
DC3out0 : BI M4 : BI#
DC3in3_n : BI W1 : BI#
DC3in3 : BI V1 : BI#
DC3in2_n : BI T1 : BI#
DC3in2 : BI T2 : BI#
DC3in1_n : BI W2 : BI#
DC3in1 : BI W3 : BI#
DC3in0_n : BI U3 : BI#
-
FPGA_Chip $783I1ep3s50.1
DC3in0 / FPGA_Chip
DC2out2_n / FPGA_Chip
DC2out2 / FPGA_Chip
DC2out1_n / FPGA_Chip
DC2out1 / FPGA_Chip
DC2out0_n / FPGA_Chip
DC2out0 / FPGA_Chip
DC2in3_n / FPGA_Chip
DC2in3 / FPGA_Chip
DC2in2_n / FPGA_Chip
DC2in2 / FPGA_Chip
DC2in1_n / FPGA_Chip
DC2in1 / FPGA_Chip
DC2in0_n / FPGA_Chip
DC2in0 / FPGA_Chip
DC1out2_n / FPGA_Chip
DC1out2 / FPGA_Chip
DC1out1_n / FPGA_Chip
DC1out1 / FPGA_Chip
DC1out0_n / FPGA_Chip
DC1out0 / FPGA_Chip
DC1in3_n / FPGA_Chip
DC1in3 / FPGA_Chip
DC1in2_n / FPGA_Chip
DC1in2 / FPGA_Chip
DC1in1_n / FPGA_Chip
DC1in1 / FPGA_Chip
DC1in0_n / FPGA_Chip
DC1in0 / FPGA_Chip
DC0out2_n / FPGA_Chip
DC0out2 / FPGA_Chip
DC0out1_n / FPGA_Chip
DC0out1 / FPGA_Chip
DC0out0_n / FPGA_Chip
DC0out0 / FPGA_Chip
DC0in3_n / FPGA_Chip
DC0in3 / FPGA_Chip
DC0in2_n / FPGA_Chip
DC0in2 / FPGA_Chip
DC0in1_n / FPGA_Chip
DC0in1 / FPGA_Chip
DC0in0_n / FPGA_Chip
DC0in0 / FPGA_Chip
CONF_DONE / FPGA_Chip
CLOCKIN_n / FPGA_Chip
CLOCKIN / FPGA_Chip
DC3in0 : BI T3 : BI#
DC2out2_n : ... H4 : BI#
DC2out2 : BI H5 : BI#
DC2out1_n : ... J3 : BI#
DC2out1 : BI J4 : BI#
DC2out0_n : ... J7 : BI#
DC2out0 : BI H7 : BI#
DC2in3_n : BI W22 : BI#
DC2in3 : BI Y22 : BI#
DC2in2_n : BI AB19 : B...
DC2in2 : BI AB18 : B...
DC2in1_n : BI T21 : BI#
DC2in1 : BI T20 : BI#
DC2in0_n : BI AA22 : B...
DC2in0 : BI AA21 : B...
DC1out2_n : ... G6 : BI#
DC1out2 : BI F7 : BI#
DC1out1_n : ... G8 : BI#
DC1out1 : BI F8 : BI#
DC1out0_n : ... J6 : BI#
DC1out0 : BI H6 : BI#
DC1in3_n : BI V22 : BI#
DC1in3 : BI V21 : BI#
DC1in2_n : BI AB21 : B...
DC1in2 : BI AB20 : B...
DC1in1_n : BI T22 : BI#
DC1in1 : BI U22 : BI#
DC1in0_n : BI W21 : BI#
DC1in0 : BI W20 : BI#
DC0out2_n : ... C4 : BI#
DC0out2 : BI B4 : BI#
DC0out1_n : ... E4 : BI#
DC0out1 : BI E5 : BI#
DC0out0_n : ... F3 : BI#
DC0out0 : BI F4 : BI#
DC0in3_n : BI R3 : BI#
DC0in3 : BI R4 : BI#
DC0in2_n : BI P1 : BI#
DC0in2 : BI P2 : BI#
DC0in1_n : BI Y1 : BI#
DC0in1 : BI Y2 : BI#
DC0in0_n : BI U1 : BI#
DC0in0 : BI U2 : BI#
CONF_DONE : ...V18 : BI#
CLOCKIN_n : ... AB13 : B...
CLOCKIN : BI AA13 : B...
-
FPGA_Chip $783I1ep3s50.1
ASDO / FPGA_Chip
altera_reserved_tms / FPGA_Chip
altera_reserved_tdo / FPGA_Chip
altera_reserved_tdi / FPGA_Chip
altera_reserved_tck / FPGA_Chip
altera_reserved_ntrst / FPGA_Chip
ALTERA_DATA7 / FPGA_Chip
ALTERA_DATA6 / FPGA_Chip
ALTERA_DATA5 / FPGA_Chip
ALTERA_DATA4 / FPGA_Chip
ALTERA_DATA3T / FPGA_Chip
ALTERA_DATA2 / FPGA_Chip
ALTERA_DATA1 / FPGA_Chip
ALTERA_DATA0 / FPGA_Chip
ASDO : BI Y3 : BI#
altera_reserved_tms : ...D17 : BI#
altera_reserved_tdo : ...A18 : BI#
altera_reserved_tdi : ...E17 : BI#
altera_reserved_tck : ...D18 : BI#
altera_reserved_ntrst : ...F18 : BI#
ALTERA_DATA7 : ...J20 : BI#
ALTERA_DATA6 : ...J21 : BI#
ALTERA_DATA5 : ...J16 : BI#
ALTERA_DATA4 : ...H17 : BI#
ALTERA_DATA3T : ...K19 : BI#
ALTERA_DATA2 : ...K20 : BI#
ALTERA_DATA1 : ...J17 : BI#
ALTERA_DATA0 : ...J18 : BI#
psec_cc Sheet 1block_fpga Sheet 1block_fpga Sheet 2FPGA_Chip
Table
dc_conn Sheet 1Power_block Sheet 1usb Sheet 1dc_conn Sheet
1ethernetblock Sheet 1systemconn Sheet 1
