+ All Categories
Home > Documents > Boolean Algebra and Logic Gates - KFUPM...Boolean Algebra- Formal Definitions deals with binary...

Boolean Algebra and Logic Gates - KFUPM...Boolean Algebra- Formal Definitions deals with binary...

Date post: 14-Feb-2021
Category:
Upload: others
View: 13 times
Download: 3 times
Share this document with a friend
74
Boolean Algebra and Logic Gates COE 202 Digital Logic Design Dr. Abdulaziz Tabbakh College of Computer Sciences and Engineering King Fahd University of Petroleum and Minerals
Transcript
  • Boolean Algebra and Logic Gates

    COE 202

    Digital Logic Design

    Dr. Abdulaziz Tabbakh

    College of Computer Sciences and Engineering

    King Fahd University of Petroleum and Minerals

  • EE 200– Digital Logic Circuit Design – KFUPM slide 2

    Outline

    Binary Logic and Gates.

    Definition of Boolean Algebra

    Axioms, Theorems and Properties of Boolean Algebra

    Boolean Functions

    Algebraic Manipulation

    Canonical & Standard Forms

    Minterms, Maxterms, SOP, POS.

    Two-Level implementation

    Physical Properties of Logic Gates:

    Fan-in and Fan-out, Propagation delay, Cost.

  • EE 200– Digital Logic Circuit Design – KFUPM slide 3

    Introduction Our objective is to learn how to design digital circuits.

    These circuits use binary systems.

    Signals in such binary systems may represent only one of 2 possible

    values 0 or 1.

    Physically, these signals are electrical voltage signals

    These signals may assume either a high or a Low voltage value.

    The High voltage value typically equals the voltage of the power

    supply (e.g. 5 volts or 3.3 volts), and the Low voltage value is

    typically 0 volts (or Ground).

    When a signal is at the High voltage value, we say that the signal

    has a Logic 1 value.

    When a signal is at the Low voltage value, we say that the signal

    has a Logic 0 value.

  • EE 200– Digital Logic Circuit Design – KFUPM slide 4

    Digital Circuits

    Generally, the circuit will have a number of input signals

    (say n of them) as x1, x2, up to xn, and a number of

    output signals (say m ) Z1, Z2, up to Zm.

    The value assumed by the ith output signal Zi depends

    on the values of the input signals x1, x2, up to xn.

    In other words, we can say that Zi is a function of the n

    input signals x1, x2, up to xn. Or we can write:

    Zi = Fi (x1, x2, ……, xn ) for i = 1, 2, 3, ….m

    The m output functions (Fi) are functions of binary

    signals and each produces a single binary output signal.

    Thus, these functions are binary functions and require

    binary logic algebra for their derivation and manipulation.

  • EE 200– Digital Logic Circuit Design – KFUPM slide 5

    Boolean Algebra

    This binary system algebra is commonly referred to as

    Boolean Algebra after the mathematician George Boole.

    The functions are known as Boolean functions while the

    binary signals are represented by Boolean variables.

    To be able to design a digital circuit, we must learn how

    to derive the Boolean function implemented by this

    circuit.

    Systems manipulating Binary Logic Signals are

    commonly referred to as Binary Logic systems.

    Digital circuits implementing a particular Binary

    (Boolean) function are commonly known as Logic

    Circuits.

  • EE 200– Digital Logic Circuit Design – KFUPM slide 6

    Binary Logic

    Binary logic deals with variables (also called literals)

    that can takes one of two possible values (1 = True, 0 =

    False) and operations that assume logical meaning.

    A literal is a binary variable or its complement

    Binary Logic is also called (Boolean Algebra)

    Binary Logic consists of binary variables and logical

    operations

    Variables can be designated by letters (A, B, C, x, y, z)

    with two possible values (1,0).

    Three basic logical operators: AND, OR, NOT

    They form logic functions

  • EE 200– Digital Logic Circuit Design – KFUPM slide 7

    Binary Logic

    Binary logic should not be confused with binary arithmetic

    Arithmetic: 1+1=10 (one plus one equals two)

    Logic: 1+1=1 (one or one equals one)

    Truth Table is a table of all possible combinations of the

    variables, showing the relation between the values the

    variables may take and the result.

  • EE 200– Digital Logic Circuit Design – KFUPM slide 8

    Elements of Boolean Algebra (Binary Logic)

    As in standard algebra, Boolean algebra has 3 main

    elements:

    1. Constants,

    2. Variables, and

    3. Operators.

    Logically

    Constant Values are either 0 or 1

    Binary Variables ∈{ 0, 1}

    3 Possible Operators: The AND operator, the OR operator, and

    the NOT operator.

  • EE 200– Digital Logic Circuit Design – KFUPM slide 9

    Elements of Boolean Algebra (Binary Logic)

    Physically

    Constants ⇒

    Power Supply Voltage (Logic 1)

    Ground Voltage (Logic 0)

    Variables ⇒ Signals (High = 1, Low = 0)

    Operators ⇒ Electronic Devices (Logic Gates)

    1. AND - Gate

    2. OR - Gate

    3. NOT - Gate (Inverter)

  • EE 200– Digital Logic Circuit Design – KFUPM slide 10

    Logic Gates

    Logic gates: Circuits that implement logic functions

    Boolean Algebra: a useful mathematical system for

    specifying and transforming logic functions

    We will study Boolean algebra as a foundation for

    designing and analyzing digital systems

    The three basic logical operations are:

    AND is denoted by a dot (·)

    OR is denoted by a plus (+)

    NOT is denoted by an overbar ( ¯ ), a single quote mark (') after,

    or (~ or #) before the literal, e.g. A, A’, ~A, or #A

    yAB

    Logic

    CircuitC

    Input literals Output literal

  • EE 200– Digital Logic Circuit Design – KFUPM slide 11

    AND Operator

    Represented as:

    𝑥. 𝑦 = 𝑧 𝑜𝑟 𝑥𝑦 = 𝑧

    read as “X and Y equals to Z”

    Z=1 if and only if x=1 and y=1

  • EE 200– Digital Logic Circuit Design – KFUPM slide 12

    OR Operator

    Represented as:

    𝑥 + 𝑦 = 𝑧

    read as “X or Y equals to Z”

    Z=1 if x=1 or y=1 or if both x=1 and y=1

  • EE 200– Digital Logic Circuit Design – KFUPM slide 13

    NOT Operator

    Represented as:

    ҧ𝑥 = 𝑧 𝑜𝑟 𝑥′ = 𝑧

    read as “Not X equals to Z” meaning z is not what x

    Also called Negation or complementing

    Z=1 if X=0 and Z=1 if X=0

  • EE 200– Digital Logic Circuit Design – KFUPM slide 14

    Logic Gates

    Logic gates are electronic circuits that operates on one

    or more input signals to produce an output signal.

    In today’s computers,

    Switches are implemented

    using transistors, e.g. 0 = Low Voltage, e.g. 0 V

    1 = High Voltage, e.g. 3 V

  • EE 200– Digital Logic Circuit Design – KFUPM slide 15

    Boolean Algebra- Formal Definitions

    deals with binary literals and logic functions

    A Boolean Expression (e.g. X+YZ) in Boolean Algebra is formed by:

    Binary literals and constants (0,1)

    Logic operations (operators) on the literals and constants

    Parenthesis

    A Boolean Function can be described by :

    Boolean Equation: Output = Boolean Expression (not unique)

    Logic Diagram (gates)(not unique)

    Truth Table (unique) maps each possible combination of the input

    literals to the corresponding output literal (n input literals 2n

    combinations)

    Simplest functions require the smallest number of the smallest gates

    and therefore are most economical to implement

  • EE 200– Digital Logic Circuit Design – KFUPM slide 16

    Logic Circuits and Boolean Expressions

    A Boolean expression (or a Boolean function) is a

    combination of Boolean variables, AND-operators, OR-

    operators, and NOT operators.

    Boolean Expressions (Functions) are fully defined by

    their truth tables.

    Each Boolean function (expression) can be implemented

    by a digital logic circuit which consists of logic gates.

    Variables of the function correspond to signals in the logic

    circuit,

    Operators of the function are converted into corresponding logic

    gates in the logic circuit.

  • EE 200– Digital Logic Circuit Design – KFUPM slide 17

    Basic Theorem

    Existence

    Exist. of comp

    Idempotence

    Existence

  • EE 200– Digital Logic Circuit Design – KFUPM slide 18

    Theorem and Properties

    1. Duality:

    Duality principle states that every algebraic expression remains

    valid if the operators and identity elements are interchanged

    (i.e. replacing each 1 with a 0, each 0 with a 1, and replacing

    each AND (.) with an OR (+), and each OR (+) with an AND(.)).

    e.g. (X+Y+Z) and X.Y.Z (are Duals)

    x+1=1 and x.0=0 (are Duals)

    a·(b+c)=(a·b)+(a·c) and a+(b·c)=(a+b)·(a+c) (are Duals)

    The dual of an expression does not equal the expression itself

    unless the dual expression is the same as the original expressions.

    E.g x’’=x (called self-dual)

  • EE 200– Digital Logic Circuit Design – KFUPM slide 19

    Duality Principle

    Given a Boolean expression,

    its dual is obtained by

    replacing each 1 with a 0, each 0

    with a 1,

    each AND (.) with an OR (+), and

    each OR (+) with an AND(.).

    The dual of an identity is also

    an identity. This is known as

    the duality principle.

    It can be easily shown that the

    AND basic identities and the

    OR basic identities are duals.

  • EE 200– Digital Logic Circuit Design – KFUPM slide 20

    Useful Theorems (in Dual forms)

    Expression Dual

    𝑥. 𝑦 + ҧ𝑥. 𝑦 = 𝑦 𝑥 + 𝑦 . ( ҧ𝑥 + 𝑦) = 𝑦 Minimization

    𝑥 + 𝑥. 𝑦 = 𝑥 𝑥. 𝑥 + 𝑦 = 𝑥 Absorption

    𝑥 + ҧ𝑥. 𝑦 = 𝑥 + 𝑦 𝑥. ( ҧ𝑥 + 𝑦) = 𝑥𝑦 Simplification

    𝑥. 𝑦 + ҧ𝑥. 𝑧 + 𝑦. 𝑧= 𝑥. 𝑦 + ҧ𝑥. 𝑧

    𝑥 + 𝑦 . ҧ𝑥 + 𝑧 . 𝑦 + 𝑧= 𝑥 + 𝑦 . ( ҧ𝑥 + 𝑧)

    Consensus

    𝑥 + 𝑦 = ҧ𝑥. ത𝑦 𝑥. 𝑦 = ҧ𝑥 + ത𝑦 DeMorgan’sTheroem

  • EE 200– Digital Logic Circuit Design – KFUPM slide 22

    Proof of Minimization

    Consider the LHS form

    x. y + തx. y = 𝑦(x + തx) = y

    𝑥. 𝑦 + ҧ𝑥. 𝑦 = 𝑦 𝑥 + 𝑦 . ( ҧ𝑥 + 𝑦) = 𝑦 Minimization

  • EE 200– Digital Logic Circuit Design – KFUPM slide 23

    Proof of Absorption

  • EE 200– Digital Logic Circuit Design – KFUPM slide 24

    Proof of Simplification

    Consider the LHS

    x + തx. y = (x + തx)(x + y)

    = 1. 𝑥 + 𝑦

    = (𝑥 + 𝑦)

    𝑥 + ҧ𝑥. 𝑦 = 𝑥 + 𝑦 𝑥. ( ҧ𝑥 + 𝑦) = 𝑥𝑦 Simplification

  • EE 200– Digital Logic Circuit Design – KFUPM slide 25

    Proof of Consensus

    Consider :

    𝑥𝑦 + 𝑥′𝑧 + 𝑦𝑧 = 𝑥𝑦 + 𝑥′𝑧 + 𝑦𝑧. 1

    = 𝑥𝑦 + 𝑥′𝑧 + 𝑦𝑧 𝑥 + 𝑥′

    = 𝑥𝑦 + 𝑥′𝑧 + 𝑥𝑦𝑧 + 𝑥′𝑦𝑧

    = 𝑥𝑦 1 + 𝑧 + 𝑥′𝑧 1 + 𝑦

    = 𝑥𝑦 + 𝑥′𝑧

    𝑥. 𝑦 + ҧ𝑥. 𝑧 + 𝑦. 𝑧= 𝑥. 𝑦 + ҧ𝑥. 𝑧

    𝑥 + 𝑦 . ҧ𝑥 + 𝑧 . 𝑦 + 𝑧= 𝑥 + 𝑦 . ( ҧ𝑥 + 𝑧)

    Consensus

  • EE 200– Digital Logic Circuit Design – KFUPM slide 26

    Proof of DeMorgan’s Law

  • EE 200– Digital Logic Circuit Design – KFUPM slide 27

    Properties, Postulates & Theorems of Boolean Algebra

    yx

  • EE 200– Digital Logic Circuit Design – KFUPM slide 28

    Operator Precedence

    Given the Boolean expression X.Y + W.Z the order of

    applying the operators will affect the final value of the

    expression.

  • EE 200– Digital Logic Circuit Design – KFUPM slide 29

    Operator Precedence

    For Boolean Algebra, the precedence rules for various

    operators are given below, in a decreasing order of

    priority:

    Parenthesis

    NOT Operator

    AND Operator

    OR Operator

  • EE 200– Digital Logic Circuit Design – KFUPM slide 30

    Boolean Functions

    A Boolean function is described by an algebraic

    expression that expresses the logical relationship

    between binary variables and consists of:

    Binary variables

    Constants (0,1)

    Logical operators

    The function can be evaluated to a specific value for

    given value of the Boolean variables.

    F = x + y’z

  • EE 200– Digital Logic Circuit Design – KFUPM slide 31

    Boolean Functions

    A Boolean function can be represented by:

    Truth Table. (2n rows)

    Circuit Diagram.

    Function of 3 input variables

    23 = 8 input combinations

    Truth table has 8 rows

    Table lists all possible

    combinations of the inputs

    and the corresponding output

  • EE 200– Digital Logic Circuit Design – KFUPM slide 32

    Boolean Functions Expression

    One truth table

    Multiple algebraic expressions multiple circuits.

    By manipulating a Boolean expression according to the

    rules of Boolean algebra, it is sometimes possible to

    obtain a simpler expression for the same function and

    thus reduce the number of gates in the circuit and the

    number of inputs to the gate.

    Designers are motivated to reduce the complexity and

    number of gates to reduce the cost of the circuit.

  • EE 200– Digital Logic Circuit Design – KFUPM slide 33

    Example

  • EE 200– Digital Logic Circuit Design – KFUPM slide 34

    Algebraic Manipulation

    A literal is a single variable within a term, in

    complemented or uncomplemented form

    Simplification means to contain the smallest number of

    literals

    Less literals and terms simpler circuit.

    Use theorem and axioms to simplify functions.

    e.g.

    F2 = x’y’z + x’yz + xy’

    = x’z(y’+y) + xy’

    = x’z(1) + xy’

    = x’z + xy’

  • EE 200– Digital Logic Circuit Design – KFUPM slide 35

    Examples

    𝑥 𝑥′ + 𝑦 = 𝑥𝑥′ + 𝑥𝑦 = 0 + 𝑥𝑦 = 𝑥𝑦

    𝑥 + 𝑥′𝑦 = 𝑥 + 𝑥′ 𝑥 + 𝑦 = 1. 𝑥 + 𝑦 = 𝑥 + 𝑦

    𝑥 + 𝑦 𝑥 + 𝑦′ = 𝑥 + 𝑥𝑦 + 𝑥𝑦′ + 𝑦𝑦′ = 𝑥 1 + 𝑦 + 𝑦′ = 𝑥

    𝑥𝑦 + 𝑥′𝑧 + 𝑦𝑧 = 𝑥𝑦 + 𝑥′𝑧 + 𝑦𝑧 𝑥 + 𝑥′

    = 𝑥𝑦 + 𝑥′𝑧 + 𝑥𝑦𝑧 + 𝑥′𝑦𝑧= 𝑥𝑦 1 + 𝑧 + 𝑥′𝑧 1 + 𝑦 = 𝑥𝑦 + 𝑥′𝑧

    𝑥 + 𝑦 𝑥′ + 𝑧 𝑦 + 𝑧 = (𝑥 + 𝑦)(𝑥′ + 𝑧)

  • EE 200– Digital Logic Circuit Design – KFUPM slide 36

    Algebraic Manipulation

    Example: Simplify the function

  • EE 200– Digital Logic Circuit Design – KFUPM slide 37

    Algebraic Manipulation

  • EE 200– Digital Logic Circuit Design – KFUPM slide 38

    Algebraic Manipulation

    Example: Simplify the function

  • EE 200– Digital Logic Circuit Design – KFUPM slide 39

    Complement of a Function The complement of a function can be derived algebraically using

    DeMorgan’s theorems for two or more variables

    (a+b+c+d)’ = a’b’c’d’

    (abcd)’ = a’+b’+c’+d’

    The generalized form of DeMorgan’s theorems states that the

    complement of a function is obtained by interchanging AND and

    OR operators and complementing each literal.

    Be careful with operators precedence!!! Start with the outermost

    operation; complement the operation and the operands, then the next

    outermost operation and so on

    The only difference between the dual of an expression and the

    complement of that expression is that

    in the dual variables are not complemented while in the complement

    expression, all variables are complemented.

  • EE 200– Digital Logic Circuit Design – KFUPM slide 40

    Example

    F=(x’yz’ + x’y’z)

    F’=(x’yz’ + x’y’z)’ = (x’yz’)’ (x’y’z)’

    = (x+y’+z)(x+y+z’)

    take the dual of the function and complement each literal

    Fdual = (x’+y+z’)(x’+y’+z)

    F’ = (x+y’+z)(x+y+z’)

    G = (a’ + bc)d’ + e

    G’ = [(a’ + bc)d+ e]’ = [(a + bc) . d’]’. e’

    = [(a’ + bc)’+ d’’]. e’

    = [a’’. (b.c)’ + d]. e’

    = [a. (b’+c’) + d]. e’

  • EE 200– Digital Logic Circuit Design – KFUPM slide 41

    Canonical and Standard Forms Minterms or standard products (AND operation)

    For a Boolean function of n variables, a product term (ANDedterm) in which each variable appears once (in either its true or complemented form) is called a minterm.

    There are 2n different Minterms.

    Maxterms or standard sums (OR operation)

    For a Boolean function of n variables, a sum term (ORed term) in which each variable appears once (in either its true or complemented form) is called a maxterm.

    There are 2n different maxterms

    Each maxterm is the complement of its corresponding minterm

    A term that is a minterm or a max term SHOULD INCLUDE ALL INPUT VARIABLES

  • EE 200– Digital Logic Circuit Design – KFUPM slide 42

    Minterms and Maxterms – variables order

    Minterms and maxterms are designated with a subscript

    The subscript is a decimal number that represents the

    binary number of input literals in the straight binary

    The bits in the pattern represent the complemented or

    normal state of each literal listed in a standard fixed

    order (MSB…LSB)

    All literals will be present in a minterm or maxterm and

    will be listed in the same order (usually alphabetically)

    Examples of Standard forms: For 3 variables: a, b, c

    Maxterms: (a+b’+c) = M010= M2, (a’+b+c’) = M101 =M5

    Minterms: abc’ = m110 = m6, a’b’c = m001 = m1

  • EE 200– Digital Logic Circuit Design – KFUPM slide 43

    Minterms Consider a system of 3 input signals (variables) x, y, & z.

    A term which ANDs all input variables, either in the true or

    complement form, is called a minterm.

    Thus, the considered 3-input system has 8 minterms, namely:

    Each minterm equals 1 at exactly one particular input combination

    and is equal to 0 at all other combinations

    Thus, for example, is always equal to 0 except for the input

    combination xyz = 000, where it is equal to 1.

    Accordingly, the minterm is referred to as m0.

    In general, minterms are designated mi, where i corresponds the

    input combination at which this minterm is equal to 1.

  • EE 200– Digital Logic Circuit Design – KFUPM slide 44

    Minterms

    For the 3-input system under consideration, the number

    of possible input combinations is 23, or 8. This means

    that the system has a total of 8 minterms as follows:

  • EE 200– Digital Logic Circuit Design – KFUPM slide 45

    Maxterms

    Consider a circuit of 3 input signals (variables) x, y, & z.

    A term which ORs all input variables, either in the true or

    complement form, is called a Maxterm.

    With 3-input variables, the system under consideration

    has a total of 8 Maxterms, namely:

    Each Maxterm equals 0 at exactly one of the 8 possible

    input combinations and is equal to 1 at all other

    combinations.

    For example, (x + y + z) equals 1 at all input combinations

    except for the combination xyz = 000, where it is equal to 0.

    Accordingly, the Maxterm (x + y + z) is referred to as M0.

  • EE 200– Digital Logic Circuit Design – KFUPM slide 46

    Maxterms

    In general, Maxterms are designated Mi, where i

    corresponds to the input combination at which this

    Maxterm is equal to 0.

    For the 3-input system, the number of possible input

    combinations is 23, or 8. This means that the system has

    a total of 8 Maxterms as follows:

  • EE 200– Digital Logic Circuit Design – KFUPM slide 47

    Minterms and Maxterms

    mi

    AND that gives 1

    Mi

    OR that gives 0The Index represents

    the Input combination

    in decimalNote: mi is the complement of Mi and vice versa

    A product that gives 1 A sum that gives 0Input Combination

  • EE 200– Digital Logic Circuit Design – KFUPM slide 48

    Miterms and Maxterms

    A Boolean function can be expressed algebraically from

    a given truth table by forming a minterm for each

    variable combination that produce a ‘1’ in the output, and

    then ORing them together. (Sum Of Products) (SOP)

    Similarly, we can express the function by forming a

    maxterm for each variable combination that produce a ‘0’

    in the output, and then ANDing them together. (Product

    Of Sums) (POS).

    A function is said to be in Canonical form if it is

    represented as a SOMinterms or POMaxterms.

  • EE 200– Digital Logic Circuit Design – KFUPM slide 49

    Example

    𝑓1(𝑥, 𝑦, 𝑧) = 𝑥′𝑦′𝑧 + 𝑥𝑦′𝑧′ + 𝑥𝑦𝑧 = 𝑚1 +𝑚4 +𝑚7 =

    σ (1,4,7)

    𝑓2(𝑥, 𝑦, 𝑧) = 𝑥′𝑦𝑧 + 𝑥𝑦′𝑧 + 𝑥𝑦𝑧′ + 𝑥𝑦𝑧 = 𝑚3 +𝑚5 +𝑚6 +

    𝑚7 = σ (3,5,6,7)

  • EE 200– Digital Logic Circuit Design – KFUPM slide 50

    Example

    𝑓1(𝑥, 𝑦, 𝑧) = 𝑥′𝑦′𝑧 + 𝑥𝑦′𝑧′ + 𝑥𝑦𝑧 = 𝑚1 +𝑚4 +𝑚7 =

    σ (1,4,7)

    X Y Z i m1 + m4 + m7 f1

    0 0 0 0 0 + 0 + 0 0

    0 0 1 1 1 + 0 + 0 1

    0 1 0 2 0 + 0 + 0 0

    0 1 1 3 0 + 0 + 0 0

    1 0 0 4 0 + 1 + 0 1

    1 0 1 5 0 + 0 + 0 0

    1 1 0 6 0 + 0 + 0 0

    1 1 1 7 0 + 0 + 1 1

    Function is 1 at each of

    its specified minterms

    So, given a truth table,

    How to determine the

    function?

    As the sum of all

    minterms for which the

    function is 1 !….

  • EE 200– Digital Logic Circuit Design – KFUPM slide 51

    Example

    𝑓1(𝑥, 𝑦, 𝑧) = 𝑥′𝑦′𝑧 + 𝑥𝑦′𝑧′ + 𝑥𝑦𝑧 = 𝑚1 +𝑚4 +𝑚7 =

    σ (1,4,7)

    𝑓1(𝑥, 𝑦, 𝑧) = 𝑥 + 𝑦 + 𝑧 . 𝑥 + 𝑦′ + 𝑧 . 𝑥 + 𝑦′ + 𝑧′ . (𝑥′ +

    X Y Z i M0 . M2 . M3 . M5 . M6 f1

    0 0 0 0 0 . 1 . 1 . 1 . 1 0

    0 0 1 1 1 . 1 . 1 . 1 . 1 1

    0 1 0 2 1 . 0 . 1 . 1 . 1 0

    0 1 1 3 1 . 1 . 0 . 1 . 1 0

    1 0 0 4 1 . 1 . 1 . 1 . 1 1

    1 0 1 5 1 . 1 . 1 . 0 . 1 0

    1 1 0 6 1 . 1 . 1 . 1 . 0 0

    1 1 1 7 1 . 1 . 1 . 1 . 1 1

    Function is 0 at each of

    its specified maxterms

    So, given a truth table,

    How to determine the

    function?

    As the product of all

    maxterms for which the

    function is 0 !….

  • EE 200– Digital Logic Circuit Design – KFUPM slide 52

    Operations on Functions

    The AND operation on two functions corresponds to the

    intersection of the two sets of minterms of the functions

    The OR operation on two functions corresponds to the

    union of the two sets of minterms of the functions

    Example

    Let F(A,B,C)=Σm(1, 3, 6, 7) and G(A,B,C)=Σm(0,1, 2, 4,6, 7)

    F . G = Σm(1, 6, 7)

    F + G = Σm(0,1, 2, 3, 4,6, 7)

    F’ . G = ?

    F’ = Σm(0, 2, 4, 5)

    F’ . G = Σm(0, 2, 4)

  • EE 200– Digital Logic Circuit Design – KFUPM slide 53

    Minterms of Function Complement

    Forming a minterm for each combination that produces a

    0 in the function and then ORing them.

    𝑓1 = 𝑚1 +𝑚4 +𝑚7 ⇒ 𝑓′1 = 𝑚0 +𝑚2 +𝑚3 +𝑚5 +𝑚6𝑓′1 = 𝑥

    ′𝑦′𝑧′ + 𝑥′𝑦𝑧′ + 𝑥′𝑦𝑧 + 𝑥𝑦′𝑧 + 𝑥𝑦𝑧′

    Take the complement of f’1 to get f1

    𝑓1 = 𝑥 + 𝑦 + 𝑧 𝑥 + 𝑦′ + 𝑧 𝑥 + 𝑦′ + 𝑧′ 𝑥′ + 𝑦 + 𝑧′ 𝑥′ + 𝑦′ + 𝑧

    𝑓1 = 𝑀0𝑀2𝑀3𝑀5𝑀6 =ෑ(0,2,3,5,6)

    𝑓1 = 𝑥′𝑦′𝑧 + 𝑥𝑦′𝑧′ + 𝑥𝑦𝑧 = 𝑚1 +𝑚4 +𝑚7 =𝑚(1,4,7)

  • EE 200– Digital Logic Circuit Design – KFUPM slide 54

    Conversion to Minterm

    It is sometimes convenient to express a Boolean function

    in its sum of minterms (SOP) form.

    Expanding the expression into a sum of AND terms

    Inspect each term

    If it contains all the variables (good)

    If it misses one or more variables, it is ANDed with an

    expression such as (x + x’)

  • EE 200– Digital Logic Circuit Design – KFUPM slide 55

    Example

    Express the Boolean function 𝐹 = 𝐴 + 𝐵′𝐶 as a sum of minterms.

    The first term A is missing two variables

    𝐴 = 𝐴 𝐵 + 𝐵′ = 𝐴𝐵 + 𝐴𝐵′ = 𝐴𝐵 𝐶 + 𝐶′ + 𝐴𝐵′(𝐶 + 𝐶′)𝐴 = 𝐴𝐵𝐶 + 𝐴𝐵𝐶′ + 𝐴𝐵′𝐶 + 𝐴𝐵′𝐶′

    The second term B’C is missing one variables

    𝐵′𝐶 = 𝐵′𝐶 𝐴 + 𝐴′ = 𝐴𝐵′𝐶 + 𝐴′𝐵′𝐶

    Combine all terms

    𝐹 = 𝐴 + 𝐵′𝐶 = 𝐴𝐵𝐶 + 𝐴𝐵𝐶′ + 𝐴𝐵′𝐶 + 𝐴𝐵′𝐶′ + 𝐴′𝐵′𝐶𝐹 = 𝑚1 +𝑚4 +𝑚5 +𝑚6 +𝑚7

    𝐹(𝐴, 𝐵, 𝐶) =(1,4,5,6,7)

  • EE 200– Digital Logic Circuit Design – KFUPM slide 56

    Example

    An alternative procedure for deriving the minterms of a

    Boolean function is to obtain the truth table of the

    function directly from the algebraic expression and then

    read the minterms from the truth table.

    𝐹 = 𝐴 + 𝐵′𝐶𝐹 = 𝑚1 +𝑚4 +𝑚5 +𝑚6 +𝑚7

  • EE 200– Digital Logic Circuit Design – KFUPM slide 57

    Conversion to Maxterms

    Express it in form of OR terms (use distributive law)

    Any missing variable x in each term is ORed with xx’

    Express the Boolean function 𝐹 = 𝑥𝑦 + 𝑥’𝑧 as a product of maxterms.

    𝐹 = 𝑥𝑦 + 𝑥’𝑧 = (𝑥𝑦 + 𝑥’)(𝑥𝑦 + 𝑧)= (𝑥 + 𝑥’)(𝑦 + 𝑥’)(𝑥 + 𝑧)(𝑦 + 𝑧)= (𝑥’ + 𝑦)(𝑥 + 𝑧)(𝑦 + 𝑧)

    Each OR term is missing one variable.

    𝑥′ + 𝑦 = 𝑥’ + 𝑦 + 𝑧𝑧’ = (𝑥’ + 𝑦 + 𝑧)(𝑥’ + 𝑦 + 𝑧’)𝑥 + 𝑧 = 𝑥 + 𝑧 + 𝑦𝑦’ = (𝑥 + 𝑦 + 𝑧)(𝑥 + 𝑦’ + 𝑧)𝑦 + 𝑧 = 𝑦 + 𝑧 + 𝑥𝑥 = (𝑥 + 𝑦 + 𝑧)(𝑥’ + 𝑦 + 𝑧)

    Combine.

    𝐹 = 𝑥 + 𝑦 + 𝑧 𝑥 + 𝑦’ + 𝑧 𝑥’ + 𝑦 + 𝑧 𝑥’ + 𝑦 + 𝑧’ = 𝑀0𝑀2𝑀4𝑀5

    𝐹(𝑥, 𝑦, 𝑧) =ෑ(0,2,4,5)

  • EE 200– Digital Logic Circuit Design – KFUPM slide 58

    Conversion between Canonical Forms

    The minterms of F’ are the minterms missing from F

    𝐹 𝐴, 𝐵, 𝐶 = σ 1,4,5,6,7 ⇒ 𝐹’ 𝐴, 𝐵, 𝐶 = σ(0,2,3)

    Now, if we take the complement of F‘ by DeMorgan’s

    theorem:

    𝐹’ ’ = 𝐹 = 𝑚0+𝑚2+𝑚3 ’ = 𝑚0′ . 𝑚2

    ′ . 𝑚3′ = 𝑀0𝑀2𝑀3

    =ෑ(0,2,3)

    To convert from one canonical form to another,

    interchange the symbols ∑ and ∏ and list those numbers

    missing from the original form.

    Maxterm with subscript j is a complement of the Minterm with the

    same subscript j and vice versa.

  • EE 200– Digital Logic Circuit Design – KFUPM slide 59

    Conversion between Canonical Forms

    𝐹 =(1,3,6,7) =ෑ(0,2,4,5)

  • EE 200– Digital Logic Circuit Design – KFUPM slide 60

    Standard Form In Canonical forms, minterms and maxterms MUST contain

    all variables.

    In Standard forms, Sum of Products (SOP) and Product of Sums (POS) contain any number variables.

    𝐹 = (𝑥 + 𝑦 + 𝑧)(𝑥 + 𝑦’ + 𝑧)(𝑥’ + 𝑦 + 𝑧)(𝑥’ + 𝑦 + 𝑧’)𝐹 = 𝑥𝑦 + 𝑥’𝑧

    The sum of products is a Boolean expression containing

    AND terms, called product terms, with one or more literals

    each. The sum denotes the ORing of these terms.

    A product of sums is a Boolean expression containing OR

    terms, called sum terms. Each term may have any number

    of literals. The product denotes the ANDing of these terms.

  • EE 200– Digital Logic Circuit Design – KFUPM slide 61

    Standard Forms

    These standard forms results in a two‐level structure of gates.

    𝐹1 = 𝑦’ + 𝑥𝑦 + 𝑥’𝑦𝑧’ 𝐹2 = 𝑥(𝑦’ + 𝑧)(𝑥’ + 𝑦 + 𝑧)

  • EE 200– Digital Logic Circuit Design – KFUPM slide 62

    Standard vs. Non-Standard Form

    a two‐level implementation is

    preferred :

    it produces the least

    amount of delay through

    the gates

    However, the number of

    inputs to a given gate

    might not be practical.

  • EE 200– Digital Logic Circuit Design – KFUPM slide 63

    Two-Level Implementations of Standard Forms

    Sum of Products Expressions (SOP):

    Any SOP expression can be implemented in 2-levels of

    gates.

    The first level consists of a number of AND gates which

    equals the number of product terms in the expression.

    Each AND gate implements one of the product terms in

    the expression.

    The second level consists of a SINGLE OR gate whose

    number of inputs equals the number of product terms in

    the expression.

  • EE 200– Digital Logic Circuit Design – KFUPM slide 64

    Two-Level Implementations of Standard Forms

    Example: Implement the following SOP function

    F = XZ + Y`Z + X`YZ

  • EE 200– Digital Logic Circuit Design – KFUPM slide 65

    Two-Level Implementations of Standard Forms

    Product of Sums Expression (POS):

    Any POS expression can be implemented in 2-levels of

    gates.

    The first level consists of a number of OR gates which

    equals the number of sum terms in the expression.

    Each gate implements one of the sum terms in the

    expression.

    The second level consists of a SINGLE AND gate whose

    number of inputs equals the number of sum terms.

  • EE 200– Digital Logic Circuit Design – KFUPM slide 66

    Two-Level Implementations of Standard Forms

    Example: Implement the following POS function

    F = (X+Z )(Y`+Z)(X`+Y+Z )

  • EE 200– Digital Logic Circuit Design – KFUPM slide 68

    VLSI Technology Parameters Propagation Delay : The time required for a change in the value of

    a signal to propagate from an input to an output

    Fan-out: number of standard loads a gate output can drive

    Fan-in: the number of inputs available on a gate. Usually limited by

    speed considerations to 4-5 inputs. Larger input gates are

    implemented from a multiple of such smaller gates

    Cost of a gate: a measure of the contribution by the gate to the cost

    of the integrated circuit (its area)

    Power Dissipation: the amount of power drawn from the power

    supply and consumed by the gate

    Noise Margin: the maximum external noise voltage that will not

    cause an undesirable change in the logic output of a gate output

    when superimposed on a normal input level

  • EE 200– Digital Logic Circuit Design – KFUPM slide 69

    Propagation Delay

    Consider the shown inverter with

    input X and output Z.

    A change in the input (X) from 0 to

    1 causes the inverter output (Z) to

    change from 1 to 0.

    The change in the output (Z),

    however is not instantaneous.

    Rather, it occurs slightly after the

    input change.

    This delay between an input signal

    change and the corresponding

    output signal change is what is

    known as the propagation delay.

  • EE 200– Digital Logic Circuit Design – KFUPM slide 70

    Propagation Delay

    A signal change on the input of some IC takes a finite

    amount of time to cause a corresponding change on the

    output.

    This finite delay time is known as Propagation Delay.

    Faster circuits are characterized by smaller propagation

    delays.

    Higher performance systems require higher speeds

    (smaller propagation delays).

  • EE 200– Digital Logic Circuit Design – KFUPM slide 71

    Timing Diagrams

    A timing diagram shows the logic values of signals in a

    circuit versus time.

    A signal shape versus time is typically referred to as

    Waveform.

    Example:

  • EE 200– Digital Logic Circuit Design – KFUPM slide 72

    Computing Longest Delay

    Each gate has a given propagation delay.

    We start at the inputs and compute the delay at the

    output of each gate as follows:

    The delay at the output of a gate = gate propagation delay +

    maximum delay at its inputs

    Maximum propagation delay from any input to any output

    is called the Critical Path.

    The critical path determines the minimum clock period

    (T) and the maximum clock frequency (f).

    Clock frequency (f) = 1 / T

  • EE 200– Digital Logic Circuit Design – KFUPM slide 73

    Computing Longest Delay

    Example: Assume that delay of each gate is related to

    number of its inputs i.e. delay of 1 input gate is 1 ns,

    delay of 2-input gate is 2 ns. Compute longest

    propagation delay and maximum frequency.

    Longest propagation delay = 7 ns

    Maximum frequency = 1 / 7ns= 143 MHZ.

  • EE 200– Digital Logic Circuit Design – KFUPM slide 78

    Exercises

  • EE 200– Digital Logic Circuit Design – KFUPM slide 79

    Exercises

  • EE 200– Digital Logic Circuit Design – KFUPM slide 80

    Exercises


Recommended