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Boosting: Min-Cut Placement with Improved Signal Delay
Andrew B. Kahng Sherief RedaCSE & ECE Departments
University of CA, San DiegoLa Jolla, CA [email protected]
CSE DepartmentUniversity of CA, San Diego
La Jolla, CA [email protected]
Igor L. MarkovEECS Department
University of MichiganAnn Arbor, MI 48109
VLSI CAD Laboratory at UCSD
Outline
Introduction and motivation
Controlling wirelength distribution
Boosting min-cut placement Effect of boosting on cut values
Experimental results Conclusions
Introduction: Min-Cut Placement
Min-cut objective: minimize cut partitions → minimizes total wirelength with the help of terminal propagation Min-cut partitioning produces slicing outlines
Introduction: Min-Cut Placement
Min-cut partitioning produces slicing outlines
Min-cut objective: minimize cut partitions → minimizes total wirelength with the help of terminal propagation
Min-cut placers
Motivation: Avoiding Global Interconnects
severely increase propagation delay since delay is proportional to square of the wirelength
take part of critical paths and degrade performance
require buffering for electrical sanity
have a propagation delay that is equivalent to several clock cycles
Conclusion: try to prevent global interconnects
Sequentially minimize wirelength, i.e., the routing demand Do not treat global interconnects in any special way
Global interconnects can
Case A
Case B
Cases A and B: same wirelength & number of cuts Case B: no global interconnects (cf. Case A)
Motivation: Example
Outline
Introduction and motivation
Controlling wirelength distribution
Boosting min-cut placement Effect of boosting on cut values
Experimental results Conclusions
Bounds on Net Length A net’s HPWL (Half Perimeter Wirelength) is bounded
from below by distances between closest points of incident partitions from above by distances between furthest points of incident partitions
These bounds are gradually refined during top-down placement
at the beginning lower bounds are ~0s, upper bounds are determined by placement region at the end, the bounds are close to (or match) HPWL
Upper bound = ¾ chip width Lower bound = ¼ chip width
Net L
Dichotomy of Lower and Upper bounds
Net L
Net L
Upper bound reduces; lower bound stays the same
Net L
Upper bound stays the same; lower bound increases
Net Extension Control
Partitioning a block extends a net L if the next two equivalent conditions occur:
(1) Cutting L increases the lower bound on its length
(2) Not cutting L decreases the upper bound on its length
Or equivalently
We use the previous conditions to detect net extension and attempt to curb it via boosting
Boosting Min-Cut Placement
Boosting = multiplying a hyperedge (net) weight by a factorboosting factor
Boosting is used only when a cut can increase a lower bound
L
Boost net L with a boosting factor of 2
L
BOOST? YES
To Boost or Not to Boost?
BOOST?
BOOST?BOOST? YES NO
NO
Effect of Boosting on Cut Value
v
u
v is connected to a net eligible for boosting, u is not either can be moved to the right
Boosting factor is 2: the gain of v grows from 1 to 2
Tie is broken by moving v → no degradation in wirelength, and a global wire is avoided
Case 1
Effect of Boosting on Cut Value
v
u
v is connected to several nets eligible for boosting, u is not
Boosting factor is 2 on each net: v’s gain grows from 3 to 6
v has a higher priority → no degradation in wirelength and a global interconnect is eliminated
Case 2
Effect of Boosting on Cut Value
v
u
v is connected to 2 nets eligible for boosting
Boosting factor is 2 gain for v increases (from 2 to 4); gain for u is the same (3)
v is moved → wirelength is degraded but global wires are prevented
Case 3
Summary
Boosting helps in eliminating global interconnects
Boosting may degrade wirelength in some cases
To reduce wirelength degradation, we only boost during first 8 levels That is where long wires are determined anyway
At the 8th placement level: → The average block perimeter is 1/256 of the original chip perimeter → Global interconnects are already established → No point in further boosting
Outline
Introduction and motivation
Controlling wirelength distribution
Boosting min-cut placement Effect of boosting on cut values
Experimental results Conclusions
Experimental Setup
Benchmark Cells Nets Core region Whitespace Metal layers
Clock period
A 21103 21230 2142x1969 13.5% 4 9.456
B 33917 39153 23157x12732 49.8% 4 30.962
C 9585 10398 8705x86968 29.7% 5 37.515
Three industrial benchmarks
Two experiments:
Effect of boosting on the wirelength distribution
Effect of boosting on timing
Experimental Results: Wirelength Histogram (Design A)
-40
-30
-20
-10
0
10
20
1 2 3 4 5 6 7
Percentage change in number of nets (%)
Bins (in terms of half the chip’s perimeter)
Boosting substantially reduces global interconnects
Experimental Results: Wirelength Histogram (Design B)
-100
-80
-60
-40
-20
0
20
1 2 3 4 5 6 7 8
Percentage change in number of nets (%)
Bins (in terms of half the chip’s perimeter)
Boosting substantially reduces global interconnects
Experimental Results: Timing
benchmark Flow Wirelength Slack (ns) TNS (ns)
Tool Mode
A Indust NTD 3491503 -0.660 28.107
TD 3570024 -0.368 12.022
Capo Regular 3335483 -0.607 23.360
Boost 3260184 -0.342 5.107
B Indust NTD 9080259 -31.793 68253.5
TD 9100552 -31.750 56618.6
Capo Regular 8375939 -29.595 44951.8
Boost 8711281 -25.757 49627.6
C Indust NTD 839408 -1.882 1870.3
TD 841585 -1.878 1750.8
Capo Regular 835962 -1.875 1810.6
boost 872089 -1.878 1799.5
Conclusions and Future work
By tracking lower/upper bounds, we identify potential long wires
By additionally increasing net weights, we decrease # of long wires
This alters wirelength distribution and reduces global interconnects Routability is slightly affected, but generally preserved
Boosting tends to improve circuit delay (timing) measured by the worst slack and total negative slack (TNS)
Ongoing work examines the impact of boosting on the number of inserted buffers
Thank you for your attention