Bourns Voiceport Protection Apno

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Protecting Legerity Subscriber Line Interface Circuits

(SLICs) with Bourns TISP Protector ProductsVersion 1

Written by im Ardley, Sr. elecom Field Applications EngineerJune 2006

Circuit Protection Solutions


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Objective

Tis engineering note provides a frst principles theory and protection solutions when designing telecomcircuit protection with Legeritys subscriber line interace circuits (SLICs). Protection against lightningdisturbances is a key concern or increased reliability o the equipment and telecom standards conormance.Tis document should be used in conjunction with the SLIC data sheet and application notes to providecorrect overvoltage interace to the SLIC.

SLICs covered in this document are intended to be protected with a battery tracking gated thyristor solutionand covers trademark names such as the VoiceEdge and VoicePort product amilies.

Note: Te high voltage ISP61089BD is discussed in this application note, but the design considerations discussedmay also be used in other voltage options in the amily.

Introduction to Legerity SLICs

VE880 series VoicePortLegeritys tracking battery VoicePort VE880 series devices provide a highly unctional line interace whichmeets the requirements o short and medium loop (up to 1500 ohms total) applications. Te VE880 seriesintegrates the CODEC and SLIC into a s ingle package to provide direct interace into a digital backplane (PMI/PCM or GCI) solution. Te VE880 series also includes a high voltage switching regulator, sel-test, line testcapabilities, integrated ringing (up to 140-Vpk), soware programmability and a exible signal generator withtone cadencing, caller ID generation and all BORSCH unctions or worldwide solutions.

VE790 series VoiceEdgeTe VoiceEdge VE790 series includes quad and octal CODES and dual SLICs which when combined with

the Bourns protectors provide a complete soware confguration to BORSCH unctions. Te VE790series also provides complete programmable control over subscriber line DC-eed characteristics such ascurrent limit and DC template. Tese chips provide a programmable solution satisying worldwide line cardsolutions by soware confguration. Te VE790 solutions include ull GR844 compatible integrated linetesting, programmable AC, DC and supervision parameters. Te VE790 series oers integrated ringing up to145 V peak or may also be used with external ringing confgurations. Te amily also provides exible signalgeneration with tone cadencing, caller ID and ull worldwide programmability.


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Graph 1 Peak AC vs. current duration o the ISP61089BD andline eed resistor

AC power contact calculationsTe circuit protection components are also subjectedto AC tests to simulate power contact and inductionconditions. Tere could be a ault condition whereAC mains voltages are accidentally connected acrossthe equipment terminals. Both the overvoltage andovercurrent components need to support the short

circuit current tests. Te gated Bourns ISP thyristoramily specifes the peak non-recurring AC currentvs. duration to aid correct design. Te ISP61089BDabsolute maximum peak rating is 4.6 A or 1 second or0.73 A or 900 seconds (900 seconds can be consideredcontinuous) using the EIA/ JESD51 environment andPCB layout (minimum copper and line interconnect) orthe test.

elecom overcurrent resistance is normally limitedto 50 or less and thereore the additional series

resistance in series with the AC generator resistancedoes not signifcantly impact the short circuit currentlevels through the Bourns ISP device. Te importantparameter is the time the overcurrent protector requiresto operate. GR-1089-CORE second level AC power ault and UL 60950 allow the overcurrent protector tooperate as a series use clearing to protect the circuit. Te circuit protection solution needs to ensure theovercurrent protector will operate beore the Bourns ISP device ails. o ensure this, the maximum currentvs. time o the protectors needs to be known. Plotting both curves on the same graph will highlight i theprotection components are suitable or each other. Te Bourns ISP device curve should ideally be abovethe overcurrent protector curve as shown in Graph 1. I this is not the case, the thyristor could ail beore the

overcurrent protector operates.

GR-1089-CORE also specifes frst level AC tests where the equipment must work as intended aer the test.Tereore, the overcurrent protector must not operate or return to its original state under these tests. Graph 1also shows the frst level test criteria where the use characteristic should also be to the right o this curve toensure conormance.


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Limiting protection overshootsTe impulse breakover voltage specifcation o the thyristor is dependent on the di/dt o the impulse waveorm.Bourns specifes a maximum gate-cathode impulse breakover voltage, VGK(BO) to reect situations underindustry-standard waveorms. Te QGS o the gated thyristor also contributes to the overshoot value and isdiscussed in the gate decoupling capacitor section on page 8.

For example, the ISP61089BD is specifed with a VGK(BO) o 12 V maximum with a 100 A 2/10 s impulse.

Tis has been tested with a VGG (gate-ground) o 100 V. Tis specifcation rom the data sheet cannot bedirectly tied into the maximum terminal ratings o the SLIC since the length o time during the 12 V ooverstress is not known.

Graph 2 shows the impulse breakovervoltage o the ISP61089BD versus time. Teimpulse is 9 V above the battery voltage witha duration o 100 ns or the ISP61089BDwith 100 A 2/10 s at 25 C. Tis protection iswithin the 250 ns, 15 V window specifed orthe SLIC.

Note: Te overshoot o the thyristor is especially important when the SLIC is being operated close to its maximum

supply voltage ratings.

Increasing the line series resistor value has the eect o reducing the peak current into the thyristor andthereore the di/dt o the transient. A single blow use such as a Bourns B0500 eleuse elecom use haslow cold resistance value o 0.35 . Tis provides ast di/dt conditions or the thyristor.

I increasing the line series resistance stops SLIC ailure, the other area to consider is the ground connectionbetween AGND and BGND and between the protector and the SLIC. Tis is discussed in Groundingtechniques on page 10.

Graph 2 Measured overshoot o ISP61089 gated thyristor


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Overshoot o the dual voltage TISP820xMD gated thyristorsTe ISP8200MD and ISP8201MD dual voltage protectors are specifed with a maximum impulse breakovervoltage o 15 V under the 100 A 2/10 s impulse. Te typical overshoot impulse waveorms are shown inGraph 3. Tese can be used with the maximum voltage ratings o the SLIC to ensure suitable protection. Teovershoot is also important when the overvoltage protection is operated close to the thyristor maximum VRRM(repetitive peak reverse voltage) value. With an absolute maximum rating o 120 V, and 15 V o additionalheadroom to accommodate overshoot and variations with temperature operation, the maximum gate battery

voltage should not exceed 100 V on these devices.

Note: Te integrated positive and negative ISP9110LDM has the same overshoot characteristics as theISP820xMD series and thereore share the same design considerations.

Graph 3 ISP820xMD overshoot characteristics

Te Le79252 dual voltage ringing SLIC has an absolute maximum VBP (positive battery) o +110 V and VBH(high battery supply) o 150 V with respect to AGND (analog ground or VCC return). At frst glance, itappears that the ISP820xMD with a recommended maximum battery voltage o 100 V would be unsuitable.However, the key parameter is the absolute maximum voltage rating between VBP with respect to VBH. Tis isspecifed to be +160 V and highlights the maximum voltage dierential or the SLIC. It is common to see VBPo +100 V and VBH o 48 V to keep the maximum dierential voltage below 150 V.

Te Le79252 specifes an envelope on its impulse ratings with respect to VBH and VBP. From Graph 3, it canbe seen that the overshoot does not exceed 10 V and is within the 15 V or 250 ns and 10 V or the 1 s

requirement. It can also be seen that the 5 V stress occurs in less than 350 ns providing excellent protectionor this SLIC under the ast 100 A 2/10 s impulse.


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Gate decoupling capacitorsBourns gated thyristor data sheets recommend a typical gate decoupling capacitor o 220 nF, but a minimumvalue o 100 nF may also be considered in the design. Tis capacitor is needed to ensure correct operationo the protector. During the initial rise o an impulse voltage, the gate current (IG) is positive duringapproximately the frst 20 % o the IK switch time as current is reected into the gate rom the cathode. Te

SCR gate then requires a negative drive current to switchthe SCR into a low impedance condition. Tis equates into

a positive and negative gate charge QGS requirement. Terequired gate charge is supported with this capacitor to keep theovershoots to a minimum. For example, a 10 A/s rate o impulsecurrent shows a positive gate charge o about 0.1 nC. For a 1 Vbattery voltage variation, this equates to 100 nF capacitor.

Tis is considered the minimum capacitance value in the datasheet or reliable operation with low overshoot properties.Reducing the value o this gate capacitor or eliminating it romthe design will increase the overshoot o the thyristor. Faster di/dt impulses will also increase the QGS o the gated thyristor and

thereore the minimum value o gate decoupling capacitanceshould be selected or the worse case situation.

Note: Te capacitor should also be placed as close as possible tothe gate connector o the protector to minimize inductive eects othe copper tracking.

Graph 4 gated thyristor switch characteristics

Te negative battery voltage supply can be decoupled by a 100-220 nF capacitor rom the dc/dc converter

output to the SLIC. Te Bourns ISP device gate decoupling capacitor can be used to provide the sameunction to save component cost i it is placed less than 1 (2.4 cm) rom the dc/dc converter output. Te gatedecoupling capacitor still needs to be as close as possible to the gate o the thyristor to limit overshoots asdiscussed on page 10.

Te NC (non-connect) pins on the ISP61089BD and ISP8200MD and ISP8201MD amilies are notconnected to the die inside the package and thereore can be used to aid tracking. Pin 3 NC can be connectedto pins 6 and 7 o the ISP61089BD to help place the decoupling capacitor next to pin 2 (gate pin) or example.Small size (1201) 100-220 nF capacitors are available that can utilize this interconnect layout across thepackage.


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Grounding techniquesPCB layout is critical to the perormance o the protection circuit and can oen be the culprit when theprotection circuit does not work as intended. Te gated thyristors anode (ground) pins need to be connectedas close as possible to the battery ground o the SLIC as shown in Figure 2. Te gated protectors primaryunction is to limit the voltage stresses seen by the SLIC. Tereore, the gated thyristor needs to be reerencedto the same ground as the SLIC to ensure minimum stresses. Te current through the protector will bedirected through the ground plane o the SLIC and thereore a suitable ground plane to support the expected

current needs to be considered.

Note: Te absolute maximum voltage rating highlighted in able 1, page 5 indicates the ground o the gatedthyristor needs to be directly connected to the SLIC ground pin. Tis point can also be called BGND and will bedependent on the SLIC used. Reerence to the data sheet is required to ensure correct connection.

Using short tracks between the gate o the thyristor and SLIC negative battery voltage is important where theresultant voltage caused by the current in the track will be added to the dynamic perormance o the thyristor.Laboratory testing shows that during the initial rise, a ast impulse (80 A/s) can cause inductive voltages o0.8 V in 2.5 cm o the printed wiring track. Tis can be attributed to the inductance o the track where:

Designers sometimes have the protection circuit reerenced directly to Earth on the equipment, rather than theSLIC ground point on the line card. Te layout methodology is to divert the load current away rom the systemwithout the current going through the back plane o the equipment. Under standard resistance measurement,these two points look the same and thereore are not considered the problem area. However, the scenario isdierent under dynamic conditions. I a SLIC is ailing under the ast transients (2/10 s or 8/20 s) but passeslong duration impulses (10/1000 s or 10/700 s) it is a good indication that the problem may be grounding inthe application.

Figure 2 grounding techniques


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Specifc Bourns TISP device design considerationsLayout o the circuit protection components can also have an eect on circuit passing conormance. elcordiaGR-1089-CORE or example has a 2500 V, 500 A impulse test where a circuit protection solution using a12.5 line eed resistor will have at least 1786 V across the line interace terminals. racks that are routedclose to the input pins can cause problems in circuit operation and the PCB isolation properties need to beconsidered or multi-layer boards.

TISP61089BD 120 A 2/10 sTe ISP61089BD has two K1 (IP) connections specifed as pins 1, 8 and two K2 (RING) pins 4, 5 o theSOIC 8-pin package. Each o these interconnects to the die have been designed to support the impulse and ACpower cross o the device. Tereore, a layout that allows the IP and RING lines to ow through the packageis possible as shown in Figure 3. Tis adds another beneft in that the bond wires in the package can act asa last resort use that will isolate the line rom the line card should the overcurrent protector not operateas intended. Te line isolation will be at least 3.81 mm. Tis layout technique is not intended to remove theneed or a suitable overcurrent protector, but to increase the level o saety should the overvoltage protectorail. It may also be considered where standards are not required such as customer premises equipment whereport conductors do not leave the building (intra-building). Tis removes the need or additional overcurrentprotectors to be used. wo ground pins (pins 6 and 7) are used to ensure a good ground return path and aid indissipating heat away rom the package under ault conditions.

Figure 3 ISP61089BD K1 and K2 connection


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Single blow uses with the TISP61089BD gated thyristorSingle blow uses are oen considered as the overcurrent protector in telecom equipment. o ensure theirsuitability, the use should ideally open beore the thyristor ails to ensure coordination between the twocomponents (page 4, AC power contact). Te 0.5 A B0500 use must only be used with the ISP61089BD,ISP820xMD and ISP9110LDM gated thyristor amilies. Te 1.25 A B1250 use is unsuitable to be usedwith these gated thyristors.

Te layout also needs to be considered since the B0500 is a slow-blow type specifcally designed or telecomapplications. In this instance, K1 and K2 pins should be connected in parallel as shown in Figure 4 toensure adequate current carrying capability rom the ISP61089BD. Te coordination time o the B0500and ISP61089BD amily is very narrow where layout is especially important in this confguration. Teminimum pad area or the use should be used to aid heating o the use and the Bourns ISP device groundconnection should be as large as possible to aid power dissipation.

Figure 4 ISP61089BD connection when using the B0500 use

Note: Te 1.25 A B1250 use should not be used with the ISP61089xD, ISP820xMD or ISP9110LDMamilies.


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TISP61089HDM 500 A 2/10 sTe integrated single port 500 A 2/10 s ISP61089HD has been integrated in the wide-body SOIC 8-pinpackage. Te lead rame in the package has been designed to be a heatsink and thereore as much copperor the connections should be used or the board layout. Tis is especially important or the ground pins(pins 6 and 7) that connect directly to the die. K1 (and K2) pins need to be connected together to ensurethe ISP61089HD coordinates correctly with the Bourns 1 .25 A B1250 eleuse elecom use. TeISP61089HDM is rated to pass the frst level AC tests in GR-1089-CORE.

GR-1089-CORE second level AC tests allow theequipment to ail, but not to cause a hazard such asfre or ragmentation. Figure 5 shows the typical timeor the B1250 use to open compared to where thepackage will sustain damage. Plotting the non-repetitivepeak on-state current versus the current duration curvehighlighted in the data sheet indicates the B1250 willclear beore the ISP61089HDM ails short to helpensure the application ails open circuit.

Figure 5 ypical time to open versus current

Te 100 A ISP61089HDM gated thyristor now allowsa single platorm to be designed to support the lowercurrent ISP61089BD option since the pin pitch andpin unction is exactly the same or both devices. Tisallows a single board design capable o supporting allregions around the world, while capitalizing on the costadvantages in packaging and die sizes between the twodevices. Figure 6 highlights the overlay between thestandard SOIC and wide-body SOIC package.

Figure 6 ISP61089BD and ISP61089HDM PCB layout consideration


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ISP61089HDM also requires a small diode plus two resistors (1 and 1 k) component network to helpensure that the device is stable at extended (above 150 C absolute maximum datasheet rated specifcation)junction temperatures. Te buer transistor can go into an intrinsic short under extended (250 C) junctiontemperatures that could short the battery supply to ground. Tis circuit can be used to drive multiple gates othe ISP61089HDM as shown in Figure 7.

Figure 7 ISP61089HDM dual SLIC layout


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Maximum battery voltageTe maximum supply voltage o the SLIC will defne which buered gated thyristor is best suited to theapplication. Te Bourns gated thyristors are specifed with an absolute maximum repetitive peak gate-cathodevoltage, VGKRM specifcation. Te ISP61089BD maximum VGKRM rating o 167 V does not indicate thata maximum o 167 V battery voltage can be used as the gate reerence voltage. Te dynamic perormanceo the device needs to be taken into account to ensure the thyristor voltage rating is not exceeded. TeISP61089BD has a maximum gate-cathode impulse breakover voltage and a VGK(BO) rating o 12 V with100 A 2/10 s impulse. With a 120 A rating and to take into account extended temperature operation, 15-20 Vshould be considered in the design. Tis increase in protection voltage is covered in more detail in the IEEEStd C62.37.1-2000, IEEE Guide or the Application o Tyristor Surge Protection Devices. Tereore, theISP61089BD should only be used or battery supplies up to 150 V. able 2 highlights the impulse and VGKRMrating o the popular gated thyristor amily.

Table 2 ISP impulse vs. absolute maximum gate-cathode voltage

Device2/10 s / 10/1000 s

current ratingVGKRM Suggested VBAT(MAX) Comments

Single Negative Voltage SLICs

TISP61089DR 120 A / 30 A -85 V -60 V TJ = -40 C to +85 C

TISP61089ADRTISP61089ASDR 120 A / 30 A -120 V -100 V TJ = -40 C to +85 C

TISP61089BDR 120 A / 30 A -167 V -150 V TJ = -40 C to +85 C

TISP61089HDMR 500 A / 100 A -167 V -150 V TA = 25 C

TISP6NTP2ADR 85 A / 20 A -90 V -70V TJ = -40 C to +85 C

TISP6NTP2CDR 90 A / 20 A -167 V -150 V TJ = 0 C to +70 C

Dual Voltage Ringing SLICs

TISP8200MDR

TISP8201MDR210 A / 45 A 120 V 100 V

TJ = -40 C to +85 C

VGKRM at TA = 25 C

TISP8210MDR

TISP8211MDR167 A / 60 A 120 V 100 V TA = 25 C

TISP9110LMDR 100 A / 30 A 120 V 100 V TA = 25 C


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TIP and RING overcurrent protection options

SLICs have traditionally required line resistance with a tight ratio-matched (0.5 %) tolerance to ensure stabilityline balance. Tis resistance is becoming less important with SLICs where line compensation is built in as anadded eature. For example, the VE880 series monitors the line current and varies the line voltage according tothe loop current. Tis also helps to lower the average power dissipation o the SLIC. For overcurrent protectorssuch as line eed resistors (LFRs), this allows the ratio matching o the line resistors to be less o a concern

where a 5 % and ratio-matched tolerance is possible.

Single blow usesSingle blow uses induce the highest di/dt transients in the gated thyristor and thereore extra caution needs tobe used in the design. Fuses open with a unction o localized heat where the using characteristics can changewith board layout. Te recommended ootprints highlighted in the datasheet should be used to ensure correctoperation. Te use characteristics can also change with excessive soldering temperatures that can annealthe use wire to change its characteristics. Te 1.25 A B1250 and 0.5 A B0500 uses are RoHS compliantand have been designed or the high reow characteristics associated with the process. Hand soldering ocomponents using high tip temperatures with extended times needs special precaution and should be avoided.

o calculate the suitability o the use under impulse test conditions, the ollowing ormula can be used orimpulse decay waveorms o 10 ms or less -

where I2t is the rating o the use, IPP is the peak current and the tD is the decay time in seconds o the impulsewaveorm.

For example, what I2t rating will be suitable or GR-1089-CORE frst level 100 A 10/1000 s impulse?

Te I2t o 7.2 is the absolute minimum rating required since GR-1089-CORE also specifes an amplitude

tolerance o 0 % to +15 % and a duration o 0 s to +500 s. Putting the new values o 115 A and 0.0015 s intothe equation, the I2t rating has to be 14. Te B1250 use is specifed or an I2t o 14 and thereore ideal or GR-1089-CORE applications.

Note: Waveorm tolerances in amplitude and wave shape decay times may be specifed in the requirements andshould be taken into account i the equipment must operate aer the tests.


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Clearing time under ACCalculating the clearing time o a use under AC conditions is di cult to do given the wide tolerances. Tesimplest method is to use the characterized curves where Graph 6 shows the Bourns B1250 and B0500clearing times under AC test conditions. Te Bourns ISP device thyristor AC withstand capability can alsobe plotted on the curve to help ensure its suitability with the overcurrent protector. Te use curve shouldideally be below the thyristor curve to ensure the use operates beore the thyristor ails.

Graph 6 AC clearing times


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Power dissipation in the LFRDefning the primary protector to be either a GD or solid-state primary protector can also provide lowerstress on the secondary protection circuit. For example, RSERIES o 10 , without the primary protectorspecifed will see a peak power o 100 kW under GR-1089-CORE, Issue 3 coordination testing. A defnedGD or the primary protector will reduce the peak power to 36 kW as shown in Graph 7. Te peak powerunder the frst level impulse is used to highlight issue 2 requirements. It can be seen that the power dissipationrequirement or the resistor has signifcantly increased. Te sweet spot is where the resistor dissipates thesame energy under Issue 3 so that the size o the LFR does not need to change or this test. Graph 7 highlightsa sweet spot or the coordination resistance o 15 when a GD primary and a 6.5 solid-state primaryprotector are used. Reducing the resistance rom these values increases the power dissipation requirement othe series resistor compared to the old GR-1089-CORE, Issue 2 requirements. Reducing the resistance willincrease the size and cost o the ceramic resistor to withstand the impulse test.

Graph 7 Power dissipation in series resistor under GR-1089-CORE coordination tests

Graph 7 highlights the beneft o increasing the series resistance to reduce the power dissipation in thesecondary protection, but the frst level AC power ault tests highlighted in able 4, page 33 also need to beconsidered. Te highest power dissipation in the series resistor is achieved with the 3 A, 1.1 second test whichmay cause the thermal use to operate. ests have shown that the LFR resistance should be 10 to 15 tokeep the size and cost o the ceramic to an acceptable level. Bourns latest GR-1089-CORE Issue 3 LFRs mustalso be specifed with a GD defned as the primary protector or the equipment to pass the new coordinationtest. Te time delay between the repetitive frst level AC tests (page 32) must be long enough to let theceramic temperature return to ambient temperature to limit the compounding temperature rise that couldprematurely activate the thermal use. A test delay time o at least 15 minutes is recommended or the frst levelGR-1089-CORE AC tests with the 4A12P-1AH-12R5 module.

Note: GR-1089-CORE, Issue 3 compliant modules need a GD specifed as the equipment primary protector.


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Positive Temperature Coe cient (PTC) thermistorPositive temperature coe cient (PC) thermistors resistance increases with its increase in body temperature.Te load current through the resistor causes a heating eect (I2R) where the PC resistance will signifcantlyincrease at a certain temperature. Tis threshold can be in the region o 85 C to 135 C depending on thepolymer compound material used. A typical resistance verses temperature curve is shown in Graph 8.

Graph 8 MF-RX018/250 PC resistance vs. temperature

Te trip resistance o the PC thermistor increases our to fve orders o magnitude more than the originalresistance and will take time to reset back to its nominal value. Bourns MF-RX018/250 specifes a one-hour post trip resistance o 4 rom the initial maximum resistance o 2 . Te hold current (IHOLD) is theminimum current the PC will conduct without tripping at the maximum rated continuous voltage (Vmax).Tis parameter is usually specifed at room temperature where an increase in ambient temperature resultsin a reduced trip current. For example, the MF-RX018/250 IHOLD value will reduce by 24 % rom an ambienttemperature o 23 C to 50 C. Tis needs to be considered in the design phase to help ensure the PC does nottrip at normal extended temperature operation o the equipment.

Te trip current (ITRIP) is the current at which the PC trips at the given VMAX specifcation. A PC can go intoits high resistance state anywhere between IHOLD and the trip current (ITRIP) and is largely dependent on thePC resistance value. Te PC will stay in its tripped state until the load current alls below its new trippedIHOLD value. Te holding current will be extremely low due to the elevated package temperature and thereoremanual reset o the system may be required. Te ITRIP value is normally 2x IHOLD value when calculating theextended ambient temperatures. As the PC trip is dependent upon current, there is a relationship betweentrip time and current. Low ault currents close to the tr ip current specifcation can exhibit long delay switchtimes as shown in Graph 9, which should also be considered.


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Graph 9 trip time vs. DC current or the MF-RX018/250

elecom PCs speciy a maximum rated continuous dc voltage (Vmax) that needs to be specifed to themaximum battery voltage. Te critical area to consider PC suitability is under the ring cycle at extendedtemperatures. A PC with a lower series resistance or higher holding current may be required. Te maximuminterrupt voltage (Vint) rating is the maximum voltage that can be applied across the device while in thetemporary tripped state and will oen be specifed with a maximum current specifcation. Te interruptvoltage specifcation is expressed in AC rms or telecom applications since the PC will protect against the ACtest voltage conditions in the telecom standards. Tereore, it is prudent to ensure the PC can support themaximum AC voltage (120 V rms, 230 V rms or 600 V rms) and withstand short circuit currents indicated inthe telecom standards without being damaged.

Note: Ceramic PCs (CPC) typically display higher resistances (50 ), but the actual value o resistance canreduce by 50 % under high voltage and/ current impulse conditions. Tis needs to be taken into account whencalculating the overvoltage impulse current requirements. Polymer PC thermistors do not exhibit this negativeresistance change and calculations can be done on the lowest ambient temperature specifcation.


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Application solutions for negative only battery supplies

Telcordia GR-1089-CORE, Issue 3 inter-building requirementselcordia GR-1089-CORE impulse requires a frst level test o 100 A 10/1000 s and 500 A 2/10 s wherethe equipment must operate aer the tests. Tereore, the overvoltage protection solution should be rated toat least these current levels i a single blow use is used. Bourns ISP61089HDM is rated or these impulsecapabilities and thereore the Bourns B1250 eleuse elecom use can be used as shown in Figure 9.

Te B1250 is designed to meet the surge withstand ratings with the quantity o repetitions in the data sheet.Te B1250 must not open under the frst level AC power contact tests while ailing saely under the secondlevel tests. Te B1250 specifes the clearing time under the key AC current test conditions. It is consideredgood design practice to ensure the overcurrent protector operates beore the overvoltage protector ails. Tisis not specifed in Issue 3, but with a use in series, it is suitably coordinated with the overvoltage protector tohelp ensure that the equipment ails open circuit rather than the overvoltage ailing short circuit without theuse operating.

Te equipment is also subjected to a current limit test where a current limiter indicator such as a MDL2.0Ause is used between the generator and the equipment. Te equipment must limit the current so that thecurrent limiter indicator does not operate. Te B1250 will help ensure that this requirement is achieved. TeISP61089HDM with the B1250 provides a simple method to help pass the coordination test in Issue 3.

Figure 9 elcordia GR-1089-CORE, Issue 3 protection solution


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Solutions that deploy the primary protector close to the secondary protection can fnd the single blow useailing beore the primary operates.Tis is due to not having any series resistance between the two (primaryand secondary) overvoltage protectors. Te secondary is normally lower in voltage operation and thereorewill operate beore the primary protector and consume the entire ault current until enough voltage isdeveloped across the primary protector. Te simplest method to ensure this voltage coordination is toadd series resistance where enough voltage is developed across the resistor (without ailure) to operate theprimary protector and allow the secondary protection to reset back into its normal condition. A use willneed to operate beore this can be achieved i there is not enough interconnect impedance (inductance or

resistance) between the two elements to create the voltage. Te 4A12P-1AH-12R5, 12.5 LFR module helpsensure voltage coordination (elcordia GR-1089-CORE, Issue 3, section 4.6.7.1 type A pass) between theprimary and secondary protection. A minimum impulse current rating o 51 A, 10/1000 s is required to meetcoordination. A solution is shown in Figure 10. Should the series resistance increase to 40 or higher, thelower impulse rated ISP61089BD can be considered in the design.

Figure 10 GR-1089-CORE voltage coordination protection

Note: Te Bourns MF-R015/600 and MF-R016/600 devices are unsuitable or ull elcordia GR-1089-COREapplications. It is also important to ensure the selected LFR module conorms to the latest standards.


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USA intra-building recommendationsCustomer premises equipment (CPE) communication ports that do not leave the building do not have anycircuit protection regulations. Equipment manuacturers recognize that equipment still needs to be protectedto reduce feld ailure returns. Using just the ISP overvoltage protector increases the system withstand toimpulse condition or engineers can consider the elcordia GR-1089-CORE intra-building requirements.

Tis requirement is or internal (within the building) communication ports within the central o ce and isa good indication o electrical disturbances occurring inside the building. GR-1089-CORE intra-building iscovered in more detail in appendix A, page 32.

GR-1089-CORE intra-building has a 100 A 2/10 s test where the equipment must work aer the test. TeISP61089BD has a 120 A, 2/10 s capability that ensures intra-building impulse requirements are achievedwithout the need o additional series resistance. Intra-building also has a 120 V rms, 25A test where theequipment can ail saely. Te ISP61089BD will need to be protected against the AC power line contact testsince it can support 0.93 A or 900 seconds. Te B0500 current versus time characteristic shows that it willoperate beore the maximum withstand o the ISP61089BD is exceeded. K1, (pins 1 and 8) and K2 (pins 4and 8) may be linked on the PCB i the 0.5 A B0500 use is used. For applications that require the overcurrentprotector to reset, the Bourns MF-RX018/250 or MF-SM013/250 Polymer PC thermistor can also be

considered in the design that can withstand the impulse and AC tests. A solution or intra-building is shown inFigure 11.

Note: Te 1.25 A B1250 use is unsuitable to be used with the ISP61089BD thyristor.

Figure 11 GR-1089-CORE intra-building requirements

Note: Intra-building is not a requirement or CPE equipment and thereore the ISP61089BD layoutconsiderations using the internal bond wires as a last resort use as discussed on page 11. Tis can save the cost ousing an overcurrent protector i thyristor ailure is acceptable.


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Dual or multiport protection or Telcordia GR-1089-CORE intra-buildingFor applications that have two or more POS (plain old telephone service) ports or intra-building, theISP6NP2CD and the MF-SM013/250 PC thermistor can be considered as shown in Figure 12. TeISP6NP2CD integrates the unction o two ISP61089BDs into a single SOIC 8-pin package to save space.Te ISP6NP2CD is rated or 90 A, 2/10 s and thereore will require a minimum series resistance o 2 orgreater to pass the elcordia intra-building impulse requirements. Te MF-SM013/250-2 has a minimum o6.5 and has 250 V rms maximum interrupt voltage to withstand the AC test. Te MF-SM013/250V providesa vertical PC to help urther reduce board space area. Te Bourns Multiuse PC device resistance can be0.5 reel-matched or better longitudinal balance i required.

Note: Te ISP6NP2CD should only be used with the MF-SM013/250 amily or 50 ceramic PCs to meet theintra-building requirements.

Figure 12 Dual port protector or intra-building


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ITU-T recommendationsTe ISP61089BD or single port applications and the ISP6NP2CD or dual port applications can beconsidered or IU- applications. Te ISP61089BD is rated or 40 A, 5/310 s or a junction temperature(J) o 40 C to +85 C where the ISP6NP2CD is also rated at 40 A, but or a J o 0 C to +70 C. I theISP6NP2CD is required to operate in ambient temperatures o -40 C to +85 C, the current rating shouldbe derated to 25 A or 5/310 s impulse.

ITU-T basic recommendationsTe impulse requirement or K.20 is 25 A, 5/310 s and thereore the ISP61089BD or ISP6NP2CD can beused without any additional resistance. K.21 and K.45 have a current requirement o 37.5 A where both ISP6series can also be considered. A series resistor o at least 7 will help ensure impulse coordination with theprimary protector under the 4 kV test. Te overcurrent protector should be rated or 230 V rms to pass thebasic AC power cross tests where the Bourns Multiuse SM013/250-B or MF-RX018/250 device can be used.Integrated voice data (IVD) solutions are sensitive to additional series resistance where the MF-RX018/250with its maximum resistance o 2 can be considered as shown in Figure 13. However, the PC resistance willnot ensure coordination with the primary protector as discussed on page 36, coordination requirements.

ITU-T enhanced recommendationsTe enhanced impulse increases the K.20 recommendation to 37.5 A and the coordination impulse voltage(with the GD in place) is increased to 6 kV. Te enhanced AC power contact tests range rom 450 V rmsto 1500 V rms between 0.18 s to 2 s. Te test time can be calculated by using the ormula on page 41, ACpower line cross. Te overcurrent protector will need to support the test voltage until enough voltage hasbeen developed across the overcurrent protector to operate the GD primary protector. 600 V polymer PCcomponents such as the MF-R015/600 may be required to help ensure suitable operation.

Figure 13 IU- basic recommendation

Note: Te MF-RX018/250 will not ensure primary coordination or basic test levels. o achieve this, a higherresistance value o 6 or the PC is required. Te design engineer must ensure the PC thermistor can supportthe AC and impulse requirements.


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Application solutions for dual battery supplies

Dual voltage ringing SLICs require two thyristor protectors to reerence to the positive and negative ringingbattery voltage. Te same design principles are used with the dual voltage protection SLICs as with the negativeonly protection solutions. Te ISP8200MD gate reerence is tied to the negative ring battery voltage and theISP8201MD gate reerence is connected to the positive ring voltage supply. Integrated architectures such asthe ISP9110LDM have the same thyristor and buer transistor topology to identiy power supply connection.

Telcordia GR-1089-CORE, Issue 3 inter-building requirementsGR-1089-CORE, Issue 2 would require a thyristor to meet 45 A to pass frst level impulse requirements witha minimum 12.5 resistor. Tis allowed the ISP8200MD and ISP8201MD dual voltage gated thyristors tobe used. Protection coordination (elcordia echnologies Generic Requirements, GR-1089-CORE, Issue 3,October 2002, section 4.6.7.1 protection coordination, page 4-15) is a new test or GR-1089-CORE or Issue 3that can increase the 10/1000 s impulse requirement o the circuit protection solution. Please see Appendix A,page 36, protection coordination or more inormation on coordination requirements or inter-building. Te4A12P-1AH-12R5 12.5 module is designed to help ensure Issue 3 compliance with a GD specifed as theprimary protector. Te ISP8210MD and ISP8211MD are 60 A 10/1000 s rated to help ensure conormanceunder the coordination test. Te solution is shown in Figure 14.

Figure 14 Dual voltage protection or inter-building requirements

Note: At the time o writing this application note, a 100 A 10/1000 s rated thyristor had not been releasedto allow the 1.25 A B1250 use to be used as the overcurrent protector. Please consult the actory or possibleoptions.


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USA intra-building recommendationsCustomer premises equipment communication ports that do not leave the building do not have any circuitprotection regulations. However, manuacturers recognize that equipment still needs to be protected to reducefeld ailure returns. Using just the ISP overvoltage protector increases the system withstand to impulsecondition or engineers can consider the elcordia GR-1089-CORE intra-building requirements.

Tis requirement is or internal (within the building) communication ports within the central o ce and is agood indication o electrical disturbances that can occur inside the building. GR-1089-CORE intra-building iscovered in more detail in Appendix A, page 35, intra-building requirements.

GR-1089-CORE intra-building has a 100 A 2/10 s test where the equipment must work aer the test. TeISP9110LDM has a 2/10 s capability o 100 A that helps ensure intra-building impulse requirements areachieved without the need o additional series resistance.

o meet the intra-building AC power contact test, the ISP9110LDM can be used with the Bourns B0500eleuse elecom use or the Bourns Multiuse MF-SM013/250 Polymer PC thermistor where a typicalcircuit protection solution is shown in Figure 15. Te ISP820xMD gated thyristors can be used i a higherprotection solution is desired as these are 210 A 2/10 s impulse rated.

Note: Te 1.25 A B1250 single blow use is unsuitable to be used with either the ISP820xMD, ISP821xMD orISP9110LDM. Te B0500 use can be considered i a use is desirable.

Figure 15 Intra-building protection solution


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ITU-T recommendationsTe ISP9110LDM is rated or 45 A 5/310 s and thereore can support the basic and enhancedrecommendations specifed in K.20, K.21 and K.45. A series resistor o at least 7 using the MF-SM013/250with the ISP9110LDM will help ensure impulse coordination. Te MF-SM013/250 is rated or 250 V rms topass the basic AC power contact test. I coordination is not required and low series resistance is desirable, theMF-RX018/250 with its maximum resistance o 2 can be considered as shown in Figure 16.

Figure 16 IU- basic recommendations protection solution

Enhanced AC test levelsTe enhanced AC power contact tests range rom 450 V rms to 1500 V rms between 0.18 s to 2 s. Te test timecan be calculated by using the ormula highlighted on page 41, AC power line cross. Te overcurrent protectorwill need to support the test voltage until enough voltage has been developed across it to operate the GDprimary protector. A 400 V or higher PC component may be required to help ensure suitable operation.Bourns has 600 V rms PC products such as the MF-R015/600-B-2 to be considered with the ISP820xMD orISP821xMD thyristors.

Te higher impulse ISP820xMD or ISP821xMD series will allow lower resistance values to be used wherea minimum o 9 can be considered. Te minimum resistance or the ISP9110LDM is 35 to meet IU-enhanced recommendations where a suitably rated ceramic PC thermistor is recommended.


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Appendix A - Telecom standards

Te countrys standards or recommendations govern what protection is required or the equipment. Centralo ce and remote access equipment in the USA need to conorm to elcordia GR-1089-CORE. elcordia GR-1089-CORE intra-building requirements apply to central o ce ports that do not leave the building. Customerpremises equipment (CPE) in the USA is required to meet IA-968-A or lightning and UL 60950 (UL 1950)or AC power line cross that interace to external communication lines. CPE SLIC ports do not normally

interace to the external ELCO lines and thereore are not covered in this document. CPE equipmentports that do not leave the building do not currently need to meet any impulse and AC tests, but protectionis desirable to increase the robustness o the equipment and limit feld returns. Reerence to the elcordiaGR-1089-CORE intra-building requirements provides an indication o what level o protection should beconsidered.

Most other countries have adopted the IU- (International elecommunications Union) recommendations.IU- is a recommendation and thereore countries can modiy this document to suit their own requirements.Te IU- recommendations break out into a series o documents where K.20 covers central o ce, K.45 orremote access equipment and K.21 or CPE. Te IU- test method is provided in a separate document andcovered in K.44. Te IU- recommendations went through a major iteration in year 2000 to include a higher

(enhanced) test level or locations that have severe lightning storms such as Japan and South Arica. Te othersignifcant addition is providing a primary and secondary protection impulse coordination test. Figure 17indicates where the telecom standards are reerenced in the communication highway.

Tis appendix will discuss the key areas o the standards and provide background material or selectingsuitable overvoltage and overcurrent solutions.

Figure 17 Overview o telecom standards


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Te frst and second level AC power ault tests are conducted under a 50 or 60 Hz sinusoidal waveorm andare tested in metallic and longitudinal confgurations. Te 1000 V rms recommendations in issue 2 have beenincluded as requirements in Issue 3. I the primary protector has not been defned in the system, the secondaryprotection circuit will need to support the ull 1 kV rms test. Tis has been added to simulate the end o liecarbon block characteristic in the feld. Te test number also highlights the number o applications or eachtest.

* Pri = Primary protector is in place during the test

Table 4 elcordia GR-1089-CORE AC power contact

First-Level AC power fault

Test # Open CircuitVoltage (V rms)

Short CircuitCurrent (A)

Duration (s)

1 x 1 50 0.33 900

2 x 1 100 0.17 900

3 x 60 600 1 1

4 x 60 1000 1 1 + *Pri

6 x 1 600 0.5 30

7 x 5 440 2.2 2

8 x 5 600 3 1.1

9 x 5 1000 5 0.4 +*Pri

Second-Level AC power fault

TestOpen Circuit

Voltage (V rms)

Short Circuit

Current (A)Duration (s)

1 277 25 900

2 600 60 5

3 600 7 5

4 600 2.2 900


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Current-limiting protector testsTe current-limiting tests are conducted with 600 V rms, with a range o short circuit currents o 15-minutedurations under metallic and longitudinal confgurations. An external current limiter indicator that is time/current dependent is used to ensure conormance, but time/current measurements can be also taken. A MQD1-6/10A or MDL 2.0A use manuactured by Bussman or their equivalent has been recommended as a suitableexternal indicator. Tis places the emphasis on the equipment to ensure this indicator use is not damagedduring test. Designing the system so that it will not ail is not a possibility without providing current limitingbelow the use indicator characteristic. Cheesecloth is also applied to the equipment as the fre hazard and

ragmentation indicator.All the tests are perormed on the equipment where test one and two do not require the external current limitindicator to be present. Te equipment passes the other tests i the equipment interrupts the line current toless than 50 mA and the external current limiter indicator is not open circuit. I the external current limiterindicator is open circuit, the equipment will require external current limiting protectors. Te frst level passcriteria shows the boundary where the overcurrent protector must not interrupt and the second level ailurecriteria boundary where the protector must operate to allow conormance. Te area between these twoboundaries provides a window where the overcurrent protector must operate during the tests as shown inGraph 10, page 35.

Table 5 elcordia GR-1089-CORE current limiting

TestShort Circuit

Current (A)

Open Circuit

Voltage

(V rms)

Duration (s)

1 2.2

600 900

2 2.6

3 3

4 3.75

5 5

6 7

7 10

8 12.5

9 20

10 25

11 30


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Graph 10 GR-1089-CORE AC power line cross acceptance window

For applications where the manuacturer specifes the complete installation o the equipment rom the networkinterace to the equipment, the MDL 2.0A use wiring simulation is replaced with a 30 cm section o 26 AWGcopper cable. Tis will allow a higher current limiter to be used in the equipment giving more impulsecurrent capability or remote terminal environments that can have surge current stress levels exceeding 100 A,10/1000 s.

Intra-building requirementsIntra-building specifcations apply to communication lines that only stay within the building with noexternal connections. Lightning disturbance can enter the building through earth reerence disturbance orelectromagnetic coupling o lightning rods or example. Communication lines to service o-site equipment willneed to conorm to elcordia GR-1089-CORE in its entirety.

wo wire communications lines will need to be tested with metallic surges o a 2/10 s waveorm with anopen circuit voltage o 800 V and short circuit current o 100 A. Te equipment also needs to withstand alongitudinal test with a waveorm o 2/10 s and an open circuit voltage o 1500 V with a short-circuit current

o 100 A. Te equipment needs to withstand a single impulse o each polarity without damage under these tests.

It is key to note that i the communication lines are shielded and terminated to ground at both ends, the impulsetest does not need to be done.

Intra-building has an AC power contact test (GR-1089-CORE, Issue 3 section 4.6.17, second level intra-building AC power ault tests or network equipment to be located on the customer premises, page 4-37). Tetest is conducted with 120 V rms, 25 A or 900 seconds where the equipment can ail saely. An external wiresimulator using a MDQ 1-6/10 A or MDL 2.0 use is used to help ensure the equipment port does not consumeexcessive currents that can damage the interconnect leads.


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l d d l l d b


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Bourns elcordia GR-1089-CORE Issue 3 modules require a GD or solid-state primary protector to bespecifed with the equipment.

Graph 11 highlights where the series resistance (RSERIES) will dictate a current or voltage coordinatedapplication across the three primary protector options. Te three options are carbon block or none specifed,GD or a solid-state (semiconductor) primary protector. For applications requiring voltage coordination,the additional series resistance, RSERIES must be outside the shaded area (right o IP curve) on Graph 11. Forexample, a line card defned with a GD primary protector will be voltage-coordinated with a series resistance

o greater than 6 and current-coordinated with less than 6 . Te maximum power transer will occur atthe crossover point o 6 , which will be the highest stress actor or the series resistance. At 6 , the seriesresistance will need to support an open circuit generator voltage o 1600 V and 100 A 10/1000 s.

Note: Te maximum power transer points should be avoided i possible.

Graph 11 Voltage or current coordination

Note: Bourns elcordia GR-1089-CORE line eed resistor modules need to be defned with either a GD or solid-state thyristor primary protector to pass the coordination requirements.


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Table 7 IU- impulse

Note: IU- impulse table was sourced rom Compliance Engineering article Te 2003 IU-elecommunications Equipment Resistibility Recommendations.


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AC li


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AC power line crossTe IU- recommendation specifes eight source-resistance values ranging rom 10 to 1000 to be testedwith a 50-60 Hz 230 V rms generator. Te test range can be narrowed i the worse case stress conditions o theequipment are known. Enhanced power contact testing uses the same resistance and voltage levels, but theequipment is also required to meet criterion A (equipment must not ail in operation) or the resistance rangeso between 160 to 600 .

Te inherent induction test is achieved with a 600 V rms, 0.2 s, 600 applied to the equipment where the

equipment must still operate as intended. Basic coordination testing increases the test time to 1 s, 600 applied to the dierent confgurations with the primary protector in place. Enhanced coordination testing isdone with a 200 generator source with various voltage and time values set between 1500 V rms or 0.18 sand 450 V rms or 2 s. Te time versus test voltage can be calculated by using the ormula -

K.44 highlights testing at 450 V & 1500 V and then at least two intermediate levels between the two should besu cient i there are no transitions specifed.

IU- does not distinguish between single and multiple ports under AC ault conditions and thereore eachport is considered a single port solution. Te table below shows the AC tests or single port applications.

Table 9 IU- single port AC power cross

Note: IU- single ports AC power cross table was sourced rom Compliance Engineering article Te 2003IU- elecommunications Equipment Resistibility Recommendations.


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Dual voltage ringing SLICs


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Dual voltage ringing SLICsDual voltage ringing SLICs require a positive buered gated thyristor protection solution that tracks the +VBATsupply. An N-channel SCR is used with a PNP buer transistor as shown in Figure 21 to provide the positivegate reerence. Te SCR will operate with the anode approximately 1.4 V above the PNP positive reerencevoltage. Te repetitive peak reverse voltage (VRRM) withstand o the positive and negative SCRs must be abovethe maximum battery voltages. Te same design principles are used with the dual voltage battery trackingdevices as with the single supply options.

Figure 21 Dual voltage ringing SLIC protection

References


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References

elcordia echnologies Generic Requirements, GR-1089-CORE, Issue 3, October 2002, ElectromagneticCompatibility and Electrical Saety Generic Criteria or Network elecommunications Equipment.

Mick J Maytum, 2002, Te New IU- elecommunication Equipment Resistibility RecommendationsCompliance Engineering article.

Mick J Maytum, 2003, Te 2003 IU- elecommunication Equipment Resistibility RecommendationsCompliance Engineering article.

I would like to thank Legerity in Austin, exas or their support in reviewing and contributing to the content othis document.

DisclaimerBourns assumes no liability or applications help or customer product design. Customers are responsible ortheir products and applications using Bourns parts. o minimize the risks associated with customer productsand applications, customers should provide satisactory design and working saeguards. It is the customers

responsibility to understand the saety practices relating to working with electrical and electronic circuitry toavoid electric shock, fre hazards and explosions.

Te inormation given here is based on data believed to be reliable, but because o the wide range o situationsin which this inormation may be used, we cannot accept responsibility or loss or damage resulting romunsatisactory perormance. Tis publication is not to be taken as license to use or a recommendation toinringe any patent. Inormation published by Bourns about third-party products or services does not orm alicense rom Bourns to use such products or services or a warranty or a product endorsement.

Copyright 2006 Bourns with all rights reserved. Bourns must give written consent to reproduce any part o this

publication. Personal use o this material is permitted. Te inormation given in this document is believed tobe accurate and reliable, it does not orm part o any quotation or contract, and changes may occur withoutnotice. Bourns will not accept liability or the results o its use. Publication does not transer nor imply anylicense under patent or other industrial or intellectual property rights.


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Specications subject to change without notice. Actual perormance in specic customer applications may dier due to the

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