AbstractThis paper describes the realisation of a differential BPSKdemodulator using a high speed ADC, an EPLD and anEPROM. By incorporating both I and Q data in thedemodulation process, a significant improvement inperformance is obtained. Computer simulation shows theBit Error Rate (BER) performance versus Received Carrierto Noise Ratio (CNR) is virtually identical to the theoreticalperformance of a differential phase shift keyed (DPSK)detector. This paper also describes the realisation of thespecial PLL required, to recover the data clock. This PLLuses an EPLD, a DAC, a conventional loop filter and aconventional VCO.

1. IntroductionThe transmission of data from the GMS weather satelliteis a BPSK signal, at a carrier frequency of 1.6871 GHzwith a 660 kbit/sec data rate. Because of the >200 dB freespace loss of the transmitted signal, the received CNR isonly a few dB above the minimum value required todemodulate the data with acceptable error rates. To receivethese signals, a low cost BPSK demodulator is required,which can accurately demodulate BPSK signals at theselow carrier to noise ratios.

The reception of Binary Phase Shift Keyed (BPSK) signalshas traditionally been difficult. The carrier has either a 0degree or a 180 degree phase shift depending on the dataand the carrier amplitude is zero during the data transitions.As a result, a conventional Phase Locked Loop (PLL)demodulator cannot be used. Differential detection ofBPSK signals is easy in theory, but difficult in practice.

A Costas Loop [1] or a Phase Locked Loop (PLL) withspecial phase detectors[2], can be used to recover the carrier.That carrier is then used to synchronously demodulate thereceived signal. From theory, synchronous demodulation ofBPSK data gives the best BER performance.

In practice a Costas Loop will only perform accurately ata high Carrier to Noise Ratio (CNR). At a low CNR theloop will tend to loose lock. The BPSK demodulatordescribed here remains locked under noisy conditions.

The new BPSK demodulator uses digital technology,resulting in a lower production cost and simpler hardwarethan the Costas Loop.

2. Practical BPSK demodulator

Communication texts [3] suggest the use of differentialphase detection, based on the block diagram of figure 1.However these texts do not mention the strictsynchronisation requirements.

If the input waveform is a carrier:

X(t) = Sin(ωct) Eqn. 1a

The delayed signal will be:

Y(t) = Sin (ωct + θ) Eqn. 1b

where θ is the phase shift of the delayed waveform withrespect to the present waveform. The output from themultiplier will then be:

)()2(21

)()]2([121

)()()()()(

)()(

c c

c c c2

c c

θωθω

θωωθω

θωω

SintSinCostCos

SintCostSinCostSin

dttSintSin

×−×−=

××−×=

+×

For a typical BPSK system, there are many carrier cyclesper data period. For ideal operation θ is 0° or 180° andthen the second term can be ignored, leaving a DCcomponent plus a large ripple.

2.1 Realisation

The signal at the multiplier output in Figure 1 and shownin equation 2 must be used as the input for the data clockrecovery circuitry. This large ripple causes problems, withthe stability of the clock recovery hardware. Using In-Phase(I) and Quadrature (Q) components as shown in Figure 2,removes most of the ripple.

The Analogue to Digital Converter (ADC) digitises theinput carrier waveform of equation 1a. The digital delayline then delays this waveform by one data bit. The signalsat the tapping points 1 and 16 then correspond to thosethat are multiplied in figure 1. The delay line is clocked

Digitally Demodulating Binary Phase Shift Keyed Data SignalsCornelis J. Kikkert, Craig Blackburn

Electrical and Computer EngineeringJames Cook University

Townsville, Qld, Australia, 4811.E-mail: Keith.Kikkert@jcu.edu.au, Craig.Blackburn@jcu.edu.au.

Figure 1. Differential BPSK demodulator.

BSPK Input

Delay of One Data Bit

Integrate Over One Data Bit

Demodulated Output

Eqn. 2

with the sampling clock that is also used for the ADC. Thesampling frequency is chosen such that one samplingperiod delay corresponds to 90° phase shift of the carrierwaveform. If a sine waveform is present at tapping point1, then a cosine waveform is present at tapping point 2.The signals at tapping points 1 and 16 will thus be In-Phase (I) components and those at tapping points 2 and 17will thus be Quadrature (Q) components. At the adder infigure 2, the following waveform will thus be present:

X(t) = Sin(ωct)×Sin(ω

ct+θ)+Cos((ω

ct+φ)×Cos(ω

ct+θ+φ)Eqn. 4.

Where θ is the phase shift of the carrier over one data bitperiod, including the BPSK modulation and φ is thevariation from the 90° phase shift. In practice φ will bezero, and θ will be either 0° or 180° depending on theBPSK data. The resulting waveform at the adder will thusbe either:

X(t) = Sin2(ωct) + Cos2(ω

ct) = 1 or

X(t) =- Sin2(ωct) - Cos2(ω

ct) = -1 Eqn. 5.

depending on the value of the BPSK data. Note that theripple at 2ω

c has been removed completely. The resulting

waveforms are shown in Figure 3.

By calculating the variation of θ and φ resulting from theBPSK carrier frequency and the sampling frequency beingnot correctly related, the tolerance of this BPSKdemodulator can be plotted as shown in figure 4.

Using both the I and Q tapping points, doubles the outputsignal and results in a minimal ripple. For an IF frequencyshift of 25% of the data rate, the ripple is less than 10%and the data output is more than 70% of the ideal outputvoltage. For hardware realisation of the BPSKdemodulator, one can thus have a frequency shift of 25%

of 660 kHz, or ±165 kHz of the 18.48 MHz BPSK carrierfor a 3 dB drop in output. This frequency stabilityrequirement is quite feasible, even for down conversionfrom a 1.6871 GHz satellite signal.

By adding two more multipliers and an adder to the blockdiagram of Figure 2, the technique can be extended todemodulate QPSK signals as well, as shown in Figure 5.

A phase locked loop (PLL) is required to recover the 660kHz data clock. The 10.56 MHz sampling frequency forthe ADC and delay line is 16 times the 660 kHz data clockand is produced by this same PLL.

2.2 Hardware

An 8 bit ADC is used as this has been demonstrated bycomputer simulation to give a satisfactory performance.The delay line is thus 17 bit long and 8 bit wide. Thisrequires 136 flip-flops and is programmed into a LatticeispLSI1032 EPLD. The multipliers shown in figure 2 needto be able to multiply two 8 bit numbers inside the 94.7 nsperiod of the 10.56 MHz sampling clock. This is achievedby using a 512 kbyte EPROM as a look-up table. The 16EPROM data inputs are formed by the two 8 bit inputs tobe multiplied. Since the multiplied I data is the same asthe multiplied Q data one clock pulse later, only oneEPROM is required if the EPLD is used to store and delaythe multiplied value for one clock period.

ADC EPLD Delay Line17 bit long, 8 wide

16 17

Input Integrateand Dump

1 2

to PLL

Data

Figure 2. New BPSK demodulator.

Figure 3. Demodulator Waveforms.

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-0.8

-0.4

0.0

0.4

0.8

1.2

Time

Am

plit

ud

e

I

2I Q2

Q

+ Q2 2

I

0.00

0.10

0.20

0.30

0.40

0.50

0.60

0.70

0.80

0.90

1.00

0% 5% 10% 15% 20% 25% 30% 35% 40% 45% 50%

Frequency Error wrt Data Frequency

Ou

tpu

t

Output

Ripple

I2 Out

I2 Ripple

Figure 4. Frequency Tolerance of BPSK demodulator.

EPLD Delay Line17 bit long, 8 wide

Integrateand Dump

Integrateand Dump

Decision Logic

1 217

16

I

Q

to PLL

to PLL

Figure 5. QPSK Demodulator.

A second ispLSI1032 EPLD is used to add the I and Qmultiplier outputs and to perform the integrate and dumpdata detection using an adder for the integrator. The addedI and Q multiplier output is the raw digital data outputrequired for the data synchronisation PLL. This signal isturned into an analogue signal using a Digital to Analogueconverter (DAC), the output of which is then filtered toprovide some smoothing. This filtered raw demodulateddata is then used as reference input to a PLL, to recoverthe 660 kHz clock and hence the 10.56 MHz samplingclock.

The whole block diagram shown in figure 2 is thus realisedusing two low cost EPLDs, one EPROM a low cost ADCand a low cost DAC. Figure 6 shows the resulting hardware.The left board is the BPSK demodulator and the right boardis the Phase Locked loop described later.

Figure 7 shows the binary input data, the BPSK data andthe demodulated output obtained with this hardware. Thetop trace is the binary data, the second trace is thedifferentially encoded signal, which is then modulated witha carrier. The bottom trace is the demodulated output. Thesystem performs very well, even under noisy signalconditions.

2.3 Error performance

Since the system has to operate under poor Carrier to Noiseconditions, the performance of the system under noisyconditions must be investigated. Figure 8 shows the errorperformance obtained from a computer simulation of thesystem, described above. There is an excellent agreementbetween the theoretical results [3] for the ideal differentialdecoder and the computer simulation of the actual system.The calculated error performance for an IF simulation,incorporating the hardware filters used in the simulation,shows a slight degradation in the error performance due tomore noise being passed by the non-ideal IF filter. Thebandwidth of the IF filter indicated, is that of an ideal filterwith the same total noise output. The noise spectral density(N

0) indicated in Figure 8 is the total noise, obtained from

the computer simulation, divided by this bandwidth. Thesimulated performance of the system at a BER less than10-4 has a larger error tolerance, as a very large computersimulation is required in order to have sufficient errors forthe results to be statistically valid.

In the computer simulation, the effects of the finite lengthand width of the EPLD delay line and the realisation ofthe multipliers using EPROMs was included. A slightlyworse, but satisfactory performance was obtained, evenwith a 4 bit wide delay line and multipliers. For 4 bit widemultipliers, both multipliers can be included in oneEPROM. The adder of Figure 2 can then also be includedin the EPROM as part of the look-up table, reducing thecost even further. Since the cost of the 8 bit wide realisationis small, and there is an improvement in performance, an8 bit wide realisation is used in the hardware.

3. Phase Locked Loop3.1 Phase Detection

The demodulator requires that the ADC and Digital Delayline clock frequency is exactly 16 times the data rate. APLL is required to recover the data clock and generate the10.56 MHz ADC sampling frequency. To minimisehardware production costs, a complete digital realisationof this phase detector is required.

Figure 6. BPSK Demodulator Harware.

1.E-06

1.E-05

1.E-04

1.E-03

1.E-02

1.E-01

1.E+00

0 2 4 6 8 10 12

Eb/No

BE

R

Baseband Simulated

Baseband Theoretical

IF Simulated

Figure 8. Frequency Tolerance of BPSK Demodulator.

Figure 7. Frequency Tolerance of BPSK Demodulator.

Data inDifferential data

BPSK Data

Data out

The binary data has a time between zero crossings thatvaries in multiples of 1.515 µs. Since the zero crossingsdo not occur every data bit, a conventional phase detectorcannot be used. One of the authors [4] has developed ananalogue phase detector, which is suitable for thisapplication. This phase detector will however only lock ifthe free running frequency of the PLL is very close to the660 kHz data rate. That cannot always be guaranteed. Toensure reliable operation of the receiver system, frequencydetection is required to ensure that the PLL always locks.

Figure 9 shows the waveforms used in the Phase/Frequencydetector developed for the Data Clock recovery. The Clockis the 660 kHz data clock, which is derived from a 84.48MHz voltage controlled oscillator (VCO) by dividing by128. The data signal is the raw binary data, obtained bydigital to analogue conversion and filtering of the adderoutput of Figure 2 (to PLL). At a transition of the data, aPhase and Period Counter is set to zero. The 84.48 MHzVCO increments that counter and its output ramps up asshown. When the falling edge of the Clock occurs, thecontent of this counter is latched and transferred to thePhase Detector Output. This Phase Detector Output isconverted to an analogue voltage, the filtered value ofwhich controls the VCO. If more than one ones or zerosare being transmitted in succession, there will not be asecond transition 1.515 µs after the first one and the countersimply keeps ramping up until the maximum count of 192is obtained, where the counter limits. If this happens, thePhase & Period Counter contents are not transferred tothe Phase Detector Output. The next data transition willthen reset the Phase and Period Counter back to zero. Thephase detector will thus only produce a phase output whentwo transitions in the data are produced 1.515 µs apart.

This will occur 25% of the time on average, which issufficient to keep the PLL phase locked. Since the analoguePhase Detector Output is produced by a DAC, no driftoccurs in-between Phase Detector Output updates.

3.2 Frequency detection

The time interval between zero crossings of the data isobtained from the Phase and Period counter shown inFigure 9 and is a measure of the frequency differencebetween the input data and the VCO. The counter containsthe data period, just before the counter is set to zero. Forthe hardware described here, the data period should be128 clock pulses of the 84.48 MHz VCO. The countercontents can thus be used as a frequency indication andused to provide frequency locking. Since on average onequarter of the number of data bits have transitions 1.515 µsapart, the VCO frequency is controlled often enough toensure proper locking of the VCO.

Figure 10 shows the resulting block diagram of the PLL.The output of the frequency control counter and the phasedetector output are added in the correct proportions toprovide the input to a DAC, which provides the analoguevoltage of the VCO after filtering. For the hardwarerealisation the Phase detector produces 128 different levelsfor a 360° range of operation. In order to produce a goodoverlap between the frequency detector and the phasedetector, the frequency step size is 64 times larger thanthe phase step size. The 84.48 MHz VCO has a 10 MHztuning range. Since a 16 bit DAC is connected to thiscontrol counter, each counter step is thus 152 Hz, whichis well within the frequency tolerance required as shownin Figure 4.

The Phase Frequency detector and the VCO frequencydividers can be realised using one EPLD. The right handboard shown in figure 6 contains the Phase/Frequencydetector, VCO and loop filter. The second EPLD on thatboard is for further processing of the received data.

3.3 Stability

This phase/ frequency detector has some interestingstability problems. If we consider the phase detector only,the gain of the analogue circuit and the corner frequency

Clock

Data

0

64

128

192

6451Phase Det O/P

Period/PhaseCounter

Figure 9. Waveforms for Phase/Frequency Detector.

Phase Detector Output

Adder DACLoopFilter VCO

Divide by 16

Divide by 8

84.48 MHz

10.56 MHz

660 kBps Data

Clock660 kHz

8 Bit

Latch16 Bit

Frequency Control Counter

15 Bit

PeriodOutput

Phase & PeriodCounter

ThresholdDetection

Figure 10.Phase/Frequency Detector and PLL Block Diagram.

of the RC filter used at the output of the DAC are carefullycontrolled to ensure the correct damping factor and naturalfrequency of the PLL. Since digital hardware of 8 bitprecision in some parts and 16 bit precision in other partsis used, a slightly conservative damping factor needs tobe used in the design, to result in a stable system. The PLLlocks easily with the phase detector only. As expected, thelock-in range is however limited..

When the frequency detector is used by itself, the resultingFrequency Locked Loop works very well and quicklyadjusts the frequency of the VCO to within 660kHz of therequired frequency, when the frequency control stopsproviding further frequency correction. This is a coarsefrequency control. Using nonlinear techniques, which arebeyond the scope of this paper, the phase detector providesa fine frequency correction,which ensures that the PLLacquires lock.

The EPLDs can simply be reporgrammed on-board tochange the phase and frequency detector to differentconfigurations during development. The use of EPLDs isthus very convenient for the development of new systemslike this.

When the phase detector and frequency detector arecombined, there can be an interaction between them, whichtogether with the finite precision used in the digitalhardware, can cause instability. This instability manifestsitself as small amplitude limit cycles. These limit cyclescan be removed using careful design of the phase/frequency detector parameters and careful selection of theloop filter parameters. In order to be able to select thecorrect phase/frequency detector parameters and thecorrect loop filter, the PLL including all its nonlinear andquantisation effects needs to be simulated using MATLABor an Excel spreadsheet.

Figure 11 shows the transient phase error response obtainedfrom this Excel simulation of the Phase/Frequency detector.The transient includes a 5 MHz initial frequency error, topermit the operation of both the frequency and phasedetector to be demonstrated and to show that the PLL willlock regardless of the initial conditions. Three operatingregions can clearly be seen. The first part up to 0.35 msconsists of region where the frequency error is large and

frequency corrections are made every 1.515 µsmeasurement interval shown in Figure 9. The secondregion is from 0.35 ms to 0.88 ms where the phase detectoris controlling the frequency counter to ensure that the PLLacquires lock. During this time the operate at the exactfrequency. The third region from 0.88 ms onwards showsthe PLL in lock. For a 5 MHz initial frequency error, thePLL locks within 1 ms.

Figure 12 shows the eye diagram and the recovered dataclock. It can be seen that the PLL locks accurately. Therecovered data clock is used to drive the timing for theintegrate and dump filter in the BPSK phase detector, thusensuring that the transmitted data is recovered with themaximum likelihood and the minimum error.

4. ConclusionA BPSK detector and its associated Data Clock recoverycircuitry is realised using low cost digital hardware. TheBPSK detector performs well and locks reliably to the data,even in high noise conditions. A novel type of Phase/Frequency detector is presented, which ensures a reliableclock recovery of random binary data using predominantlydigital hardware. This recovered data clock permits therecovery of the received data using an integrate and dumpfilter, thus ensuring the optimum detection of the BPSK data.

5. References[1] Costas, J. P. “Synchronous communications”

proceedings of the IRE, Vol 47 pp 2058-2068, 1959.[2] Piper B. and Kikkert C. J. “The hardware design for

the reception of GMS SVISSR Weather SatelliteSignals.” Workshop on Applications of RadioScience, Canberra, June 1995.

[3] Roden, M. R. “Digital Communication SystemDesign”, Book, Prentice Hall, 1988.

[4] Kikkert C. J. Appendix 1 of D. A. Pucknell,“Fundamentals of Digital Logic Design: with VLSICircuit Applications”, Book, Prentice Hall, 1990.

Figure 11. PLL Phase Error for 5 MHz Frequency Step.

Figure 12. BPSK Demodulator Eye Diagram.

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0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

Time (ms)

Ph

ase

Err

or

(deg

rees

)