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Basic Principle of Buck-Boost
The buck-boost is a popular non-isolated inverting power stage topology, sometimes
called a step-up/down power stage. Power supply designers choose the buck-boost
power stage because the required output is inverted from the input voltage, and the
output voltage can be either higher or lower than the input voltage. The input current
for a buck-boost power stage is discontinuous, or pulsating, because the power switch
(Q1) current that pulses from zero to IL every switching cycle. The output current for
a buck-boost power stage is also discontinuous or pulsating because the output diode
only conducts during a portion of the switching cycle.
Figure 1 shows a simplified schematic of the buck-boost power stage. Inductor L and
capacitor C make up the effective output filter. The capacitor equivalent series
resistance (ESR), RC, and the inductor dc resistance, RL, are included in the analysis.
Resistor R represents the load seen by the power supply output. The diode D1 is
usually called the catch diode, or freewheeling diode.
Figure 1. Buck Power Stage Schematic
During normal operation of the buck-boost power stage, Q1 is repeatedly switched on
and off with the on- and off-times governed by the control circuit. This switching
action gives rise to a train of pulses at the junction of Q1, D1, and L. Although the
inductor, L, is connected to the output capacitor, C, only when D1 conducts, an
effective L/C output filter is formed. It filters the train of pulses to produce a DC
output voltage.
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Figure 2. Buck Power Stage States
The inductor current increase during the on state is given by:
The quantity IL(+) is the inductor ripple current.
The inductor current decrease during the off state is given by:
The quantity IL(-) is also the inductor ripple current.In steady conditions, the current increase, IL(+) and the current decrease IL(-) must
be equal. Solving for VO:
)1(...)(
)( ONLLQi
L TL
RIVVI
+=+
)2(...)(
)( OFFLLdO
L TL
RIVVI
=
)3(.....)1(1
)(
)()(
=
+=
D
RIV
D
DVV
T
TTRIV
T
TVVV
LLdQi
OFF
OFFONLLd
OFF
ONQiO
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A common simplification is to assume VQ, Vd, and RL are small enough to ignore.
Setting VQ, Vd, and RL to zero, the above equation simplifies considerably to:
Unlike the buck power stage, the average of the inductor current is not equal to the
output current. To relate the inductor current to the output current, referring to Figures
2 and 3, note that the inductor delivers current to the output only during the off state
of the power stage. This current averaged over a complete switching cycle is equal to
the output current because the average current in the output capacitor must be equal to
zero.
Figure 3. CCM Buck Power Stage Waveforms
)4(.....1 D
DVV iO
=
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Figure 4. Boundary Between Continuous and Discontinuous Mode
Further reduction in output load current puts the power stage into discontinuous
current conduction mode(DCM). The discontinuous mode power stage input-to-output
relationship is quite different from the continuous mode.
Figure 5. Discontinuous Current Mode
The duration of the on state is TON=DTS, where D is the duty cycle set by the
control circuit. The duration of the off state is TOFF=D2TS. The idle time is the
remainder of the switching cycle and is given as TS-TON-TOFF= D3TS. These
times are shown with the waveforms in Figure 5.
The inductor current increase during the on state is given by:
The ripple current magnitude, IL(+), is also the peak inductor current, Ipk, becausein discontinuous mode. The current starts at zero each cycle.
)5()1()()( OAvgLS
OFF
AvgL IDIT
TI ==
)6()( PKSi
ON
i
L ITDL
VT
L
VI ===+
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The inductor current decrease during the off state is given by:
As in the continuous conduction mode case, the current increase, IL(+), during the
on time and the current decrease during the off time, IL(-), are equal. So,
Figure 6. Discontinuous Mode Buck Power Stage Waveforms
)7(2)( SO
OFFO
L TDL
VT
L
VI
=
=
)8(2D
DV
T
TVV i
OFF
ON
iO ==
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Now calculate the output current. It is the average over one switching cycle of the
inductor current during the time when D1 conducts(D2*Ts).
Now solve two equations, IO and VO (equation 8 and 10), the discontinuous
conduction mode buck voltage conversion relationship is given by:
Where K is defined as:
)9(22
1)(
=== SPK
S
O
avgLO TDI
TR
VII
)10(2
2
2)()1(2
11
L
TDDV
TDTDL
V
TR
VI
Si
SSi
S
OO
=
==
K
DVV iO =
STRLK
=2
)11(KMD =
)12(i
O
VVM =
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Critical Inductance
The previous analyses for the buck-boost power stage have been for continuous and
discontinuous conduction modes of steady-state operation. The conduction mode of a
power stage is a function of input voltage, output voltage, output current, and the
value of the inductor. A buck-boost power stage can be designed to operate in
continuous mode for load currents above a certain level usually5 to 10% of full load.
Usually, the input voltage range, output voltage, and load current are defined by the
power stage specification. This leaves the inductor value as the design parameter to
maintain continuous conduction mode.
The minimum value of inductor to maintain continuous conduction mode can be
determined by the following procedure.
First, define IOB as the minimum output current to maintain continuous conduction
mode, normally referred to as the critical current. This value is shown in Figure 4. In
boundary between CCM and DCM,
On Boundary:
CCM:
)1(2 D
III OBLLB
=
=
)15(2
)(
2OFF
LLdOON
LLOiLB T
L
RIVVT
L
RIVVI
=
=
)16()(22
)(
2
(max)
2
(max)
(min)
(max)
min
io
i
OB
SO
ON
LB
LLQi
VV
V
I
TV
TI
RIVV
L
=
)13(ONLLQi
L TL
RIVVI
=
)14(
1 D
DVVo i
=
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Output Capacitor
In switching power supply power stages, the function of output capacitor is to store
energy. The output capacitance for a boost power stage is generally selected to limit
output voltage ripple to the level required by the specification. The series impedance
of the capacitor and the power stage output current determine the output voltage ripple.
The three elements of the capacitor that contribute to its impedance (and output
voltage ripple) are equivalent series resistance (ESR), equivalent series inductance
(ESL), and capacitance (C). The voltage variation due to the inductor current flow in
the output capacitor is approximately:
For CCM Mode:
For DCM Mode
)(2
2
INdO
PKO
VVVC
LIV
+
=OS
O
Vf
DIC
maxmax
os
s
O
Vf
TR
LI
C
21(max)
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The above equation is based on the assumption that all inductor ripple current flows
through the capacitor and the ESR is zero. Now, assuming that the capacitor is very
large, the ESR needed to Limit the ripple to VOmax is:
For CCM Mode:
For DCM Mode:
*The output filter capacitor should be rated at least 10~20 times the calculated
capacitance and 30 to 50 percent lower than the calculated ESR.
The RMS value of the ripple current flowing in the output capacitance(CCM) is given
by:
PK
O
O
Max
O
O
I
V
I
D
I
VESR max
(max)
max
)21
(
=
+
PK
O
O
O
I
V
I
VESR maxmax
=
D
DII OCRMS
=1
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Buck-Boost DC/DC Converter Small Signal Model (Transfer Function):
)1
)(()()
1
)(()()
1(
1)()(
T
sZsi
T
sGVsV
T
T
HsVsV OUTload
g
grefO +
++
+=
gainloopV
sGVsGsHsT
M
dC ==)()()(
)(
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11
For CCM Mode:
*Two Pole fLC , One Zero fESRfor GVd(s) and One Right-Half-Plane zero
z From a practical view, at RHP zero frequency, the loop gain starts increasing at a20dB/decade rate but the loop phase decreases by 45 degrees (in a normal, LHPzero, the loop phase will increase by +45 degrees). This imposes the restriction
that the gain be rolled off to 0dB before encountering the RHP zero.
z The output inductor, capacitor and the capacitors ESR must be selected so thatthe double pole occurs first and then the output capacitor zero and then the RHP
zero. This assures that the loop gain crosses 0dB at a slope that is first order
(20dB/decade) and that the instability inherently associated with the RHP zero is
circumvented by crossing 0dB before the RHP zero frequency occurs.
( )
++
+
=
2
00
21
2
1
11
1)(
w
s
Qw
s
w
s
w
s
D
VsGV
ZZg
d
C
L
RDQ
)1(
LC
D
R
RDR
LCw L
)1()1(1 2
0
+=
CRw
C
Z
11 =
( )DL
RD
L
RRDw LZ
22
2
)1(1
=
Compensate rule:
4.Decrease the double pole influence. LCrcompensatoZ ff4
3)(
5.Crossover frequency fC SCESRC ffff )6
1~
10
1(> )(
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Figure 11. Flyback converter CCM waveforms
The simplified voltage conversion relationship for the flyback power stage operating
in CCM is given by:
D
Dn
V
V
i
O
=
1
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Figure 12. Flyback converter DCM waveforms
The simplified voltage conversion relationship for the flyback power stage operating
in DCM is given by:
S
SEC
i
O
TR
LK
K
Dn
V
V
==
2
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Flyback DC/DC Converter Small Signal Model (Transfer Function):
)1
)(()()
1
)(()()
1(
1)()(
T
sZsi
T
sGVsV
T
T
HsVsV OUTload
g
grefO +
++
+=
gainloopV
sGVsGsHsT
M
dC ==)()()(
)(
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For CCM Mode:
*Two Pole fLC , One Zero fESRfor GVd(s) and One Right-Half-Plane zero
z From a practical view, at RHP zero frequency, the loop gain starts increasing at a20dB/decade rate but the loop phase decreases by 45 degrees (in a normal, LHPzero, the loop phase will increase by +45 degrees). This imposes the restriction
that the gain be rolled off to 0dB before encountering the RHP zero.
z The output inductor, capacitor and the capacitors ESR must be selected so thatthe double pole occurs first and then the output capacitor zero and then the RHP
zero. This assures that the loop gain crosses 0dB at a slope that is first order
(20dB/decade) and that the instability inherently associated with the RHP zero is
circumvented by crossing 0dB before the RHP zero frequency occurs.
( )
++
+
=
2
00
21
2
1
11
1)(
w
s
Qw
s
w
s
w
s
D
VnsGV
ZZg
d
C
L
RDQ
SEC
)1(
CL
D
R
RDR
CLw
SEC
L
SEC
)1()1(12
0
+=
CRw
C
Z
11 =
SEC
ZLD
RDw
2
2
)1(
Compensate rule:
1.Decrease the double pole influence. LCrcompensatoZ ff4
3)(
2.Crossover frequency fC SCESRC ffff )6
1~
10
1(