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BUD17-214: Bus scaling QoS update

Date post: 19-Mar-2017
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Bus scaling QoS update Georgi Djakov
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Page 1: BUD17-214: Bus scaling QoS update

Bus scaling QoS updateGeorgi Djakov

Page 2: BUD17-214: Bus scaling QoS update

ENGINEERS AND DEVICES

WORKING TOGETHER

Agenda

● Background● The problem● The solution● Next steps

Page 3: BUD17-214: Bus scaling QoS update

ENGINEERS AND DEVICESWORKING TOGETHER

Background● Challenges of SoC architecture

○ More and more features (IP cores)○ Many components talking to each other○ Multiple sources of traffic○ Concurrent transfers○ Predictability

● Evolution of on-chip interconnects○ Buses, crossbars, network-on-chip

● Benefits○ Scalability - packet communication○ Power efficiency - shorter wires

Page 4: BUD17-214: Bus scaling QoS update

ENGINEERS AND DEVICESWORKING TOGETHER

An example NoC topology

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ENGINEERS AND DEVICES

WORKING TOGETHER

The problem

● On-chip interconnect buses can handle high throughput data transfers, but most of the time they may be idle.

● Simultaneous data flows across the SoC with different sources and destinations, interleaved traffic.

● Interconnect buses can be configured according to the use-case and demand.

● Each SoC vendor has its own custom implementation in the downstream kernel.

● Need a common solution in the upstream Linux kernel.

Page 6: BUD17-214: Bus scaling QoS update

ENGINEERS AND DEVICESWORKING TOGETHER

Requirements

● Description of the topology.

● Expose path between endpoints as resources. The path is claimed by

consumer drivers and they set constraints on it.

● A common framework for that can traverse the topology and allow a consumer

driver to get() a path.

● Track and aggregate requests received from drivers.

● Update constraints and set hardware to most optimal configuration.

● The vendor specific interconnect controller drivers register the topology with

the framework and implements low-level operations.

Page 7: BUD17-214: Bus scaling QoS update

ENGINEERS AND DEVICES

WORKING TOGETHER

The solution

● A new framework - interconnect framework

● Vendor specific low-level drivers that control the hardware

● Consumer API to set constraints from drivers

Page 8: BUD17-214: Bus scaling QoS update

ENGINEERS AND DEVICESWORKING TOGETHER

Device-Tree binding

● Interconnect provider

snoc: snoc@0580000 {

compatible = "qcom,msm-bus-snoc";

#interconnect-cells = <1>;

interconnect-port = <&bimc MAS_SNOC_CFG>,

<&bimc SNOC_BIMC_0_MAS>,

<&bimc SNOC_BIMC_1_MAS>,

<&pnoc SNOC_PNOC_SLV>;

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ENGINEERS AND DEVICESWORKING TOGETHER

Device-Tree binding

● Interconnect consumer

sdhc_1: sdhci@07824000 {

interconnect-port = <&pnoc MAS_PNOC_SDCC_1>;

interconnect-path = <&mem>, <&usb_otg>;

interconnect-path-names = "mem", "usb";

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ENGINEERS AND DEVICESWORKING TOGETHER

Interconnect API

● struct interconnect_path *interconnect_get(struct device *dev, const char *id);

● int interconnect_set(struct interconnect_path *path, u32 bandwidth);

● void interconnect_put(struct interconnect_path *path);

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ENGINEERS AND DEVICESWORKING TOGETHER

Interconnect API

● Currently works only with device-tree and platform drivers

● Use device-tree to denote path endpoints

● Types of constraints

● PM QoS

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ENGINEERS AND DEVICESWORKING TOGETHER

The first vendor specific driver

● Dragonboard 410c as a test platform.

● Test scenarios○ Data transfers between peripherals

○ Data transfers from/to memory

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ENGINEERS AND DEVICES

WORKING TOGETHER

Future work● Feedback

○ LKML

○ Should we use PM QoS?

○ Remove dependency on DT

○ Support for ACPI?

○ Use integers instead of string ids for the binding

● Add support for other types of QoS constraints○ Average bandwidth

○ Peak bandwidth

○ Round-trip latency

○ Priority

● Extend the Qualcomm msm8916 interconnect driver○ Include the full topology

● Practical and easy example for testing

Page 14: BUD17-214: Bus scaling QoS update

Thank You#BUD17

For further information: www.linaro.orgBUD17 keynotes and videos on: connect.linaro.org


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