CONCORDIA VLSI DESIGN LAB 1 Buffering To Drive large load, special buffers capable of delivering current at high speed are essential. Load may be on-chip such as the clock distribution network or off-chip such as the pad drivers. An effective way to minimize large capacitive load is to implement a Tapered Buffer that is a chain of inverters with a gradual increase in driving capability • The Objective: Given a load capacitance, C L design a scaled (tapered) chain of N inverters such that the delay time between the logic gate and the load capacitance node is minimized The task is to determine: number of stages (N) and the tapering factor (S) Buffer Large Load
Transcript
CONCORDIAVLSI DESIGN LAB
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Buffering To Drive large load, special buffers capable of delivering current at high speed are essential.
Load may be on-chip such as the clock distribution network or off-chip such as the pad drivers.
An effective way to minimize largecapacitive load is to implement aTapered Buffer that is a chain of
inverters with a gradual increase in driving capability
• The Objective: Given a load capacitance, CL design a scaled (tapered)chain of N inverters such that the delay time between the logic gate and the load capacitance node is minimizedThe task is to determine: number of stages (N) and the tapering factor (S)
Buffer
Large Load
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OUTPUT Pad and Driver
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CLOCK DRIVER
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Buffering
S = scaling or tapering factor
CL = SN+1 Cg ………………
All inverters have identical delay of
to = delay of the first stage (load =Cd+Cg)
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Buffering
0 1 2 3
3
4
5
Cd/Cg
S
If the diffusion capacitance Cd is neglected, then S = e = 2.7
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Layout of a standard inverter
PMOS
NMOS
VinVo
VSS
Wn
L
WpPolysilicon
Metal
Diffusion
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Layout of Large Device
•Drain-Source Area
•Delay of Gate
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Layout of a Buffer
S
S
G
D
G(ate)
S(ource)
D(rain)
Multiple
Contacts
(a) small transistors in parallel (b) circular transistors
Prentice Hall/Rabaey
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Large Transistor Layout
Increase # of Contacts
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Output Drivers
Standard CMOS Driver
Open Drain/Source Driver: Single Transistors
Tri-state Driver
Bi-directional Circuit
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Output Drivers
Bonding Pad
Out
InVDD GND
100 m
m
GND
Out
Prentice Hall/Rabaey
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Tri-state Driver
In
VDD
En
EnOut
Tri-state or High impedance Used to drive internal or external busses Two inputs:
Data In and Enable Various signal assertions Two types:
C2MOS CMOS with Control Logic
C2MOS
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VDD
En
En
PADOut
In
Control logic could be modified to obtainInversion/non-inversionActive low/high Enable
For large load, pre-driversare required
Tri-state Driver
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Latch-up on CMOS
Inherent in bulk CMOS processes are parasitic bipolar transistors forming p+/n /p /n+ path between VDD and VSS
The four layer path is equivalent to SCR which when triggered can cause self sustaining latch-up between power supplies resulting in total or local destruction.
n+ p+ p+ n+ n+ p+
Rs
T1 T2
VDDVSS
P-well
n-substrate
Rw
Rs
Rw
Drain of
PMOS
Drain ofNMOS
T1T2
VDD
Vss
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Latch-up: Analysis
T1
VDD
VSS
If VA>VDD+0.6, T1 will be turned ON Ic1 causes a voltage drop across Rw If V(Rw) > 0.6V V, T2 will be turned ON, this forces Ic2 to be supplied by VDD throughn+ substrate contact, then the bulk to p-well.
Increase in voltage across Rs causes and in increase in Ic1, hence sustaining SCR action.
The same action will take place when: VB< -0.6V
Hence to prevent latch-up, limit the output voltage
-0.6< Vout < VDD+0.6V
VA
VB
T2
IE1
IC1
IB1
IB2
IC1
IE1
Rs
Rw
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Latch-up: Trigger
Factors which trigger latch-up
transmission line reflections or ringing voltage drop on the VDD bus “hot plug in” of unpowered circuit board electrostatic discharge sudden transient on power and ground busses leakage current across the junction radiation: x-ray, cosmic
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Latch-up: Prevention1. Layout techniques:
Incorporate collectors for latch-up current:
Create diffused n and p guard rings that surround active devicesThese collectors can sink the current but are incapable of sustaining the latch-up mechanism once the cause is removed
n+n+
p+p+
n+n+
p+p+
guard ring
GND
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Input protection
Electrostatic discharge can take place through transfer of charges from the human body to the device.
Human body can carry up to 8000V.Discharge can happen within hundreds of nanoseconds.Critical field for SiO2 is about 7X106 V/cm.For 0.5u CMOS process the gate oxide can withstand around 8VSome protection technique is required with minimum impact on
performance
DUT
100pF
1.5K1M
Vesd
Human Body model
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Input PAD
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Protection Circuitry Principles
Punch Through Avalanche
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Input
Pad
Vd
d
Vs
s
Circu
it
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ESD StructuresBasic technique is to include series resistance and two clamping diodes.The resistance R is to limit the current and to slow down the high voltage transitions.R could be polysilicon or diffusion resistanceDiffusion resistance could be part of the diode structureTypical values of R: 500 to 1k
